1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "i915_gem_gtt.h" 39 #include <linux/io-mapping.h> 40 #include <linux/i2c.h> 41 #include <linux/i2c-algo-bit.h> 42 #include <drm/intel-gtt.h> 43 #include <linux/backlight.h> 44 #include <linux/hashtable.h> 45 #include <linux/intel-iommu.h> 46 #include <linux/kref.h> 47 #include <linux/pm_qos.h> 48 49 /* General customization: 50 */ 51 52 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 53 54 #define DRIVER_NAME "i915" 55 #define DRIVER_DESC "Intel Graphics" 56 #define DRIVER_DATE "20140725" 57 58 enum pipe { 59 INVALID_PIPE = -1, 60 PIPE_A = 0, 61 PIPE_B, 62 PIPE_C, 63 _PIPE_EDP, 64 I915_MAX_PIPES = _PIPE_EDP 65 }; 66 #define pipe_name(p) ((p) + 'A') 67 68 enum transcoder { 69 TRANSCODER_A = 0, 70 TRANSCODER_B, 71 TRANSCODER_C, 72 TRANSCODER_EDP, 73 I915_MAX_TRANSCODERS 74 }; 75 #define transcoder_name(t) ((t) + 'A') 76 77 enum plane { 78 PLANE_A = 0, 79 PLANE_B, 80 PLANE_C, 81 }; 82 #define plane_name(p) ((p) + 'A') 83 84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 85 86 enum port { 87 PORT_A = 0, 88 PORT_B, 89 PORT_C, 90 PORT_D, 91 PORT_E, 92 I915_MAX_PORTS 93 }; 94 #define port_name(p) ((p) + 'A') 95 96 #define I915_NUM_PHYS_VLV 2 97 98 enum dpio_channel { 99 DPIO_CH0, 100 DPIO_CH1 101 }; 102 103 enum dpio_phy { 104 DPIO_PHY0, 105 DPIO_PHY1 106 }; 107 108 enum intel_display_power_domain { 109 POWER_DOMAIN_PIPE_A, 110 POWER_DOMAIN_PIPE_B, 111 POWER_DOMAIN_PIPE_C, 112 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 113 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 114 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 115 POWER_DOMAIN_TRANSCODER_A, 116 POWER_DOMAIN_TRANSCODER_B, 117 POWER_DOMAIN_TRANSCODER_C, 118 POWER_DOMAIN_TRANSCODER_EDP, 119 POWER_DOMAIN_PORT_DDI_A_2_LANES, 120 POWER_DOMAIN_PORT_DDI_A_4_LANES, 121 POWER_DOMAIN_PORT_DDI_B_2_LANES, 122 POWER_DOMAIN_PORT_DDI_B_4_LANES, 123 POWER_DOMAIN_PORT_DDI_C_2_LANES, 124 POWER_DOMAIN_PORT_DDI_C_4_LANES, 125 POWER_DOMAIN_PORT_DDI_D_2_LANES, 126 POWER_DOMAIN_PORT_DDI_D_4_LANES, 127 POWER_DOMAIN_PORT_DSI, 128 POWER_DOMAIN_PORT_CRT, 129 POWER_DOMAIN_PORT_OTHER, 130 POWER_DOMAIN_VGA, 131 POWER_DOMAIN_AUDIO, 132 POWER_DOMAIN_PLLS, 133 POWER_DOMAIN_INIT, 134 135 POWER_DOMAIN_NUM, 136 }; 137 138 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 139 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 140 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 141 #define POWER_DOMAIN_TRANSCODER(tran) \ 142 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 143 (tran) + POWER_DOMAIN_TRANSCODER_A) 144 145 enum hpd_pin { 146 HPD_NONE = 0, 147 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 148 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 149 HPD_CRT, 150 HPD_SDVO_B, 151 HPD_SDVO_C, 152 HPD_PORT_B, 153 HPD_PORT_C, 154 HPD_PORT_D, 155 HPD_NUM_PINS 156 }; 157 158 #define I915_GEM_GPU_DOMAINS \ 159 (I915_GEM_DOMAIN_RENDER | \ 160 I915_GEM_DOMAIN_SAMPLER | \ 161 I915_GEM_DOMAIN_COMMAND | \ 162 I915_GEM_DOMAIN_INSTRUCTION | \ 163 I915_GEM_DOMAIN_VERTEX) 164 165 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 166 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 167 168 #define for_each_crtc(dev, crtc) \ 169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 170 171 #define for_each_intel_crtc(dev, intel_crtc) \ 172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 173 174 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 175 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 176 if ((intel_encoder)->base.crtc == (__crtc)) 177 178 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 179 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 180 if ((intel_connector)->base.encoder == (__encoder)) 181 182 #define for_each_power_domain(domain, mask) \ 183 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 184 if ((1 << (domain)) & (mask)) 185 186 struct drm_i915_private; 187 struct i915_mmu_object; 188 189 enum intel_dpll_id { 190 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 191 /* real shared dpll ids must be >= 0 */ 192 DPLL_ID_PCH_PLL_A = 0, 193 DPLL_ID_PCH_PLL_B = 1, 194 DPLL_ID_WRPLL1 = 0, 195 DPLL_ID_WRPLL2 = 1, 196 }; 197 #define I915_NUM_PLLS 2 198 199 struct intel_dpll_hw_state { 200 uint32_t dpll; 201 uint32_t dpll_md; 202 uint32_t fp0; 203 uint32_t fp1; 204 uint32_t wrpll; 205 }; 206 207 struct intel_shared_dpll { 208 int refcount; /* count of number of CRTCs sharing this PLL */ 209 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 210 bool on; /* is the PLL actually active? Disabled during modeset */ 211 const char *name; 212 /* should match the index in the dev_priv->shared_dplls array */ 213 enum intel_dpll_id id; 214 struct intel_dpll_hw_state hw_state; 215 /* The mode_set hook is optional and should be used together with the 216 * intel_prepare_shared_dpll function. */ 217 void (*mode_set)(struct drm_i915_private *dev_priv, 218 struct intel_shared_dpll *pll); 219 void (*enable)(struct drm_i915_private *dev_priv, 220 struct intel_shared_dpll *pll); 221 void (*disable)(struct drm_i915_private *dev_priv, 222 struct intel_shared_dpll *pll); 223 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 224 struct intel_shared_dpll *pll, 225 struct intel_dpll_hw_state *hw_state); 226 }; 227 228 /* Used by dp and fdi links */ 229 struct intel_link_m_n { 230 uint32_t tu; 231 uint32_t gmch_m; 232 uint32_t gmch_n; 233 uint32_t link_m; 234 uint32_t link_n; 235 }; 236 237 void intel_link_compute_m_n(int bpp, int nlanes, 238 int pixel_clock, int link_clock, 239 struct intel_link_m_n *m_n); 240 241 /* Interface history: 242 * 243 * 1.1: Original. 244 * 1.2: Add Power Management 245 * 1.3: Add vblank support 246 * 1.4: Fix cmdbuffer path, add heap destroy 247 * 1.5: Add vblank pipe configuration 248 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 249 * - Support vertical blank on secondary display pipe 250 */ 251 #define DRIVER_MAJOR 1 252 #define DRIVER_MINOR 6 253 #define DRIVER_PATCHLEVEL 0 254 255 #define WATCH_LISTS 0 256 #define WATCH_GTT 0 257 258 struct opregion_header; 259 struct opregion_acpi; 260 struct opregion_swsci; 261 struct opregion_asle; 262 263 struct intel_opregion { 264 struct opregion_header __iomem *header; 265 struct opregion_acpi __iomem *acpi; 266 struct opregion_swsci __iomem *swsci; 267 u32 swsci_gbda_sub_functions; 268 u32 swsci_sbcb_sub_functions; 269 struct opregion_asle __iomem *asle; 270 void __iomem *vbt; 271 u32 __iomem *lid_state; 272 struct work_struct asle_work; 273 }; 274 #define OPREGION_SIZE (8*1024) 275 276 struct intel_overlay; 277 struct intel_overlay_error_state; 278 279 struct drm_i915_master_private { 280 drm_local_map_t *sarea; 281 struct _drm_i915_sarea *sarea_priv; 282 }; 283 #define I915_FENCE_REG_NONE -1 284 #define I915_MAX_NUM_FENCES 32 285 /* 32 fences + sign bit for FENCE_REG_NONE */ 286 #define I915_MAX_NUM_FENCE_BITS 6 287 288 struct drm_i915_fence_reg { 289 struct list_head lru_list; 290 struct drm_i915_gem_object *obj; 291 int pin_count; 292 }; 293 294 struct sdvo_device_mapping { 295 u8 initialized; 296 u8 dvo_port; 297 u8 slave_addr; 298 u8 dvo_wiring; 299 u8 i2c_pin; 300 u8 ddc_pin; 301 }; 302 303 struct intel_display_error_state; 304 305 struct drm_i915_error_state { 306 struct kref ref; 307 struct timeval time; 308 309 char error_msg[128]; 310 u32 reset_count; 311 u32 suspend_count; 312 313 /* Generic register state */ 314 u32 eir; 315 u32 pgtbl_er; 316 u32 ier; 317 u32 gtier[4]; 318 u32 ccid; 319 u32 derrmr; 320 u32 forcewake; 321 u32 error; /* gen6+ */ 322 u32 err_int; /* gen7 */ 323 u32 done_reg; 324 u32 gac_eco; 325 u32 gam_ecochk; 326 u32 gab_ctl; 327 u32 gfx_mode; 328 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 329 u64 fence[I915_MAX_NUM_FENCES]; 330 struct intel_overlay_error_state *overlay; 331 struct intel_display_error_state *display; 332 struct drm_i915_error_object *semaphore_obj; 333 334 struct drm_i915_error_ring { 335 bool valid; 336 /* Software tracked state */ 337 bool waiting; 338 int hangcheck_score; 339 enum intel_ring_hangcheck_action hangcheck_action; 340 int num_requests; 341 342 /* our own tracking of ring head and tail */ 343 u32 cpu_ring_head; 344 u32 cpu_ring_tail; 345 346 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 347 348 /* Register state */ 349 u32 tail; 350 u32 head; 351 u32 ctl; 352 u32 hws; 353 u32 ipeir; 354 u32 ipehr; 355 u32 instdone; 356 u32 bbstate; 357 u32 instpm; 358 u32 instps; 359 u32 seqno; 360 u64 bbaddr; 361 u64 acthd; 362 u32 fault_reg; 363 u64 faddr; 364 u32 rc_psmi; /* sleep state */ 365 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 366 367 struct drm_i915_error_object { 368 int page_count; 369 u32 gtt_offset; 370 u32 *pages[0]; 371 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 372 373 struct drm_i915_error_request { 374 long jiffies; 375 u32 seqno; 376 u32 tail; 377 } *requests; 378 379 struct { 380 u32 gfx_mode; 381 union { 382 u64 pdp[4]; 383 u32 pp_dir_base; 384 }; 385 } vm_info; 386 387 pid_t pid; 388 char comm[TASK_COMM_LEN]; 389 } ring[I915_NUM_RINGS]; 390 struct drm_i915_error_buffer { 391 u32 size; 392 u32 name; 393 u32 rseqno, wseqno; 394 u32 gtt_offset; 395 u32 read_domains; 396 u32 write_domain; 397 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 398 s32 pinned:2; 399 u32 tiling:2; 400 u32 dirty:1; 401 u32 purgeable:1; 402 u32 userptr:1; 403 s32 ring:4; 404 u32 cache_level:3; 405 } **active_bo, **pinned_bo; 406 407 u32 *active_bo_count, *pinned_bo_count; 408 }; 409 410 struct intel_connector; 411 struct intel_crtc_config; 412 struct intel_plane_config; 413 struct intel_crtc; 414 struct intel_limit; 415 struct dpll; 416 417 struct drm_i915_display_funcs { 418 bool (*fbc_enabled)(struct drm_device *dev); 419 void (*enable_fbc)(struct drm_crtc *crtc); 420 void (*disable_fbc)(struct drm_device *dev); 421 int (*get_display_clock_speed)(struct drm_device *dev); 422 int (*get_fifo_size)(struct drm_device *dev, int plane); 423 /** 424 * find_dpll() - Find the best values for the PLL 425 * @limit: limits for the PLL 426 * @crtc: current CRTC 427 * @target: target frequency in kHz 428 * @refclk: reference clock frequency in kHz 429 * @match_clock: if provided, @best_clock P divider must 430 * match the P divider from @match_clock 431 * used for LVDS downclocking 432 * @best_clock: best PLL values found 433 * 434 * Returns true on success, false on failure. 435 */ 436 bool (*find_dpll)(const struct intel_limit *limit, 437 struct drm_crtc *crtc, 438 int target, int refclk, 439 struct dpll *match_clock, 440 struct dpll *best_clock); 441 void (*update_wm)(struct drm_crtc *crtc); 442 void (*update_sprite_wm)(struct drm_plane *plane, 443 struct drm_crtc *crtc, 444 uint32_t sprite_width, uint32_t sprite_height, 445 int pixel_size, bool enable, bool scaled); 446 void (*modeset_global_resources)(struct drm_device *dev); 447 /* Returns the active state of the crtc, and if the crtc is active, 448 * fills out the pipe-config with the hw state. */ 449 bool (*get_pipe_config)(struct intel_crtc *, 450 struct intel_crtc_config *); 451 void (*get_plane_config)(struct intel_crtc *, 452 struct intel_plane_config *); 453 int (*crtc_mode_set)(struct drm_crtc *crtc, 454 int x, int y, 455 struct drm_framebuffer *old_fb); 456 void (*crtc_enable)(struct drm_crtc *crtc); 457 void (*crtc_disable)(struct drm_crtc *crtc); 458 void (*off)(struct drm_crtc *crtc); 459 void (*write_eld)(struct drm_connector *connector, 460 struct drm_crtc *crtc, 461 struct drm_display_mode *mode); 462 void (*fdi_link_train)(struct drm_crtc *crtc); 463 void (*init_clock_gating)(struct drm_device *dev); 464 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 465 struct drm_framebuffer *fb, 466 struct drm_i915_gem_object *obj, 467 struct intel_engine_cs *ring, 468 uint32_t flags); 469 void (*update_primary_plane)(struct drm_crtc *crtc, 470 struct drm_framebuffer *fb, 471 int x, int y); 472 void (*hpd_irq_setup)(struct drm_device *dev); 473 /* clock updates for mode set */ 474 /* cursor updates */ 475 /* render clock increase/decrease */ 476 /* display clock increase/decrease */ 477 /* pll clock increase/decrease */ 478 479 int (*setup_backlight)(struct intel_connector *connector); 480 uint32_t (*get_backlight)(struct intel_connector *connector); 481 void (*set_backlight)(struct intel_connector *connector, 482 uint32_t level); 483 void (*disable_backlight)(struct intel_connector *connector); 484 void (*enable_backlight)(struct intel_connector *connector); 485 }; 486 487 struct intel_uncore_funcs { 488 void (*force_wake_get)(struct drm_i915_private *dev_priv, 489 int fw_engine); 490 void (*force_wake_put)(struct drm_i915_private *dev_priv, 491 int fw_engine); 492 493 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 494 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 495 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 496 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 497 498 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 499 uint8_t val, bool trace); 500 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 501 uint16_t val, bool trace); 502 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 503 uint32_t val, bool trace); 504 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 505 uint64_t val, bool trace); 506 }; 507 508 struct intel_uncore { 509 spinlock_t lock; /** lock is also taken in irq contexts. */ 510 511 struct intel_uncore_funcs funcs; 512 513 unsigned fifo_count; 514 unsigned forcewake_count; 515 516 unsigned fw_rendercount; 517 unsigned fw_mediacount; 518 519 struct timer_list force_wake_timer; 520 }; 521 522 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 523 func(is_mobile) sep \ 524 func(is_i85x) sep \ 525 func(is_i915g) sep \ 526 func(is_i945gm) sep \ 527 func(is_g33) sep \ 528 func(need_gfx_hws) sep \ 529 func(is_g4x) sep \ 530 func(is_pineview) sep \ 531 func(is_broadwater) sep \ 532 func(is_crestline) sep \ 533 func(is_ivybridge) sep \ 534 func(is_valleyview) sep \ 535 func(is_haswell) sep \ 536 func(is_preliminary) sep \ 537 func(has_fbc) sep \ 538 func(has_pipe_cxsr) sep \ 539 func(has_hotplug) sep \ 540 func(cursor_needs_physical) sep \ 541 func(has_overlay) sep \ 542 func(overlay_needs_physical) sep \ 543 func(supports_tv) sep \ 544 func(has_llc) sep \ 545 func(has_ddi) sep \ 546 func(has_fpga_dbg) 547 548 #define DEFINE_FLAG(name) u8 name:1 549 #define SEP_SEMICOLON ; 550 551 struct intel_device_info { 552 u32 display_mmio_offset; 553 u8 num_pipes:3; 554 u8 num_sprites[I915_MAX_PIPES]; 555 u8 gen; 556 u8 ring_mask; /* Rings supported by the HW */ 557 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 558 /* Register offsets for the various display pipes and transcoders */ 559 int pipe_offsets[I915_MAX_TRANSCODERS]; 560 int trans_offsets[I915_MAX_TRANSCODERS]; 561 int palette_offsets[I915_MAX_PIPES]; 562 int cursor_offsets[I915_MAX_PIPES]; 563 }; 564 565 #undef DEFINE_FLAG 566 #undef SEP_SEMICOLON 567 568 enum i915_cache_level { 569 I915_CACHE_NONE = 0, 570 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 571 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 572 caches, eg sampler/render caches, and the 573 large Last-Level-Cache. LLC is coherent with 574 the CPU, but L3 is only visible to the GPU. */ 575 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 576 }; 577 578 struct i915_ctx_hang_stats { 579 /* This context had batch pending when hang was declared */ 580 unsigned batch_pending; 581 582 /* This context had batch active when hang was declared */ 583 unsigned batch_active; 584 585 /* Time when this context was last blamed for a GPU reset */ 586 unsigned long guilty_ts; 587 588 /* This context is banned to submit more work */ 589 bool banned; 590 }; 591 592 /* This must match up with the value previously used for execbuf2.rsvd1. */ 593 #define DEFAULT_CONTEXT_HANDLE 0 594 /** 595 * struct intel_context - as the name implies, represents a context. 596 * @ref: reference count. 597 * @user_handle: userspace tracking identity for this context. 598 * @remap_slice: l3 row remapping information. 599 * @file_priv: filp associated with this context (NULL for global default 600 * context). 601 * @hang_stats: information about the role of this context in possible GPU 602 * hangs. 603 * @vm: virtual memory space used by this context. 604 * @legacy_hw_ctx: render context backing object and whether it is correctly 605 * initialized (legacy ring submission mechanism only). 606 * @link: link in the global list of contexts. 607 * 608 * Contexts are memory images used by the hardware to store copies of their 609 * internal state. 610 */ 611 struct intel_context { 612 struct kref ref; 613 int user_handle; 614 uint8_t remap_slice; 615 struct drm_i915_file_private *file_priv; 616 struct i915_ctx_hang_stats hang_stats; 617 struct i915_address_space *vm; 618 619 struct { 620 struct drm_i915_gem_object *rcs_state; 621 bool initialized; 622 } legacy_hw_ctx; 623 624 struct list_head link; 625 }; 626 627 struct i915_fbc { 628 unsigned long size; 629 unsigned threshold; 630 unsigned int fb_id; 631 enum plane plane; 632 int y; 633 634 struct drm_mm_node compressed_fb; 635 struct drm_mm_node *compressed_llb; 636 637 struct intel_fbc_work { 638 struct delayed_work work; 639 struct drm_crtc *crtc; 640 struct drm_framebuffer *fb; 641 } *fbc_work; 642 643 enum no_fbc_reason { 644 FBC_OK, /* FBC is enabled */ 645 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 646 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 647 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 648 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 649 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 650 FBC_BAD_PLANE, /* fbc not supported on plane */ 651 FBC_NOT_TILED, /* buffer not tiled */ 652 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 653 FBC_MODULE_PARAM, 654 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 655 } no_fbc_reason; 656 }; 657 658 struct i915_drrs { 659 struct intel_connector *connector; 660 }; 661 662 struct intel_dp; 663 struct i915_psr { 664 struct mutex lock; 665 bool sink_support; 666 bool source_ok; 667 struct intel_dp *enabled; 668 bool active; 669 struct delayed_work work; 670 unsigned busy_frontbuffer_bits; 671 }; 672 673 enum intel_pch { 674 PCH_NONE = 0, /* No PCH present */ 675 PCH_IBX, /* Ibexpeak PCH */ 676 PCH_CPT, /* Cougarpoint PCH */ 677 PCH_LPT, /* Lynxpoint PCH */ 678 PCH_NOP, 679 }; 680 681 enum intel_sbi_destination { 682 SBI_ICLK, 683 SBI_MPHY, 684 }; 685 686 #define QUIRK_PIPEA_FORCE (1<<0) 687 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 688 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 689 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 690 691 struct intel_fbdev; 692 struct intel_fbc_work; 693 694 struct intel_gmbus { 695 struct i2c_adapter adapter; 696 u32 force_bit; 697 u32 reg0; 698 u32 gpio_reg; 699 struct i2c_algo_bit_data bit_algo; 700 struct drm_i915_private *dev_priv; 701 }; 702 703 struct i915_suspend_saved_registers { 704 u8 saveLBB; 705 u32 saveDSPACNTR; 706 u32 saveDSPBCNTR; 707 u32 saveDSPARB; 708 u32 savePIPEACONF; 709 u32 savePIPEBCONF; 710 u32 savePIPEASRC; 711 u32 savePIPEBSRC; 712 u32 saveFPA0; 713 u32 saveFPA1; 714 u32 saveDPLL_A; 715 u32 saveDPLL_A_MD; 716 u32 saveHTOTAL_A; 717 u32 saveHBLANK_A; 718 u32 saveHSYNC_A; 719 u32 saveVTOTAL_A; 720 u32 saveVBLANK_A; 721 u32 saveVSYNC_A; 722 u32 saveBCLRPAT_A; 723 u32 saveTRANSACONF; 724 u32 saveTRANS_HTOTAL_A; 725 u32 saveTRANS_HBLANK_A; 726 u32 saveTRANS_HSYNC_A; 727 u32 saveTRANS_VTOTAL_A; 728 u32 saveTRANS_VBLANK_A; 729 u32 saveTRANS_VSYNC_A; 730 u32 savePIPEASTAT; 731 u32 saveDSPASTRIDE; 732 u32 saveDSPASIZE; 733 u32 saveDSPAPOS; 734 u32 saveDSPAADDR; 735 u32 saveDSPASURF; 736 u32 saveDSPATILEOFF; 737 u32 savePFIT_PGM_RATIOS; 738 u32 saveBLC_HIST_CTL; 739 u32 saveBLC_PWM_CTL; 740 u32 saveBLC_PWM_CTL2; 741 u32 saveBLC_HIST_CTL_B; 742 u32 saveBLC_CPU_PWM_CTL; 743 u32 saveBLC_CPU_PWM_CTL2; 744 u32 saveFPB0; 745 u32 saveFPB1; 746 u32 saveDPLL_B; 747 u32 saveDPLL_B_MD; 748 u32 saveHTOTAL_B; 749 u32 saveHBLANK_B; 750 u32 saveHSYNC_B; 751 u32 saveVTOTAL_B; 752 u32 saveVBLANK_B; 753 u32 saveVSYNC_B; 754 u32 saveBCLRPAT_B; 755 u32 saveTRANSBCONF; 756 u32 saveTRANS_HTOTAL_B; 757 u32 saveTRANS_HBLANK_B; 758 u32 saveTRANS_HSYNC_B; 759 u32 saveTRANS_VTOTAL_B; 760 u32 saveTRANS_VBLANK_B; 761 u32 saveTRANS_VSYNC_B; 762 u32 savePIPEBSTAT; 763 u32 saveDSPBSTRIDE; 764 u32 saveDSPBSIZE; 765 u32 saveDSPBPOS; 766 u32 saveDSPBADDR; 767 u32 saveDSPBSURF; 768 u32 saveDSPBTILEOFF; 769 u32 saveVGA0; 770 u32 saveVGA1; 771 u32 saveVGA_PD; 772 u32 saveVGACNTRL; 773 u32 saveADPA; 774 u32 saveLVDS; 775 u32 savePP_ON_DELAYS; 776 u32 savePP_OFF_DELAYS; 777 u32 saveDVOA; 778 u32 saveDVOB; 779 u32 saveDVOC; 780 u32 savePP_ON; 781 u32 savePP_OFF; 782 u32 savePP_CONTROL; 783 u32 savePP_DIVISOR; 784 u32 savePFIT_CONTROL; 785 u32 save_palette_a[256]; 786 u32 save_palette_b[256]; 787 u32 saveFBC_CONTROL; 788 u32 saveIER; 789 u32 saveIIR; 790 u32 saveIMR; 791 u32 saveDEIER; 792 u32 saveDEIMR; 793 u32 saveGTIER; 794 u32 saveGTIMR; 795 u32 saveFDI_RXA_IMR; 796 u32 saveFDI_RXB_IMR; 797 u32 saveCACHE_MODE_0; 798 u32 saveMI_ARB_STATE; 799 u32 saveSWF0[16]; 800 u32 saveSWF1[16]; 801 u32 saveSWF2[3]; 802 u8 saveMSR; 803 u8 saveSR[8]; 804 u8 saveGR[25]; 805 u8 saveAR_INDEX; 806 u8 saveAR[21]; 807 u8 saveDACMASK; 808 u8 saveCR[37]; 809 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 810 u32 saveCURACNTR; 811 u32 saveCURAPOS; 812 u32 saveCURABASE; 813 u32 saveCURBCNTR; 814 u32 saveCURBPOS; 815 u32 saveCURBBASE; 816 u32 saveCURSIZE; 817 u32 saveDP_B; 818 u32 saveDP_C; 819 u32 saveDP_D; 820 u32 savePIPEA_GMCH_DATA_M; 821 u32 savePIPEB_GMCH_DATA_M; 822 u32 savePIPEA_GMCH_DATA_N; 823 u32 savePIPEB_GMCH_DATA_N; 824 u32 savePIPEA_DP_LINK_M; 825 u32 savePIPEB_DP_LINK_M; 826 u32 savePIPEA_DP_LINK_N; 827 u32 savePIPEB_DP_LINK_N; 828 u32 saveFDI_RXA_CTL; 829 u32 saveFDI_TXA_CTL; 830 u32 saveFDI_RXB_CTL; 831 u32 saveFDI_TXB_CTL; 832 u32 savePFA_CTL_1; 833 u32 savePFB_CTL_1; 834 u32 savePFA_WIN_SZ; 835 u32 savePFB_WIN_SZ; 836 u32 savePFA_WIN_POS; 837 u32 savePFB_WIN_POS; 838 u32 savePCH_DREF_CONTROL; 839 u32 saveDISP_ARB_CTL; 840 u32 savePIPEA_DATA_M1; 841 u32 savePIPEA_DATA_N1; 842 u32 savePIPEA_LINK_M1; 843 u32 savePIPEA_LINK_N1; 844 u32 savePIPEB_DATA_M1; 845 u32 savePIPEB_DATA_N1; 846 u32 savePIPEB_LINK_M1; 847 u32 savePIPEB_LINK_N1; 848 u32 saveMCHBAR_RENDER_STANDBY; 849 u32 savePCH_PORT_HOTPLUG; 850 }; 851 852 struct vlv_s0ix_state { 853 /* GAM */ 854 u32 wr_watermark; 855 u32 gfx_prio_ctrl; 856 u32 arb_mode; 857 u32 gfx_pend_tlb0; 858 u32 gfx_pend_tlb1; 859 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 860 u32 media_max_req_count; 861 u32 gfx_max_req_count; 862 u32 render_hwsp; 863 u32 ecochk; 864 u32 bsd_hwsp; 865 u32 blt_hwsp; 866 u32 tlb_rd_addr; 867 868 /* MBC */ 869 u32 g3dctl; 870 u32 gsckgctl; 871 u32 mbctl; 872 873 /* GCP */ 874 u32 ucgctl1; 875 u32 ucgctl3; 876 u32 rcgctl1; 877 u32 rcgctl2; 878 u32 rstctl; 879 u32 misccpctl; 880 881 /* GPM */ 882 u32 gfxpause; 883 u32 rpdeuhwtc; 884 u32 rpdeuc; 885 u32 ecobus; 886 u32 pwrdwnupctl; 887 u32 rp_down_timeout; 888 u32 rp_deucsw; 889 u32 rcubmabdtmr; 890 u32 rcedata; 891 u32 spare2gh; 892 893 /* Display 1 CZ domain */ 894 u32 gt_imr; 895 u32 gt_ier; 896 u32 pm_imr; 897 u32 pm_ier; 898 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 899 900 /* GT SA CZ domain */ 901 u32 tilectl; 902 u32 gt_fifoctl; 903 u32 gtlc_wake_ctrl; 904 u32 gtlc_survive; 905 u32 pmwgicz; 906 907 /* Display 2 CZ domain */ 908 u32 gu_ctl0; 909 u32 gu_ctl1; 910 u32 clock_gate_dis2; 911 }; 912 913 struct intel_rps_ei { 914 u32 cz_clock; 915 u32 render_c0; 916 u32 media_c0; 917 }; 918 919 struct intel_gen6_power_mgmt { 920 /* work and pm_iir are protected by dev_priv->irq_lock */ 921 struct work_struct work; 922 u32 pm_iir; 923 924 /* Frequencies are stored in potentially platform dependent multiples. 925 * In other words, *_freq needs to be multiplied by X to be interesting. 926 * Soft limits are those which are used for the dynamic reclocking done 927 * by the driver (raise frequencies under heavy loads, and lower for 928 * lighter loads). Hard limits are those imposed by the hardware. 929 * 930 * A distinction is made for overclocking, which is never enabled by 931 * default, and is considered to be above the hard limit if it's 932 * possible at all. 933 */ 934 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 935 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 936 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 937 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 938 u8 min_freq; /* AKA RPn. Minimum frequency */ 939 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 940 u8 rp1_freq; /* "less than" RP0 power/freqency */ 941 u8 rp0_freq; /* Non-overclocked max frequency. */ 942 u32 cz_freq; 943 944 u32 ei_interrupt_count; 945 946 int last_adj; 947 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 948 949 bool enabled; 950 struct delayed_work delayed_resume_work; 951 952 /* manual wa residency calculations */ 953 struct intel_rps_ei up_ei, down_ei; 954 955 /* 956 * Protects RPS/RC6 register access and PCU communication. 957 * Must be taken after struct_mutex if nested. 958 */ 959 struct mutex hw_lock; 960 }; 961 962 /* defined intel_pm.c */ 963 extern spinlock_t mchdev_lock; 964 965 struct intel_ilk_power_mgmt { 966 u8 cur_delay; 967 u8 min_delay; 968 u8 max_delay; 969 u8 fmax; 970 u8 fstart; 971 972 u64 last_count1; 973 unsigned long last_time1; 974 unsigned long chipset_power; 975 u64 last_count2; 976 u64 last_time2; 977 unsigned long gfx_power; 978 u8 corr; 979 980 int c_m; 981 int r_t; 982 983 struct drm_i915_gem_object *pwrctx; 984 struct drm_i915_gem_object *renderctx; 985 }; 986 987 struct drm_i915_private; 988 struct i915_power_well; 989 990 struct i915_power_well_ops { 991 /* 992 * Synchronize the well's hw state to match the current sw state, for 993 * example enable/disable it based on the current refcount. Called 994 * during driver init and resume time, possibly after first calling 995 * the enable/disable handlers. 996 */ 997 void (*sync_hw)(struct drm_i915_private *dev_priv, 998 struct i915_power_well *power_well); 999 /* 1000 * Enable the well and resources that depend on it (for example 1001 * interrupts located on the well). Called after the 0->1 refcount 1002 * transition. 1003 */ 1004 void (*enable)(struct drm_i915_private *dev_priv, 1005 struct i915_power_well *power_well); 1006 /* 1007 * Disable the well and resources that depend on it. Called after 1008 * the 1->0 refcount transition. 1009 */ 1010 void (*disable)(struct drm_i915_private *dev_priv, 1011 struct i915_power_well *power_well); 1012 /* Returns the hw enabled state. */ 1013 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1014 struct i915_power_well *power_well); 1015 }; 1016 1017 /* Power well structure for haswell */ 1018 struct i915_power_well { 1019 const char *name; 1020 bool always_on; 1021 /* power well enable/disable usage count */ 1022 int count; 1023 /* cached hw enabled state */ 1024 bool hw_enabled; 1025 unsigned long domains; 1026 unsigned long data; 1027 const struct i915_power_well_ops *ops; 1028 }; 1029 1030 struct i915_power_domains { 1031 /* 1032 * Power wells needed for initialization at driver init and suspend 1033 * time are on. They are kept on until after the first modeset. 1034 */ 1035 bool init_power_on; 1036 bool initializing; 1037 int power_well_count; 1038 1039 struct mutex lock; 1040 int domain_use_count[POWER_DOMAIN_NUM]; 1041 struct i915_power_well *power_wells; 1042 }; 1043 1044 struct i915_dri1_state { 1045 unsigned allow_batchbuffer : 1; 1046 u32 __iomem *gfx_hws_cpu_addr; 1047 1048 unsigned int cpp; 1049 int back_offset; 1050 int front_offset; 1051 int current_page; 1052 int page_flipping; 1053 1054 uint32_t counter; 1055 }; 1056 1057 struct i915_ums_state { 1058 /** 1059 * Flag if the X Server, and thus DRM, is not currently in 1060 * control of the device. 1061 * 1062 * This is set between LeaveVT and EnterVT. It needs to be 1063 * replaced with a semaphore. It also needs to be 1064 * transitioned away from for kernel modesetting. 1065 */ 1066 int mm_suspended; 1067 }; 1068 1069 #define MAX_L3_SLICES 2 1070 struct intel_l3_parity { 1071 u32 *remap_info[MAX_L3_SLICES]; 1072 struct work_struct error_work; 1073 int which_slice; 1074 }; 1075 1076 struct i915_gem_mm { 1077 /** Memory allocator for GTT stolen memory */ 1078 struct drm_mm stolen; 1079 /** List of all objects in gtt_space. Used to restore gtt 1080 * mappings on resume */ 1081 struct list_head bound_list; 1082 /** 1083 * List of objects which are not bound to the GTT (thus 1084 * are idle and not used by the GPU) but still have 1085 * (presumably uncached) pages still attached. 1086 */ 1087 struct list_head unbound_list; 1088 1089 /** Usable portion of the GTT for GEM */ 1090 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1091 1092 /** PPGTT used for aliasing the PPGTT with the GTT */ 1093 struct i915_hw_ppgtt *aliasing_ppgtt; 1094 1095 struct notifier_block oom_notifier; 1096 struct shrinker shrinker; 1097 bool shrinker_no_lock_stealing; 1098 1099 /** LRU list of objects with fence regs on them. */ 1100 struct list_head fence_list; 1101 1102 /** 1103 * We leave the user IRQ off as much as possible, 1104 * but this means that requests will finish and never 1105 * be retired once the system goes idle. Set a timer to 1106 * fire periodically while the ring is running. When it 1107 * fires, go retire requests. 1108 */ 1109 struct delayed_work retire_work; 1110 1111 /** 1112 * When we detect an idle GPU, we want to turn on 1113 * powersaving features. So once we see that there 1114 * are no more requests outstanding and no more 1115 * arrive within a small period of time, we fire 1116 * off the idle_work. 1117 */ 1118 struct delayed_work idle_work; 1119 1120 /** 1121 * Are we in a non-interruptible section of code like 1122 * modesetting? 1123 */ 1124 bool interruptible; 1125 1126 /** 1127 * Is the GPU currently considered idle, or busy executing userspace 1128 * requests? Whilst idle, we attempt to power down the hardware and 1129 * display clocks. In order to reduce the effect on performance, there 1130 * is a slight delay before we do so. 1131 */ 1132 bool busy; 1133 1134 /* the indicator for dispatch video commands on two BSD rings */ 1135 int bsd_ring_dispatch_index; 1136 1137 /** Bit 6 swizzling required for X tiling */ 1138 uint32_t bit_6_swizzle_x; 1139 /** Bit 6 swizzling required for Y tiling */ 1140 uint32_t bit_6_swizzle_y; 1141 1142 /* accounting, useful for userland debugging */ 1143 spinlock_t object_stat_lock; 1144 size_t object_memory; 1145 u32 object_count; 1146 }; 1147 1148 struct drm_i915_error_state_buf { 1149 unsigned bytes; 1150 unsigned size; 1151 int err; 1152 u8 *buf; 1153 loff_t start; 1154 loff_t pos; 1155 }; 1156 1157 struct i915_error_state_file_priv { 1158 struct drm_device *dev; 1159 struct drm_i915_error_state *error; 1160 }; 1161 1162 struct i915_gpu_error { 1163 /* For hangcheck timer */ 1164 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1165 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1166 /* Hang gpu twice in this window and your context gets banned */ 1167 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1168 1169 struct timer_list hangcheck_timer; 1170 1171 /* For reset and error_state handling. */ 1172 spinlock_t lock; 1173 /* Protected by the above dev->gpu_error.lock. */ 1174 struct drm_i915_error_state *first_error; 1175 struct work_struct work; 1176 1177 1178 unsigned long missed_irq_rings; 1179 1180 /** 1181 * State variable controlling the reset flow and count 1182 * 1183 * This is a counter which gets incremented when reset is triggered, 1184 * and again when reset has been handled. So odd values (lowest bit set) 1185 * means that reset is in progress and even values that 1186 * (reset_counter >> 1):th reset was successfully completed. 1187 * 1188 * If reset is not completed succesfully, the I915_WEDGE bit is 1189 * set meaning that hardware is terminally sour and there is no 1190 * recovery. All waiters on the reset_queue will be woken when 1191 * that happens. 1192 * 1193 * This counter is used by the wait_seqno code to notice that reset 1194 * event happened and it needs to restart the entire ioctl (since most 1195 * likely the seqno it waited for won't ever signal anytime soon). 1196 * 1197 * This is important for lock-free wait paths, where no contended lock 1198 * naturally enforces the correct ordering between the bail-out of the 1199 * waiter and the gpu reset work code. 1200 */ 1201 atomic_t reset_counter; 1202 1203 #define I915_RESET_IN_PROGRESS_FLAG 1 1204 #define I915_WEDGED (1 << 31) 1205 1206 /** 1207 * Waitqueue to signal when the reset has completed. Used by clients 1208 * that wait for dev_priv->mm.wedged to settle. 1209 */ 1210 wait_queue_head_t reset_queue; 1211 1212 /* Userspace knobs for gpu hang simulation; 1213 * combines both a ring mask, and extra flags 1214 */ 1215 u32 stop_rings; 1216 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1217 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1218 1219 /* For missed irq/seqno simulation. */ 1220 unsigned int test_irq_rings; 1221 }; 1222 1223 enum modeset_restore { 1224 MODESET_ON_LID_OPEN, 1225 MODESET_DONE, 1226 MODESET_SUSPENDED, 1227 }; 1228 1229 struct ddi_vbt_port_info { 1230 uint8_t hdmi_level_shift; 1231 1232 uint8_t supports_dvi:1; 1233 uint8_t supports_hdmi:1; 1234 uint8_t supports_dp:1; 1235 }; 1236 1237 enum drrs_support_type { 1238 DRRS_NOT_SUPPORTED = 0, 1239 STATIC_DRRS_SUPPORT = 1, 1240 SEAMLESS_DRRS_SUPPORT = 2 1241 }; 1242 1243 struct intel_vbt_data { 1244 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1245 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1246 1247 /* Feature bits */ 1248 unsigned int int_tv_support:1; 1249 unsigned int lvds_dither:1; 1250 unsigned int lvds_vbt:1; 1251 unsigned int int_crt_support:1; 1252 unsigned int lvds_use_ssc:1; 1253 unsigned int display_clock_mode:1; 1254 unsigned int fdi_rx_polarity_inverted:1; 1255 unsigned int has_mipi:1; 1256 int lvds_ssc_freq; 1257 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1258 1259 enum drrs_support_type drrs_type; 1260 1261 /* eDP */ 1262 int edp_rate; 1263 int edp_lanes; 1264 int edp_preemphasis; 1265 int edp_vswing; 1266 bool edp_initialized; 1267 bool edp_support; 1268 int edp_bpp; 1269 struct edp_power_seq edp_pps; 1270 1271 struct { 1272 u16 pwm_freq_hz; 1273 bool present; 1274 bool active_low_pwm; 1275 u8 min_brightness; /* min_brightness/255 of max */ 1276 } backlight; 1277 1278 /* MIPI DSI */ 1279 struct { 1280 u16 port; 1281 u16 panel_id; 1282 struct mipi_config *config; 1283 struct mipi_pps_data *pps; 1284 u8 seq_version; 1285 u32 size; 1286 u8 *data; 1287 u8 *sequence[MIPI_SEQ_MAX]; 1288 } dsi; 1289 1290 int crt_ddc_pin; 1291 1292 int child_dev_num; 1293 union child_device_config *child_dev; 1294 1295 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1296 }; 1297 1298 enum intel_ddb_partitioning { 1299 INTEL_DDB_PART_1_2, 1300 INTEL_DDB_PART_5_6, /* IVB+ */ 1301 }; 1302 1303 struct intel_wm_level { 1304 bool enable; 1305 uint32_t pri_val; 1306 uint32_t spr_val; 1307 uint32_t cur_val; 1308 uint32_t fbc_val; 1309 }; 1310 1311 struct ilk_wm_values { 1312 uint32_t wm_pipe[3]; 1313 uint32_t wm_lp[3]; 1314 uint32_t wm_lp_spr[3]; 1315 uint32_t wm_linetime[3]; 1316 bool enable_fbc_wm; 1317 enum intel_ddb_partitioning partitioning; 1318 }; 1319 1320 /* 1321 * This struct helps tracking the state needed for runtime PM, which puts the 1322 * device in PCI D3 state. Notice that when this happens, nothing on the 1323 * graphics device works, even register access, so we don't get interrupts nor 1324 * anything else. 1325 * 1326 * Every piece of our code that needs to actually touch the hardware needs to 1327 * either call intel_runtime_pm_get or call intel_display_power_get with the 1328 * appropriate power domain. 1329 * 1330 * Our driver uses the autosuspend delay feature, which means we'll only really 1331 * suspend if we stay with zero refcount for a certain amount of time. The 1332 * default value is currently very conservative (see intel_init_runtime_pm), but 1333 * it can be changed with the standard runtime PM files from sysfs. 1334 * 1335 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1336 * goes back to false exactly before we reenable the IRQs. We use this variable 1337 * to check if someone is trying to enable/disable IRQs while they're supposed 1338 * to be disabled. This shouldn't happen and we'll print some error messages in 1339 * case it happens. 1340 * 1341 * For more, read the Documentation/power/runtime_pm.txt. 1342 */ 1343 struct i915_runtime_pm { 1344 bool suspended; 1345 bool _irqs_disabled; 1346 }; 1347 1348 enum intel_pipe_crc_source { 1349 INTEL_PIPE_CRC_SOURCE_NONE, 1350 INTEL_PIPE_CRC_SOURCE_PLANE1, 1351 INTEL_PIPE_CRC_SOURCE_PLANE2, 1352 INTEL_PIPE_CRC_SOURCE_PF, 1353 INTEL_PIPE_CRC_SOURCE_PIPE, 1354 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1355 INTEL_PIPE_CRC_SOURCE_TV, 1356 INTEL_PIPE_CRC_SOURCE_DP_B, 1357 INTEL_PIPE_CRC_SOURCE_DP_C, 1358 INTEL_PIPE_CRC_SOURCE_DP_D, 1359 INTEL_PIPE_CRC_SOURCE_AUTO, 1360 INTEL_PIPE_CRC_SOURCE_MAX, 1361 }; 1362 1363 struct intel_pipe_crc_entry { 1364 uint32_t frame; 1365 uint32_t crc[5]; 1366 }; 1367 1368 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1369 struct intel_pipe_crc { 1370 spinlock_t lock; 1371 bool opened; /* exclusive access to the result file */ 1372 struct intel_pipe_crc_entry *entries; 1373 enum intel_pipe_crc_source source; 1374 int head, tail; 1375 wait_queue_head_t wq; 1376 }; 1377 1378 struct i915_frontbuffer_tracking { 1379 struct mutex lock; 1380 1381 /* 1382 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1383 * scheduled flips. 1384 */ 1385 unsigned busy_bits; 1386 unsigned flip_bits; 1387 }; 1388 1389 struct drm_i915_private { 1390 struct drm_device *dev; 1391 struct kmem_cache *slab; 1392 1393 const struct intel_device_info info; 1394 1395 int relative_constants_mode; 1396 1397 void __iomem *regs; 1398 1399 struct intel_uncore uncore; 1400 1401 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1402 1403 1404 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1405 * controller on different i2c buses. */ 1406 struct mutex gmbus_mutex; 1407 1408 /** 1409 * Base address of the gmbus and gpio block. 1410 */ 1411 uint32_t gpio_mmio_base; 1412 1413 /* MMIO base address for MIPI regs */ 1414 uint32_t mipi_mmio_base; 1415 1416 wait_queue_head_t gmbus_wait_queue; 1417 1418 struct pci_dev *bridge_dev; 1419 struct intel_engine_cs ring[I915_NUM_RINGS]; 1420 struct drm_i915_gem_object *semaphore_obj; 1421 uint32_t last_seqno, next_seqno; 1422 1423 drm_dma_handle_t *status_page_dmah; 1424 struct resource mch_res; 1425 1426 /* protects the irq masks */ 1427 spinlock_t irq_lock; 1428 1429 /* protects the mmio flip data */ 1430 spinlock_t mmio_flip_lock; 1431 1432 bool display_irqs_enabled; 1433 1434 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1435 struct pm_qos_request pm_qos; 1436 1437 /* DPIO indirect register protection */ 1438 struct mutex dpio_lock; 1439 1440 /** Cached value of IMR to avoid reads in updating the bitfield */ 1441 union { 1442 u32 irq_mask; 1443 u32 de_irq_mask[I915_MAX_PIPES]; 1444 }; 1445 u32 gt_irq_mask; 1446 u32 pm_irq_mask; 1447 u32 pm_rps_events; 1448 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1449 1450 struct work_struct hotplug_work; 1451 struct { 1452 unsigned long hpd_last_jiffies; 1453 int hpd_cnt; 1454 enum { 1455 HPD_ENABLED = 0, 1456 HPD_DISABLED = 1, 1457 HPD_MARK_DISABLED = 2 1458 } hpd_mark; 1459 } hpd_stats[HPD_NUM_PINS]; 1460 u32 hpd_event_bits; 1461 struct delayed_work hotplug_reenable_work; 1462 1463 struct i915_fbc fbc; 1464 struct i915_drrs drrs; 1465 struct intel_opregion opregion; 1466 struct intel_vbt_data vbt; 1467 1468 /* overlay */ 1469 struct intel_overlay *overlay; 1470 1471 /* backlight registers and fields in struct intel_panel */ 1472 spinlock_t backlight_lock; 1473 1474 /* LVDS info */ 1475 bool no_aux_handshake; 1476 1477 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1478 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1479 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1480 1481 unsigned int fsb_freq, mem_freq, is_ddr3; 1482 unsigned int vlv_cdclk_freq; 1483 1484 /** 1485 * wq - Driver workqueue for GEM. 1486 * 1487 * NOTE: Work items scheduled here are not allowed to grab any modeset 1488 * locks, for otherwise the flushing done in the pageflip code will 1489 * result in deadlocks. 1490 */ 1491 struct workqueue_struct *wq; 1492 1493 /* Display functions */ 1494 struct drm_i915_display_funcs display; 1495 1496 /* PCH chipset type */ 1497 enum intel_pch pch_type; 1498 unsigned short pch_id; 1499 1500 unsigned long quirks; 1501 1502 enum modeset_restore modeset_restore; 1503 struct mutex modeset_restore_lock; 1504 1505 struct list_head vm_list; /* Global list of all address spaces */ 1506 struct i915_gtt gtt; /* VM representing the global address space */ 1507 1508 struct i915_gem_mm mm; 1509 #if defined(CONFIG_MMU_NOTIFIER) 1510 DECLARE_HASHTABLE(mmu_notifiers, 7); 1511 #endif 1512 1513 /* Kernel Modesetting */ 1514 1515 struct sdvo_device_mapping sdvo_mappings[2]; 1516 1517 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1518 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1519 wait_queue_head_t pending_flip_queue; 1520 1521 #ifdef CONFIG_DEBUG_FS 1522 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1523 #endif 1524 1525 int num_shared_dpll; 1526 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1527 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1528 1529 /* Reclocking support */ 1530 bool render_reclock_avail; 1531 bool lvds_downclock_avail; 1532 /* indicates the reduced downclock for LVDS*/ 1533 int lvds_downclock; 1534 1535 struct i915_frontbuffer_tracking fb_tracking; 1536 1537 u16 orig_clock; 1538 1539 bool mchbar_need_disable; 1540 1541 struct intel_l3_parity l3_parity; 1542 1543 /* Cannot be determined by PCIID. You must always read a register. */ 1544 size_t ellc_size; 1545 1546 /* gen6+ rps state */ 1547 struct intel_gen6_power_mgmt rps; 1548 1549 /* ilk-only ips/rps state. Everything in here is protected by the global 1550 * mchdev_lock in intel_pm.c */ 1551 struct intel_ilk_power_mgmt ips; 1552 1553 struct i915_power_domains power_domains; 1554 1555 struct i915_psr psr; 1556 1557 struct i915_gpu_error gpu_error; 1558 1559 struct drm_i915_gem_object *vlv_pctx; 1560 1561 #ifdef CONFIG_DRM_I915_FBDEV 1562 /* list of fbdev register on this device */ 1563 struct intel_fbdev *fbdev; 1564 #endif 1565 1566 /* 1567 * The console may be contended at resume, but we don't 1568 * want it to block on it. 1569 */ 1570 struct work_struct console_resume_work; 1571 1572 struct drm_property *broadcast_rgb_property; 1573 struct drm_property *force_audio_property; 1574 1575 uint32_t hw_context_size; 1576 struct list_head context_list; 1577 1578 u32 fdi_rx_config; 1579 1580 u32 suspend_count; 1581 struct i915_suspend_saved_registers regfile; 1582 struct vlv_s0ix_state vlv_s0ix_state; 1583 1584 struct { 1585 /* 1586 * Raw watermark latency values: 1587 * in 0.1us units for WM0, 1588 * in 0.5us units for WM1+. 1589 */ 1590 /* primary */ 1591 uint16_t pri_latency[5]; 1592 /* sprite */ 1593 uint16_t spr_latency[5]; 1594 /* cursor */ 1595 uint16_t cur_latency[5]; 1596 1597 /* current hardware state */ 1598 struct ilk_wm_values hw; 1599 } wm; 1600 1601 struct i915_runtime_pm pm; 1602 1603 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1604 u32 long_hpd_port_mask; 1605 u32 short_hpd_port_mask; 1606 struct work_struct dig_port_work; 1607 1608 /* 1609 * if we get a HPD irq from DP and a HPD irq from non-DP 1610 * the non-DP HPD could block the workqueue on a mode config 1611 * mutex getting, that userspace may have taken. However 1612 * userspace is waiting on the DP workqueue to run which is 1613 * blocked behind the non-DP one. 1614 */ 1615 struct workqueue_struct *dp_wq; 1616 1617 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1618 * here! */ 1619 struct i915_dri1_state dri1; 1620 /* Old ums support infrastructure, same warning applies. */ 1621 struct i915_ums_state ums; 1622 1623 /* 1624 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1625 * will be rejected. Instead look for a better place. 1626 */ 1627 }; 1628 1629 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1630 { 1631 return dev->dev_private; 1632 } 1633 1634 /* Iterate over initialised rings */ 1635 #define for_each_ring(ring__, dev_priv__, i__) \ 1636 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1637 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1638 1639 enum hdmi_force_audio { 1640 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1641 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1642 HDMI_AUDIO_AUTO, /* trust EDID */ 1643 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1644 }; 1645 1646 #define I915_GTT_OFFSET_NONE ((u32)-1) 1647 1648 struct drm_i915_gem_object_ops { 1649 /* Interface between the GEM object and its backing storage. 1650 * get_pages() is called once prior to the use of the associated set 1651 * of pages before to binding them into the GTT, and put_pages() is 1652 * called after we no longer need them. As we expect there to be 1653 * associated cost with migrating pages between the backing storage 1654 * and making them available for the GPU (e.g. clflush), we may hold 1655 * onto the pages after they are no longer referenced by the GPU 1656 * in case they may be used again shortly (for example migrating the 1657 * pages to a different memory domain within the GTT). put_pages() 1658 * will therefore most likely be called when the object itself is 1659 * being released or under memory pressure (where we attempt to 1660 * reap pages for the shrinker). 1661 */ 1662 int (*get_pages)(struct drm_i915_gem_object *); 1663 void (*put_pages)(struct drm_i915_gem_object *); 1664 int (*dmabuf_export)(struct drm_i915_gem_object *); 1665 void (*release)(struct drm_i915_gem_object *); 1666 }; 1667 1668 /* 1669 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1670 * considered to be the frontbuffer for the given plane interface-vise. This 1671 * doesn't mean that the hw necessarily already scans it out, but that any 1672 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1673 * 1674 * We have one bit per pipe and per scanout plane type. 1675 */ 1676 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1677 #define INTEL_FRONTBUFFER_BITS \ 1678 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1679 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1680 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1681 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1682 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1683 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1684 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1685 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1686 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1687 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1688 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1689 1690 struct drm_i915_gem_object { 1691 struct drm_gem_object base; 1692 1693 const struct drm_i915_gem_object_ops *ops; 1694 1695 /** List of VMAs backed by this object */ 1696 struct list_head vma_list; 1697 1698 /** Stolen memory for this object, instead of being backed by shmem. */ 1699 struct drm_mm_node *stolen; 1700 struct list_head global_list; 1701 1702 struct list_head ring_list; 1703 /** Used in execbuf to temporarily hold a ref */ 1704 struct list_head obj_exec_link; 1705 1706 /** 1707 * This is set if the object is on the active lists (has pending 1708 * rendering and so a non-zero seqno), and is not set if it i s on 1709 * inactive (ready to be unbound) list. 1710 */ 1711 unsigned int active:1; 1712 1713 /** 1714 * This is set if the object has been written to since last bound 1715 * to the GTT 1716 */ 1717 unsigned int dirty:1; 1718 1719 /** 1720 * Fence register bits (if any) for this object. Will be set 1721 * as needed when mapped into the GTT. 1722 * Protected by dev->struct_mutex. 1723 */ 1724 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1725 1726 /** 1727 * Advice: are the backing pages purgeable? 1728 */ 1729 unsigned int madv:2; 1730 1731 /** 1732 * Current tiling mode for the object. 1733 */ 1734 unsigned int tiling_mode:2; 1735 /** 1736 * Whether the tiling parameters for the currently associated fence 1737 * register have changed. Note that for the purposes of tracking 1738 * tiling changes we also treat the unfenced register, the register 1739 * slot that the object occupies whilst it executes a fenced 1740 * command (such as BLT on gen2/3), as a "fence". 1741 */ 1742 unsigned int fence_dirty:1; 1743 1744 /** 1745 * Is the object at the current location in the gtt mappable and 1746 * fenceable? Used to avoid costly recalculations. 1747 */ 1748 unsigned int map_and_fenceable:1; 1749 1750 /** 1751 * Whether the current gtt mapping needs to be mappable (and isn't just 1752 * mappable by accident). Track pin and fault separate for a more 1753 * accurate mappable working set. 1754 */ 1755 unsigned int fault_mappable:1; 1756 unsigned int pin_mappable:1; 1757 unsigned int pin_display:1; 1758 1759 /* 1760 * Is the object to be mapped as read-only to the GPU 1761 * Only honoured if hardware has relevant pte bit 1762 */ 1763 unsigned long gt_ro:1; 1764 1765 /* 1766 * Is the GPU currently using a fence to access this buffer, 1767 */ 1768 unsigned int pending_fenced_gpu_access:1; 1769 unsigned int fenced_gpu_access:1; 1770 1771 unsigned int cache_level:3; 1772 1773 unsigned int has_aliasing_ppgtt_mapping:1; 1774 unsigned int has_global_gtt_mapping:1; 1775 unsigned int has_dma_mapping:1; 1776 1777 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 1778 1779 struct sg_table *pages; 1780 int pages_pin_count; 1781 1782 /* prime dma-buf support */ 1783 void *dma_buf_vmapping; 1784 int vmapping_count; 1785 1786 struct intel_engine_cs *ring; 1787 1788 /** Breadcrumb of last rendering to the buffer. */ 1789 uint32_t last_read_seqno; 1790 uint32_t last_write_seqno; 1791 /** Breadcrumb of last fenced GPU access to the buffer. */ 1792 uint32_t last_fenced_seqno; 1793 1794 /** Current tiling stride for the object, if it's tiled. */ 1795 uint32_t stride; 1796 1797 /** References from framebuffers, locks out tiling changes. */ 1798 unsigned long framebuffer_references; 1799 1800 /** Record of address bit 17 of each page at last unbind. */ 1801 unsigned long *bit_17; 1802 1803 /** User space pin count and filp owning the pin */ 1804 unsigned long user_pin_count; 1805 struct drm_file *pin_filp; 1806 1807 /** for phy allocated objects */ 1808 drm_dma_handle_t *phys_handle; 1809 1810 union { 1811 struct i915_gem_userptr { 1812 uintptr_t ptr; 1813 unsigned read_only :1; 1814 unsigned workers :4; 1815 #define I915_GEM_USERPTR_MAX_WORKERS 15 1816 1817 struct mm_struct *mm; 1818 struct i915_mmu_object *mn; 1819 struct work_struct *work; 1820 } userptr; 1821 }; 1822 }; 1823 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1824 1825 void i915_gem_track_fb(struct drm_i915_gem_object *old, 1826 struct drm_i915_gem_object *new, 1827 unsigned frontbuffer_bits); 1828 1829 /** 1830 * Request queue structure. 1831 * 1832 * The request queue allows us to note sequence numbers that have been emitted 1833 * and may be associated with active buffers to be retired. 1834 * 1835 * By keeping this list, we can avoid having to do questionable 1836 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1837 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1838 */ 1839 struct drm_i915_gem_request { 1840 /** On Which ring this request was generated */ 1841 struct intel_engine_cs *ring; 1842 1843 /** GEM sequence number associated with this request. */ 1844 uint32_t seqno; 1845 1846 /** Position in the ringbuffer of the start of the request */ 1847 u32 head; 1848 1849 /** Position in the ringbuffer of the end of the request */ 1850 u32 tail; 1851 1852 /** Context related to this request */ 1853 struct intel_context *ctx; 1854 1855 /** Batch buffer related to this request if any */ 1856 struct drm_i915_gem_object *batch_obj; 1857 1858 /** Time at which this request was emitted, in jiffies. */ 1859 unsigned long emitted_jiffies; 1860 1861 /** global list entry for this request */ 1862 struct list_head list; 1863 1864 struct drm_i915_file_private *file_priv; 1865 /** file_priv list entry for this request */ 1866 struct list_head client_list; 1867 }; 1868 1869 struct drm_i915_file_private { 1870 struct drm_i915_private *dev_priv; 1871 struct drm_file *file; 1872 1873 struct { 1874 spinlock_t lock; 1875 struct list_head request_list; 1876 struct delayed_work idle_work; 1877 } mm; 1878 struct idr context_idr; 1879 1880 atomic_t rps_wait_boost; 1881 struct intel_engine_cs *bsd_ring; 1882 }; 1883 1884 /* 1885 * A command that requires special handling by the command parser. 1886 */ 1887 struct drm_i915_cmd_descriptor { 1888 /* 1889 * Flags describing how the command parser processes the command. 1890 * 1891 * CMD_DESC_FIXED: The command has a fixed length if this is set, 1892 * a length mask if not set 1893 * CMD_DESC_SKIP: The command is allowed but does not follow the 1894 * standard length encoding for the opcode range in 1895 * which it falls 1896 * CMD_DESC_REJECT: The command is never allowed 1897 * CMD_DESC_REGISTER: The command should be checked against the 1898 * register whitelist for the appropriate ring 1899 * CMD_DESC_MASTER: The command is allowed if the submitting process 1900 * is the DRM master 1901 */ 1902 u32 flags; 1903 #define CMD_DESC_FIXED (1<<0) 1904 #define CMD_DESC_SKIP (1<<1) 1905 #define CMD_DESC_REJECT (1<<2) 1906 #define CMD_DESC_REGISTER (1<<3) 1907 #define CMD_DESC_BITMASK (1<<4) 1908 #define CMD_DESC_MASTER (1<<5) 1909 1910 /* 1911 * The command's unique identification bits and the bitmask to get them. 1912 * This isn't strictly the opcode field as defined in the spec and may 1913 * also include type, subtype, and/or subop fields. 1914 */ 1915 struct { 1916 u32 value; 1917 u32 mask; 1918 } cmd; 1919 1920 /* 1921 * The command's length. The command is either fixed length (i.e. does 1922 * not include a length field) or has a length field mask. The flag 1923 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 1924 * a length mask. All command entries in a command table must include 1925 * length information. 1926 */ 1927 union { 1928 u32 fixed; 1929 u32 mask; 1930 } length; 1931 1932 /* 1933 * Describes where to find a register address in the command to check 1934 * against the ring's register whitelist. Only valid if flags has the 1935 * CMD_DESC_REGISTER bit set. 1936 */ 1937 struct { 1938 u32 offset; 1939 u32 mask; 1940 } reg; 1941 1942 #define MAX_CMD_DESC_BITMASKS 3 1943 /* 1944 * Describes command checks where a particular dword is masked and 1945 * compared against an expected value. If the command does not match 1946 * the expected value, the parser rejects it. Only valid if flags has 1947 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 1948 * are valid. 1949 * 1950 * If the check specifies a non-zero condition_mask then the parser 1951 * only performs the check when the bits specified by condition_mask 1952 * are non-zero. 1953 */ 1954 struct { 1955 u32 offset; 1956 u32 mask; 1957 u32 expected; 1958 u32 condition_offset; 1959 u32 condition_mask; 1960 } bits[MAX_CMD_DESC_BITMASKS]; 1961 }; 1962 1963 /* 1964 * A table of commands requiring special handling by the command parser. 1965 * 1966 * Each ring has an array of tables. Each table consists of an array of command 1967 * descriptors, which must be sorted with command opcodes in ascending order. 1968 */ 1969 struct drm_i915_cmd_table { 1970 const struct drm_i915_cmd_descriptor *table; 1971 int count; 1972 }; 1973 1974 #define INTEL_INFO(dev) (&to_i915(dev)->info) 1975 1976 #define IS_I830(dev) ((dev)->pdev->device == 0x3577) 1977 #define IS_845G(dev) ((dev)->pdev->device == 0x2562) 1978 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1979 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) 1980 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1981 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) 1982 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) 1983 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1984 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1985 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1986 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) 1987 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1988 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) 1989 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) 1990 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1991 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1992 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) 1993 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1994 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ 1995 (dev)->pdev->device == 0x0152 || \ 1996 (dev)->pdev->device == 0x015a) 1997 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ 1998 (dev)->pdev->device == 0x0106 || \ 1999 (dev)->pdev->device == 0x010A) 2000 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2001 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2002 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2003 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2004 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2005 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2006 ((dev)->pdev->device & 0xFF00) == 0x0C00) 2007 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2008 (((dev)->pdev->device & 0xf) == 0x2 || \ 2009 ((dev)->pdev->device & 0xf) == 0x6 || \ 2010 ((dev)->pdev->device & 0xf) == 0xe)) 2011 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2012 ((dev)->pdev->device & 0xFF00) == 0x0A00) 2013 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 2014 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2015 ((dev)->pdev->device & 0x00F0) == 0x0020) 2016 /* ULX machines are also considered ULT. */ 2017 #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ 2018 (dev)->pdev->device == 0x0A1E) 2019 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2020 2021 /* 2022 * The genX designation typically refers to the render engine, so render 2023 * capability related checks should use IS_GEN, while display and other checks 2024 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2025 * chips, etc.). 2026 */ 2027 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2028 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2029 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2030 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2031 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2032 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2033 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2034 2035 #define RENDER_RING (1<<RCS) 2036 #define BSD_RING (1<<VCS) 2037 #define BLT_RING (1<<BCS) 2038 #define VEBOX_RING (1<<VECS) 2039 #define BSD2_RING (1<<VCS2) 2040 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2041 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2042 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2043 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2044 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2045 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2046 to_i915(dev)->ellc_size) 2047 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2048 2049 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2050 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) 2051 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) 2052 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) 2053 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) 2054 2055 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2056 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2057 2058 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2059 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2060 /* 2061 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2062 * even when in MSI mode. This results in spurious interrupt warnings if the 2063 * legacy irq no. is shared with another device. The kernel then disables that 2064 * interrupt source and so prevents the other device from working properly. 2065 */ 2066 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2067 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2068 2069 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2070 * rows, which changed the alignment requirements and fence programming. 2071 */ 2072 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2073 IS_I915GM(dev))) 2074 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2075 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2076 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2077 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2078 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2079 2080 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2081 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2082 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2083 2084 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 2085 2086 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2087 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2088 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2089 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2090 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2091 2092 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2093 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2094 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2095 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2096 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2097 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2098 2099 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 2100 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2101 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2102 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2103 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2104 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2105 2106 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2107 2108 /* DPF == dynamic parity feature */ 2109 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2110 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2111 2112 #define GT_FREQUENCY_MULTIPLIER 50 2113 2114 #include "i915_trace.h" 2115 2116 extern const struct drm_ioctl_desc i915_ioctls[]; 2117 extern int i915_max_ioctl; 2118 2119 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 2120 extern int i915_resume(struct drm_device *dev); 2121 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2122 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2123 2124 /* i915_params.c */ 2125 struct i915_params { 2126 int modeset; 2127 int panel_ignore_lid; 2128 unsigned int powersave; 2129 int semaphores; 2130 unsigned int lvds_downclock; 2131 int lvds_channel_mode; 2132 int panel_use_ssc; 2133 int vbt_sdvo_panel_type; 2134 int enable_rc6; 2135 int enable_fbc; 2136 int enable_ppgtt; 2137 int enable_psr; 2138 unsigned int preliminary_hw_support; 2139 int disable_power_well; 2140 int enable_ips; 2141 int invert_brightness; 2142 int enable_cmd_parser; 2143 /* leave bools at the end to not create holes */ 2144 bool enable_hangcheck; 2145 bool fastboot; 2146 bool prefault_disable; 2147 bool reset; 2148 bool disable_display; 2149 bool disable_vtd_wa; 2150 int use_mmio_flip; 2151 bool mmio_debug; 2152 }; 2153 extern struct i915_params i915 __read_mostly; 2154 2155 /* i915_dma.c */ 2156 void i915_update_dri1_breadcrumb(struct drm_device *dev); 2157 extern void i915_kernel_lost_context(struct drm_device * dev); 2158 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2159 extern int i915_driver_unload(struct drm_device *); 2160 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2161 extern void i915_driver_lastclose(struct drm_device * dev); 2162 extern void i915_driver_preclose(struct drm_device *dev, 2163 struct drm_file *file); 2164 extern void i915_driver_postclose(struct drm_device *dev, 2165 struct drm_file *file); 2166 extern int i915_driver_device_is_agp(struct drm_device * dev); 2167 #ifdef CONFIG_COMPAT 2168 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2169 unsigned long arg); 2170 #endif 2171 extern int i915_emit_box(struct drm_device *dev, 2172 struct drm_clip_rect *box, 2173 int DR1, int DR4); 2174 extern int intel_gpu_reset(struct drm_device *dev); 2175 extern int i915_reset(struct drm_device *dev); 2176 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2177 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2178 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2179 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2180 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2181 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2182 2183 extern void intel_console_resume(struct work_struct *work); 2184 2185 /* i915_irq.c */ 2186 void i915_queue_hangcheck(struct drm_device *dev); 2187 __printf(3, 4) 2188 void i915_handle_error(struct drm_device *dev, bool wedged, 2189 const char *fmt, ...); 2190 2191 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, 2192 int new_delay); 2193 extern void intel_irq_init(struct drm_device *dev); 2194 extern void intel_hpd_init(struct drm_device *dev); 2195 2196 extern void intel_uncore_sanitize(struct drm_device *dev); 2197 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2198 bool restore_forcewake); 2199 extern void intel_uncore_init(struct drm_device *dev); 2200 extern void intel_uncore_check_errors(struct drm_device *dev); 2201 extern void intel_uncore_fini(struct drm_device *dev); 2202 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2203 2204 void 2205 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2206 u32 status_mask); 2207 2208 void 2209 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2210 u32 status_mask); 2211 2212 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2213 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2214 2215 /* i915_gem.c */ 2216 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 2217 struct drm_file *file_priv); 2218 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2219 struct drm_file *file_priv); 2220 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2221 struct drm_file *file_priv); 2222 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2223 struct drm_file *file_priv); 2224 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2225 struct drm_file *file_priv); 2226 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2227 struct drm_file *file_priv); 2228 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2229 struct drm_file *file_priv); 2230 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2231 struct drm_file *file_priv); 2232 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2233 struct drm_file *file_priv); 2234 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2235 struct drm_file *file_priv); 2236 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2237 struct drm_file *file_priv); 2238 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2239 struct drm_file *file_priv); 2240 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2241 struct drm_file *file_priv); 2242 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *file); 2244 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2245 struct drm_file *file); 2246 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2247 struct drm_file *file_priv); 2248 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2249 struct drm_file *file_priv); 2250 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 2251 struct drm_file *file_priv); 2252 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2253 struct drm_file *file_priv); 2254 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2255 struct drm_file *file_priv); 2256 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2257 struct drm_file *file_priv); 2258 int i915_gem_init_userptr(struct drm_device *dev); 2259 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2260 struct drm_file *file); 2261 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2262 struct drm_file *file_priv); 2263 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2264 struct drm_file *file_priv); 2265 void i915_gem_load(struct drm_device *dev); 2266 void *i915_gem_object_alloc(struct drm_device *dev); 2267 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2268 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2269 const struct drm_i915_gem_object_ops *ops); 2270 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2271 size_t size); 2272 void i915_init_vm(struct drm_i915_private *dev_priv, 2273 struct i915_address_space *vm); 2274 void i915_gem_free_object(struct drm_gem_object *obj); 2275 void i915_gem_vma_destroy(struct i915_vma *vma); 2276 2277 #define PIN_MAPPABLE 0x1 2278 #define PIN_NONBLOCK 0x2 2279 #define PIN_GLOBAL 0x4 2280 #define PIN_OFFSET_BIAS 0x8 2281 #define PIN_OFFSET_MASK (~4095) 2282 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2283 struct i915_address_space *vm, 2284 uint32_t alignment, 2285 uint64_t flags); 2286 int __must_check i915_vma_unbind(struct i915_vma *vma); 2287 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2288 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2289 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2290 void i915_gem_lastclose(struct drm_device *dev); 2291 2292 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2293 int *needs_clflush); 2294 2295 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2296 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2297 { 2298 struct sg_page_iter sg_iter; 2299 2300 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 2301 return sg_page_iter_page(&sg_iter); 2302 2303 return NULL; 2304 } 2305 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2306 { 2307 BUG_ON(obj->pages == NULL); 2308 obj->pages_pin_count++; 2309 } 2310 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2311 { 2312 BUG_ON(obj->pages_pin_count == 0); 2313 obj->pages_pin_count--; 2314 } 2315 2316 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2317 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2318 struct intel_engine_cs *to); 2319 void i915_vma_move_to_active(struct i915_vma *vma, 2320 struct intel_engine_cs *ring); 2321 int i915_gem_dumb_create(struct drm_file *file_priv, 2322 struct drm_device *dev, 2323 struct drm_mode_create_dumb *args); 2324 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2325 uint32_t handle, uint64_t *offset); 2326 /** 2327 * Returns true if seq1 is later than seq2. 2328 */ 2329 static inline bool 2330 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2331 { 2332 return (int32_t)(seq1 - seq2) >= 0; 2333 } 2334 2335 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2336 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2337 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2338 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2339 2340 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2341 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2342 2343 struct drm_i915_gem_request * 2344 i915_gem_find_active_request(struct intel_engine_cs *ring); 2345 2346 bool i915_gem_retire_requests(struct drm_device *dev); 2347 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2348 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2349 bool interruptible); 2350 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); 2351 2352 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2353 { 2354 return unlikely(atomic_read(&error->reset_counter) 2355 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2356 } 2357 2358 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2359 { 2360 return atomic_read(&error->reset_counter) & I915_WEDGED; 2361 } 2362 2363 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2364 { 2365 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2366 } 2367 2368 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2369 { 2370 return dev_priv->gpu_error.stop_rings == 0 || 2371 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2372 } 2373 2374 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2375 { 2376 return dev_priv->gpu_error.stop_rings == 0 || 2377 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2378 } 2379 2380 void i915_gem_reset(struct drm_device *dev); 2381 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2382 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2383 int __must_check i915_gem_init(struct drm_device *dev); 2384 int __must_check i915_gem_init_hw(struct drm_device *dev); 2385 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2386 void i915_gem_init_swizzling(struct drm_device *dev); 2387 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2388 int __must_check i915_gpu_idle(struct drm_device *dev); 2389 int __must_check i915_gem_suspend(struct drm_device *dev); 2390 int __i915_add_request(struct intel_engine_cs *ring, 2391 struct drm_file *file, 2392 struct drm_i915_gem_object *batch_obj, 2393 u32 *seqno); 2394 #define i915_add_request(ring, seqno) \ 2395 __i915_add_request(ring, NULL, NULL, seqno) 2396 int __must_check i915_wait_seqno(struct intel_engine_cs *ring, 2397 uint32_t seqno); 2398 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 2399 int __must_check 2400 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2401 bool write); 2402 int __must_check 2403 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2404 int __must_check 2405 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2406 u32 alignment, 2407 struct intel_engine_cs *pipelined); 2408 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2409 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2410 int align); 2411 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2412 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2413 2414 uint32_t 2415 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2416 uint32_t 2417 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2418 int tiling_mode, bool fenced); 2419 2420 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2421 enum i915_cache_level cache_level); 2422 2423 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2424 struct dma_buf *dma_buf); 2425 2426 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2427 struct drm_gem_object *gem_obj, int flags); 2428 2429 void i915_gem_restore_fences(struct drm_device *dev); 2430 2431 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2432 struct i915_address_space *vm); 2433 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2434 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2435 struct i915_address_space *vm); 2436 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2437 struct i915_address_space *vm); 2438 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2439 struct i915_address_space *vm); 2440 struct i915_vma * 2441 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2442 struct i915_address_space *vm); 2443 2444 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2445 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2446 struct i915_vma *vma; 2447 list_for_each_entry(vma, &obj->vma_list, vma_link) 2448 if (vma->pin_count > 0) 2449 return true; 2450 return false; 2451 } 2452 2453 /* Some GGTT VM helpers */ 2454 #define obj_to_ggtt(obj) \ 2455 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2456 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2457 { 2458 struct i915_address_space *ggtt = 2459 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2460 return vm == ggtt; 2461 } 2462 2463 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2464 { 2465 return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); 2466 } 2467 2468 static inline unsigned long 2469 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2470 { 2471 return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); 2472 } 2473 2474 static inline unsigned long 2475 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2476 { 2477 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 2478 } 2479 2480 static inline int __must_check 2481 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2482 uint32_t alignment, 2483 unsigned flags) 2484 { 2485 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); 2486 } 2487 2488 static inline int 2489 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2490 { 2491 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2492 } 2493 2494 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2495 2496 /* i915_gem_context.c */ 2497 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) 2498 int __must_check i915_gem_context_init(struct drm_device *dev); 2499 void i915_gem_context_fini(struct drm_device *dev); 2500 void i915_gem_context_reset(struct drm_device *dev); 2501 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2502 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2503 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2504 int i915_switch_context(struct intel_engine_cs *ring, 2505 struct intel_context *to); 2506 struct intel_context * 2507 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2508 void i915_gem_context_free(struct kref *ctx_ref); 2509 static inline void i915_gem_context_reference(struct intel_context *ctx) 2510 { 2511 kref_get(&ctx->ref); 2512 } 2513 2514 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2515 { 2516 kref_put(&ctx->ref, i915_gem_context_free); 2517 } 2518 2519 static inline bool i915_gem_context_is_default(const struct intel_context *c) 2520 { 2521 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 2522 } 2523 2524 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2525 struct drm_file *file); 2526 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2527 struct drm_file *file); 2528 2529 /* i915_gem_render_state.c */ 2530 int i915_gem_render_state_init(struct intel_engine_cs *ring); 2531 /* i915_gem_evict.c */ 2532 int __must_check i915_gem_evict_something(struct drm_device *dev, 2533 struct i915_address_space *vm, 2534 int min_size, 2535 unsigned alignment, 2536 unsigned cache_level, 2537 unsigned long start, 2538 unsigned long end, 2539 unsigned flags); 2540 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2541 int i915_gem_evict_everything(struct drm_device *dev); 2542 2543 /* belongs in i915_gem_gtt.h */ 2544 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2545 { 2546 if (INTEL_INFO(dev)->gen < 6) 2547 intel_gtt_chipset_flush(); 2548 } 2549 2550 /* i915_gem_stolen.c */ 2551 int i915_gem_init_stolen(struct drm_device *dev); 2552 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 2553 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2554 void i915_gem_cleanup_stolen(struct drm_device *dev); 2555 struct drm_i915_gem_object * 2556 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2557 struct drm_i915_gem_object * 2558 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2559 u32 stolen_offset, 2560 u32 gtt_offset, 2561 u32 size); 2562 2563 /* i915_gem_tiling.c */ 2564 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2565 { 2566 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2567 2568 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2569 obj->tiling_mode != I915_TILING_NONE; 2570 } 2571 2572 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2573 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2574 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2575 2576 /* i915_gem_debug.c */ 2577 #if WATCH_LISTS 2578 int i915_verify_lists(struct drm_device *dev); 2579 #else 2580 #define i915_verify_lists(dev) 0 2581 #endif 2582 2583 /* i915_debugfs.c */ 2584 int i915_debugfs_init(struct drm_minor *minor); 2585 void i915_debugfs_cleanup(struct drm_minor *minor); 2586 #ifdef CONFIG_DEBUG_FS 2587 void intel_display_crc_init(struct drm_device *dev); 2588 #else 2589 static inline void intel_display_crc_init(struct drm_device *dev) {} 2590 #endif 2591 2592 /* i915_gpu_error.c */ 2593 __printf(2, 3) 2594 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2595 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2596 const struct i915_error_state_file_priv *error); 2597 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2598 size_t count, loff_t pos); 2599 static inline void i915_error_state_buf_release( 2600 struct drm_i915_error_state_buf *eb) 2601 { 2602 kfree(eb->buf); 2603 } 2604 void i915_capture_error_state(struct drm_device *dev, bool wedge, 2605 const char *error_msg); 2606 void i915_error_state_get(struct drm_device *dev, 2607 struct i915_error_state_file_priv *error_priv); 2608 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2609 void i915_destroy_error_state(struct drm_device *dev); 2610 2611 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2612 const char *i915_cache_level_str(int type); 2613 2614 /* i915_cmd_parser.c */ 2615 int i915_cmd_parser_get_version(void); 2616 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 2617 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 2618 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 2619 int i915_parse_cmds(struct intel_engine_cs *ring, 2620 struct drm_i915_gem_object *batch_obj, 2621 u32 batch_start_offset, 2622 bool is_master); 2623 2624 /* i915_suspend.c */ 2625 extern int i915_save_state(struct drm_device *dev); 2626 extern int i915_restore_state(struct drm_device *dev); 2627 2628 /* i915_ums.c */ 2629 void i915_save_display_reg(struct drm_device *dev); 2630 void i915_restore_display_reg(struct drm_device *dev); 2631 2632 /* i915_sysfs.c */ 2633 void i915_setup_sysfs(struct drm_device *dev_priv); 2634 void i915_teardown_sysfs(struct drm_device *dev_priv); 2635 2636 /* intel_i2c.c */ 2637 extern int intel_setup_gmbus(struct drm_device *dev); 2638 extern void intel_teardown_gmbus(struct drm_device *dev); 2639 static inline bool intel_gmbus_is_port_valid(unsigned port) 2640 { 2641 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2642 } 2643 2644 extern struct i2c_adapter *intel_gmbus_get_adapter( 2645 struct drm_i915_private *dev_priv, unsigned port); 2646 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 2647 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 2648 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 2649 { 2650 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 2651 } 2652 extern void intel_i2c_reset(struct drm_device *dev); 2653 2654 /* intel_opregion.c */ 2655 struct intel_encoder; 2656 #ifdef CONFIG_ACPI 2657 extern int intel_opregion_setup(struct drm_device *dev); 2658 extern void intel_opregion_init(struct drm_device *dev); 2659 extern void intel_opregion_fini(struct drm_device *dev); 2660 extern void intel_opregion_asle_intr(struct drm_device *dev); 2661 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2662 bool enable); 2663 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2664 pci_power_t state); 2665 #else 2666 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2667 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2668 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2669 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2670 static inline int 2671 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2672 { 2673 return 0; 2674 } 2675 static inline int 2676 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2677 { 2678 return 0; 2679 } 2680 #endif 2681 2682 /* intel_acpi.c */ 2683 #ifdef CONFIG_ACPI 2684 extern void intel_register_dsm_handler(void); 2685 extern void intel_unregister_dsm_handler(void); 2686 #else 2687 static inline void intel_register_dsm_handler(void) { return; } 2688 static inline void intel_unregister_dsm_handler(void) { return; } 2689 #endif /* CONFIG_ACPI */ 2690 2691 /* modesetting */ 2692 extern void intel_modeset_init_hw(struct drm_device *dev); 2693 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2694 extern void intel_modeset_init(struct drm_device *dev); 2695 extern void intel_modeset_gem_init(struct drm_device *dev); 2696 extern void intel_modeset_cleanup(struct drm_device *dev); 2697 extern void intel_connector_unregister(struct intel_connector *); 2698 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2699 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2700 bool force_restore); 2701 extern void i915_redisable_vga(struct drm_device *dev); 2702 extern void i915_redisable_vga_power_on(struct drm_device *dev); 2703 extern bool intel_fbc_enabled(struct drm_device *dev); 2704 extern void intel_disable_fbc(struct drm_device *dev); 2705 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2706 extern void intel_init_pch_refclk(struct drm_device *dev); 2707 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2708 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2709 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2710 bool enable); 2711 extern void intel_detect_pch(struct drm_device *dev); 2712 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2713 extern int intel_enable_rc6(const struct drm_device *dev); 2714 2715 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2716 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2717 struct drm_file *file); 2718 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2719 struct drm_file *file); 2720 2721 void intel_notify_mmio_flip(struct intel_engine_cs *ring); 2722 2723 /* overlay */ 2724 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2725 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2726 struct intel_overlay_error_state *error); 2727 2728 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2729 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2730 struct drm_device *dev, 2731 struct intel_display_error_state *error); 2732 2733 /* On SNB platform, before reading ring registers forcewake bit 2734 * must be set to prevent GT core from power down and stale values being 2735 * returned. 2736 */ 2737 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2738 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2739 void assert_force_wake_inactive(struct drm_i915_private *dev_priv); 2740 2741 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2742 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2743 2744 /* intel_sideband.c */ 2745 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2746 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2747 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2748 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2749 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2750 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2751 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2752 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2753 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2754 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2755 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2756 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2757 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2758 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 2759 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); 2760 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2761 enum intel_sbi_destination destination); 2762 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2763 enum intel_sbi_destination destination); 2764 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2765 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2766 2767 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2768 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2769 2770 #define FORCEWAKE_RENDER (1 << 0) 2771 #define FORCEWAKE_MEDIA (1 << 1) 2772 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2773 2774 2775 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2776 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2777 2778 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2779 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2780 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2781 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2782 2783 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2784 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2785 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2786 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2787 2788 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 2789 * will be implemented using 2 32-bit writes in an arbitrary order with 2790 * an arbitrary delay between them. This can cause the hardware to 2791 * act upon the intermediate value, possibly leading to corruption and 2792 * machine death. You have been warned. 2793 */ 2794 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2795 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2796 2797 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 2798 u32 upper = I915_READ(upper_reg); \ 2799 u32 lower = I915_READ(lower_reg); \ 2800 u32 tmp = I915_READ(upper_reg); \ 2801 if (upper != tmp) { \ 2802 upper = tmp; \ 2803 lower = I915_READ(lower_reg); \ 2804 WARN_ON(I915_READ(upper_reg) != upper); \ 2805 } \ 2806 (u64)upper << 32 | lower; }) 2807 2808 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2809 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2810 2811 /* "Broadcast RGB" property */ 2812 #define INTEL_BROADCAST_RGB_AUTO 0 2813 #define INTEL_BROADCAST_RGB_FULL 1 2814 #define INTEL_BROADCAST_RGB_LIMITED 2 2815 2816 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2817 { 2818 if (IS_VALLEYVIEW(dev)) 2819 return VLV_VGACNTRL; 2820 else if (INTEL_INFO(dev)->gen >= 5) 2821 return CPU_VGACNTRL; 2822 else 2823 return VGACNTRL; 2824 } 2825 2826 static inline void __user *to_user_ptr(u64 address) 2827 { 2828 return (void __user *)(uintptr_t)address; 2829 } 2830 2831 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2832 { 2833 unsigned long j = msecs_to_jiffies(m); 2834 2835 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2836 } 2837 2838 static inline unsigned long 2839 timespec_to_jiffies_timeout(const struct timespec *value) 2840 { 2841 unsigned long j = timespec_to_jiffies(value); 2842 2843 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2844 } 2845 2846 /* 2847 * If you need to wait X milliseconds between events A and B, but event B 2848 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 2849 * when event A happened, then just before event B you call this function and 2850 * pass the timestamp as the first argument, and X as the second argument. 2851 */ 2852 static inline void 2853 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 2854 { 2855 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 2856 2857 /* 2858 * Don't re-read the value of "jiffies" every time since it may change 2859 * behind our back and break the math. 2860 */ 2861 tmp_jiffies = jiffies; 2862 target_jiffies = timestamp_jiffies + 2863 msecs_to_jiffies_timeout(to_wait_ms); 2864 2865 if (time_after(target_jiffies, tmp_jiffies)) { 2866 remaining_jiffies = target_jiffies - tmp_jiffies; 2867 while (remaining_jiffies) 2868 remaining_jiffies = 2869 schedule_timeout_uninterruptible(remaining_jiffies); 2870 } 2871 } 2872 2873 #endif 2874