1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <asm/hypervisor.h> 37 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/backlight.h> 42 #include <linux/hash.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/mm_types.h> 46 #include <linux/perf_event.h> 47 #include <linux/pm_qos.h> 48 #include <linux/dma-resv.h> 49 #include <linux/shmem_fs.h> 50 #include <linux/stackdepot.h> 51 #include <linux/xarray.h> 52 53 #include <drm/intel-gtt.h> 54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 55 #include <drm/drm_gem.h> 56 #include <drm/drm_auth.h> 57 #include <drm/drm_cache.h> 58 #include <drm/drm_util.h> 59 #include <drm/drm_dsc.h> 60 #include <drm/drm_atomic.h> 61 #include <drm/drm_connector.h> 62 #include <drm/i915_mei_hdcp_interface.h> 63 64 #include "i915_params.h" 65 #include "i915_reg.h" 66 #include "i915_utils.h" 67 68 #include "display/intel_bios.h" 69 #include "display/intel_display.h" 70 #include "display/intel_display_power.h" 71 #include "display/intel_dpll_mgr.h" 72 #include "display/intel_dsb.h" 73 #include "display/intel_frontbuffer.h" 74 #include "display/intel_global_state.h" 75 #include "display/intel_gmbus.h" 76 #include "display/intel_opregion.h" 77 78 #include "gem/i915_gem_context_types.h" 79 #include "gem/i915_gem_shrinker.h" 80 #include "gem/i915_gem_stolen.h" 81 82 #include "gt/intel_engine.h" 83 #include "gt/intel_gt_types.h" 84 #include "gt/intel_region_lmem.h" 85 #include "gt/intel_workarounds.h" 86 #include "gt/uc/intel_uc.h" 87 88 #include "intel_device_info.h" 89 #include "intel_pch.h" 90 #include "intel_runtime_pm.h" 91 #include "intel_memory_region.h" 92 #include "intel_uncore.h" 93 #include "intel_wakeref.h" 94 #include "intel_wopcm.h" 95 96 #include "i915_gem.h" 97 #include "i915_gem_gtt.h" 98 #include "i915_gpu_error.h" 99 #include "i915_perf_types.h" 100 #include "i915_request.h" 101 #include "i915_scheduler.h" 102 #include "gt/intel_timeline.h" 103 #include "i915_vma.h" 104 #include "i915_irq.h" 105 106 107 /* General customization: 108 */ 109 110 #define DRIVER_NAME "i915" 111 #define DRIVER_DESC "Intel Graphics" 112 #define DRIVER_DATE "20201103" 113 #define DRIVER_TIMESTAMP 1604406085 114 115 struct drm_i915_gem_object; 116 117 enum hpd_pin { 118 HPD_NONE = 0, 119 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 120 HPD_CRT, 121 HPD_SDVO_B, 122 HPD_SDVO_C, 123 HPD_PORT_A, 124 HPD_PORT_B, 125 HPD_PORT_C, 126 HPD_PORT_D, 127 HPD_PORT_E, 128 HPD_PORT_TC1, 129 HPD_PORT_TC2, 130 HPD_PORT_TC3, 131 HPD_PORT_TC4, 132 HPD_PORT_TC5, 133 HPD_PORT_TC6, 134 135 HPD_NUM_PINS 136 }; 137 138 #define for_each_hpd_pin(__pin) \ 139 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 140 141 /* Threshold == 5 for long IRQs, 50 for short */ 142 #define HPD_STORM_DEFAULT_THRESHOLD 50 143 144 struct i915_hotplug { 145 struct delayed_work hotplug_work; 146 147 const u32 *hpd, *pch_hpd; 148 149 struct { 150 unsigned long last_jiffies; 151 int count; 152 enum { 153 HPD_ENABLED = 0, 154 HPD_DISABLED = 1, 155 HPD_MARK_DISABLED = 2 156 } state; 157 } stats[HPD_NUM_PINS]; 158 u32 event_bits; 159 u32 retry_bits; 160 struct delayed_work reenable_work; 161 162 u32 long_port_mask; 163 u32 short_port_mask; 164 struct work_struct dig_port_work; 165 166 struct work_struct poll_init_work; 167 bool poll_enabled; 168 169 unsigned int hpd_storm_threshold; 170 /* Whether or not to count short HPD IRQs in HPD storms */ 171 u8 hpd_short_storm_enabled; 172 173 /* 174 * if we get a HPD irq from DP and a HPD irq from non-DP 175 * the non-DP HPD could block the workqueue on a mode config 176 * mutex getting, that userspace may have taken. However 177 * userspace is waiting on the DP workqueue to run which is 178 * blocked behind the non-DP one. 179 */ 180 struct workqueue_struct *dp_wq; 181 }; 182 183 #define I915_GEM_GPU_DOMAINS \ 184 (I915_GEM_DOMAIN_RENDER | \ 185 I915_GEM_DOMAIN_SAMPLER | \ 186 I915_GEM_DOMAIN_COMMAND | \ 187 I915_GEM_DOMAIN_INSTRUCTION | \ 188 I915_GEM_DOMAIN_VERTEX) 189 190 struct drm_i915_private; 191 struct i915_mm_struct; 192 struct i915_mmu_object; 193 194 struct drm_i915_file_private { 195 struct drm_i915_private *dev_priv; 196 197 union { 198 struct drm_file *file; 199 struct rcu_head rcu; 200 }; 201 202 struct xarray context_xa; 203 struct xarray vm_xa; 204 205 unsigned int bsd_engine; 206 207 /* 208 * Every context ban increments per client ban score. Also 209 * hangs in short succession increments ban score. If ban threshold 210 * is reached, client is considered banned and submitting more work 211 * will fail. This is a stop gap measure to limit the badly behaving 212 * clients access to gpu. Note that unbannable contexts never increment 213 * the client ban score. 214 */ 215 #define I915_CLIENT_SCORE_HANG_FAST 1 216 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 217 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 218 #define I915_CLIENT_SCORE_BANNED 9 219 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 220 atomic_t ban_score; 221 unsigned long hang_timestamp; 222 }; 223 224 /* Interface history: 225 * 226 * 1.1: Original. 227 * 1.2: Add Power Management 228 * 1.3: Add vblank support 229 * 1.4: Fix cmdbuffer path, add heap destroy 230 * 1.5: Add vblank pipe configuration 231 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 232 * - Support vertical blank on secondary display pipe 233 */ 234 #define DRIVER_MAJOR 1 235 #define DRIVER_MINOR 6 236 #define DRIVER_PATCHLEVEL 0 237 238 struct intel_overlay; 239 struct intel_overlay_error_state; 240 241 struct sdvo_device_mapping { 242 u8 initialized; 243 u8 dvo_port; 244 u8 slave_addr; 245 u8 dvo_wiring; 246 u8 i2c_pin; 247 u8 ddc_pin; 248 }; 249 250 struct intel_connector; 251 struct intel_encoder; 252 struct intel_atomic_state; 253 struct intel_cdclk_config; 254 struct intel_cdclk_state; 255 struct intel_cdclk_vals; 256 struct intel_initial_plane_config; 257 struct intel_crtc; 258 struct intel_limit; 259 struct dpll; 260 261 struct drm_i915_display_funcs { 262 void (*get_cdclk)(struct drm_i915_private *dev_priv, 263 struct intel_cdclk_config *cdclk_config); 264 void (*set_cdclk)(struct drm_i915_private *dev_priv, 265 const struct intel_cdclk_config *cdclk_config, 266 enum pipe pipe); 267 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 268 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 269 enum i9xx_plane_id i9xx_plane); 270 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 271 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 272 void (*initial_watermarks)(struct intel_atomic_state *state, 273 struct intel_crtc *crtc); 274 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 275 struct intel_crtc *crtc); 276 void (*optimize_watermarks)(struct intel_atomic_state *state, 277 struct intel_crtc *crtc); 278 int (*compute_global_watermarks)(struct intel_atomic_state *state); 279 void (*update_wm)(struct intel_crtc *crtc); 280 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 281 u8 (*calc_voltage_level)(int cdclk); 282 /* Returns the active state of the crtc, and if the crtc is active, 283 * fills out the pipe-config with the hw state. */ 284 bool (*get_pipe_config)(struct intel_crtc *, 285 struct intel_crtc_state *); 286 void (*get_initial_plane_config)(struct intel_crtc *, 287 struct intel_initial_plane_config *); 288 int (*crtc_compute_clock)(struct intel_crtc *crtc, 289 struct intel_crtc_state *crtc_state); 290 void (*crtc_enable)(struct intel_atomic_state *state, 291 struct intel_crtc *crtc); 292 void (*crtc_disable)(struct intel_atomic_state *state, 293 struct intel_crtc *crtc); 294 void (*commit_modeset_enables)(struct intel_atomic_state *state); 295 void (*commit_modeset_disables)(struct intel_atomic_state *state); 296 void (*audio_codec_enable)(struct intel_encoder *encoder, 297 const struct intel_crtc_state *crtc_state, 298 const struct drm_connector_state *conn_state); 299 void (*audio_codec_disable)(struct intel_encoder *encoder, 300 const struct intel_crtc_state *old_crtc_state, 301 const struct drm_connector_state *old_conn_state); 302 void (*fdi_link_train)(struct intel_crtc *crtc, 303 const struct intel_crtc_state *crtc_state); 304 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 305 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 306 /* clock updates for mode set */ 307 /* cursor updates */ 308 /* render clock increase/decrease */ 309 /* display clock increase/decrease */ 310 /* pll clock increase/decrease */ 311 312 int (*color_check)(struct intel_crtc_state *crtc_state); 313 /* 314 * Program double buffered color management registers during 315 * vblank evasion. The registers should then latch during the 316 * next vblank start, alongside any other double buffered registers 317 * involved with the same commit. 318 */ 319 void (*color_commit)(const struct intel_crtc_state *crtc_state); 320 /* 321 * Load LUTs (and other single buffered color management 322 * registers). Will (hopefully) be called during the vblank 323 * following the latching of any double buffered registers 324 * involved with the same commit. 325 */ 326 void (*load_luts)(const struct intel_crtc_state *crtc_state); 327 void (*read_luts)(struct intel_crtc_state *crtc_state); 328 }; 329 330 struct intel_csr { 331 struct work_struct work; 332 const char *fw_path; 333 u32 required_version; 334 u32 max_fw_size; /* bytes */ 335 u32 *dmc_payload; 336 u32 dmc_fw_size; /* dwords */ 337 u32 version; 338 u32 mmio_count; 339 i915_reg_t mmioaddr[20]; 340 u32 mmiodata[20]; 341 u32 dc_state; 342 u32 target_dc_state; 343 u32 allowed_dc_mask; 344 intel_wakeref_t wakeref; 345 }; 346 347 enum i915_cache_level { 348 I915_CACHE_NONE = 0, 349 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 350 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 351 caches, eg sampler/render caches, and the 352 large Last-Level-Cache. LLC is coherent with 353 the CPU, but L3 is only visible to the GPU. */ 354 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 355 }; 356 357 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 358 359 struct intel_fbc { 360 /* This is always the inner lock when overlapping with struct_mutex and 361 * it's the outer lock when overlapping with stolen_lock. */ 362 struct mutex lock; 363 unsigned threshold; 364 unsigned int possible_framebuffer_bits; 365 unsigned int busy_bits; 366 struct intel_crtc *crtc; 367 368 struct drm_mm_node compressed_fb; 369 struct drm_mm_node *compressed_llb; 370 371 bool false_color; 372 373 bool active; 374 bool activated; 375 bool flip_pending; 376 377 bool underrun_detected; 378 struct work_struct underrun_work; 379 380 /* 381 * Due to the atomic rules we can't access some structures without the 382 * appropriate locking, so we cache information here in order to avoid 383 * these problems. 384 */ 385 struct intel_fbc_state_cache { 386 struct { 387 unsigned int mode_flags; 388 u32 hsw_bdw_pixel_rate; 389 } crtc; 390 391 struct { 392 unsigned int rotation; 393 int src_w; 394 int src_h; 395 bool visible; 396 /* 397 * Display surface base address adjustement for 398 * pageflips. Note that on gen4+ this only adjusts up 399 * to a tile, offsets within a tile are handled in 400 * the hw itself (with the TILEOFF register). 401 */ 402 int adjusted_x; 403 int adjusted_y; 404 405 u16 pixel_blend_mode; 406 } plane; 407 408 struct { 409 const struct drm_format_info *format; 410 unsigned int stride; 411 u64 modifier; 412 } fb; 413 414 unsigned int fence_y_offset; 415 u16 gen9_wa_cfb_stride; 416 u16 interval; 417 s8 fence_id; 418 bool psr2_active; 419 } state_cache; 420 421 /* 422 * This structure contains everything that's relevant to program the 423 * hardware registers. When we want to figure out if we need to disable 424 * and re-enable FBC for a new configuration we just check if there's 425 * something different in the struct. The genx_fbc_activate functions 426 * are supposed to read from it in order to program the registers. 427 */ 428 struct intel_fbc_reg_params { 429 struct { 430 enum pipe pipe; 431 enum i9xx_plane_id i9xx_plane; 432 } crtc; 433 434 struct { 435 const struct drm_format_info *format; 436 unsigned int stride; 437 u64 modifier; 438 } fb; 439 440 int cfb_size; 441 unsigned int fence_y_offset; 442 u16 gen9_wa_cfb_stride; 443 u16 interval; 444 s8 fence_id; 445 bool plane_visible; 446 } params; 447 448 const char *no_fbc_reason; 449 }; 450 451 /* 452 * HIGH_RR is the highest eDP panel refresh rate read from EDID 453 * LOW_RR is the lowest eDP panel refresh rate found from EDID 454 * parsing for same resolution. 455 */ 456 enum drrs_refresh_rate_type { 457 DRRS_HIGH_RR, 458 DRRS_LOW_RR, 459 DRRS_MAX_RR, /* RR count */ 460 }; 461 462 enum drrs_support_type { 463 DRRS_NOT_SUPPORTED = 0, 464 STATIC_DRRS_SUPPORT = 1, 465 SEAMLESS_DRRS_SUPPORT = 2 466 }; 467 468 struct intel_dp; 469 struct i915_drrs { 470 struct mutex mutex; 471 struct delayed_work work; 472 struct intel_dp *dp; 473 unsigned busy_frontbuffer_bits; 474 enum drrs_refresh_rate_type refresh_rate_type; 475 enum drrs_support_type type; 476 }; 477 478 struct i915_psr { 479 struct mutex lock; 480 481 #define I915_PSR_DEBUG_MODE_MASK 0x0f 482 #define I915_PSR_DEBUG_DEFAULT 0x00 483 #define I915_PSR_DEBUG_DISABLE 0x01 484 #define I915_PSR_DEBUG_ENABLE 0x02 485 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 486 #define I915_PSR_DEBUG_IRQ 0x10 487 488 u32 debug; 489 bool sink_support; 490 bool enabled; 491 struct intel_dp *dp; 492 enum pipe pipe; 493 enum transcoder transcoder; 494 bool active; 495 struct work_struct work; 496 unsigned busy_frontbuffer_bits; 497 bool sink_psr2_support; 498 bool link_standby; 499 bool colorimetry_support; 500 bool psr2_enabled; 501 bool psr2_sel_fetch_enabled; 502 u8 sink_sync_latency; 503 ktime_t last_entry_attempt; 504 ktime_t last_exit; 505 bool sink_not_reliable; 506 bool irq_aux_error; 507 u16 su_x_granularity; 508 bool dc3co_enabled; 509 u32 dc3co_exit_delay; 510 struct delayed_work dc3co_work; 511 struct drm_dp_vsc_sdp vsc; 512 }; 513 514 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 515 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 516 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 517 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 518 #define QUIRK_INCREASE_T12_DELAY (1<<6) 519 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 520 521 struct intel_fbdev; 522 struct intel_fbc_work; 523 524 struct intel_gmbus { 525 struct i2c_adapter adapter; 526 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 527 u32 force_bit; 528 u32 reg0; 529 i915_reg_t gpio_reg; 530 struct i2c_algo_bit_data bit_algo; 531 struct drm_i915_private *dev_priv; 532 }; 533 534 struct i915_suspend_saved_registers { 535 u32 saveDSPARB; 536 u32 saveSWF0[16]; 537 u32 saveSWF1[16]; 538 u32 saveSWF3[3]; 539 u16 saveGCDGMBUS; 540 }; 541 542 struct vlv_s0ix_state; 543 544 #define MAX_L3_SLICES 2 545 struct intel_l3_parity { 546 u32 *remap_info[MAX_L3_SLICES]; 547 struct work_struct error_work; 548 int which_slice; 549 }; 550 551 struct i915_gem_mm { 552 /** Memory allocator for GTT stolen memory */ 553 struct drm_mm stolen; 554 /** Protects the usage of the GTT stolen memory allocator. This is 555 * always the inner lock when overlapping with struct_mutex. */ 556 struct mutex stolen_lock; 557 558 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 559 spinlock_t obj_lock; 560 561 /** 562 * List of objects which are purgeable. 563 */ 564 struct list_head purge_list; 565 566 /** 567 * List of objects which have allocated pages and are shrinkable. 568 */ 569 struct list_head shrink_list; 570 571 /** 572 * List of objects which are pending destruction. 573 */ 574 struct llist_head free_list; 575 struct work_struct free_work; 576 /** 577 * Count of objects pending destructions. Used to skip needlessly 578 * waiting on an RCU barrier if no objects are waiting to be freed. 579 */ 580 atomic_t free_count; 581 582 /** 583 * tmpfs instance used for shmem backed objects 584 */ 585 struct vfsmount *gemfs; 586 587 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 588 589 struct notifier_block oom_notifier; 590 struct notifier_block vmap_notifier; 591 struct shrinker shrinker; 592 593 /** 594 * Workqueue to fault in userptr pages, flushed by the execbuf 595 * when required but otherwise left to userspace to try again 596 * on EAGAIN. 597 */ 598 struct workqueue_struct *userptr_wq; 599 600 /* shrinker accounting, also useful for userland debugging */ 601 u64 shrink_memory; 602 u32 shrink_count; 603 }; 604 605 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 606 607 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 608 u64 context); 609 610 static inline unsigned long 611 i915_fence_timeout(const struct drm_i915_private *i915) 612 { 613 return i915_fence_context_timeout(i915, U64_MAX); 614 } 615 616 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 617 #define I915_NUM_QGV_POINTS 8 618 619 struct ddi_vbt_port_info { 620 /* Non-NULL if port present. */ 621 const struct child_device_config *child; 622 623 int max_tmds_clock; 624 625 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 626 u8 hdmi_level_shift; 627 u8 hdmi_level_shift_set:1; 628 629 u8 supports_dvi:1; 630 u8 supports_hdmi:1; 631 u8 supports_dp:1; 632 u8 supports_edp:1; 633 u8 supports_typec_usb:1; 634 u8 supports_tbt:1; 635 636 u8 alternate_aux_channel; 637 u8 alternate_ddc_pin; 638 639 u8 dp_boost_level; 640 u8 hdmi_boost_level; 641 int dp_max_link_rate; /* 0 for not limited by VBT */ 642 }; 643 644 enum psr_lines_to_wait { 645 PSR_0_LINES_TO_WAIT = 0, 646 PSR_1_LINE_TO_WAIT, 647 PSR_4_LINES_TO_WAIT, 648 PSR_8_LINES_TO_WAIT 649 }; 650 651 struct intel_vbt_data { 652 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 653 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 654 655 /* Feature bits */ 656 unsigned int int_tv_support:1; 657 unsigned int lvds_dither:1; 658 unsigned int int_crt_support:1; 659 unsigned int lvds_use_ssc:1; 660 unsigned int int_lvds_support:1; 661 unsigned int display_clock_mode:1; 662 unsigned int fdi_rx_polarity_inverted:1; 663 unsigned int panel_type:4; 664 int lvds_ssc_freq; 665 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 666 enum drm_panel_orientation orientation; 667 668 enum drrs_support_type drrs_type; 669 670 struct { 671 int rate; 672 int lanes; 673 int preemphasis; 674 int vswing; 675 bool low_vswing; 676 bool initialized; 677 int bpp; 678 struct edp_power_seq pps; 679 bool hobl; 680 } edp; 681 682 struct { 683 bool enable; 684 bool full_link; 685 bool require_aux_wakeup; 686 int idle_frames; 687 enum psr_lines_to_wait lines_to_wait; 688 int tp1_wakeup_time_us; 689 int tp2_tp3_wakeup_time_us; 690 int psr2_tp2_tp3_wakeup_time_us; 691 } psr; 692 693 struct { 694 u16 pwm_freq_hz; 695 bool present; 696 bool active_low_pwm; 697 u8 min_brightness; /* min_brightness/255 of max */ 698 u8 controller; /* brightness controller number */ 699 enum intel_backlight_type type; 700 } backlight; 701 702 /* MIPI DSI */ 703 struct { 704 u16 panel_id; 705 struct mipi_config *config; 706 struct mipi_pps_data *pps; 707 u16 bl_ports; 708 u16 cabc_ports; 709 u8 seq_version; 710 u32 size; 711 u8 *data; 712 const u8 *sequence[MIPI_SEQ_MAX]; 713 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 714 enum drm_panel_orientation orientation; 715 } dsi; 716 717 int crt_ddc_pin; 718 719 struct list_head display_devices; 720 721 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 722 struct sdvo_device_mapping sdvo_mappings[2]; 723 }; 724 725 enum intel_ddb_partitioning { 726 INTEL_DDB_PART_1_2, 727 INTEL_DDB_PART_5_6, /* IVB+ */ 728 }; 729 730 struct ilk_wm_values { 731 u32 wm_pipe[3]; 732 u32 wm_lp[3]; 733 u32 wm_lp_spr[3]; 734 bool enable_fbc_wm; 735 enum intel_ddb_partitioning partitioning; 736 }; 737 738 struct g4x_pipe_wm { 739 u16 plane[I915_MAX_PLANES]; 740 u16 fbc; 741 }; 742 743 struct g4x_sr_wm { 744 u16 plane; 745 u16 cursor; 746 u16 fbc; 747 }; 748 749 struct vlv_wm_ddl_values { 750 u8 plane[I915_MAX_PLANES]; 751 }; 752 753 struct vlv_wm_values { 754 struct g4x_pipe_wm pipe[3]; 755 struct g4x_sr_wm sr; 756 struct vlv_wm_ddl_values ddl[3]; 757 u8 level; 758 bool cxsr; 759 }; 760 761 struct g4x_wm_values { 762 struct g4x_pipe_wm pipe[2]; 763 struct g4x_sr_wm sr; 764 struct g4x_sr_wm hpll; 765 bool cxsr; 766 bool hpll_en; 767 bool fbc_en; 768 }; 769 770 struct skl_ddb_entry { 771 u16 start, end; /* in number of blocks, 'end' is exclusive */ 772 }; 773 774 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 775 { 776 return entry->end - entry->start; 777 } 778 779 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 780 const struct skl_ddb_entry *e2) 781 { 782 if (e1->start == e2->start && e1->end == e2->end) 783 return true; 784 785 return false; 786 } 787 788 struct i915_frontbuffer_tracking { 789 spinlock_t lock; 790 791 /* 792 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 793 * scheduled flips. 794 */ 795 unsigned busy_bits; 796 unsigned flip_bits; 797 }; 798 799 struct i915_virtual_gpu { 800 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 801 bool active; 802 u32 caps; 803 }; 804 805 struct intel_cdclk_config { 806 unsigned int cdclk, vco, ref, bypass; 807 u8 voltage_level; 808 }; 809 810 struct i915_selftest_stash { 811 atomic_t counter; 812 }; 813 814 struct drm_i915_private { 815 struct drm_device drm; 816 817 /* FIXME: Device release actions should all be moved to drmm_ */ 818 bool do_release; 819 820 /* i915 device parameters */ 821 struct i915_params params; 822 823 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 824 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 825 struct intel_driver_caps caps; 826 827 /** 828 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 829 * end of stolen which we can optionally use to create GEM objects 830 * backed by stolen memory. Note that stolen_usable_size tells us 831 * exactly how much of this we are actually allowed to use, given that 832 * some portion of it is in fact reserved for use by hardware functions. 833 */ 834 struct resource dsm; 835 /** 836 * Reseved portion of Data Stolen Memory 837 */ 838 struct resource dsm_reserved; 839 840 /* 841 * Stolen memory is segmented in hardware with different portions 842 * offlimits to certain functions. 843 * 844 * The drm_mm is initialised to the total accessible range, as found 845 * from the PCI config. On Broadwell+, this is further restricted to 846 * avoid the first page! The upper end of stolen memory is reserved for 847 * hardware functions and similarly removed from the accessible range. 848 */ 849 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 850 851 struct intel_uncore uncore; 852 struct intel_uncore_mmio_debug mmio_debug; 853 854 struct i915_virtual_gpu vgpu; 855 856 struct intel_gvt *gvt; 857 858 struct intel_wopcm wopcm; 859 860 struct intel_csr csr; 861 862 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 863 864 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 865 * controller on different i2c buses. */ 866 struct mutex gmbus_mutex; 867 868 /** 869 * Base address of where the gmbus and gpio blocks are located (either 870 * on PCH or on SoC for platforms without PCH). 871 */ 872 u32 gpio_mmio_base; 873 874 u32 hsw_psr_mmio_adjust; 875 876 /* MMIO base address for MIPI regs */ 877 u32 mipi_mmio_base; 878 879 u32 pps_mmio_base; 880 881 wait_queue_head_t gmbus_wait_queue; 882 883 struct pci_dev *bridge_dev; 884 885 struct rb_root uabi_engines; 886 887 struct resource mch_res; 888 889 /* protects the irq masks */ 890 spinlock_t irq_lock; 891 892 bool display_irqs_enabled; 893 894 /* Sideband mailbox protection */ 895 struct mutex sb_lock; 896 struct pm_qos_request sb_qos; 897 898 /** Cached value of IMR to avoid reads in updating the bitfield */ 899 union { 900 u32 irq_mask; 901 u32 de_irq_mask[I915_MAX_PIPES]; 902 }; 903 u32 pipestat_irq_mask[I915_MAX_PIPES]; 904 905 struct i915_hotplug hotplug; 906 struct intel_fbc fbc; 907 struct i915_drrs drrs; 908 struct intel_opregion opregion; 909 struct intel_vbt_data vbt; 910 911 bool preserve_bios_swizzle; 912 913 /* overlay */ 914 struct intel_overlay *overlay; 915 916 /* backlight registers and fields in struct intel_panel */ 917 struct mutex backlight_lock; 918 919 /* protects panel power sequencer state */ 920 struct mutex pps_mutex; 921 922 unsigned int fsb_freq, mem_freq, is_ddr3; 923 unsigned int skl_preferred_vco_freq; 924 unsigned int max_cdclk_freq; 925 926 unsigned int max_dotclk_freq; 927 unsigned int hpll_freq; 928 unsigned int fdi_pll_freq; 929 unsigned int czclk_freq; 930 931 struct { 932 /* The current hardware cdclk configuration */ 933 struct intel_cdclk_config hw; 934 935 /* cdclk, divider, and ratio table from bspec */ 936 const struct intel_cdclk_vals *table; 937 938 struct intel_global_obj obj; 939 } cdclk; 940 941 struct { 942 /* The current hardware dbuf configuration */ 943 u8 enabled_slices; 944 945 struct intel_global_obj obj; 946 } dbuf; 947 948 /** 949 * wq - Driver workqueue for GEM. 950 * 951 * NOTE: Work items scheduled here are not allowed to grab any modeset 952 * locks, for otherwise the flushing done in the pageflip code will 953 * result in deadlocks. 954 */ 955 struct workqueue_struct *wq; 956 957 /* ordered wq for modesets */ 958 struct workqueue_struct *modeset_wq; 959 /* unbound hipri wq for page flips/plane updates */ 960 struct workqueue_struct *flip_wq; 961 962 /* Display functions */ 963 struct drm_i915_display_funcs display; 964 965 /* PCH chipset type */ 966 enum intel_pch pch_type; 967 unsigned short pch_id; 968 969 unsigned long quirks; 970 971 struct drm_atomic_state *modeset_restore_state; 972 struct drm_modeset_acquire_ctx reset_ctx; 973 974 struct i915_ggtt ggtt; /* VM representing the global address space */ 975 976 struct i915_gem_mm mm; 977 DECLARE_HASHTABLE(mm_structs, 7); 978 spinlock_t mm_lock; 979 980 /* Kernel Modesetting */ 981 982 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 983 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 984 985 /** 986 * dpll and cdclk state is protected by connection_mutex 987 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 988 * Must be global rather than per dpll, because on some platforms plls 989 * share registers. 990 */ 991 struct { 992 struct mutex lock; 993 994 int num_shared_dpll; 995 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 996 const struct intel_dpll_mgr *mgr; 997 998 struct { 999 int nssc; 1000 int ssc; 1001 } ref_clks; 1002 } dpll; 1003 1004 struct list_head global_obj_list; 1005 1006 /* 1007 * For reading active_pipes holding any crtc lock is 1008 * sufficient, for writing must hold all of them. 1009 */ 1010 u8 active_pipes; 1011 1012 struct i915_wa_list gt_wa_list; 1013 1014 struct i915_frontbuffer_tracking fb_tracking; 1015 1016 struct intel_atomic_helper { 1017 struct llist_head free_list; 1018 struct work_struct free_work; 1019 } atomic_helper; 1020 1021 bool mchbar_need_disable; 1022 1023 struct intel_l3_parity l3_parity; 1024 1025 /* 1026 * HTI (aka HDPORT) state read during initial hw readout. Most 1027 * platforms don't have HTI, so this will just stay 0. Those that do 1028 * will use this later to figure out which PLLs and PHYs are unavailable 1029 * for driver usage. 1030 */ 1031 u32 hti_state; 1032 1033 /* 1034 * edram size in MB. 1035 * Cannot be determined by PCIID. You must always read a register. 1036 */ 1037 u32 edram_size_mb; 1038 1039 struct i915_power_domains power_domains; 1040 1041 struct i915_psr psr; 1042 1043 struct i915_gpu_error gpu_error; 1044 1045 struct drm_i915_gem_object *vlv_pctx; 1046 1047 /* list of fbdev register on this device */ 1048 struct intel_fbdev *fbdev; 1049 struct work_struct fbdev_suspend_work; 1050 1051 struct drm_property *broadcast_rgb_property; 1052 struct drm_property *force_audio_property; 1053 1054 /* hda/i915 audio component */ 1055 struct i915_audio_component *audio_component; 1056 bool audio_component_registered; 1057 /** 1058 * av_mutex - mutex for audio/video sync 1059 * 1060 */ 1061 struct mutex av_mutex; 1062 int audio_power_refcount; 1063 u32 audio_freq_cntrl; 1064 1065 u32 fdi_rx_config; 1066 1067 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1068 u32 chv_phy_control; 1069 /* 1070 * Shadows for CHV DPLL_MD regs to keep the state 1071 * checker somewhat working in the presence hardware 1072 * crappiness (can't read out DPLL_MD for pipes B & C). 1073 */ 1074 u32 chv_dpll_md[I915_MAX_PIPES]; 1075 u32 bxt_phy_grc; 1076 1077 u32 suspend_count; 1078 bool power_domains_suspended; 1079 struct i915_suspend_saved_registers regfile; 1080 struct vlv_s0ix_state *vlv_s0ix_state; 1081 1082 enum { 1083 I915_SAGV_UNKNOWN = 0, 1084 I915_SAGV_DISABLED, 1085 I915_SAGV_ENABLED, 1086 I915_SAGV_NOT_CONTROLLED 1087 } sagv_status; 1088 1089 u32 sagv_block_time_us; 1090 1091 struct { 1092 /* 1093 * Raw watermark latency values: 1094 * in 0.1us units for WM0, 1095 * in 0.5us units for WM1+. 1096 */ 1097 /* primary */ 1098 u16 pri_latency[5]; 1099 /* sprite */ 1100 u16 spr_latency[5]; 1101 /* cursor */ 1102 u16 cur_latency[5]; 1103 /* 1104 * Raw watermark memory latency values 1105 * for SKL for all 8 levels 1106 * in 1us units. 1107 */ 1108 u16 skl_latency[8]; 1109 1110 /* current hardware state */ 1111 union { 1112 struct ilk_wm_values hw; 1113 struct vlv_wm_values vlv; 1114 struct g4x_wm_values g4x; 1115 }; 1116 1117 u8 max_level; 1118 1119 /* 1120 * Should be held around atomic WM register writing; also 1121 * protects * intel_crtc->wm.active and 1122 * crtc_state->wm.need_postvbl_update. 1123 */ 1124 struct mutex wm_mutex; 1125 } wm; 1126 1127 struct dram_info { 1128 bool wm_lv_0_adjust_needed; 1129 u8 num_channels; 1130 bool symmetric_memory; 1131 enum intel_dram_type { 1132 INTEL_DRAM_UNKNOWN, 1133 INTEL_DRAM_DDR3, 1134 INTEL_DRAM_DDR4, 1135 INTEL_DRAM_LPDDR3, 1136 INTEL_DRAM_LPDDR4 1137 } type; 1138 u8 num_qgv_points; 1139 } dram_info; 1140 1141 struct intel_bw_info { 1142 /* for each QGV point */ 1143 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1144 u8 num_qgv_points; 1145 u8 num_planes; 1146 } max_bw[6]; 1147 1148 struct intel_global_obj bw_obj; 1149 1150 struct intel_runtime_pm runtime_pm; 1151 1152 struct i915_perf perf; 1153 1154 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1155 struct intel_gt gt; 1156 1157 struct { 1158 struct i915_gem_contexts { 1159 spinlock_t lock; /* locks list */ 1160 struct list_head list; 1161 } contexts; 1162 1163 /* 1164 * We replace the local file with a global mappings as the 1165 * backing storage for the mmap is on the device and not 1166 * on the struct file, and we do not want to prolong the 1167 * lifetime of the local fd. To minimise the number of 1168 * anonymous inodes we create, we use a global singleton to 1169 * share the global mapping. 1170 */ 1171 struct file *mmap_singleton; 1172 } gem; 1173 1174 u8 framestart_delay; 1175 1176 u8 pch_ssc_use; 1177 1178 /* For i915gm/i945gm vblank irq workaround */ 1179 u8 vblank_enabled; 1180 1181 /* perform PHY state sanity checks? */ 1182 bool chv_phy_assert[2]; 1183 1184 bool ipc_enabled; 1185 1186 /* Used to save the pipe-to-encoder mapping for audio */ 1187 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1188 1189 /* necessary resource sharing with HDMI LPE audio driver. */ 1190 struct { 1191 struct platform_device *platdev; 1192 int irq; 1193 } lpe_audio; 1194 1195 struct i915_pmu pmu; 1196 1197 struct i915_hdcp_comp_master *hdcp_master; 1198 bool hdcp_comp_added; 1199 1200 /* Mutex to protect the above hdcp component related values. */ 1201 struct mutex hdcp_comp_mutex; 1202 1203 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1204 1205 /* 1206 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1207 * will be rejected. Instead look for a better place. 1208 */ 1209 }; 1210 1211 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1212 { 1213 return container_of(dev, struct drm_i915_private, drm); 1214 } 1215 1216 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1217 { 1218 return dev_get_drvdata(kdev); 1219 } 1220 1221 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1222 { 1223 return pci_get_drvdata(pdev); 1224 } 1225 1226 /* Simple iterator over all initialised engines */ 1227 #define for_each_engine(engine__, dev_priv__, id__) \ 1228 for ((id__) = 0; \ 1229 (id__) < I915_NUM_ENGINES; \ 1230 (id__)++) \ 1231 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1232 1233 /* Iterator over subset of engines selected by mask */ 1234 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1235 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 1236 (tmp__) ? \ 1237 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1238 0;) 1239 1240 #define rb_to_uabi_engine(rb) \ 1241 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1242 1243 #define for_each_uabi_engine(engine__, i915__) \ 1244 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1245 (engine__); \ 1246 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1247 1248 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 1249 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 1250 (engine__) && (engine__)->uabi_class == (class__); \ 1251 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1252 1253 #define I915_GTT_OFFSET_NONE ((u32)-1) 1254 1255 /* 1256 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1257 * considered to be the frontbuffer for the given plane interface-wise. This 1258 * doesn't mean that the hw necessarily already scans it out, but that any 1259 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1260 * 1261 * We have one bit per pipe and per scanout plane type. 1262 */ 1263 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1264 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1265 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1266 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1267 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1268 }) 1269 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1270 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1271 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1272 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1273 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1274 1275 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1276 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1277 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1278 1279 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1280 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1281 1282 #define REVID_FOREVER 0xff 1283 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1284 1285 #define INTEL_GEN_MASK(s, e) ( \ 1286 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1287 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1288 GENMASK((e) - 1, (s) - 1)) 1289 1290 /* Returns true if Gen is in inclusive range [Start, End] */ 1291 #define IS_GEN_RANGE(dev_priv, s, e) \ 1292 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1293 1294 #define IS_GEN(dev_priv, n) \ 1295 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1296 INTEL_INFO(dev_priv)->gen == (n)) 1297 1298 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1299 1300 /* 1301 * Return true if revision is in range [since,until] inclusive. 1302 * 1303 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1304 */ 1305 #define IS_REVID(p, since, until) \ 1306 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1307 1308 static __always_inline unsigned int 1309 __platform_mask_index(const struct intel_runtime_info *info, 1310 enum intel_platform p) 1311 { 1312 const unsigned int pbits = 1313 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1314 1315 /* Expand the platform_mask array if this fails. */ 1316 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1317 pbits * ARRAY_SIZE(info->platform_mask)); 1318 1319 return p / pbits; 1320 } 1321 1322 static __always_inline unsigned int 1323 __platform_mask_bit(const struct intel_runtime_info *info, 1324 enum intel_platform p) 1325 { 1326 const unsigned int pbits = 1327 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1328 1329 return p % pbits + INTEL_SUBPLATFORM_BITS; 1330 } 1331 1332 static inline u32 1333 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1334 { 1335 const unsigned int pi = __platform_mask_index(info, p); 1336 1337 return info->platform_mask[pi] & ((1 << INTEL_SUBPLATFORM_BITS) - 1); 1338 } 1339 1340 static __always_inline bool 1341 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1342 { 1343 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1344 const unsigned int pi = __platform_mask_index(info, p); 1345 const unsigned int pb = __platform_mask_bit(info, p); 1346 1347 BUILD_BUG_ON(!__builtin_constant_p(p)); 1348 1349 return info->platform_mask[pi] & BIT(pb); 1350 } 1351 1352 static __always_inline bool 1353 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1354 enum intel_platform p, unsigned int s) 1355 { 1356 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1357 const unsigned int pi = __platform_mask_index(info, p); 1358 const unsigned int pb = __platform_mask_bit(info, p); 1359 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1360 const u32 mask = info->platform_mask[pi]; 1361 1362 BUILD_BUG_ON(!__builtin_constant_p(p)); 1363 BUILD_BUG_ON(!__builtin_constant_p(s)); 1364 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1365 1366 /* Shift and test on the MSB position so sign flag can be used. */ 1367 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1368 } 1369 1370 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1371 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1372 1373 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1374 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1375 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1376 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1377 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1378 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1379 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1380 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1381 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1382 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1383 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1384 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1385 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1386 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1387 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1388 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1389 #define IS_IRONLAKE_M(dev_priv) \ 1390 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1391 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1392 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1393 INTEL_INFO(dev_priv)->gt == 1) 1394 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1395 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1396 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1397 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1398 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1399 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1400 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1401 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1402 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1403 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 1404 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1405 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1406 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 1407 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1408 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1409 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 1410 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 1411 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1412 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1413 #define IS_BDW_ULT(dev_priv) \ 1414 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1415 #define IS_BDW_ULX(dev_priv) \ 1416 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1417 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1418 INTEL_INFO(dev_priv)->gt == 3) 1419 #define IS_HSW_ULT(dev_priv) \ 1420 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1421 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1422 INTEL_INFO(dev_priv)->gt == 3) 1423 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1424 INTEL_INFO(dev_priv)->gt == 1) 1425 /* ULX machines are also considered ULT. */ 1426 #define IS_HSW_ULX(dev_priv) \ 1427 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1428 #define IS_SKL_ULT(dev_priv) \ 1429 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1430 #define IS_SKL_ULX(dev_priv) \ 1431 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1432 #define IS_KBL_ULT(dev_priv) \ 1433 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1434 #define IS_KBL_ULX(dev_priv) \ 1435 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1436 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1437 INTEL_INFO(dev_priv)->gt == 2) 1438 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1439 INTEL_INFO(dev_priv)->gt == 3) 1440 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1441 INTEL_INFO(dev_priv)->gt == 4) 1442 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1443 INTEL_INFO(dev_priv)->gt == 2) 1444 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1445 INTEL_INFO(dev_priv)->gt == 3) 1446 #define IS_CFL_ULT(dev_priv) \ 1447 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1448 #define IS_CFL_ULX(dev_priv) \ 1449 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1450 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1451 INTEL_INFO(dev_priv)->gt == 2) 1452 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1453 INTEL_INFO(dev_priv)->gt == 3) 1454 1455 #define IS_CML_ULT(dev_priv) \ 1456 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 1457 #define IS_CML_ULX(dev_priv) \ 1458 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 1459 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 1460 INTEL_INFO(dev_priv)->gt == 2) 1461 1462 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1463 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1464 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1465 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1466 1467 #define IS_TGL_U(dev_priv) \ 1468 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) 1469 1470 #define IS_TGL_Y(dev_priv) \ 1471 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) 1472 1473 #define SKL_REVID_A0 0x0 1474 #define SKL_REVID_B0 0x1 1475 #define SKL_REVID_C0 0x2 1476 #define SKL_REVID_D0 0x3 1477 #define SKL_REVID_E0 0x4 1478 #define SKL_REVID_F0 0x5 1479 #define SKL_REVID_G0 0x6 1480 #define SKL_REVID_H0 0x7 1481 1482 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1483 1484 #define BXT_REVID_A0 0x0 1485 #define BXT_REVID_A1 0x1 1486 #define BXT_REVID_B0 0x3 1487 #define BXT_REVID_B_LAST 0x8 1488 #define BXT_REVID_C0 0x9 1489 1490 #define IS_BXT_REVID(dev_priv, since, until) \ 1491 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1492 1493 enum { 1494 KBL_REVID_A0, 1495 KBL_REVID_B0, 1496 KBL_REVID_B1, 1497 KBL_REVID_C0, 1498 KBL_REVID_D0, 1499 KBL_REVID_D1, 1500 KBL_REVID_E0, 1501 KBL_REVID_F0, 1502 KBL_REVID_G0, 1503 }; 1504 1505 struct i915_rev_steppings { 1506 u8 gt_stepping; 1507 u8 disp_stepping; 1508 }; 1509 1510 /* Defined in intel_workarounds.c */ 1511 extern const struct i915_rev_steppings kbl_revids[]; 1512 1513 #define IS_KBL_GT_REVID(dev_priv, since, until) \ 1514 (IS_KABYLAKE(dev_priv) && \ 1515 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \ 1516 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until) 1517 #define IS_KBL_DISP_REVID(dev_priv, since, until) \ 1518 (IS_KABYLAKE(dev_priv) && \ 1519 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \ 1520 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until) 1521 1522 #define GLK_REVID_A0 0x0 1523 #define GLK_REVID_A1 0x1 1524 #define GLK_REVID_A2 0x2 1525 #define GLK_REVID_B0 0x3 1526 1527 #define IS_GLK_REVID(dev_priv, since, until) \ 1528 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1529 1530 #define CNL_REVID_A0 0x0 1531 #define CNL_REVID_B0 0x1 1532 #define CNL_REVID_C0 0x2 1533 1534 #define IS_CNL_REVID(p, since, until) \ 1535 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1536 1537 #define ICL_REVID_A0 0x0 1538 #define ICL_REVID_A2 0x1 1539 #define ICL_REVID_B0 0x3 1540 #define ICL_REVID_B2 0x4 1541 #define ICL_REVID_C0 0x5 1542 1543 #define IS_ICL_REVID(p, since, until) \ 1544 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1545 1546 #define EHL_REVID_A0 0x0 1547 #define EHL_REVID_B0 0x1 1548 1549 #define IS_JSL_EHL_REVID(p, since, until) \ 1550 (IS_JSL_EHL(p) && IS_REVID(p, since, until)) 1551 1552 enum { 1553 TGL_REVID_A0, 1554 TGL_REVID_B0, 1555 TGL_REVID_B1, 1556 TGL_REVID_C0, 1557 TGL_REVID_D0, 1558 }; 1559 1560 #define TGL_UY_REVIDS_SIZE 4 1561 #define TGL_REVIDS_SIZE 2 1562 1563 extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE]; 1564 extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE]; 1565 1566 static inline const struct i915_rev_steppings * 1567 tgl_revids_get(struct drm_i915_private *dev_priv) 1568 { 1569 u8 revid = INTEL_REVID(dev_priv); 1570 u8 size; 1571 const struct i915_rev_steppings *tgl_revid_tbl; 1572 1573 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { 1574 tgl_revid_tbl = tgl_uy_revids; 1575 size = ARRAY_SIZE(tgl_uy_revids); 1576 } else { 1577 tgl_revid_tbl = tgl_revids; 1578 size = ARRAY_SIZE(tgl_revids); 1579 } 1580 1581 revid = min_t(u8, revid, size - 1); 1582 1583 return &tgl_revid_tbl[revid]; 1584 } 1585 1586 #define IS_TGL_DISP_REVID(p, since, until) \ 1587 (IS_TIGERLAKE(p) && \ 1588 tgl_revids_get(p)->disp_stepping >= (since) && \ 1589 tgl_revids_get(p)->disp_stepping <= (until)) 1590 1591 #define IS_TGL_UY_GT_REVID(p, since, until) \ 1592 ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ 1593 tgl_revids_get(p)->gt_stepping >= (since) && \ 1594 tgl_revids_get(p)->gt_stepping <= (until)) 1595 1596 #define IS_TGL_GT_REVID(p, since, until) \ 1597 (IS_TIGERLAKE(p) && \ 1598 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ 1599 tgl_revids_get(p)->gt_stepping >= (since) && \ 1600 tgl_revids_get(p)->gt_stepping <= (until)) 1601 1602 #define RKL_REVID_A0 0x0 1603 #define RKL_REVID_B0 0x1 1604 #define RKL_REVID_C0 0x4 1605 1606 #define IS_RKL_REVID(p, since, until) \ 1607 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) 1608 1609 #define DG1_REVID_A0 0x0 1610 #define DG1_REVID_B0 0x1 1611 1612 #define IS_DG1_REVID(p, since, until) \ 1613 (IS_DG1(p) && IS_REVID(p, since, until)) 1614 1615 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1616 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1617 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1618 1619 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 1620 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 1621 1622 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 1623 unsigned int first__ = (first); \ 1624 unsigned int count__ = (count); \ 1625 ((gt)->info.engine_mask & \ 1626 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1627 }) 1628 #define VDBOX_MASK(gt) \ 1629 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 1630 #define VEBOX_MASK(gt) \ 1631 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 1632 1633 /* 1634 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1635 * All later gens can run the final buffer from the ppgtt 1636 */ 1637 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1638 1639 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1640 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1641 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1642 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1643 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 1644 1645 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1646 1647 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1648 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1649 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1650 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1651 1652 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq) 1653 1654 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1655 1656 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1657 #define HAS_PPGTT(dev_priv) \ 1658 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1659 #define HAS_FULL_PPGTT(dev_priv) \ 1660 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1661 1662 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1663 GEM_BUG_ON((sizes) == 0); \ 1664 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1665 }) 1666 1667 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1668 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1669 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1670 1671 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1672 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1673 1674 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1675 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1676 1677 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1678 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1679 (IS_CANNONLAKE(dev_priv) || \ 1680 IS_SKL_GT3(dev_priv) || \ 1681 IS_SKL_GT4(dev_priv)) 1682 1683 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1684 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1685 IS_GEMINILAKE(dev_priv) || \ 1686 IS_KABYLAKE(dev_priv)) 1687 1688 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1689 * rows, which changed the alignment requirements and fence programming. 1690 */ 1691 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1692 !(IS_I915G(dev_priv) || \ 1693 IS_I915GM(dev_priv))) 1694 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1695 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1696 1697 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1698 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1699 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1700 1701 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1702 1703 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1704 1705 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1706 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1707 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1708 #define HAS_PSR_HW_TRACKING(dev_priv) \ 1709 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 1710 #define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) 1711 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1712 1713 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1714 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1715 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1716 1717 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1718 1719 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1720 1721 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1722 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1723 1724 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1725 1726 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1727 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1728 1729 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1730 1731 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1732 1733 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1734 1735 1736 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1737 1738 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1739 1740 /* DPF == dynamic parity feature */ 1741 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1742 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1743 2 : HAS_L3_DPF(dev_priv)) 1744 1745 #define GT_FREQUENCY_MULTIPLIER 50 1746 #define GEN9_FREQ_SCALER 3 1747 1748 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1749 1750 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1751 1752 #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12) 1753 1754 /* Only valid when HAS_DISPLAY() is true */ 1755 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 1756 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) 1757 1758 static inline bool run_as_guest(void) 1759 { 1760 return !hypervisor_is_type(X86_HYPER_NATIVE); 1761 } 1762 1763 static inline bool intel_vtd_active(void) 1764 { 1765 #ifdef CONFIG_INTEL_IOMMU 1766 if (intel_iommu_gfx_mapped) 1767 return true; 1768 #endif 1769 1770 /* Running as a guest, we assume the host is enforcing VT'd */ 1771 return run_as_guest(); 1772 } 1773 1774 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1775 { 1776 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1777 } 1778 1779 static inline bool 1780 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1781 { 1782 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1783 } 1784 1785 /* i915_drv.c */ 1786 extern const struct dev_pm_ops i915_pm_ops; 1787 1788 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1789 void i915_driver_remove(struct drm_i915_private *i915); 1790 void i915_driver_shutdown(struct drm_i915_private *i915); 1791 1792 int i915_resume_switcheroo(struct drm_i915_private *i915); 1793 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1794 1795 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1796 struct drm_file *file_priv); 1797 1798 /* i915_gem.c */ 1799 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1800 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1801 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1802 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1803 1804 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1805 1806 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1807 { 1808 /* 1809 * A single pass should suffice to release all the freed objects (along 1810 * most call paths) , but be a little more paranoid in that freeing 1811 * the objects does take a little amount of time, during which the rcu 1812 * callbacks could have added new objects into the freed list, and 1813 * armed the work again. 1814 */ 1815 while (atomic_read(&i915->mm.free_count)) { 1816 flush_work(&i915->mm.free_work); 1817 rcu_barrier(); 1818 } 1819 } 1820 1821 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1822 { 1823 /* 1824 * Similar to objects above (see i915_gem_drain_freed-objects), in 1825 * general we have workers that are armed by RCU and then rearm 1826 * themselves in their callbacks. To be paranoid, we need to 1827 * drain the workqueue a second time after waiting for the RCU 1828 * grace period so that we catch work queued via RCU from the first 1829 * pass. As neither drain_workqueue() nor flush_workqueue() report 1830 * a result, we make an assumption that we only don't require more 1831 * than 3 passes to catch all _recursive_ RCU delayed work. 1832 * 1833 */ 1834 int pass = 3; 1835 do { 1836 flush_workqueue(i915->wq); 1837 rcu_barrier(); 1838 i915_gem_drain_freed_objects(i915); 1839 } while (--pass); 1840 drain_workqueue(i915->wq); 1841 } 1842 1843 struct i915_vma * __must_check 1844 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, 1845 struct i915_gem_ww_ctx *ww, 1846 const struct i915_ggtt_view *view, 1847 u64 size, u64 alignment, u64 flags); 1848 1849 static inline struct i915_vma * __must_check 1850 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1851 const struct i915_ggtt_view *view, 1852 u64 size, u64 alignment, u64 flags) 1853 { 1854 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); 1855 } 1856 1857 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1858 unsigned long flags); 1859 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1860 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1861 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1862 1863 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1864 1865 int i915_gem_dumb_create(struct drm_file *file_priv, 1866 struct drm_device *dev, 1867 struct drm_mode_create_dumb *args); 1868 1869 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1870 1871 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1872 { 1873 return atomic_read(&error->reset_count); 1874 } 1875 1876 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1877 const struct intel_engine_cs *engine) 1878 { 1879 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1880 } 1881 1882 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1883 void i915_gem_driver_register(struct drm_i915_private *i915); 1884 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1885 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1886 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1887 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1888 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1889 void i915_gem_resume(struct drm_i915_private *dev_priv); 1890 1891 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1892 1893 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1894 enum i915_cache_level cache_level); 1895 1896 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1897 struct dma_buf *dma_buf); 1898 1899 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1900 1901 static inline struct i915_gem_context * 1902 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1903 { 1904 return xa_load(&file_priv->context_xa, id); 1905 } 1906 1907 static inline struct i915_gem_context * 1908 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1909 { 1910 struct i915_gem_context *ctx; 1911 1912 rcu_read_lock(); 1913 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1914 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1915 ctx = NULL; 1916 rcu_read_unlock(); 1917 1918 return ctx; 1919 } 1920 1921 /* i915_gem_evict.c */ 1922 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1923 u64 min_size, u64 alignment, 1924 unsigned long color, 1925 u64 start, u64 end, 1926 unsigned flags); 1927 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1928 struct drm_mm_node *node, 1929 unsigned int flags); 1930 int i915_gem_evict_vm(struct i915_address_space *vm); 1931 1932 /* i915_gem_internal.c */ 1933 struct drm_i915_gem_object * 1934 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1935 phys_addr_t size); 1936 1937 /* i915_gem_tiling.c */ 1938 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1939 { 1940 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1941 1942 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1943 i915_gem_object_is_tiled(obj); 1944 } 1945 1946 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1947 unsigned int tiling, unsigned int stride); 1948 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1949 unsigned int tiling, unsigned int stride); 1950 1951 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1952 1953 /* i915_cmd_parser.c */ 1954 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1955 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1956 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1957 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1958 struct i915_vma *batch, 1959 unsigned long batch_offset, 1960 unsigned long batch_length, 1961 struct i915_vma *shadow, 1962 bool trampoline); 1963 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1964 1965 /* intel_device_info.c */ 1966 static inline struct intel_device_info * 1967 mkwrite_device_info(struct drm_i915_private *dev_priv) 1968 { 1969 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1970 } 1971 1972 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1973 struct drm_file *file); 1974 1975 /* i915_mm.c */ 1976 int remap_io_mapping(struct vm_area_struct *vma, 1977 unsigned long addr, unsigned long pfn, unsigned long size, 1978 struct io_mapping *iomap); 1979 int remap_io_sg(struct vm_area_struct *vma, 1980 unsigned long addr, unsigned long size, 1981 struct scatterlist *sgl, resource_size_t iobase); 1982 1983 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1984 { 1985 if (INTEL_GEN(i915) >= 10) 1986 return CNL_HWS_CSB_WRITE_INDEX; 1987 else 1988 return I915_HWS_CSB_WRITE_INDEX; 1989 } 1990 1991 static inline enum i915_map_type 1992 i915_coherent_map_type(struct drm_i915_private *i915) 1993 { 1994 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 1995 } 1996 1997 #endif 1998