1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <asm/hypervisor.h> 37 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/backlight.h> 42 #include <linux/hash.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/mm_types.h> 46 #include <linux/perf_event.h> 47 #include <linux/pm_qos.h> 48 #include <linux/dma-resv.h> 49 #include <linux/shmem_fs.h> 50 #include <linux/stackdepot.h> 51 #include <linux/xarray.h> 52 53 #include <drm/intel-gtt.h> 54 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 55 #include <drm/drm_gem.h> 56 #include <drm/drm_auth.h> 57 #include <drm/drm_cache.h> 58 #include <drm/drm_util.h> 59 #include <drm/drm_dsc.h> 60 #include <drm/drm_atomic.h> 61 #include <drm/drm_connector.h> 62 #include <drm/i915_mei_hdcp_interface.h> 63 64 #include "i915_params.h" 65 #include "i915_reg.h" 66 #include "i915_utils.h" 67 68 #include "display/intel_bios.h" 69 #include "display/intel_display.h" 70 #include "display/intel_display_power.h" 71 #include "display/intel_dpll_mgr.h" 72 #include "display/intel_dsb.h" 73 #include "display/intel_frontbuffer.h" 74 #include "display/intel_global_state.h" 75 #include "display/intel_gmbus.h" 76 #include "display/intel_opregion.h" 77 78 #include "gem/i915_gem_context_types.h" 79 #include "gem/i915_gem_shrinker.h" 80 #include "gem/i915_gem_stolen.h" 81 82 #include "gt/intel_lrc.h" 83 #include "gt/intel_engine.h" 84 #include "gt/intel_gt_types.h" 85 #include "gt/intel_workarounds.h" 86 #include "gt/uc/intel_uc.h" 87 88 #include "intel_device_info.h" 89 #include "intel_pch.h" 90 #include "intel_runtime_pm.h" 91 #include "intel_memory_region.h" 92 #include "intel_uncore.h" 93 #include "intel_wakeref.h" 94 #include "intel_wopcm.h" 95 96 #include "i915_gem.h" 97 #include "i915_gem_gtt.h" 98 #include "i915_gpu_error.h" 99 #include "i915_perf_types.h" 100 #include "i915_request.h" 101 #include "i915_scheduler.h" 102 #include "gt/intel_timeline.h" 103 #include "i915_vma.h" 104 #include "i915_irq.h" 105 106 #include "intel_region_lmem.h" 107 108 /* General customization: 109 */ 110 111 #define DRIVER_NAME "i915" 112 #define DRIVER_DESC "Intel Graphics" 113 #define DRIVER_DATE "20201103" 114 #define DRIVER_TIMESTAMP 1604406085 115 116 struct drm_i915_gem_object; 117 118 enum hpd_pin { 119 HPD_NONE = 0, 120 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 121 HPD_CRT, 122 HPD_SDVO_B, 123 HPD_SDVO_C, 124 HPD_PORT_A, 125 HPD_PORT_B, 126 HPD_PORT_C, 127 HPD_PORT_D, 128 HPD_PORT_E, 129 HPD_PORT_TC1, 130 HPD_PORT_TC2, 131 HPD_PORT_TC3, 132 HPD_PORT_TC4, 133 HPD_PORT_TC5, 134 HPD_PORT_TC6, 135 136 HPD_NUM_PINS 137 }; 138 139 #define for_each_hpd_pin(__pin) \ 140 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 141 142 /* Threshold == 5 for long IRQs, 50 for short */ 143 #define HPD_STORM_DEFAULT_THRESHOLD 50 144 145 struct i915_hotplug { 146 struct delayed_work hotplug_work; 147 148 const u32 *hpd, *pch_hpd; 149 150 struct { 151 unsigned long last_jiffies; 152 int count; 153 enum { 154 HPD_ENABLED = 0, 155 HPD_DISABLED = 1, 156 HPD_MARK_DISABLED = 2 157 } state; 158 } stats[HPD_NUM_PINS]; 159 u32 event_bits; 160 u32 retry_bits; 161 struct delayed_work reenable_work; 162 163 u32 long_port_mask; 164 u32 short_port_mask; 165 struct work_struct dig_port_work; 166 167 struct work_struct poll_init_work; 168 bool poll_enabled; 169 170 unsigned int hpd_storm_threshold; 171 /* Whether or not to count short HPD IRQs in HPD storms */ 172 u8 hpd_short_storm_enabled; 173 174 /* 175 * if we get a HPD irq from DP and a HPD irq from non-DP 176 * the non-DP HPD could block the workqueue on a mode config 177 * mutex getting, that userspace may have taken. However 178 * userspace is waiting on the DP workqueue to run which is 179 * blocked behind the non-DP one. 180 */ 181 struct workqueue_struct *dp_wq; 182 }; 183 184 #define I915_GEM_GPU_DOMAINS \ 185 (I915_GEM_DOMAIN_RENDER | \ 186 I915_GEM_DOMAIN_SAMPLER | \ 187 I915_GEM_DOMAIN_COMMAND | \ 188 I915_GEM_DOMAIN_INSTRUCTION | \ 189 I915_GEM_DOMAIN_VERTEX) 190 191 struct drm_i915_private; 192 struct i915_mm_struct; 193 struct i915_mmu_object; 194 195 struct drm_i915_file_private { 196 struct drm_i915_private *dev_priv; 197 198 union { 199 struct drm_file *file; 200 struct rcu_head rcu; 201 }; 202 203 struct xarray context_xa; 204 struct xarray vm_xa; 205 206 unsigned int bsd_engine; 207 208 /* 209 * Every context ban increments per client ban score. Also 210 * hangs in short succession increments ban score. If ban threshold 211 * is reached, client is considered banned and submitting more work 212 * will fail. This is a stop gap measure to limit the badly behaving 213 * clients access to gpu. Note that unbannable contexts never increment 214 * the client ban score. 215 */ 216 #define I915_CLIENT_SCORE_HANG_FAST 1 217 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 218 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 219 #define I915_CLIENT_SCORE_BANNED 9 220 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 221 atomic_t ban_score; 222 unsigned long hang_timestamp; 223 }; 224 225 /* Interface history: 226 * 227 * 1.1: Original. 228 * 1.2: Add Power Management 229 * 1.3: Add vblank support 230 * 1.4: Fix cmdbuffer path, add heap destroy 231 * 1.5: Add vblank pipe configuration 232 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 233 * - Support vertical blank on secondary display pipe 234 */ 235 #define DRIVER_MAJOR 1 236 #define DRIVER_MINOR 6 237 #define DRIVER_PATCHLEVEL 0 238 239 struct intel_overlay; 240 struct intel_overlay_error_state; 241 242 struct sdvo_device_mapping { 243 u8 initialized; 244 u8 dvo_port; 245 u8 slave_addr; 246 u8 dvo_wiring; 247 u8 i2c_pin; 248 u8 ddc_pin; 249 }; 250 251 struct intel_connector; 252 struct intel_encoder; 253 struct intel_atomic_state; 254 struct intel_cdclk_config; 255 struct intel_cdclk_state; 256 struct intel_cdclk_vals; 257 struct intel_initial_plane_config; 258 struct intel_crtc; 259 struct intel_limit; 260 struct dpll; 261 262 struct drm_i915_display_funcs { 263 void (*get_cdclk)(struct drm_i915_private *dev_priv, 264 struct intel_cdclk_config *cdclk_config); 265 void (*set_cdclk)(struct drm_i915_private *dev_priv, 266 const struct intel_cdclk_config *cdclk_config, 267 enum pipe pipe); 268 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 269 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 270 enum i9xx_plane_id i9xx_plane); 271 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 272 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 273 void (*initial_watermarks)(struct intel_atomic_state *state, 274 struct intel_crtc *crtc); 275 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 276 struct intel_crtc *crtc); 277 void (*optimize_watermarks)(struct intel_atomic_state *state, 278 struct intel_crtc *crtc); 279 int (*compute_global_watermarks)(struct intel_atomic_state *state); 280 void (*update_wm)(struct intel_crtc *crtc); 281 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 282 u8 (*calc_voltage_level)(int cdclk); 283 /* Returns the active state of the crtc, and if the crtc is active, 284 * fills out the pipe-config with the hw state. */ 285 bool (*get_pipe_config)(struct intel_crtc *, 286 struct intel_crtc_state *); 287 void (*get_initial_plane_config)(struct intel_crtc *, 288 struct intel_initial_plane_config *); 289 int (*crtc_compute_clock)(struct intel_crtc *crtc, 290 struct intel_crtc_state *crtc_state); 291 void (*crtc_enable)(struct intel_atomic_state *state, 292 struct intel_crtc *crtc); 293 void (*crtc_disable)(struct intel_atomic_state *state, 294 struct intel_crtc *crtc); 295 void (*commit_modeset_enables)(struct intel_atomic_state *state); 296 void (*commit_modeset_disables)(struct intel_atomic_state *state); 297 void (*audio_codec_enable)(struct intel_encoder *encoder, 298 const struct intel_crtc_state *crtc_state, 299 const struct drm_connector_state *conn_state); 300 void (*audio_codec_disable)(struct intel_encoder *encoder, 301 const struct intel_crtc_state *old_crtc_state, 302 const struct drm_connector_state *old_conn_state); 303 void (*fdi_link_train)(struct intel_crtc *crtc, 304 const struct intel_crtc_state *crtc_state); 305 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 306 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 307 /* clock updates for mode set */ 308 /* cursor updates */ 309 /* render clock increase/decrease */ 310 /* display clock increase/decrease */ 311 /* pll clock increase/decrease */ 312 313 int (*color_check)(struct intel_crtc_state *crtc_state); 314 /* 315 * Program double buffered color management registers during 316 * vblank evasion. The registers should then latch during the 317 * next vblank start, alongside any other double buffered registers 318 * involved with the same commit. 319 */ 320 void (*color_commit)(const struct intel_crtc_state *crtc_state); 321 /* 322 * Load LUTs (and other single buffered color management 323 * registers). Will (hopefully) be called during the vblank 324 * following the latching of any double buffered registers 325 * involved with the same commit. 326 */ 327 void (*load_luts)(const struct intel_crtc_state *crtc_state); 328 void (*read_luts)(struct intel_crtc_state *crtc_state); 329 }; 330 331 struct intel_csr { 332 struct work_struct work; 333 const char *fw_path; 334 u32 required_version; 335 u32 max_fw_size; /* bytes */ 336 u32 *dmc_payload; 337 u32 dmc_fw_size; /* dwords */ 338 u32 version; 339 u32 mmio_count; 340 i915_reg_t mmioaddr[20]; 341 u32 mmiodata[20]; 342 u32 dc_state; 343 u32 target_dc_state; 344 u32 allowed_dc_mask; 345 intel_wakeref_t wakeref; 346 }; 347 348 enum i915_cache_level { 349 I915_CACHE_NONE = 0, 350 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 351 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 352 caches, eg sampler/render caches, and the 353 large Last-Level-Cache. LLC is coherent with 354 the CPU, but L3 is only visible to the GPU. */ 355 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 356 }; 357 358 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 359 360 struct intel_fbc { 361 /* This is always the inner lock when overlapping with struct_mutex and 362 * it's the outer lock when overlapping with stolen_lock. */ 363 struct mutex lock; 364 unsigned threshold; 365 unsigned int possible_framebuffer_bits; 366 unsigned int busy_bits; 367 struct intel_crtc *crtc; 368 369 struct drm_mm_node compressed_fb; 370 struct drm_mm_node *compressed_llb; 371 372 bool false_color; 373 374 bool active; 375 bool activated; 376 bool flip_pending; 377 378 bool underrun_detected; 379 struct work_struct underrun_work; 380 381 /* 382 * Due to the atomic rules we can't access some structures without the 383 * appropriate locking, so we cache information here in order to avoid 384 * these problems. 385 */ 386 struct intel_fbc_state_cache { 387 struct { 388 unsigned int mode_flags; 389 u32 hsw_bdw_pixel_rate; 390 } crtc; 391 392 struct { 393 unsigned int rotation; 394 int src_w; 395 int src_h; 396 bool visible; 397 /* 398 * Display surface base address adjustement for 399 * pageflips. Note that on gen4+ this only adjusts up 400 * to a tile, offsets within a tile are handled in 401 * the hw itself (with the TILEOFF register). 402 */ 403 int adjusted_x; 404 int adjusted_y; 405 406 u16 pixel_blend_mode; 407 } plane; 408 409 struct { 410 const struct drm_format_info *format; 411 unsigned int stride; 412 u64 modifier; 413 } fb; 414 415 unsigned int fence_y_offset; 416 u16 gen9_wa_cfb_stride; 417 u16 interval; 418 s8 fence_id; 419 } state_cache; 420 421 /* 422 * This structure contains everything that's relevant to program the 423 * hardware registers. When we want to figure out if we need to disable 424 * and re-enable FBC for a new configuration we just check if there's 425 * something different in the struct. The genx_fbc_activate functions 426 * are supposed to read from it in order to program the registers. 427 */ 428 struct intel_fbc_reg_params { 429 struct { 430 enum pipe pipe; 431 enum i9xx_plane_id i9xx_plane; 432 } crtc; 433 434 struct { 435 const struct drm_format_info *format; 436 unsigned int stride; 437 u64 modifier; 438 } fb; 439 440 int cfb_size; 441 unsigned int fence_y_offset; 442 u16 gen9_wa_cfb_stride; 443 u16 interval; 444 s8 fence_id; 445 bool plane_visible; 446 } params; 447 448 const char *no_fbc_reason; 449 }; 450 451 /* 452 * HIGH_RR is the highest eDP panel refresh rate read from EDID 453 * LOW_RR is the lowest eDP panel refresh rate found from EDID 454 * parsing for same resolution. 455 */ 456 enum drrs_refresh_rate_type { 457 DRRS_HIGH_RR, 458 DRRS_LOW_RR, 459 DRRS_MAX_RR, /* RR count */ 460 }; 461 462 enum drrs_support_type { 463 DRRS_NOT_SUPPORTED = 0, 464 STATIC_DRRS_SUPPORT = 1, 465 SEAMLESS_DRRS_SUPPORT = 2 466 }; 467 468 struct intel_dp; 469 struct i915_drrs { 470 struct mutex mutex; 471 struct delayed_work work; 472 struct intel_dp *dp; 473 unsigned busy_frontbuffer_bits; 474 enum drrs_refresh_rate_type refresh_rate_type; 475 enum drrs_support_type type; 476 }; 477 478 struct i915_psr { 479 struct mutex lock; 480 481 #define I915_PSR_DEBUG_MODE_MASK 0x0f 482 #define I915_PSR_DEBUG_DEFAULT 0x00 483 #define I915_PSR_DEBUG_DISABLE 0x01 484 #define I915_PSR_DEBUG_ENABLE 0x02 485 #define I915_PSR_DEBUG_FORCE_PSR1 0x03 486 #define I915_PSR_DEBUG_IRQ 0x10 487 488 u32 debug; 489 bool sink_support; 490 bool enabled; 491 struct intel_dp *dp; 492 enum pipe pipe; 493 enum transcoder transcoder; 494 bool active; 495 struct work_struct work; 496 unsigned busy_frontbuffer_bits; 497 bool sink_psr2_support; 498 bool link_standby; 499 bool colorimetry_support; 500 bool psr2_enabled; 501 bool psr2_sel_fetch_enabled; 502 u8 sink_sync_latency; 503 ktime_t last_entry_attempt; 504 ktime_t last_exit; 505 bool sink_not_reliable; 506 bool irq_aux_error; 507 u16 su_x_granularity; 508 bool dc3co_enabled; 509 u32 dc3co_exit_delay; 510 struct delayed_work dc3co_work; 511 struct drm_dp_vsc_sdp vsc; 512 }; 513 514 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 515 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 516 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 517 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 518 #define QUIRK_INCREASE_T12_DELAY (1<<6) 519 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 520 521 struct intel_fbdev; 522 struct intel_fbc_work; 523 524 struct intel_gmbus { 525 struct i2c_adapter adapter; 526 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 527 u32 force_bit; 528 u32 reg0; 529 i915_reg_t gpio_reg; 530 struct i2c_algo_bit_data bit_algo; 531 struct drm_i915_private *dev_priv; 532 }; 533 534 struct i915_suspend_saved_registers { 535 u32 saveDSPARB; 536 u32 saveSWF0[16]; 537 u32 saveSWF1[16]; 538 u32 saveSWF3[3]; 539 u16 saveGCDGMBUS; 540 }; 541 542 struct vlv_s0ix_state; 543 544 #define MAX_L3_SLICES 2 545 struct intel_l3_parity { 546 u32 *remap_info[MAX_L3_SLICES]; 547 struct work_struct error_work; 548 int which_slice; 549 }; 550 551 struct i915_gem_mm { 552 /** Memory allocator for GTT stolen memory */ 553 struct drm_mm stolen; 554 /** Protects the usage of the GTT stolen memory allocator. This is 555 * always the inner lock when overlapping with struct_mutex. */ 556 struct mutex stolen_lock; 557 558 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 559 spinlock_t obj_lock; 560 561 /** 562 * List of objects which are purgeable. 563 */ 564 struct list_head purge_list; 565 566 /** 567 * List of objects which have allocated pages and are shrinkable. 568 */ 569 struct list_head shrink_list; 570 571 /** 572 * List of objects which are pending destruction. 573 */ 574 struct llist_head free_list; 575 struct work_struct free_work; 576 /** 577 * Count of objects pending destructions. Used to skip needlessly 578 * waiting on an RCU barrier if no objects are waiting to be freed. 579 */ 580 atomic_t free_count; 581 582 /** 583 * tmpfs instance used for shmem backed objects 584 */ 585 struct vfsmount *gemfs; 586 587 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 588 589 struct notifier_block oom_notifier; 590 struct notifier_block vmap_notifier; 591 struct shrinker shrinker; 592 593 /** 594 * Workqueue to fault in userptr pages, flushed by the execbuf 595 * when required but otherwise left to userspace to try again 596 * on EAGAIN. 597 */ 598 struct workqueue_struct *userptr_wq; 599 600 /* shrinker accounting, also useful for userland debugging */ 601 u64 shrink_memory; 602 u32 shrink_count; 603 }; 604 605 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 606 607 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 608 u64 context); 609 610 static inline unsigned long 611 i915_fence_timeout(const struct drm_i915_private *i915) 612 { 613 return i915_fence_context_timeout(i915, U64_MAX); 614 } 615 616 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 617 #define I915_NUM_QGV_POINTS 8 618 619 struct ddi_vbt_port_info { 620 /* Non-NULL if port present. */ 621 const struct child_device_config *child; 622 623 int max_tmds_clock; 624 625 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 626 u8 hdmi_level_shift; 627 u8 hdmi_level_shift_set:1; 628 629 u8 supports_dvi:1; 630 u8 supports_hdmi:1; 631 u8 supports_dp:1; 632 u8 supports_edp:1; 633 u8 supports_typec_usb:1; 634 u8 supports_tbt:1; 635 636 u8 alternate_aux_channel; 637 u8 alternate_ddc_pin; 638 639 u8 dp_boost_level; 640 u8 hdmi_boost_level; 641 int dp_max_link_rate; /* 0 for not limited by VBT */ 642 }; 643 644 enum psr_lines_to_wait { 645 PSR_0_LINES_TO_WAIT = 0, 646 PSR_1_LINE_TO_WAIT, 647 PSR_4_LINES_TO_WAIT, 648 PSR_8_LINES_TO_WAIT 649 }; 650 651 struct intel_vbt_data { 652 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 653 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 654 655 /* Feature bits */ 656 unsigned int int_tv_support:1; 657 unsigned int lvds_dither:1; 658 unsigned int int_crt_support:1; 659 unsigned int lvds_use_ssc:1; 660 unsigned int int_lvds_support:1; 661 unsigned int display_clock_mode:1; 662 unsigned int fdi_rx_polarity_inverted:1; 663 unsigned int panel_type:4; 664 int lvds_ssc_freq; 665 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 666 enum drm_panel_orientation orientation; 667 668 enum drrs_support_type drrs_type; 669 670 struct { 671 int rate; 672 int lanes; 673 int preemphasis; 674 int vswing; 675 bool low_vswing; 676 bool initialized; 677 int bpp; 678 struct edp_power_seq pps; 679 bool hobl; 680 } edp; 681 682 struct { 683 bool enable; 684 bool full_link; 685 bool require_aux_wakeup; 686 int idle_frames; 687 enum psr_lines_to_wait lines_to_wait; 688 int tp1_wakeup_time_us; 689 int tp2_tp3_wakeup_time_us; 690 int psr2_tp2_tp3_wakeup_time_us; 691 } psr; 692 693 struct { 694 u16 pwm_freq_hz; 695 bool present; 696 bool active_low_pwm; 697 u8 min_brightness; /* min_brightness/255 of max */ 698 u8 controller; /* brightness controller number */ 699 enum intel_backlight_type type; 700 } backlight; 701 702 /* MIPI DSI */ 703 struct { 704 u16 panel_id; 705 struct mipi_config *config; 706 struct mipi_pps_data *pps; 707 u16 bl_ports; 708 u16 cabc_ports; 709 u8 seq_version; 710 u32 size; 711 u8 *data; 712 const u8 *sequence[MIPI_SEQ_MAX]; 713 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 714 enum drm_panel_orientation orientation; 715 } dsi; 716 717 int crt_ddc_pin; 718 719 struct list_head display_devices; 720 721 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 722 struct sdvo_device_mapping sdvo_mappings[2]; 723 }; 724 725 enum intel_ddb_partitioning { 726 INTEL_DDB_PART_1_2, 727 INTEL_DDB_PART_5_6, /* IVB+ */ 728 }; 729 730 struct ilk_wm_values { 731 u32 wm_pipe[3]; 732 u32 wm_lp[3]; 733 u32 wm_lp_spr[3]; 734 bool enable_fbc_wm; 735 enum intel_ddb_partitioning partitioning; 736 }; 737 738 struct g4x_pipe_wm { 739 u16 plane[I915_MAX_PLANES]; 740 u16 fbc; 741 }; 742 743 struct g4x_sr_wm { 744 u16 plane; 745 u16 cursor; 746 u16 fbc; 747 }; 748 749 struct vlv_wm_ddl_values { 750 u8 plane[I915_MAX_PLANES]; 751 }; 752 753 struct vlv_wm_values { 754 struct g4x_pipe_wm pipe[3]; 755 struct g4x_sr_wm sr; 756 struct vlv_wm_ddl_values ddl[3]; 757 u8 level; 758 bool cxsr; 759 }; 760 761 struct g4x_wm_values { 762 struct g4x_pipe_wm pipe[2]; 763 struct g4x_sr_wm sr; 764 struct g4x_sr_wm hpll; 765 bool cxsr; 766 bool hpll_en; 767 bool fbc_en; 768 }; 769 770 struct skl_ddb_entry { 771 u16 start, end; /* in number of blocks, 'end' is exclusive */ 772 }; 773 774 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 775 { 776 return entry->end - entry->start; 777 } 778 779 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 780 const struct skl_ddb_entry *e2) 781 { 782 if (e1->start == e2->start && e1->end == e2->end) 783 return true; 784 785 return false; 786 } 787 788 struct i915_frontbuffer_tracking { 789 spinlock_t lock; 790 791 /* 792 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 793 * scheduled flips. 794 */ 795 unsigned busy_bits; 796 unsigned flip_bits; 797 }; 798 799 struct i915_virtual_gpu { 800 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 801 bool active; 802 u32 caps; 803 }; 804 805 struct intel_cdclk_config { 806 unsigned int cdclk, vco, ref, bypass; 807 u8 voltage_level; 808 }; 809 810 struct i915_selftest_stash { 811 atomic_t counter; 812 }; 813 814 struct drm_i915_private { 815 struct drm_device drm; 816 817 /* FIXME: Device release actions should all be moved to drmm_ */ 818 bool do_release; 819 820 /* i915 device parameters */ 821 struct i915_params params; 822 823 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 824 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 825 struct intel_driver_caps caps; 826 827 /** 828 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 829 * end of stolen which we can optionally use to create GEM objects 830 * backed by stolen memory. Note that stolen_usable_size tells us 831 * exactly how much of this we are actually allowed to use, given that 832 * some portion of it is in fact reserved for use by hardware functions. 833 */ 834 struct resource dsm; 835 /** 836 * Reseved portion of Data Stolen Memory 837 */ 838 struct resource dsm_reserved; 839 840 /* 841 * Stolen memory is segmented in hardware with different portions 842 * offlimits to certain functions. 843 * 844 * The drm_mm is initialised to the total accessible range, as found 845 * from the PCI config. On Broadwell+, this is further restricted to 846 * avoid the first page! The upper end of stolen memory is reserved for 847 * hardware functions and similarly removed from the accessible range. 848 */ 849 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 850 851 struct intel_uncore uncore; 852 struct intel_uncore_mmio_debug mmio_debug; 853 854 struct i915_virtual_gpu vgpu; 855 856 struct intel_gvt *gvt; 857 858 struct intel_wopcm wopcm; 859 860 struct intel_csr csr; 861 862 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 863 864 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 865 * controller on different i2c buses. */ 866 struct mutex gmbus_mutex; 867 868 /** 869 * Base address of where the gmbus and gpio blocks are located (either 870 * on PCH or on SoC for platforms without PCH). 871 */ 872 u32 gpio_mmio_base; 873 874 u32 hsw_psr_mmio_adjust; 875 876 /* MMIO base address for MIPI regs */ 877 u32 mipi_mmio_base; 878 879 u32 pps_mmio_base; 880 881 wait_queue_head_t gmbus_wait_queue; 882 883 struct pci_dev *bridge_dev; 884 885 struct rb_root uabi_engines; 886 887 struct resource mch_res; 888 889 /* protects the irq masks */ 890 spinlock_t irq_lock; 891 892 bool display_irqs_enabled; 893 894 /* Sideband mailbox protection */ 895 struct mutex sb_lock; 896 struct pm_qos_request sb_qos; 897 898 /** Cached value of IMR to avoid reads in updating the bitfield */ 899 union { 900 u32 irq_mask; 901 u32 de_irq_mask[I915_MAX_PIPES]; 902 }; 903 u32 pipestat_irq_mask[I915_MAX_PIPES]; 904 905 struct i915_hotplug hotplug; 906 struct intel_fbc fbc; 907 struct i915_drrs drrs; 908 struct intel_opregion opregion; 909 struct intel_vbt_data vbt; 910 911 bool preserve_bios_swizzle; 912 913 /* overlay */ 914 struct intel_overlay *overlay; 915 916 /* backlight registers and fields in struct intel_panel */ 917 struct mutex backlight_lock; 918 919 /* protects panel power sequencer state */ 920 struct mutex pps_mutex; 921 922 unsigned int fsb_freq, mem_freq, is_ddr3; 923 unsigned int skl_preferred_vco_freq; 924 unsigned int max_cdclk_freq; 925 926 unsigned int max_dotclk_freq; 927 unsigned int hpll_freq; 928 unsigned int fdi_pll_freq; 929 unsigned int czclk_freq; 930 931 struct { 932 /* The current hardware cdclk configuration */ 933 struct intel_cdclk_config hw; 934 935 /* cdclk, divider, and ratio table from bspec */ 936 const struct intel_cdclk_vals *table; 937 938 struct intel_global_obj obj; 939 } cdclk; 940 941 struct { 942 /* The current hardware dbuf configuration */ 943 u8 enabled_slices; 944 945 struct intel_global_obj obj; 946 } dbuf; 947 948 /** 949 * wq - Driver workqueue for GEM. 950 * 951 * NOTE: Work items scheduled here are not allowed to grab any modeset 952 * locks, for otherwise the flushing done in the pageflip code will 953 * result in deadlocks. 954 */ 955 struct workqueue_struct *wq; 956 957 /* ordered wq for modesets */ 958 struct workqueue_struct *modeset_wq; 959 /* unbound hipri wq for page flips/plane updates */ 960 struct workqueue_struct *flip_wq; 961 962 /* Display functions */ 963 struct drm_i915_display_funcs display; 964 965 /* PCH chipset type */ 966 enum intel_pch pch_type; 967 unsigned short pch_id; 968 969 unsigned long quirks; 970 971 struct drm_atomic_state *modeset_restore_state; 972 struct drm_modeset_acquire_ctx reset_ctx; 973 974 struct i915_ggtt ggtt; /* VM representing the global address space */ 975 976 struct i915_gem_mm mm; 977 DECLARE_HASHTABLE(mm_structs, 7); 978 spinlock_t mm_lock; 979 980 /* Kernel Modesetting */ 981 982 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 983 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 984 985 /** 986 * dpll and cdclk state is protected by connection_mutex 987 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 988 * Must be global rather than per dpll, because on some platforms plls 989 * share registers. 990 */ 991 struct { 992 struct mutex lock; 993 994 int num_shared_dpll; 995 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 996 const struct intel_dpll_mgr *mgr; 997 998 struct { 999 int nssc; 1000 int ssc; 1001 } ref_clks; 1002 } dpll; 1003 1004 struct list_head global_obj_list; 1005 1006 /* 1007 * For reading active_pipes holding any crtc lock is 1008 * sufficient, for writing must hold all of them. 1009 */ 1010 u8 active_pipes; 1011 1012 struct i915_wa_list gt_wa_list; 1013 1014 struct i915_frontbuffer_tracking fb_tracking; 1015 1016 struct intel_atomic_helper { 1017 struct llist_head free_list; 1018 struct work_struct free_work; 1019 } atomic_helper; 1020 1021 bool mchbar_need_disable; 1022 1023 struct intel_l3_parity l3_parity; 1024 1025 /* 1026 * HTI (aka HDPORT) state read during initial hw readout. Most 1027 * platforms don't have HTI, so this will just stay 0. Those that do 1028 * will use this later to figure out which PLLs and PHYs are unavailable 1029 * for driver usage. 1030 */ 1031 u32 hti_state; 1032 1033 /* 1034 * edram size in MB. 1035 * Cannot be determined by PCIID. You must always read a register. 1036 */ 1037 u32 edram_size_mb; 1038 1039 struct i915_power_domains power_domains; 1040 1041 struct i915_psr psr; 1042 1043 struct i915_gpu_error gpu_error; 1044 1045 struct drm_i915_gem_object *vlv_pctx; 1046 1047 /* list of fbdev register on this device */ 1048 struct intel_fbdev *fbdev; 1049 struct work_struct fbdev_suspend_work; 1050 1051 struct drm_property *broadcast_rgb_property; 1052 struct drm_property *force_audio_property; 1053 1054 /* hda/i915 audio component */ 1055 struct i915_audio_component *audio_component; 1056 bool audio_component_registered; 1057 /** 1058 * av_mutex - mutex for audio/video sync 1059 * 1060 */ 1061 struct mutex av_mutex; 1062 int audio_power_refcount; 1063 u32 audio_freq_cntrl; 1064 1065 u32 fdi_rx_config; 1066 1067 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1068 u32 chv_phy_control; 1069 /* 1070 * Shadows for CHV DPLL_MD regs to keep the state 1071 * checker somewhat working in the presence hardware 1072 * crappiness (can't read out DPLL_MD for pipes B & C). 1073 */ 1074 u32 chv_dpll_md[I915_MAX_PIPES]; 1075 u32 bxt_phy_grc; 1076 1077 u32 suspend_count; 1078 bool power_domains_suspended; 1079 struct i915_suspend_saved_registers regfile; 1080 struct vlv_s0ix_state *vlv_s0ix_state; 1081 1082 enum { 1083 I915_SAGV_UNKNOWN = 0, 1084 I915_SAGV_DISABLED, 1085 I915_SAGV_ENABLED, 1086 I915_SAGV_NOT_CONTROLLED 1087 } sagv_status; 1088 1089 u32 sagv_block_time_us; 1090 1091 struct { 1092 /* 1093 * Raw watermark latency values: 1094 * in 0.1us units for WM0, 1095 * in 0.5us units for WM1+. 1096 */ 1097 /* primary */ 1098 u16 pri_latency[5]; 1099 /* sprite */ 1100 u16 spr_latency[5]; 1101 /* cursor */ 1102 u16 cur_latency[5]; 1103 /* 1104 * Raw watermark memory latency values 1105 * for SKL for all 8 levels 1106 * in 1us units. 1107 */ 1108 u16 skl_latency[8]; 1109 1110 /* current hardware state */ 1111 union { 1112 struct ilk_wm_values hw; 1113 struct vlv_wm_values vlv; 1114 struct g4x_wm_values g4x; 1115 }; 1116 1117 u8 max_level; 1118 1119 /* 1120 * Should be held around atomic WM register writing; also 1121 * protects * intel_crtc->wm.active and 1122 * crtc_state->wm.need_postvbl_update. 1123 */ 1124 struct mutex wm_mutex; 1125 1126 /* 1127 * Set during HW readout of watermarks/DDB. Some platforms 1128 * need to know when we're still using BIOS-provided values 1129 * (which we don't fully trust). 1130 * 1131 * FIXME get rid of this. 1132 */ 1133 bool distrust_bios_wm; 1134 } wm; 1135 1136 struct dram_info { 1137 bool valid; 1138 bool is_16gb_dimm; 1139 u8 num_channels; 1140 u8 ranks; 1141 u32 bandwidth_kbps; 1142 bool symmetric_memory; 1143 enum intel_dram_type { 1144 INTEL_DRAM_UNKNOWN, 1145 INTEL_DRAM_DDR3, 1146 INTEL_DRAM_DDR4, 1147 INTEL_DRAM_LPDDR3, 1148 INTEL_DRAM_LPDDR4 1149 } type; 1150 } dram_info; 1151 1152 struct intel_bw_info { 1153 /* for each QGV point */ 1154 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1155 u8 num_qgv_points; 1156 u8 num_planes; 1157 } max_bw[6]; 1158 1159 struct intel_global_obj bw_obj; 1160 1161 struct intel_runtime_pm runtime_pm; 1162 1163 struct i915_perf perf; 1164 1165 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1166 struct intel_gt gt; 1167 1168 struct { 1169 struct i915_gem_contexts { 1170 spinlock_t lock; /* locks list */ 1171 struct list_head list; 1172 1173 struct llist_head free_list; 1174 struct work_struct free_work; 1175 } contexts; 1176 1177 /* 1178 * We replace the local file with a global mappings as the 1179 * backing storage for the mmap is on the device and not 1180 * on the struct file, and we do not want to prolong the 1181 * lifetime of the local fd. To minimise the number of 1182 * anonymous inodes we create, we use a global singleton to 1183 * share the global mapping. 1184 */ 1185 struct file *mmap_singleton; 1186 } gem; 1187 1188 u8 pch_ssc_use; 1189 1190 /* For i915gm/i945gm vblank irq workaround */ 1191 u8 vblank_enabled; 1192 1193 /* perform PHY state sanity checks? */ 1194 bool chv_phy_assert[2]; 1195 1196 bool ipc_enabled; 1197 1198 /* Used to save the pipe-to-encoder mapping for audio */ 1199 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1200 1201 /* necessary resource sharing with HDMI LPE audio driver. */ 1202 struct { 1203 struct platform_device *platdev; 1204 int irq; 1205 } lpe_audio; 1206 1207 struct i915_pmu pmu; 1208 1209 struct i915_hdcp_comp_master *hdcp_master; 1210 bool hdcp_comp_added; 1211 1212 /* Mutex to protect the above hdcp component related values. */ 1213 struct mutex hdcp_comp_mutex; 1214 1215 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1216 1217 /* 1218 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1219 * will be rejected. Instead look for a better place. 1220 */ 1221 }; 1222 1223 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1224 { 1225 return container_of(dev, struct drm_i915_private, drm); 1226 } 1227 1228 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1229 { 1230 return dev_get_drvdata(kdev); 1231 } 1232 1233 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1234 { 1235 return pci_get_drvdata(pdev); 1236 } 1237 1238 /* Simple iterator over all initialised engines */ 1239 #define for_each_engine(engine__, dev_priv__, id__) \ 1240 for ((id__) = 0; \ 1241 (id__) < I915_NUM_ENGINES; \ 1242 (id__)++) \ 1243 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1244 1245 /* Iterator over subset of engines selected by mask */ 1246 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1247 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 1248 (tmp__) ? \ 1249 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1250 0;) 1251 1252 #define rb_to_uabi_engine(rb) \ 1253 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1254 1255 #define for_each_uabi_engine(engine__, i915__) \ 1256 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1257 (engine__); \ 1258 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1259 1260 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 1261 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 1262 (engine__) && (engine__)->uabi_class == (class__); \ 1263 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1264 1265 #define I915_GTT_OFFSET_NONE ((u32)-1) 1266 1267 /* 1268 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1269 * considered to be the frontbuffer for the given plane interface-wise. This 1270 * doesn't mean that the hw necessarily already scans it out, but that any 1271 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1272 * 1273 * We have one bit per pipe and per scanout plane type. 1274 */ 1275 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1276 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1277 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1278 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1279 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1280 }) 1281 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1282 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1283 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1284 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1285 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1286 1287 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1288 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1289 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1290 1291 #define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen) 1292 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1293 1294 #define REVID_FOREVER 0xff 1295 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) 1296 1297 #define INTEL_GEN_MASK(s, e) ( \ 1298 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ 1299 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ 1300 GENMASK((e) - 1, (s) - 1)) 1301 1302 /* Returns true if Gen is in inclusive range [Start, End] */ 1303 #define IS_GEN_RANGE(dev_priv, s, e) \ 1304 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e)))) 1305 1306 #define IS_GEN(dev_priv, n) \ 1307 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ 1308 INTEL_INFO(dev_priv)->gen == (n)) 1309 1310 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1311 1312 /* 1313 * Return true if revision is in range [since,until] inclusive. 1314 * 1315 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1316 */ 1317 #define IS_REVID(p, since, until) \ 1318 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1319 1320 static __always_inline unsigned int 1321 __platform_mask_index(const struct intel_runtime_info *info, 1322 enum intel_platform p) 1323 { 1324 const unsigned int pbits = 1325 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1326 1327 /* Expand the platform_mask array if this fails. */ 1328 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1329 pbits * ARRAY_SIZE(info->platform_mask)); 1330 1331 return p / pbits; 1332 } 1333 1334 static __always_inline unsigned int 1335 __platform_mask_bit(const struct intel_runtime_info *info, 1336 enum intel_platform p) 1337 { 1338 const unsigned int pbits = 1339 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1340 1341 return p % pbits + INTEL_SUBPLATFORM_BITS; 1342 } 1343 1344 static inline u32 1345 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1346 { 1347 const unsigned int pi = __platform_mask_index(info, p); 1348 1349 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS; 1350 } 1351 1352 static __always_inline bool 1353 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1354 { 1355 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1356 const unsigned int pi = __platform_mask_index(info, p); 1357 const unsigned int pb = __platform_mask_bit(info, p); 1358 1359 BUILD_BUG_ON(!__builtin_constant_p(p)); 1360 1361 return info->platform_mask[pi] & BIT(pb); 1362 } 1363 1364 static __always_inline bool 1365 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1366 enum intel_platform p, unsigned int s) 1367 { 1368 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1369 const unsigned int pi = __platform_mask_index(info, p); 1370 const unsigned int pb = __platform_mask_bit(info, p); 1371 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1372 const u32 mask = info->platform_mask[pi]; 1373 1374 BUILD_BUG_ON(!__builtin_constant_p(p)); 1375 BUILD_BUG_ON(!__builtin_constant_p(s)); 1376 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1377 1378 /* Shift and test on the MSB position so sign flag can be used. */ 1379 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1380 } 1381 1382 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1383 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1384 1385 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1386 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1387 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1388 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1389 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1390 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1391 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1392 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1393 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1394 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1395 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1396 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1397 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1398 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1399 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1400 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1401 #define IS_IRONLAKE_M(dev_priv) \ 1402 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1403 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1404 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1405 INTEL_INFO(dev_priv)->gt == 1) 1406 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1407 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1408 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1409 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1410 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1411 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1412 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1413 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1414 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1415 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 1416 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1417 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1418 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 1419 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1420 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1421 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 1422 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 1423 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1424 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1425 #define IS_BDW_ULT(dev_priv) \ 1426 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1427 #define IS_BDW_ULX(dev_priv) \ 1428 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1429 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1430 INTEL_INFO(dev_priv)->gt == 3) 1431 #define IS_HSW_ULT(dev_priv) \ 1432 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1433 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1434 INTEL_INFO(dev_priv)->gt == 3) 1435 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1436 INTEL_INFO(dev_priv)->gt == 1) 1437 /* ULX machines are also considered ULT. */ 1438 #define IS_HSW_ULX(dev_priv) \ 1439 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1440 #define IS_SKL_ULT(dev_priv) \ 1441 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1442 #define IS_SKL_ULX(dev_priv) \ 1443 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1444 #define IS_KBL_ULT(dev_priv) \ 1445 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1446 #define IS_KBL_ULX(dev_priv) \ 1447 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1448 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1449 INTEL_INFO(dev_priv)->gt == 2) 1450 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1451 INTEL_INFO(dev_priv)->gt == 3) 1452 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1453 INTEL_INFO(dev_priv)->gt == 4) 1454 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1455 INTEL_INFO(dev_priv)->gt == 2) 1456 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1457 INTEL_INFO(dev_priv)->gt == 3) 1458 #define IS_CFL_ULT(dev_priv) \ 1459 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1460 #define IS_CFL_ULX(dev_priv) \ 1461 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1462 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1463 INTEL_INFO(dev_priv)->gt == 2) 1464 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1465 INTEL_INFO(dev_priv)->gt == 3) 1466 1467 #define IS_CML_ULT(dev_priv) \ 1468 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 1469 #define IS_CML_ULX(dev_priv) \ 1470 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 1471 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 1472 INTEL_INFO(dev_priv)->gt == 2) 1473 1474 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1475 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1476 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1477 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1478 1479 #define IS_TGL_U(dev_priv) \ 1480 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) 1481 1482 #define IS_TGL_Y(dev_priv) \ 1483 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) 1484 1485 #define SKL_REVID_A0 0x0 1486 #define SKL_REVID_B0 0x1 1487 #define SKL_REVID_C0 0x2 1488 #define SKL_REVID_D0 0x3 1489 #define SKL_REVID_E0 0x4 1490 #define SKL_REVID_F0 0x5 1491 #define SKL_REVID_G0 0x6 1492 #define SKL_REVID_H0 0x7 1493 1494 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1495 1496 #define BXT_REVID_A0 0x0 1497 #define BXT_REVID_A1 0x1 1498 #define BXT_REVID_B0 0x3 1499 #define BXT_REVID_B_LAST 0x8 1500 #define BXT_REVID_C0 0x9 1501 1502 #define IS_BXT_REVID(dev_priv, since, until) \ 1503 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1504 1505 enum { 1506 KBL_REVID_A0, 1507 KBL_REVID_B0, 1508 KBL_REVID_B1, 1509 KBL_REVID_C0, 1510 KBL_REVID_D0, 1511 KBL_REVID_D1, 1512 KBL_REVID_E0, 1513 KBL_REVID_F0, 1514 KBL_REVID_G0, 1515 }; 1516 1517 struct i915_rev_steppings { 1518 u8 gt_stepping; 1519 u8 disp_stepping; 1520 }; 1521 1522 /* Defined in intel_workarounds.c */ 1523 extern const struct i915_rev_steppings kbl_revids[]; 1524 1525 #define IS_KBL_GT_REVID(dev_priv, since, until) \ 1526 (IS_KABYLAKE(dev_priv) && \ 1527 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \ 1528 kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until) 1529 #define IS_KBL_DISP_REVID(dev_priv, since, until) \ 1530 (IS_KABYLAKE(dev_priv) && \ 1531 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \ 1532 kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until) 1533 1534 #define GLK_REVID_A0 0x0 1535 #define GLK_REVID_A1 0x1 1536 #define GLK_REVID_A2 0x2 1537 #define GLK_REVID_B0 0x3 1538 1539 #define IS_GLK_REVID(dev_priv, since, until) \ 1540 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1541 1542 #define CNL_REVID_A0 0x0 1543 #define CNL_REVID_B0 0x1 1544 #define CNL_REVID_C0 0x2 1545 1546 #define IS_CNL_REVID(p, since, until) \ 1547 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1548 1549 #define ICL_REVID_A0 0x0 1550 #define ICL_REVID_A2 0x1 1551 #define ICL_REVID_B0 0x3 1552 #define ICL_REVID_B2 0x4 1553 #define ICL_REVID_C0 0x5 1554 1555 #define IS_ICL_REVID(p, since, until) \ 1556 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1557 1558 #define EHL_REVID_A0 0x0 1559 #define EHL_REVID_B0 0x1 1560 1561 #define IS_JSL_EHL_REVID(p, since, until) \ 1562 (IS_JSL_EHL(p) && IS_REVID(p, since, until)) 1563 1564 enum { 1565 TGL_REVID_A0, 1566 TGL_REVID_B0, 1567 TGL_REVID_B1, 1568 TGL_REVID_C0, 1569 TGL_REVID_D0, 1570 }; 1571 1572 extern const struct i915_rev_steppings tgl_uy_revids[]; 1573 extern const struct i915_rev_steppings tgl_revids[]; 1574 1575 static inline const struct i915_rev_steppings * 1576 tgl_revids_get(struct drm_i915_private *dev_priv) 1577 { 1578 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) 1579 return &tgl_uy_revids[INTEL_REVID(dev_priv)]; 1580 else 1581 return &tgl_revids[INTEL_REVID(dev_priv)]; 1582 } 1583 1584 #define IS_TGL_DISP_REVID(p, since, until) \ 1585 (IS_TIGERLAKE(p) && \ 1586 tgl_revids_get(p)->disp_stepping >= (since) && \ 1587 tgl_revids_get(p)->disp_stepping <= (until)) 1588 1589 #define IS_TGL_UY_GT_REVID(p, since, until) \ 1590 ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ 1591 tgl_uy_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ 1592 tgl_uy_revids[INTEL_REVID(p)].gt_stepping <= (until)) 1593 1594 #define IS_TGL_GT_REVID(p, since, until) \ 1595 (IS_TIGERLAKE(p) && \ 1596 !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ 1597 tgl_revids[INTEL_REVID(p)].gt_stepping >= (since) && \ 1598 tgl_revids[INTEL_REVID(p)].gt_stepping <= (until)) 1599 1600 #define RKL_REVID_A0 0x0 1601 #define RKL_REVID_B0 0x1 1602 #define RKL_REVID_C0 0x4 1603 1604 #define IS_RKL_REVID(p, since, until) \ 1605 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) 1606 1607 #define DG1_REVID_A0 0x0 1608 #define DG1_REVID_B0 0x1 1609 1610 #define IS_DG1_REVID(p, since, until) \ 1611 (IS_DG1(p) && IS_REVID(p, since, until)) 1612 1613 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1614 #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) 1615 #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv)) 1616 1617 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 1618 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 1619 1620 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 1621 unsigned int first__ = (first); \ 1622 unsigned int count__ = (count); \ 1623 ((gt)->info.engine_mask & \ 1624 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1625 }) 1626 #define VDBOX_MASK(gt) \ 1627 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 1628 #define VEBOX_MASK(gt) \ 1629 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 1630 1631 /* 1632 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1633 * All later gens can run the final buffer from the ppgtt 1634 */ 1635 #define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7) 1636 1637 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1638 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1639 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1640 #define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6) 1641 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 1642 1643 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1644 1645 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1646 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1647 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1648 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1649 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ 1650 (INTEL_INFO(dev_priv)->has_logical_ring_preemption) 1651 1652 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq) 1653 1654 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1655 1656 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1657 #define HAS_PPGTT(dev_priv) \ 1658 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1659 #define HAS_FULL_PPGTT(dev_priv) \ 1660 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1661 1662 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1663 GEM_BUG_ON((sizes) == 0); \ 1664 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1665 }) 1666 1667 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1668 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1669 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1670 1671 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1672 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1673 1674 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1675 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1676 1677 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1678 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1679 (IS_CANNONLAKE(dev_priv) || \ 1680 IS_SKL_GT3(dev_priv) || \ 1681 IS_SKL_GT4(dev_priv)) 1682 1683 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1684 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ 1685 IS_GEMINILAKE(dev_priv) || \ 1686 IS_KABYLAKE(dev_priv)) 1687 1688 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1689 * rows, which changed the alignment requirements and fence programming. 1690 */ 1691 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \ 1692 !(IS_I915G(dev_priv) || \ 1693 IS_I915GM(dev_priv))) 1694 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1695 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1696 1697 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 1698 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1699 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7) 1700 1701 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1702 1703 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1704 1705 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1706 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg) 1707 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1708 #define HAS_PSR_HW_TRACKING(dev_priv) \ 1709 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 1710 #define HAS_PSR2_SEL_FETCH(dev_priv) (INTEL_GEN(dev_priv) >= 12) 1711 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1712 1713 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1714 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1715 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1716 1717 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1718 1719 #define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr) 1720 1721 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1722 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1723 1724 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1725 1726 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1727 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1728 1729 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1730 1731 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1732 1733 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1734 1735 1736 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1737 1738 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 1739 1740 /* DPF == dynamic parity feature */ 1741 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1742 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1743 2 : HAS_L3_DPF(dev_priv)) 1744 1745 #define GT_FREQUENCY_MULTIPLIER 50 1746 #define GEN9_FREQ_SCALER 3 1747 1748 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1749 1750 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1751 1752 /* Only valid when HAS_DISPLAY() is true */ 1753 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 1754 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) 1755 1756 static inline bool intel_vtd_active(void) 1757 { 1758 #ifdef CONFIG_INTEL_IOMMU 1759 if (intel_iommu_gfx_mapped) 1760 return true; 1761 #endif 1762 1763 /* Running as a guest, we assume the host is enforcing VT'd */ 1764 return !hypervisor_is_type(X86_HYPER_NATIVE); 1765 } 1766 1767 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1768 { 1769 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); 1770 } 1771 1772 static inline bool 1773 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) 1774 { 1775 return IS_BROXTON(dev_priv) && intel_vtd_active(); 1776 } 1777 1778 /* i915_drv.c */ 1779 extern const struct dev_pm_ops i915_pm_ops; 1780 1781 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1782 void i915_driver_remove(struct drm_i915_private *i915); 1783 void i915_driver_shutdown(struct drm_i915_private *i915); 1784 1785 int i915_resume_switcheroo(struct drm_i915_private *i915); 1786 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1787 1788 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1789 struct drm_file *file_priv); 1790 1791 /* i915_gem.c */ 1792 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1793 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1794 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1795 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1796 int i915_gem_freeze(struct drm_i915_private *dev_priv); 1797 int i915_gem_freeze_late(struct drm_i915_private *dev_priv); 1798 1799 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915); 1800 1801 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1802 { 1803 /* 1804 * A single pass should suffice to release all the freed objects (along 1805 * most call paths) , but be a little more paranoid in that freeing 1806 * the objects does take a little amount of time, during which the rcu 1807 * callbacks could have added new objects into the freed list, and 1808 * armed the work again. 1809 */ 1810 while (atomic_read(&i915->mm.free_count)) { 1811 flush_work(&i915->mm.free_work); 1812 rcu_barrier(); 1813 } 1814 } 1815 1816 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1817 { 1818 /* 1819 * Similar to objects above (see i915_gem_drain_freed-objects), in 1820 * general we have workers that are armed by RCU and then rearm 1821 * themselves in their callbacks. To be paranoid, we need to 1822 * drain the workqueue a second time after waiting for the RCU 1823 * grace period so that we catch work queued via RCU from the first 1824 * pass. As neither drain_workqueue() nor flush_workqueue() report 1825 * a result, we make an assumption that we only don't require more 1826 * than 3 passes to catch all _recursive_ RCU delayed work. 1827 * 1828 */ 1829 int pass = 3; 1830 do { 1831 flush_workqueue(i915->wq); 1832 rcu_barrier(); 1833 i915_gem_drain_freed_objects(i915); 1834 } while (--pass); 1835 drain_workqueue(i915->wq); 1836 } 1837 1838 struct i915_vma * __must_check 1839 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, 1840 struct i915_gem_ww_ctx *ww, 1841 const struct i915_ggtt_view *view, 1842 u64 size, u64 alignment, u64 flags); 1843 1844 static inline struct i915_vma * __must_check 1845 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1846 const struct i915_ggtt_view *view, 1847 u64 size, u64 alignment, u64 flags) 1848 { 1849 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); 1850 } 1851 1852 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1853 unsigned long flags); 1854 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1855 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1856 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1857 1858 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1859 1860 int i915_gem_dumb_create(struct drm_file *file_priv, 1861 struct drm_device *dev, 1862 struct drm_mode_create_dumb *args); 1863 1864 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1865 1866 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1867 { 1868 return atomic_read(&error->reset_count); 1869 } 1870 1871 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1872 const struct intel_engine_cs *engine) 1873 { 1874 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1875 } 1876 1877 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1878 void i915_gem_driver_register(struct drm_i915_private *i915); 1879 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1880 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1881 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1882 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1883 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1884 void i915_gem_resume(struct drm_i915_private *dev_priv); 1885 1886 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1887 1888 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1889 enum i915_cache_level cache_level); 1890 1891 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1892 struct dma_buf *dma_buf); 1893 1894 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1895 1896 static inline struct i915_gem_context * 1897 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1898 { 1899 return xa_load(&file_priv->context_xa, id); 1900 } 1901 1902 static inline struct i915_gem_context * 1903 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1904 { 1905 struct i915_gem_context *ctx; 1906 1907 rcu_read_lock(); 1908 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1909 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1910 ctx = NULL; 1911 rcu_read_unlock(); 1912 1913 return ctx; 1914 } 1915 1916 /* i915_gem_evict.c */ 1917 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1918 u64 min_size, u64 alignment, 1919 unsigned long color, 1920 u64 start, u64 end, 1921 unsigned flags); 1922 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1923 struct drm_mm_node *node, 1924 unsigned int flags); 1925 int i915_gem_evict_vm(struct i915_address_space *vm); 1926 1927 /* i915_gem_internal.c */ 1928 struct drm_i915_gem_object * 1929 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1930 phys_addr_t size); 1931 1932 /* i915_gem_tiling.c */ 1933 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1934 { 1935 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1936 1937 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1938 i915_gem_object_is_tiled(obj); 1939 } 1940 1941 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1942 unsigned int tiling, unsigned int stride); 1943 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1944 unsigned int tiling, unsigned int stride); 1945 1946 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1947 1948 /* i915_cmd_parser.c */ 1949 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1950 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1951 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1952 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1953 struct i915_vma *batch, 1954 unsigned long batch_offset, 1955 unsigned long batch_length, 1956 struct i915_vma *shadow, 1957 bool trampoline); 1958 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1959 1960 /* intel_device_info.c */ 1961 static inline struct intel_device_info * 1962 mkwrite_device_info(struct drm_i915_private *dev_priv) 1963 { 1964 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1965 } 1966 1967 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1968 struct drm_file *file); 1969 1970 #define __I915_REG_OP(op__, dev_priv__, ...) \ 1971 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__) 1972 1973 #define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__)) 1974 #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__)) 1975 1976 #define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__)) 1977 1978 /* These are untraced mmio-accessors that are only valid to be used inside 1979 * critical sections, such as inside IRQ handlers, where forcewake is explicitly 1980 * controlled. 1981 * 1982 * Think twice, and think again, before using these. 1983 * 1984 * As an example, these accessors can possibly be used between: 1985 * 1986 * spin_lock_irq(&dev_priv->uncore.lock); 1987 * intel_uncore_forcewake_get__locked(); 1988 * 1989 * and 1990 * 1991 * intel_uncore_forcewake_put__locked(); 1992 * spin_unlock_irq(&dev_priv->uncore.lock); 1993 * 1994 * 1995 * Note: some registers may not need forcewake held, so 1996 * intel_uncore_forcewake_{get,put} can be omitted, see 1997 * intel_uncore_forcewake_for_reg(). 1998 * 1999 * Certain architectures will die if the same cacheline is concurrently accessed 2000 * by different clients (e.g. on Ivybridge). Access to registers should 2001 * therefore generally be serialised, by either the dev_priv->uncore.lock or 2002 * a more localised lock guarding all access to that bank of registers. 2003 */ 2004 #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__)) 2005 #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__)) 2006 2007 /* i915_mm.c */ 2008 int remap_io_mapping(struct vm_area_struct *vma, 2009 unsigned long addr, unsigned long pfn, unsigned long size, 2010 struct io_mapping *iomap); 2011 int remap_io_sg(struct vm_area_struct *vma, 2012 unsigned long addr, unsigned long size, 2013 struct scatterlist *sgl, resource_size_t iobase); 2014 2015 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 2016 { 2017 if (INTEL_GEN(i915) >= 10) 2018 return CNL_HWS_CSB_WRITE_INDEX; 2019 else 2020 return I915_HWS_CSB_WRITE_INDEX; 2021 } 2022 2023 static inline enum i915_map_type 2024 i915_coherent_map_type(struct drm_i915_private *i915) 2025 { 2026 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC; 2027 } 2028 2029 static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val) 2030 { 2031 return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz, 2032 1000000000); 2033 } 2034 2035 static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val) 2036 { 2037 return div_u64(val * 1000000000, 2038 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz); 2039 } 2040 2041 #endif 2042