1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <drm/intel-gtt.h> 42 #include <linux/backlight.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/pm_qos.h> 46 47 /* General customization: 48 */ 49 50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 51 52 #define DRIVER_NAME "i915" 53 #define DRIVER_DESC "Intel Graphics" 54 #define DRIVER_DATE "20080730" 55 56 enum pipe { 57 PIPE_A = 0, 58 PIPE_B, 59 PIPE_C, 60 I915_MAX_PIPES 61 }; 62 #define pipe_name(p) ((p) + 'A') 63 64 enum transcoder { 65 TRANSCODER_A = 0, 66 TRANSCODER_B, 67 TRANSCODER_C, 68 TRANSCODER_EDP = 0xF, 69 }; 70 #define transcoder_name(t) ((t) + 'A') 71 72 enum plane { 73 PLANE_A = 0, 74 PLANE_B, 75 PLANE_C, 76 }; 77 #define plane_name(p) ((p) + 'A') 78 79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') 80 81 enum port { 82 PORT_A = 0, 83 PORT_B, 84 PORT_C, 85 PORT_D, 86 PORT_E, 87 I915_MAX_PORTS 88 }; 89 #define port_name(p) ((p) + 'A') 90 91 enum intel_display_power_domain { 92 POWER_DOMAIN_PIPE_A, 93 POWER_DOMAIN_PIPE_B, 94 POWER_DOMAIN_PIPE_C, 95 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 96 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 97 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 98 POWER_DOMAIN_TRANSCODER_A, 99 POWER_DOMAIN_TRANSCODER_B, 100 POWER_DOMAIN_TRANSCODER_C, 101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF, 102 }; 103 104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A) 108 109 enum hpd_pin { 110 HPD_NONE = 0, 111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 113 HPD_CRT, 114 HPD_SDVO_B, 115 HPD_SDVO_C, 116 HPD_PORT_B, 117 HPD_PORT_C, 118 HPD_PORT_D, 119 HPD_NUM_PINS 120 }; 121 122 #define I915_GEM_GPU_DOMAINS \ 123 (I915_GEM_DOMAIN_RENDER | \ 124 I915_GEM_DOMAIN_SAMPLER | \ 125 I915_GEM_DOMAIN_COMMAND | \ 126 I915_GEM_DOMAIN_INSTRUCTION | \ 127 I915_GEM_DOMAIN_VERTEX) 128 129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 130 131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 133 if ((intel_encoder)->base.crtc == (__crtc)) 134 135 struct drm_i915_private; 136 137 enum intel_dpll_id { 138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 139 /* real shared dpll ids must be >= 0 */ 140 DPLL_ID_PCH_PLL_A, 141 DPLL_ID_PCH_PLL_B, 142 }; 143 #define I915_NUM_PLLS 2 144 145 struct intel_dpll_hw_state { 146 uint32_t dpll; 147 uint32_t dpll_md; 148 uint32_t fp0; 149 uint32_t fp1; 150 }; 151 152 struct intel_shared_dpll { 153 int refcount; /* count of number of CRTCs sharing this PLL */ 154 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 155 bool on; /* is the PLL actually active? Disabled during modeset */ 156 const char *name; 157 /* should match the index in the dev_priv->shared_dplls array */ 158 enum intel_dpll_id id; 159 struct intel_dpll_hw_state hw_state; 160 void (*mode_set)(struct drm_i915_private *dev_priv, 161 struct intel_shared_dpll *pll); 162 void (*enable)(struct drm_i915_private *dev_priv, 163 struct intel_shared_dpll *pll); 164 void (*disable)(struct drm_i915_private *dev_priv, 165 struct intel_shared_dpll *pll); 166 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 167 struct intel_shared_dpll *pll, 168 struct intel_dpll_hw_state *hw_state); 169 }; 170 171 /* Used by dp and fdi links */ 172 struct intel_link_m_n { 173 uint32_t tu; 174 uint32_t gmch_m; 175 uint32_t gmch_n; 176 uint32_t link_m; 177 uint32_t link_n; 178 }; 179 180 void intel_link_compute_m_n(int bpp, int nlanes, 181 int pixel_clock, int link_clock, 182 struct intel_link_m_n *m_n); 183 184 struct intel_ddi_plls { 185 int spll_refcount; 186 int wrpll1_refcount; 187 int wrpll2_refcount; 188 }; 189 190 /* Interface history: 191 * 192 * 1.1: Original. 193 * 1.2: Add Power Management 194 * 1.3: Add vblank support 195 * 1.4: Fix cmdbuffer path, add heap destroy 196 * 1.5: Add vblank pipe configuration 197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 198 * - Support vertical blank on secondary display pipe 199 */ 200 #define DRIVER_MAJOR 1 201 #define DRIVER_MINOR 6 202 #define DRIVER_PATCHLEVEL 0 203 204 #define WATCH_LISTS 0 205 #define WATCH_GTT 0 206 207 #define I915_GEM_PHYS_CURSOR_0 1 208 #define I915_GEM_PHYS_CURSOR_1 2 209 #define I915_GEM_PHYS_OVERLAY_REGS 3 210 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 211 212 struct drm_i915_gem_phys_object { 213 int id; 214 struct page **page_list; 215 drm_dma_handle_t *handle; 216 struct drm_i915_gem_object *cur_obj; 217 }; 218 219 struct opregion_header; 220 struct opregion_acpi; 221 struct opregion_swsci; 222 struct opregion_asle; 223 224 struct intel_opregion { 225 struct opregion_header __iomem *header; 226 struct opregion_acpi __iomem *acpi; 227 struct opregion_swsci __iomem *swsci; 228 struct opregion_asle __iomem *asle; 229 void __iomem *vbt; 230 u32 __iomem *lid_state; 231 }; 232 #define OPREGION_SIZE (8*1024) 233 234 struct intel_overlay; 235 struct intel_overlay_error_state; 236 237 struct drm_i915_master_private { 238 drm_local_map_t *sarea; 239 struct _drm_i915_sarea *sarea_priv; 240 }; 241 #define I915_FENCE_REG_NONE -1 242 #define I915_MAX_NUM_FENCES 32 243 /* 32 fences + sign bit for FENCE_REG_NONE */ 244 #define I915_MAX_NUM_FENCE_BITS 6 245 246 struct drm_i915_fence_reg { 247 struct list_head lru_list; 248 struct drm_i915_gem_object *obj; 249 int pin_count; 250 }; 251 252 struct sdvo_device_mapping { 253 u8 initialized; 254 u8 dvo_port; 255 u8 slave_addr; 256 u8 dvo_wiring; 257 u8 i2c_pin; 258 u8 ddc_pin; 259 }; 260 261 struct intel_display_error_state; 262 263 struct drm_i915_error_state { 264 struct kref ref; 265 u32 eir; 266 u32 pgtbl_er; 267 u32 ier; 268 u32 ccid; 269 u32 derrmr; 270 u32 forcewake; 271 bool waiting[I915_NUM_RINGS]; 272 u32 pipestat[I915_MAX_PIPES]; 273 u32 tail[I915_NUM_RINGS]; 274 u32 head[I915_NUM_RINGS]; 275 u32 ctl[I915_NUM_RINGS]; 276 u32 ipeir[I915_NUM_RINGS]; 277 u32 ipehr[I915_NUM_RINGS]; 278 u32 instdone[I915_NUM_RINGS]; 279 u32 acthd[I915_NUM_RINGS]; 280 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 281 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 282 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 283 /* our own tracking of ring head and tail */ 284 u32 cpu_ring_head[I915_NUM_RINGS]; 285 u32 cpu_ring_tail[I915_NUM_RINGS]; 286 u32 error; /* gen6+ */ 287 u32 err_int; /* gen7 */ 288 u32 instpm[I915_NUM_RINGS]; 289 u32 instps[I915_NUM_RINGS]; 290 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 291 u32 seqno[I915_NUM_RINGS]; 292 u64 bbaddr; 293 u32 fault_reg[I915_NUM_RINGS]; 294 u32 done_reg; 295 u32 faddr[I915_NUM_RINGS]; 296 u64 fence[I915_MAX_NUM_FENCES]; 297 struct timeval time; 298 struct drm_i915_error_ring { 299 struct drm_i915_error_object { 300 int page_count; 301 u32 gtt_offset; 302 u32 *pages[0]; 303 } *ringbuffer, *batchbuffer, *ctx; 304 struct drm_i915_error_request { 305 long jiffies; 306 u32 seqno; 307 u32 tail; 308 } *requests; 309 int num_requests; 310 } ring[I915_NUM_RINGS]; 311 struct drm_i915_error_buffer { 312 u32 size; 313 u32 name; 314 u32 rseqno, wseqno; 315 u32 gtt_offset; 316 u32 read_domains; 317 u32 write_domain; 318 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 319 s32 pinned:2; 320 u32 tiling:2; 321 u32 dirty:1; 322 u32 purgeable:1; 323 s32 ring:4; 324 u32 cache_level:2; 325 } **active_bo, **pinned_bo; 326 u32 *active_bo_count, *pinned_bo_count; 327 struct intel_overlay_error_state *overlay; 328 struct intel_display_error_state *display; 329 }; 330 331 struct intel_crtc_config; 332 struct intel_crtc; 333 struct intel_limit; 334 struct dpll; 335 336 struct drm_i915_display_funcs { 337 bool (*fbc_enabled)(struct drm_device *dev); 338 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 339 void (*disable_fbc)(struct drm_device *dev); 340 int (*get_display_clock_speed)(struct drm_device *dev); 341 int (*get_fifo_size)(struct drm_device *dev, int plane); 342 /** 343 * find_dpll() - Find the best values for the PLL 344 * @limit: limits for the PLL 345 * @crtc: current CRTC 346 * @target: target frequency in kHz 347 * @refclk: reference clock frequency in kHz 348 * @match_clock: if provided, @best_clock P divider must 349 * match the P divider from @match_clock 350 * used for LVDS downclocking 351 * @best_clock: best PLL values found 352 * 353 * Returns true on success, false on failure. 354 */ 355 bool (*find_dpll)(const struct intel_limit *limit, 356 struct drm_crtc *crtc, 357 int target, int refclk, 358 struct dpll *match_clock, 359 struct dpll *best_clock); 360 void (*update_wm)(struct drm_device *dev); 361 void (*update_sprite_wm)(struct drm_plane *plane, 362 struct drm_crtc *crtc, 363 uint32_t sprite_width, int pixel_size, 364 bool enable, bool scaled); 365 void (*modeset_global_resources)(struct drm_device *dev); 366 /* Returns the active state of the crtc, and if the crtc is active, 367 * fills out the pipe-config with the hw state. */ 368 bool (*get_pipe_config)(struct intel_crtc *, 369 struct intel_crtc_config *); 370 void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *); 371 int (*crtc_mode_set)(struct drm_crtc *crtc, 372 int x, int y, 373 struct drm_framebuffer *old_fb); 374 void (*crtc_enable)(struct drm_crtc *crtc); 375 void (*crtc_disable)(struct drm_crtc *crtc); 376 void (*off)(struct drm_crtc *crtc); 377 void (*write_eld)(struct drm_connector *connector, 378 struct drm_crtc *crtc); 379 void (*fdi_link_train)(struct drm_crtc *crtc); 380 void (*init_clock_gating)(struct drm_device *dev); 381 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 382 struct drm_framebuffer *fb, 383 struct drm_i915_gem_object *obj, 384 uint32_t flags); 385 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 386 int x, int y); 387 void (*hpd_irq_setup)(struct drm_device *dev); 388 /* clock updates for mode set */ 389 /* cursor updates */ 390 /* render clock increase/decrease */ 391 /* display clock increase/decrease */ 392 /* pll clock increase/decrease */ 393 }; 394 395 struct intel_uncore_funcs { 396 void (*force_wake_get)(struct drm_i915_private *dev_priv); 397 void (*force_wake_put)(struct drm_i915_private *dev_priv); 398 }; 399 400 struct intel_uncore { 401 spinlock_t lock; /** lock is also taken in irq contexts. */ 402 403 struct intel_uncore_funcs funcs; 404 405 unsigned fifo_count; 406 unsigned forcewake_count; 407 }; 408 409 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 410 func(is_mobile) sep \ 411 func(is_i85x) sep \ 412 func(is_i915g) sep \ 413 func(is_i945gm) sep \ 414 func(is_g33) sep \ 415 func(need_gfx_hws) sep \ 416 func(is_g4x) sep \ 417 func(is_pineview) sep \ 418 func(is_broadwater) sep \ 419 func(is_crestline) sep \ 420 func(is_ivybridge) sep \ 421 func(is_valleyview) sep \ 422 func(is_haswell) sep \ 423 func(has_force_wake) sep \ 424 func(has_fbc) sep \ 425 func(has_pipe_cxsr) sep \ 426 func(has_hotplug) sep \ 427 func(cursor_needs_physical) sep \ 428 func(has_overlay) sep \ 429 func(overlay_needs_physical) sep \ 430 func(supports_tv) sep \ 431 func(has_bsd_ring) sep \ 432 func(has_blt_ring) sep \ 433 func(has_vebox_ring) sep \ 434 func(has_llc) sep \ 435 func(has_ddi) sep \ 436 func(has_fpga_dbg) 437 438 #define DEFINE_FLAG(name) u8 name:1 439 #define SEP_SEMICOLON ; 440 441 struct intel_device_info { 442 u32 display_mmio_offset; 443 u8 num_pipes:3; 444 u8 gen; 445 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 446 }; 447 448 #undef DEFINE_FLAG 449 #undef SEP_SEMICOLON 450 451 enum i915_cache_level { 452 I915_CACHE_NONE = 0, 453 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 454 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 455 caches, eg sampler/render caches, and the 456 large Last-Level-Cache. LLC is coherent with 457 the CPU, but L3 is only visible to the GPU. */ 458 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 459 }; 460 461 typedef uint32_t gen6_gtt_pte_t; 462 463 struct i915_address_space { 464 struct drm_mm mm; 465 struct drm_device *dev; 466 struct list_head global_link; 467 unsigned long start; /* Start offset always 0 for dri2 */ 468 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 469 470 struct { 471 dma_addr_t addr; 472 struct page *page; 473 } scratch; 474 475 /** 476 * List of objects currently involved in rendering. 477 * 478 * Includes buffers having the contents of their GPU caches 479 * flushed, not necessarily primitives. last_rendering_seqno 480 * represents when the rendering involved will be completed. 481 * 482 * A reference is held on the buffer while on this list. 483 */ 484 struct list_head active_list; 485 486 /** 487 * LRU list of objects which are not in the ringbuffer and 488 * are ready to unbind, but are still in the GTT. 489 * 490 * last_rendering_seqno is 0 while an object is in this list. 491 * 492 * A reference is not held on the buffer while on this list, 493 * as merely being GTT-bound shouldn't prevent its being 494 * freed, and we'll pull it off the list in the free path. 495 */ 496 struct list_head inactive_list; 497 498 /* FIXME: Need a more generic return type */ 499 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 500 enum i915_cache_level level); 501 void (*clear_range)(struct i915_address_space *vm, 502 unsigned int first_entry, 503 unsigned int num_entries); 504 void (*insert_entries)(struct i915_address_space *vm, 505 struct sg_table *st, 506 unsigned int first_entry, 507 enum i915_cache_level cache_level); 508 void (*cleanup)(struct i915_address_space *vm); 509 }; 510 511 /* The Graphics Translation Table is the way in which GEN hardware translates a 512 * Graphics Virtual Address into a Physical Address. In addition to the normal 513 * collateral associated with any va->pa translations GEN hardware also has a 514 * portion of the GTT which can be mapped by the CPU and remain both coherent 515 * and correct (in cases like swizzling). That region is referred to as GMADR in 516 * the spec. 517 */ 518 struct i915_gtt { 519 struct i915_address_space base; 520 size_t stolen_size; /* Total size of stolen memory */ 521 522 unsigned long mappable_end; /* End offset that we can CPU map */ 523 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 524 phys_addr_t mappable_base; /* PA of our GMADR */ 525 526 /** "Graphics Stolen Memory" holds the global PTEs */ 527 void __iomem *gsm; 528 529 bool do_idle_maps; 530 531 int mtrr; 532 533 /* global gtt ops */ 534 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 535 size_t *stolen, phys_addr_t *mappable_base, 536 unsigned long *mappable_end); 537 }; 538 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 539 540 struct i915_hw_ppgtt { 541 struct i915_address_space base; 542 unsigned num_pd_entries; 543 struct page **pt_pages; 544 uint32_t pd_offset; 545 dma_addr_t *pt_dma_addr; 546 547 int (*enable)(struct drm_device *dev); 548 }; 549 550 /** 551 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 552 * VMA's presence cannot be guaranteed before binding, or after unbinding the 553 * object into/from the address space. 554 * 555 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 556 * will always be <= an objects lifetime. So object refcounting should cover us. 557 */ 558 struct i915_vma { 559 struct drm_mm_node node; 560 struct drm_i915_gem_object *obj; 561 struct i915_address_space *vm; 562 563 /** This object's place on the active/inactive lists */ 564 struct list_head mm_list; 565 566 struct list_head vma_link; /* Link in the object's VMA list */ 567 568 /** This vma's place in the batchbuffer or on the eviction list */ 569 struct list_head exec_list; 570 571 }; 572 573 struct i915_ctx_hang_stats { 574 /* This context had batch pending when hang was declared */ 575 unsigned batch_pending; 576 577 /* This context had batch active when hang was declared */ 578 unsigned batch_active; 579 }; 580 581 /* This must match up with the value previously used for execbuf2.rsvd1. */ 582 #define DEFAULT_CONTEXT_ID 0 583 struct i915_hw_context { 584 struct kref ref; 585 int id; 586 bool is_initialized; 587 struct drm_i915_file_private *file_priv; 588 struct intel_ring_buffer *ring; 589 struct drm_i915_gem_object *obj; 590 struct i915_ctx_hang_stats hang_stats; 591 }; 592 593 struct i915_fbc { 594 unsigned long size; 595 unsigned int fb_id; 596 enum plane plane; 597 int y; 598 599 struct drm_mm_node *compressed_fb; 600 struct drm_mm_node *compressed_llb; 601 602 struct intel_fbc_work { 603 struct delayed_work work; 604 struct drm_crtc *crtc; 605 struct drm_framebuffer *fb; 606 int interval; 607 } *fbc_work; 608 609 enum no_fbc_reason { 610 FBC_OK, /* FBC is enabled */ 611 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 612 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 613 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 614 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 615 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 616 FBC_BAD_PLANE, /* fbc not supported on plane */ 617 FBC_NOT_TILED, /* buffer not tiled */ 618 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 619 FBC_MODULE_PARAM, 620 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 621 } no_fbc_reason; 622 }; 623 624 enum no_psr_reason { 625 PSR_NO_SOURCE, /* Not supported on platform */ 626 PSR_NO_SINK, /* Not supported by panel */ 627 PSR_MODULE_PARAM, 628 PSR_CRTC_NOT_ACTIVE, 629 PSR_PWR_WELL_ENABLED, 630 PSR_NOT_TILED, 631 PSR_SPRITE_ENABLED, 632 PSR_S3D_ENABLED, 633 PSR_INTERLACED_ENABLED, 634 PSR_HSW_NOT_DDIA, 635 }; 636 637 enum intel_pch { 638 PCH_NONE = 0, /* No PCH present */ 639 PCH_IBX, /* Ibexpeak PCH */ 640 PCH_CPT, /* Cougarpoint PCH */ 641 PCH_LPT, /* Lynxpoint PCH */ 642 PCH_NOP, 643 }; 644 645 enum intel_sbi_destination { 646 SBI_ICLK, 647 SBI_MPHY, 648 }; 649 650 #define QUIRK_PIPEA_FORCE (1<<0) 651 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 652 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 653 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3) 654 655 struct intel_fbdev; 656 struct intel_fbc_work; 657 658 struct intel_gmbus { 659 struct i2c_adapter adapter; 660 u32 force_bit; 661 u32 reg0; 662 u32 gpio_reg; 663 struct i2c_algo_bit_data bit_algo; 664 struct drm_i915_private *dev_priv; 665 }; 666 667 struct i915_suspend_saved_registers { 668 u8 saveLBB; 669 u32 saveDSPACNTR; 670 u32 saveDSPBCNTR; 671 u32 saveDSPARB; 672 u32 savePIPEACONF; 673 u32 savePIPEBCONF; 674 u32 savePIPEASRC; 675 u32 savePIPEBSRC; 676 u32 saveFPA0; 677 u32 saveFPA1; 678 u32 saveDPLL_A; 679 u32 saveDPLL_A_MD; 680 u32 saveHTOTAL_A; 681 u32 saveHBLANK_A; 682 u32 saveHSYNC_A; 683 u32 saveVTOTAL_A; 684 u32 saveVBLANK_A; 685 u32 saveVSYNC_A; 686 u32 saveBCLRPAT_A; 687 u32 saveTRANSACONF; 688 u32 saveTRANS_HTOTAL_A; 689 u32 saveTRANS_HBLANK_A; 690 u32 saveTRANS_HSYNC_A; 691 u32 saveTRANS_VTOTAL_A; 692 u32 saveTRANS_VBLANK_A; 693 u32 saveTRANS_VSYNC_A; 694 u32 savePIPEASTAT; 695 u32 saveDSPASTRIDE; 696 u32 saveDSPASIZE; 697 u32 saveDSPAPOS; 698 u32 saveDSPAADDR; 699 u32 saveDSPASURF; 700 u32 saveDSPATILEOFF; 701 u32 savePFIT_PGM_RATIOS; 702 u32 saveBLC_HIST_CTL; 703 u32 saveBLC_PWM_CTL; 704 u32 saveBLC_PWM_CTL2; 705 u32 saveBLC_CPU_PWM_CTL; 706 u32 saveBLC_CPU_PWM_CTL2; 707 u32 saveFPB0; 708 u32 saveFPB1; 709 u32 saveDPLL_B; 710 u32 saveDPLL_B_MD; 711 u32 saveHTOTAL_B; 712 u32 saveHBLANK_B; 713 u32 saveHSYNC_B; 714 u32 saveVTOTAL_B; 715 u32 saveVBLANK_B; 716 u32 saveVSYNC_B; 717 u32 saveBCLRPAT_B; 718 u32 saveTRANSBCONF; 719 u32 saveTRANS_HTOTAL_B; 720 u32 saveTRANS_HBLANK_B; 721 u32 saveTRANS_HSYNC_B; 722 u32 saveTRANS_VTOTAL_B; 723 u32 saveTRANS_VBLANK_B; 724 u32 saveTRANS_VSYNC_B; 725 u32 savePIPEBSTAT; 726 u32 saveDSPBSTRIDE; 727 u32 saveDSPBSIZE; 728 u32 saveDSPBPOS; 729 u32 saveDSPBADDR; 730 u32 saveDSPBSURF; 731 u32 saveDSPBTILEOFF; 732 u32 saveVGA0; 733 u32 saveVGA1; 734 u32 saveVGA_PD; 735 u32 saveVGACNTRL; 736 u32 saveADPA; 737 u32 saveLVDS; 738 u32 savePP_ON_DELAYS; 739 u32 savePP_OFF_DELAYS; 740 u32 saveDVOA; 741 u32 saveDVOB; 742 u32 saveDVOC; 743 u32 savePP_ON; 744 u32 savePP_OFF; 745 u32 savePP_CONTROL; 746 u32 savePP_DIVISOR; 747 u32 savePFIT_CONTROL; 748 u32 save_palette_a[256]; 749 u32 save_palette_b[256]; 750 u32 saveDPFC_CB_BASE; 751 u32 saveFBC_CFB_BASE; 752 u32 saveFBC_LL_BASE; 753 u32 saveFBC_CONTROL; 754 u32 saveFBC_CONTROL2; 755 u32 saveIER; 756 u32 saveIIR; 757 u32 saveIMR; 758 u32 saveDEIER; 759 u32 saveDEIMR; 760 u32 saveGTIER; 761 u32 saveGTIMR; 762 u32 saveFDI_RXA_IMR; 763 u32 saveFDI_RXB_IMR; 764 u32 saveCACHE_MODE_0; 765 u32 saveMI_ARB_STATE; 766 u32 saveSWF0[16]; 767 u32 saveSWF1[16]; 768 u32 saveSWF2[3]; 769 u8 saveMSR; 770 u8 saveSR[8]; 771 u8 saveGR[25]; 772 u8 saveAR_INDEX; 773 u8 saveAR[21]; 774 u8 saveDACMASK; 775 u8 saveCR[37]; 776 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 777 u32 saveCURACNTR; 778 u32 saveCURAPOS; 779 u32 saveCURABASE; 780 u32 saveCURBCNTR; 781 u32 saveCURBPOS; 782 u32 saveCURBBASE; 783 u32 saveCURSIZE; 784 u32 saveDP_B; 785 u32 saveDP_C; 786 u32 saveDP_D; 787 u32 savePIPEA_GMCH_DATA_M; 788 u32 savePIPEB_GMCH_DATA_M; 789 u32 savePIPEA_GMCH_DATA_N; 790 u32 savePIPEB_GMCH_DATA_N; 791 u32 savePIPEA_DP_LINK_M; 792 u32 savePIPEB_DP_LINK_M; 793 u32 savePIPEA_DP_LINK_N; 794 u32 savePIPEB_DP_LINK_N; 795 u32 saveFDI_RXA_CTL; 796 u32 saveFDI_TXA_CTL; 797 u32 saveFDI_RXB_CTL; 798 u32 saveFDI_TXB_CTL; 799 u32 savePFA_CTL_1; 800 u32 savePFB_CTL_1; 801 u32 savePFA_WIN_SZ; 802 u32 savePFB_WIN_SZ; 803 u32 savePFA_WIN_POS; 804 u32 savePFB_WIN_POS; 805 u32 savePCH_DREF_CONTROL; 806 u32 saveDISP_ARB_CTL; 807 u32 savePIPEA_DATA_M1; 808 u32 savePIPEA_DATA_N1; 809 u32 savePIPEA_LINK_M1; 810 u32 savePIPEA_LINK_N1; 811 u32 savePIPEB_DATA_M1; 812 u32 savePIPEB_DATA_N1; 813 u32 savePIPEB_LINK_M1; 814 u32 savePIPEB_LINK_N1; 815 u32 saveMCHBAR_RENDER_STANDBY; 816 u32 savePCH_PORT_HOTPLUG; 817 }; 818 819 struct intel_gen6_power_mgmt { 820 /* work and pm_iir are protected by dev_priv->irq_lock */ 821 struct work_struct work; 822 u32 pm_iir; 823 824 /* On vlv we need to manually drop to Vmin with a delayed work. */ 825 struct delayed_work vlv_work; 826 827 /* The below variables an all the rps hw state are protected by 828 * dev->struct mutext. */ 829 u8 cur_delay; 830 u8 min_delay; 831 u8 max_delay; 832 u8 rpe_delay; 833 u8 hw_max; 834 835 struct delayed_work delayed_resume_work; 836 837 /* 838 * Protects RPS/RC6 register access and PCU communication. 839 * Must be taken after struct_mutex if nested. 840 */ 841 struct mutex hw_lock; 842 }; 843 844 /* defined intel_pm.c */ 845 extern spinlock_t mchdev_lock; 846 847 struct intel_ilk_power_mgmt { 848 u8 cur_delay; 849 u8 min_delay; 850 u8 max_delay; 851 u8 fmax; 852 u8 fstart; 853 854 u64 last_count1; 855 unsigned long last_time1; 856 unsigned long chipset_power; 857 u64 last_count2; 858 struct timespec last_time2; 859 unsigned long gfx_power; 860 u8 corr; 861 862 int c_m; 863 int r_t; 864 865 struct drm_i915_gem_object *pwrctx; 866 struct drm_i915_gem_object *renderctx; 867 }; 868 869 /* Power well structure for haswell */ 870 struct i915_power_well { 871 struct drm_device *device; 872 spinlock_t lock; 873 /* power well enable/disable usage count */ 874 int count; 875 int i915_request; 876 }; 877 878 struct i915_dri1_state { 879 unsigned allow_batchbuffer : 1; 880 u32 __iomem *gfx_hws_cpu_addr; 881 882 unsigned int cpp; 883 int back_offset; 884 int front_offset; 885 int current_page; 886 int page_flipping; 887 888 uint32_t counter; 889 }; 890 891 struct i915_ums_state { 892 /** 893 * Flag if the X Server, and thus DRM, is not currently in 894 * control of the device. 895 * 896 * This is set between LeaveVT and EnterVT. It needs to be 897 * replaced with a semaphore. It also needs to be 898 * transitioned away from for kernel modesetting. 899 */ 900 int mm_suspended; 901 }; 902 903 struct intel_l3_parity { 904 u32 *remap_info; 905 struct work_struct error_work; 906 }; 907 908 struct i915_gem_mm { 909 /** Memory allocator for GTT stolen memory */ 910 struct drm_mm stolen; 911 /** List of all objects in gtt_space. Used to restore gtt 912 * mappings on resume */ 913 struct list_head bound_list; 914 /** 915 * List of objects which are not bound to the GTT (thus 916 * are idle and not used by the GPU) but still have 917 * (presumably uncached) pages still attached. 918 */ 919 struct list_head unbound_list; 920 921 /** Usable portion of the GTT for GEM */ 922 unsigned long stolen_base; /* limited to low memory (32-bit) */ 923 924 /** PPGTT used for aliasing the PPGTT with the GTT */ 925 struct i915_hw_ppgtt *aliasing_ppgtt; 926 927 struct shrinker inactive_shrinker; 928 bool shrinker_no_lock_stealing; 929 930 /** LRU list of objects with fence regs on them. */ 931 struct list_head fence_list; 932 933 /** 934 * We leave the user IRQ off as much as possible, 935 * but this means that requests will finish and never 936 * be retired once the system goes idle. Set a timer to 937 * fire periodically while the ring is running. When it 938 * fires, go retire requests. 939 */ 940 struct delayed_work retire_work; 941 942 /** 943 * Are we in a non-interruptible section of code like 944 * modesetting? 945 */ 946 bool interruptible; 947 948 /** Bit 6 swizzling required for X tiling */ 949 uint32_t bit_6_swizzle_x; 950 /** Bit 6 swizzling required for Y tiling */ 951 uint32_t bit_6_swizzle_y; 952 953 /* storage for physical objects */ 954 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 955 956 /* accounting, useful for userland debugging */ 957 spinlock_t object_stat_lock; 958 size_t object_memory; 959 u32 object_count; 960 }; 961 962 struct drm_i915_error_state_buf { 963 unsigned bytes; 964 unsigned size; 965 int err; 966 u8 *buf; 967 loff_t start; 968 loff_t pos; 969 }; 970 971 struct i915_error_state_file_priv { 972 struct drm_device *dev; 973 struct drm_i915_error_state *error; 974 }; 975 976 struct i915_gpu_error { 977 /* For hangcheck timer */ 978 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 979 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 980 struct timer_list hangcheck_timer; 981 982 /* For reset and error_state handling. */ 983 spinlock_t lock; 984 /* Protected by the above dev->gpu_error.lock. */ 985 struct drm_i915_error_state *first_error; 986 struct work_struct work; 987 988 unsigned long last_reset; 989 990 /** 991 * State variable and reset counter controlling the reset flow 992 * 993 * Upper bits are for the reset counter. This counter is used by the 994 * wait_seqno code to race-free noticed that a reset event happened and 995 * that it needs to restart the entire ioctl (since most likely the 996 * seqno it waited for won't ever signal anytime soon). 997 * 998 * This is important for lock-free wait paths, where no contended lock 999 * naturally enforces the correct ordering between the bail-out of the 1000 * waiter and the gpu reset work code. 1001 * 1002 * Lowest bit controls the reset state machine: Set means a reset is in 1003 * progress. This state will (presuming we don't have any bugs) decay 1004 * into either unset (successful reset) or the special WEDGED value (hw 1005 * terminally sour). All waiters on the reset_queue will be woken when 1006 * that happens. 1007 */ 1008 atomic_t reset_counter; 1009 1010 /** 1011 * Special values/flags for reset_counter 1012 * 1013 * Note that the code relies on 1014 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG 1015 * being true. 1016 */ 1017 #define I915_RESET_IN_PROGRESS_FLAG 1 1018 #define I915_WEDGED 0xffffffff 1019 1020 /** 1021 * Waitqueue to signal when the reset has completed. Used by clients 1022 * that wait for dev_priv->mm.wedged to settle. 1023 */ 1024 wait_queue_head_t reset_queue; 1025 1026 /* For gpu hang simulation. */ 1027 unsigned int stop_rings; 1028 }; 1029 1030 enum modeset_restore { 1031 MODESET_ON_LID_OPEN, 1032 MODESET_DONE, 1033 MODESET_SUSPENDED, 1034 }; 1035 1036 struct intel_vbt_data { 1037 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1038 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1039 1040 /* Feature bits */ 1041 unsigned int int_tv_support:1; 1042 unsigned int lvds_dither:1; 1043 unsigned int lvds_vbt:1; 1044 unsigned int int_crt_support:1; 1045 unsigned int lvds_use_ssc:1; 1046 unsigned int display_clock_mode:1; 1047 unsigned int fdi_rx_polarity_inverted:1; 1048 int lvds_ssc_freq; 1049 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1050 1051 /* eDP */ 1052 int edp_rate; 1053 int edp_lanes; 1054 int edp_preemphasis; 1055 int edp_vswing; 1056 bool edp_initialized; 1057 bool edp_support; 1058 int edp_bpp; 1059 struct edp_power_seq edp_pps; 1060 1061 int crt_ddc_pin; 1062 1063 int child_dev_num; 1064 struct child_device_config *child_dev; 1065 }; 1066 1067 enum intel_ddb_partitioning { 1068 INTEL_DDB_PART_1_2, 1069 INTEL_DDB_PART_5_6, /* IVB+ */ 1070 }; 1071 1072 struct intel_wm_level { 1073 bool enable; 1074 uint32_t pri_val; 1075 uint32_t spr_val; 1076 uint32_t cur_val; 1077 uint32_t fbc_val; 1078 }; 1079 1080 /* 1081 * This struct tracks the state needed for the Package C8+ feature. 1082 * 1083 * Package states C8 and deeper are really deep PC states that can only be 1084 * reached when all the devices on the system allow it, so even if the graphics 1085 * device allows PC8+, it doesn't mean the system will actually get to these 1086 * states. 1087 * 1088 * Our driver only allows PC8+ when all the outputs are disabled, the power well 1089 * is disabled and the GPU is idle. When these conditions are met, we manually 1090 * do the other conditions: disable the interrupts, clocks and switch LCPLL 1091 * refclk to Fclk. 1092 * 1093 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1094 * the state of some registers, so when we come back from PC8+ we need to 1095 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1096 * need to take care of the registers kept by RC6. 1097 * 1098 * The interrupt disabling is part of the requirements. We can only leave the 1099 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we 1100 * can lock the machine. 1101 * 1102 * Ideally every piece of our code that needs PC8+ disabled would call 1103 * hsw_disable_package_c8, which would increment disable_count and prevent the 1104 * system from reaching PC8+. But we don't have a symmetric way to do this for 1105 * everything, so we have the requirements_met and gpu_idle variables. When we 1106 * switch requirements_met or gpu_idle to true we decrease disable_count, and 1107 * increase it in the opposite case. The requirements_met variable is true when 1108 * all the CRTCs, encoders and the power well are disabled. The gpu_idle 1109 * variable is true when the GPU is idle. 1110 * 1111 * In addition to everything, we only actually enable PC8+ if disable_count 1112 * stays at zero for at least some seconds. This is implemented with the 1113 * enable_work variable. We do this so we don't enable/disable PC8 dozens of 1114 * consecutive times when all screens are disabled and some background app 1115 * queries the state of our connectors, or we have some application constantly 1116 * waking up to use the GPU. Only after the enable_work function actually 1117 * enables PC8+ the "enable" variable will become true, which means that it can 1118 * be false even if disable_count is 0. 1119 * 1120 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1121 * goes back to false exactly before we reenable the IRQs. We use this variable 1122 * to check if someone is trying to enable/disable IRQs while they're supposed 1123 * to be disabled. This shouldn't happen and we'll print some error messages in 1124 * case it happens, but if it actually happens we'll also update the variables 1125 * inside struct regsave so when we restore the IRQs they will contain the 1126 * latest expected values. 1127 * 1128 * For more, read "Display Sequences for Package C8" on our documentation. 1129 */ 1130 struct i915_package_c8 { 1131 bool requirements_met; 1132 bool gpu_idle; 1133 bool irqs_disabled; 1134 /* Only true after the delayed work task actually enables it. */ 1135 bool enabled; 1136 int disable_count; 1137 struct mutex lock; 1138 struct delayed_work enable_work; 1139 1140 struct { 1141 uint32_t deimr; 1142 uint32_t sdeimr; 1143 uint32_t gtimr; 1144 uint32_t gtier; 1145 uint32_t gen6_pmimr; 1146 } regsave; 1147 }; 1148 1149 typedef struct drm_i915_private { 1150 struct drm_device *dev; 1151 struct kmem_cache *slab; 1152 1153 const struct intel_device_info *info; 1154 1155 int relative_constants_mode; 1156 1157 void __iomem *regs; 1158 1159 struct intel_uncore uncore; 1160 1161 struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; 1162 1163 1164 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1165 * controller on different i2c buses. */ 1166 struct mutex gmbus_mutex; 1167 1168 /** 1169 * Base address of the gmbus and gpio block. 1170 */ 1171 uint32_t gpio_mmio_base; 1172 1173 wait_queue_head_t gmbus_wait_queue; 1174 1175 struct pci_dev *bridge_dev; 1176 struct intel_ring_buffer ring[I915_NUM_RINGS]; 1177 uint32_t last_seqno, next_seqno; 1178 1179 drm_dma_handle_t *status_page_dmah; 1180 struct resource mch_res; 1181 1182 atomic_t irq_received; 1183 1184 /* protects the irq masks */ 1185 spinlock_t irq_lock; 1186 1187 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1188 struct pm_qos_request pm_qos; 1189 1190 /* DPIO indirect register protection */ 1191 struct mutex dpio_lock; 1192 1193 /** Cached value of IMR to avoid reads in updating the bitfield */ 1194 u32 irq_mask; 1195 u32 gt_irq_mask; 1196 u32 pm_irq_mask; 1197 1198 struct work_struct hotplug_work; 1199 bool enable_hotplug_processing; 1200 struct { 1201 unsigned long hpd_last_jiffies; 1202 int hpd_cnt; 1203 enum { 1204 HPD_ENABLED = 0, 1205 HPD_DISABLED = 1, 1206 HPD_MARK_DISABLED = 2 1207 } hpd_mark; 1208 } hpd_stats[HPD_NUM_PINS]; 1209 u32 hpd_event_bits; 1210 struct timer_list hotplug_reenable_timer; 1211 1212 int num_plane; 1213 1214 struct i915_fbc fbc; 1215 struct intel_opregion opregion; 1216 struct intel_vbt_data vbt; 1217 1218 /* overlay */ 1219 struct intel_overlay *overlay; 1220 unsigned int sprite_scaling_enabled; 1221 1222 /* backlight */ 1223 struct { 1224 int level; 1225 bool enabled; 1226 spinlock_t lock; /* bl registers and the above bl fields */ 1227 struct backlight_device *device; 1228 } backlight; 1229 1230 /* LVDS info */ 1231 bool no_aux_handshake; 1232 1233 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1234 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1235 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1236 1237 unsigned int fsb_freq, mem_freq, is_ddr3; 1238 1239 /** 1240 * wq - Driver workqueue for GEM. 1241 * 1242 * NOTE: Work items scheduled here are not allowed to grab any modeset 1243 * locks, for otherwise the flushing done in the pageflip code will 1244 * result in deadlocks. 1245 */ 1246 struct workqueue_struct *wq; 1247 1248 /* Display functions */ 1249 struct drm_i915_display_funcs display; 1250 1251 /* PCH chipset type */ 1252 enum intel_pch pch_type; 1253 unsigned short pch_id; 1254 1255 unsigned long quirks; 1256 1257 enum modeset_restore modeset_restore; 1258 struct mutex modeset_restore_lock; 1259 1260 struct list_head vm_list; /* Global list of all address spaces */ 1261 struct i915_gtt gtt; /* VMA representing the global address space */ 1262 1263 struct i915_gem_mm mm; 1264 1265 /* Kernel Modesetting */ 1266 1267 struct sdvo_device_mapping sdvo_mappings[2]; 1268 1269 struct drm_crtc *plane_to_crtc_mapping[3]; 1270 struct drm_crtc *pipe_to_crtc_mapping[3]; 1271 wait_queue_head_t pending_flip_queue; 1272 1273 int num_shared_dpll; 1274 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1275 struct intel_ddi_plls ddi_plls; 1276 1277 /* Reclocking support */ 1278 bool render_reclock_avail; 1279 bool lvds_downclock_avail; 1280 /* indicates the reduced downclock for LVDS*/ 1281 int lvds_downclock; 1282 u16 orig_clock; 1283 1284 bool mchbar_need_disable; 1285 1286 struct intel_l3_parity l3_parity; 1287 1288 /* Cannot be determined by PCIID. You must always read a register. */ 1289 size_t ellc_size; 1290 1291 /* gen6+ rps state */ 1292 struct intel_gen6_power_mgmt rps; 1293 1294 /* ilk-only ips/rps state. Everything in here is protected by the global 1295 * mchdev_lock in intel_pm.c */ 1296 struct intel_ilk_power_mgmt ips; 1297 1298 /* Haswell power well */ 1299 struct i915_power_well power_well; 1300 1301 enum no_psr_reason no_psr_reason; 1302 1303 struct i915_gpu_error gpu_error; 1304 1305 struct drm_i915_gem_object *vlv_pctx; 1306 1307 /* list of fbdev register on this device */ 1308 struct intel_fbdev *fbdev; 1309 1310 /* 1311 * The console may be contended at resume, but we don't 1312 * want it to block on it. 1313 */ 1314 struct work_struct console_resume_work; 1315 1316 struct drm_property *broadcast_rgb_property; 1317 struct drm_property *force_audio_property; 1318 1319 bool hw_contexts_disabled; 1320 uint32_t hw_context_size; 1321 1322 u32 fdi_rx_config; 1323 1324 struct i915_suspend_saved_registers regfile; 1325 1326 struct { 1327 /* 1328 * Raw watermark latency values: 1329 * in 0.1us units for WM0, 1330 * in 0.5us units for WM1+. 1331 */ 1332 /* primary */ 1333 uint16_t pri_latency[5]; 1334 /* sprite */ 1335 uint16_t spr_latency[5]; 1336 /* cursor */ 1337 uint16_t cur_latency[5]; 1338 } wm; 1339 1340 struct i915_package_c8 pc8; 1341 1342 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1343 * here! */ 1344 struct i915_dri1_state dri1; 1345 /* Old ums support infrastructure, same warning applies. */ 1346 struct i915_ums_state ums; 1347 } drm_i915_private_t; 1348 1349 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1350 { 1351 return dev->dev_private; 1352 } 1353 1354 /* Iterate over initialised rings */ 1355 #define for_each_ring(ring__, dev_priv__, i__) \ 1356 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1357 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1358 1359 enum hdmi_force_audio { 1360 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1361 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1362 HDMI_AUDIO_AUTO, /* trust EDID */ 1363 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1364 }; 1365 1366 #define I915_GTT_OFFSET_NONE ((u32)-1) 1367 1368 struct drm_i915_gem_object_ops { 1369 /* Interface between the GEM object and its backing storage. 1370 * get_pages() is called once prior to the use of the associated set 1371 * of pages before to binding them into the GTT, and put_pages() is 1372 * called after we no longer need them. As we expect there to be 1373 * associated cost with migrating pages between the backing storage 1374 * and making them available for the GPU (e.g. clflush), we may hold 1375 * onto the pages after they are no longer referenced by the GPU 1376 * in case they may be used again shortly (for example migrating the 1377 * pages to a different memory domain within the GTT). put_pages() 1378 * will therefore most likely be called when the object itself is 1379 * being released or under memory pressure (where we attempt to 1380 * reap pages for the shrinker). 1381 */ 1382 int (*get_pages)(struct drm_i915_gem_object *); 1383 void (*put_pages)(struct drm_i915_gem_object *); 1384 }; 1385 1386 struct drm_i915_gem_object { 1387 struct drm_gem_object base; 1388 1389 const struct drm_i915_gem_object_ops *ops; 1390 1391 /** List of VMAs backed by this object */ 1392 struct list_head vma_list; 1393 1394 /** Stolen memory for this object, instead of being backed by shmem. */ 1395 struct drm_mm_node *stolen; 1396 struct list_head global_list; 1397 1398 struct list_head ring_list; 1399 /** Used in execbuf to temporarily hold a ref */ 1400 struct list_head obj_exec_link; 1401 /** This object's place in the batchbuffer or on the eviction list */ 1402 struct list_head exec_list; 1403 1404 /** 1405 * This is set if the object is on the active lists (has pending 1406 * rendering and so a non-zero seqno), and is not set if it i s on 1407 * inactive (ready to be unbound) list. 1408 */ 1409 unsigned int active:1; 1410 1411 /** 1412 * This is set if the object has been written to since last bound 1413 * to the GTT 1414 */ 1415 unsigned int dirty:1; 1416 1417 /** 1418 * Fence register bits (if any) for this object. Will be set 1419 * as needed when mapped into the GTT. 1420 * Protected by dev->struct_mutex. 1421 */ 1422 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1423 1424 /** 1425 * Advice: are the backing pages purgeable? 1426 */ 1427 unsigned int madv:2; 1428 1429 /** 1430 * Current tiling mode for the object. 1431 */ 1432 unsigned int tiling_mode:2; 1433 /** 1434 * Whether the tiling parameters for the currently associated fence 1435 * register have changed. Note that for the purposes of tracking 1436 * tiling changes we also treat the unfenced register, the register 1437 * slot that the object occupies whilst it executes a fenced 1438 * command (such as BLT on gen2/3), as a "fence". 1439 */ 1440 unsigned int fence_dirty:1; 1441 1442 /** How many users have pinned this object in GTT space. The following 1443 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1444 * (via user_pin_count), execbuffer (objects are not allowed multiple 1445 * times for the same batchbuffer), and the framebuffer code. When 1446 * switching/pageflipping, the framebuffer code has at most two buffers 1447 * pinned per crtc. 1448 * 1449 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1450 * bits with absolutely no headroom. So use 4 bits. */ 1451 unsigned int pin_count:4; 1452 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1453 1454 /** 1455 * Is the object at the current location in the gtt mappable and 1456 * fenceable? Used to avoid costly recalculations. 1457 */ 1458 unsigned int map_and_fenceable:1; 1459 1460 /** 1461 * Whether the current gtt mapping needs to be mappable (and isn't just 1462 * mappable by accident). Track pin and fault separate for a more 1463 * accurate mappable working set. 1464 */ 1465 unsigned int fault_mappable:1; 1466 unsigned int pin_mappable:1; 1467 unsigned int pin_display:1; 1468 1469 /* 1470 * Is the GPU currently using a fence to access this buffer, 1471 */ 1472 unsigned int pending_fenced_gpu_access:1; 1473 unsigned int fenced_gpu_access:1; 1474 1475 unsigned int cache_level:3; 1476 1477 unsigned int has_aliasing_ppgtt_mapping:1; 1478 unsigned int has_global_gtt_mapping:1; 1479 unsigned int has_dma_mapping:1; 1480 1481 struct sg_table *pages; 1482 int pages_pin_count; 1483 1484 /* prime dma-buf support */ 1485 void *dma_buf_vmapping; 1486 int vmapping_count; 1487 1488 /** 1489 * Used for performing relocations during execbuffer insertion. 1490 */ 1491 struct hlist_node exec_node; 1492 unsigned long exec_handle; 1493 struct drm_i915_gem_exec_object2 *exec_entry; 1494 1495 struct intel_ring_buffer *ring; 1496 1497 /** Breadcrumb of last rendering to the buffer. */ 1498 uint32_t last_read_seqno; 1499 uint32_t last_write_seqno; 1500 /** Breadcrumb of last fenced GPU access to the buffer. */ 1501 uint32_t last_fenced_seqno; 1502 1503 /** Current tiling stride for the object, if it's tiled. */ 1504 uint32_t stride; 1505 1506 /** Record of address bit 17 of each page at last unbind. */ 1507 unsigned long *bit_17; 1508 1509 /** User space pin count and filp owning the pin */ 1510 uint32_t user_pin_count; 1511 struct drm_file *pin_filp; 1512 1513 /** for phy allocated objects */ 1514 struct drm_i915_gem_phys_object *phys_obj; 1515 }; 1516 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1517 1518 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1519 1520 /** 1521 * Request queue structure. 1522 * 1523 * The request queue allows us to note sequence numbers that have been emitted 1524 * and may be associated with active buffers to be retired. 1525 * 1526 * By keeping this list, we can avoid having to do questionable 1527 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1528 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1529 */ 1530 struct drm_i915_gem_request { 1531 /** On Which ring this request was generated */ 1532 struct intel_ring_buffer *ring; 1533 1534 /** GEM sequence number associated with this request. */ 1535 uint32_t seqno; 1536 1537 /** Position in the ringbuffer of the start of the request */ 1538 u32 head; 1539 1540 /** Position in the ringbuffer of the end of the request */ 1541 u32 tail; 1542 1543 /** Context related to this request */ 1544 struct i915_hw_context *ctx; 1545 1546 /** Batch buffer related to this request if any */ 1547 struct drm_i915_gem_object *batch_obj; 1548 1549 /** Time at which this request was emitted, in jiffies. */ 1550 unsigned long emitted_jiffies; 1551 1552 /** global list entry for this request */ 1553 struct list_head list; 1554 1555 struct drm_i915_file_private *file_priv; 1556 /** file_priv list entry for this request */ 1557 struct list_head client_list; 1558 }; 1559 1560 struct drm_i915_file_private { 1561 struct { 1562 spinlock_t lock; 1563 struct list_head request_list; 1564 } mm; 1565 struct idr context_idr; 1566 1567 struct i915_ctx_hang_stats hang_stats; 1568 }; 1569 1570 #define INTEL_INFO(dev) (to_i915(dev)->info) 1571 1572 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1573 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1574 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1575 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1576 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1577 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1578 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1579 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1580 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1581 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1582 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1583 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1584 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1585 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1586 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1587 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1588 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1589 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1590 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1591 (dev)->pci_device == 0x0152 || \ 1592 (dev)->pci_device == 0x015a) 1593 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1594 (dev)->pci_device == 0x0106 || \ 1595 (dev)->pci_device == 0x010A) 1596 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1597 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1598 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1599 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1600 ((dev)->pci_device & 0xFF00) == 0x0C00) 1601 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1602 ((dev)->pci_device & 0xFF00) == 0x0A00) 1603 1604 /* 1605 * The genX designation typically refers to the render engine, so render 1606 * capability related checks should use IS_GEN, while display and other checks 1607 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1608 * chips, etc.). 1609 */ 1610 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1611 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1612 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1613 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1614 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1615 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1616 1617 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1618 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1619 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring) 1620 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1621 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) 1622 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1623 1624 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1625 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1626 1627 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1628 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1629 1630 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1631 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1632 1633 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1634 * rows, which changed the alignment requirements and fence programming. 1635 */ 1636 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1637 IS_I915GM(dev))) 1638 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1639 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1640 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1641 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1642 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1643 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1644 1645 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1646 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1647 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1648 1649 #define HAS_IPS(dev) (IS_ULT(dev)) 1650 1651 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1652 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev)) 1653 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1654 1655 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1656 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1657 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1658 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1659 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1660 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1661 1662 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 1663 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1664 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1665 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1666 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 1667 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1668 1669 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1670 1671 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1672 1673 #define GT_FREQUENCY_MULTIPLIER 50 1674 1675 #include "i915_trace.h" 1676 1677 /** 1678 * RC6 is a special power stage which allows the GPU to enter an very 1679 * low-voltage mode when idle, using down to 0V while at this stage. This 1680 * stage is entered automatically when the GPU is idle when RC6 support is 1681 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1682 * 1683 * There are different RC6 modes available in Intel GPU, which differentiate 1684 * among each other with the latency required to enter and leave RC6 and 1685 * voltage consumed by the GPU in different states. 1686 * 1687 * The combination of the following flags define which states GPU is allowed 1688 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1689 * RC6pp is deepest RC6. Their support by hardware varies according to the 1690 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1691 * which brings the most power savings; deeper states save more power, but 1692 * require higher latency to switch to and wake up. 1693 */ 1694 #define INTEL_RC6_ENABLE (1<<0) 1695 #define INTEL_RC6p_ENABLE (1<<1) 1696 #define INTEL_RC6pp_ENABLE (1<<2) 1697 1698 extern const struct drm_ioctl_desc i915_ioctls[]; 1699 extern int i915_max_ioctl; 1700 extern unsigned int i915_fbpercrtc __always_unused; 1701 extern int i915_panel_ignore_lid __read_mostly; 1702 extern unsigned int i915_powersave __read_mostly; 1703 extern int i915_semaphores __read_mostly; 1704 extern unsigned int i915_lvds_downclock __read_mostly; 1705 extern int i915_lvds_channel_mode __read_mostly; 1706 extern int i915_panel_use_ssc __read_mostly; 1707 extern int i915_vbt_sdvo_panel_type __read_mostly; 1708 extern int i915_enable_rc6 __read_mostly; 1709 extern int i915_enable_fbc __read_mostly; 1710 extern bool i915_enable_hangcheck __read_mostly; 1711 extern int i915_enable_ppgtt __read_mostly; 1712 extern int i915_enable_psr __read_mostly; 1713 extern unsigned int i915_preliminary_hw_support __read_mostly; 1714 extern int i915_disable_power_well __read_mostly; 1715 extern int i915_enable_ips __read_mostly; 1716 extern bool i915_fastboot __read_mostly; 1717 extern int i915_enable_pc8 __read_mostly; 1718 extern int i915_pc8_timeout __read_mostly; 1719 extern bool i915_prefault_disable __read_mostly; 1720 1721 extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1722 extern int i915_resume(struct drm_device *dev); 1723 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1724 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1725 1726 /* i915_dma.c */ 1727 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1728 extern void i915_kernel_lost_context(struct drm_device * dev); 1729 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1730 extern int i915_driver_unload(struct drm_device *); 1731 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1732 extern void i915_driver_lastclose(struct drm_device * dev); 1733 extern void i915_driver_preclose(struct drm_device *dev, 1734 struct drm_file *file_priv); 1735 extern void i915_driver_postclose(struct drm_device *dev, 1736 struct drm_file *file_priv); 1737 extern int i915_driver_device_is_agp(struct drm_device * dev); 1738 #ifdef CONFIG_COMPAT 1739 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1740 unsigned long arg); 1741 #endif 1742 extern int i915_emit_box(struct drm_device *dev, 1743 struct drm_clip_rect *box, 1744 int DR1, int DR4); 1745 extern int intel_gpu_reset(struct drm_device *dev); 1746 extern int i915_reset(struct drm_device *dev); 1747 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1748 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1749 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1750 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1751 1752 extern void intel_console_resume(struct work_struct *work); 1753 1754 /* i915_irq.c */ 1755 void i915_queue_hangcheck(struct drm_device *dev); 1756 void i915_handle_error(struct drm_device *dev, bool wedged); 1757 1758 extern void intel_irq_init(struct drm_device *dev); 1759 extern void intel_pm_init(struct drm_device *dev); 1760 extern void intel_hpd_init(struct drm_device *dev); 1761 extern void intel_pm_init(struct drm_device *dev); 1762 1763 extern void intel_uncore_sanitize(struct drm_device *dev); 1764 extern void intel_uncore_early_sanitize(struct drm_device *dev); 1765 extern void intel_uncore_init(struct drm_device *dev); 1766 extern void intel_uncore_clear_errors(struct drm_device *dev); 1767 extern void intel_uncore_check_errors(struct drm_device *dev); 1768 1769 void 1770 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1771 1772 void 1773 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1774 1775 /* i915_gem.c */ 1776 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1777 struct drm_file *file_priv); 1778 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1779 struct drm_file *file_priv); 1780 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1781 struct drm_file *file_priv); 1782 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1783 struct drm_file *file_priv); 1784 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1785 struct drm_file *file_priv); 1786 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1787 struct drm_file *file_priv); 1788 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1789 struct drm_file *file_priv); 1790 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1791 struct drm_file *file_priv); 1792 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1793 struct drm_file *file_priv); 1794 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1795 struct drm_file *file_priv); 1796 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1797 struct drm_file *file_priv); 1798 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1799 struct drm_file *file_priv); 1800 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1801 struct drm_file *file_priv); 1802 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 1803 struct drm_file *file); 1804 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 1805 struct drm_file *file); 1806 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1807 struct drm_file *file_priv); 1808 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1809 struct drm_file *file_priv); 1810 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1811 struct drm_file *file_priv); 1812 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1813 struct drm_file *file_priv); 1814 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1815 struct drm_file *file_priv); 1816 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1817 struct drm_file *file_priv); 1818 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1819 struct drm_file *file_priv); 1820 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 1821 struct drm_file *file_priv); 1822 void i915_gem_load(struct drm_device *dev); 1823 void *i915_gem_object_alloc(struct drm_device *dev); 1824 void i915_gem_object_free(struct drm_i915_gem_object *obj); 1825 int i915_gem_init_object(struct drm_gem_object *obj); 1826 void i915_gem_object_init(struct drm_i915_gem_object *obj, 1827 const struct drm_i915_gem_object_ops *ops); 1828 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1829 size_t size); 1830 void i915_gem_free_object(struct drm_gem_object *obj); 1831 struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, 1832 struct i915_address_space *vm); 1833 void i915_gem_vma_destroy(struct i915_vma *vma); 1834 1835 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 1836 struct i915_address_space *vm, 1837 uint32_t alignment, 1838 bool map_and_fenceable, 1839 bool nonblocking); 1840 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1841 int __must_check i915_vma_unbind(struct i915_vma *vma); 1842 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); 1843 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 1844 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1845 void i915_gem_lastclose(struct drm_device *dev); 1846 1847 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 1848 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 1849 { 1850 struct sg_page_iter sg_iter; 1851 1852 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) 1853 return sg_page_iter_page(&sg_iter); 1854 1855 return NULL; 1856 } 1857 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 1858 { 1859 BUG_ON(obj->pages == NULL); 1860 obj->pages_pin_count++; 1861 } 1862 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 1863 { 1864 BUG_ON(obj->pages_pin_count == 0); 1865 obj->pages_pin_count--; 1866 } 1867 1868 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 1869 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1870 struct intel_ring_buffer *to); 1871 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1872 struct intel_ring_buffer *ring); 1873 1874 int i915_gem_dumb_create(struct drm_file *file_priv, 1875 struct drm_device *dev, 1876 struct drm_mode_create_dumb *args); 1877 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1878 uint32_t handle, uint64_t *offset); 1879 /** 1880 * Returns true if seq1 is later than seq2. 1881 */ 1882 static inline bool 1883 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1884 { 1885 return (int32_t)(seq1 - seq2) >= 0; 1886 } 1887 1888 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1889 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 1890 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1891 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1892 1893 static inline bool 1894 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1895 { 1896 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1897 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1898 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1899 return true; 1900 } else 1901 return false; 1902 } 1903 1904 static inline void 1905 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1906 { 1907 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1908 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1909 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); 1910 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1911 } 1912 } 1913 1914 void i915_gem_retire_requests(struct drm_device *dev); 1915 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1916 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 1917 bool interruptible); 1918 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 1919 { 1920 return unlikely(atomic_read(&error->reset_counter) 1921 & I915_RESET_IN_PROGRESS_FLAG); 1922 } 1923 1924 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 1925 { 1926 return atomic_read(&error->reset_counter) == I915_WEDGED; 1927 } 1928 1929 void i915_gem_reset(struct drm_device *dev); 1930 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 1931 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1932 int __must_check i915_gem_init(struct drm_device *dev); 1933 int __must_check i915_gem_init_hw(struct drm_device *dev); 1934 void i915_gem_l3_remap(struct drm_device *dev); 1935 void i915_gem_init_swizzling(struct drm_device *dev); 1936 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1937 int __must_check i915_gpu_idle(struct drm_device *dev); 1938 int __must_check i915_gem_idle(struct drm_device *dev); 1939 int __i915_add_request(struct intel_ring_buffer *ring, 1940 struct drm_file *file, 1941 struct drm_i915_gem_object *batch_obj, 1942 u32 *seqno); 1943 #define i915_add_request(ring, seqno) \ 1944 __i915_add_request(ring, NULL, NULL, seqno) 1945 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 1946 uint32_t seqno); 1947 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 1948 int __must_check 1949 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1950 bool write); 1951 int __must_check 1952 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1953 int __must_check 1954 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1955 u32 alignment, 1956 struct intel_ring_buffer *pipelined); 1957 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 1958 int i915_gem_attach_phys_object(struct drm_device *dev, 1959 struct drm_i915_gem_object *obj, 1960 int id, 1961 int align); 1962 void i915_gem_detach_phys_object(struct drm_device *dev, 1963 struct drm_i915_gem_object *obj); 1964 void i915_gem_free_all_phys_object(struct drm_device *dev); 1965 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1966 1967 uint32_t 1968 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 1969 uint32_t 1970 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 1971 int tiling_mode, bool fenced); 1972 1973 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1974 enum i915_cache_level cache_level); 1975 1976 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1977 struct dma_buf *dma_buf); 1978 1979 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 1980 struct drm_gem_object *gem_obj, int flags); 1981 1982 void i915_gem_restore_fences(struct drm_device *dev); 1983 1984 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 1985 struct i915_address_space *vm); 1986 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 1987 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 1988 struct i915_address_space *vm); 1989 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 1990 struct i915_address_space *vm); 1991 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 1992 struct i915_address_space *vm); 1993 struct i915_vma * 1994 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 1995 struct i915_address_space *vm); 1996 /* Some GGTT VM helpers */ 1997 #define obj_to_ggtt(obj) \ 1998 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 1999 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2000 { 2001 struct i915_address_space *ggtt = 2002 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2003 return vm == ggtt; 2004 } 2005 2006 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2007 { 2008 return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); 2009 } 2010 2011 static inline unsigned long 2012 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2013 { 2014 return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); 2015 } 2016 2017 static inline unsigned long 2018 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2019 { 2020 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 2021 } 2022 2023 static inline int __must_check 2024 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2025 uint32_t alignment, 2026 bool map_and_fenceable, 2027 bool nonblocking) 2028 { 2029 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, 2030 map_and_fenceable, nonblocking); 2031 } 2032 #undef obj_to_ggtt 2033 2034 /* i915_gem_context.c */ 2035 void i915_gem_context_init(struct drm_device *dev); 2036 void i915_gem_context_fini(struct drm_device *dev); 2037 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2038 int i915_switch_context(struct intel_ring_buffer *ring, 2039 struct drm_file *file, int to_id); 2040 void i915_gem_context_free(struct kref *ctx_ref); 2041 static inline void i915_gem_context_reference(struct i915_hw_context *ctx) 2042 { 2043 kref_get(&ctx->ref); 2044 } 2045 2046 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) 2047 { 2048 kref_put(&ctx->ref, i915_gem_context_free); 2049 } 2050 2051 struct i915_ctx_hang_stats * __must_check 2052 i915_gem_context_get_hang_stats(struct drm_device *dev, 2053 struct drm_file *file, 2054 u32 id); 2055 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2056 struct drm_file *file); 2057 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2058 struct drm_file *file); 2059 2060 /* i915_gem_gtt.c */ 2061 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 2062 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 2063 struct drm_i915_gem_object *obj, 2064 enum i915_cache_level cache_level); 2065 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 2066 struct drm_i915_gem_object *obj); 2067 2068 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 2069 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 2070 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 2071 enum i915_cache_level cache_level); 2072 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 2073 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 2074 void i915_gem_init_global_gtt(struct drm_device *dev); 2075 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 2076 unsigned long mappable_end, unsigned long end); 2077 int i915_gem_gtt_init(struct drm_device *dev); 2078 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2079 { 2080 if (INTEL_INFO(dev)->gen < 6) 2081 intel_gtt_chipset_flush(); 2082 } 2083 2084 2085 /* i915_gem_evict.c */ 2086 int __must_check i915_gem_evict_something(struct drm_device *dev, 2087 struct i915_address_space *vm, 2088 int min_size, 2089 unsigned alignment, 2090 unsigned cache_level, 2091 bool mappable, 2092 bool nonblock); 2093 int i915_gem_evict_everything(struct drm_device *dev); 2094 2095 /* i915_gem_stolen.c */ 2096 int i915_gem_init_stolen(struct drm_device *dev); 2097 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 2098 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2099 void i915_gem_cleanup_stolen(struct drm_device *dev); 2100 struct drm_i915_gem_object * 2101 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2102 struct drm_i915_gem_object * 2103 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2104 u32 stolen_offset, 2105 u32 gtt_offset, 2106 u32 size); 2107 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 2108 2109 /* i915_gem_tiling.c */ 2110 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2111 { 2112 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 2113 2114 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2115 obj->tiling_mode != I915_TILING_NONE; 2116 } 2117 2118 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2119 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2120 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2121 2122 /* i915_gem_debug.c */ 2123 #if WATCH_LISTS 2124 int i915_verify_lists(struct drm_device *dev); 2125 #else 2126 #define i915_verify_lists(dev) 0 2127 #endif 2128 2129 /* i915_debugfs.c */ 2130 int i915_debugfs_init(struct drm_minor *minor); 2131 void i915_debugfs_cleanup(struct drm_minor *minor); 2132 2133 /* i915_gpu_error.c */ 2134 __printf(2, 3) 2135 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2136 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2137 const struct i915_error_state_file_priv *error); 2138 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2139 size_t count, loff_t pos); 2140 static inline void i915_error_state_buf_release( 2141 struct drm_i915_error_state_buf *eb) 2142 { 2143 kfree(eb->buf); 2144 } 2145 void i915_capture_error_state(struct drm_device *dev); 2146 void i915_error_state_get(struct drm_device *dev, 2147 struct i915_error_state_file_priv *error_priv); 2148 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2149 void i915_destroy_error_state(struct drm_device *dev); 2150 2151 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2152 const char *i915_cache_level_str(int type); 2153 2154 /* i915_suspend.c */ 2155 extern int i915_save_state(struct drm_device *dev); 2156 extern int i915_restore_state(struct drm_device *dev); 2157 2158 /* i915_ums.c */ 2159 void i915_save_display_reg(struct drm_device *dev); 2160 void i915_restore_display_reg(struct drm_device *dev); 2161 2162 /* i915_sysfs.c */ 2163 void i915_setup_sysfs(struct drm_device *dev_priv); 2164 void i915_teardown_sysfs(struct drm_device *dev_priv); 2165 2166 /* intel_i2c.c */ 2167 extern int intel_setup_gmbus(struct drm_device *dev); 2168 extern void intel_teardown_gmbus(struct drm_device *dev); 2169 static inline bool intel_gmbus_is_port_valid(unsigned port) 2170 { 2171 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2172 } 2173 2174 extern struct i2c_adapter *intel_gmbus_get_adapter( 2175 struct drm_i915_private *dev_priv, unsigned port); 2176 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); 2177 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); 2178 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 2179 { 2180 return container_of(adapter, struct intel_gmbus, adapter)->force_bit; 2181 } 2182 extern void intel_i2c_reset(struct drm_device *dev); 2183 2184 /* intel_opregion.c */ 2185 extern int intel_opregion_setup(struct drm_device *dev); 2186 #ifdef CONFIG_ACPI 2187 extern void intel_opregion_init(struct drm_device *dev); 2188 extern void intel_opregion_fini(struct drm_device *dev); 2189 extern void intel_opregion_asle_intr(struct drm_device *dev); 2190 #else 2191 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2192 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2193 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2194 #endif 2195 2196 /* intel_acpi.c */ 2197 #ifdef CONFIG_ACPI 2198 extern void intel_register_dsm_handler(void); 2199 extern void intel_unregister_dsm_handler(void); 2200 #else 2201 static inline void intel_register_dsm_handler(void) { return; } 2202 static inline void intel_unregister_dsm_handler(void) { return; } 2203 #endif /* CONFIG_ACPI */ 2204 2205 /* modesetting */ 2206 extern void intel_modeset_init_hw(struct drm_device *dev); 2207 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2208 extern void intel_modeset_init(struct drm_device *dev); 2209 extern void intel_modeset_gem_init(struct drm_device *dev); 2210 extern void intel_modeset_cleanup(struct drm_device *dev); 2211 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2212 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2213 bool force_restore); 2214 extern void i915_redisable_vga(struct drm_device *dev); 2215 extern bool intel_fbc_enabled(struct drm_device *dev); 2216 extern void intel_disable_fbc(struct drm_device *dev); 2217 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2218 extern void intel_init_pch_refclk(struct drm_device *dev); 2219 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2220 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2221 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); 2222 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); 2223 extern void intel_detect_pch(struct drm_device *dev); 2224 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2225 extern int intel_enable_rc6(const struct drm_device *dev); 2226 2227 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2228 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2229 struct drm_file *file); 2230 2231 /* overlay */ 2232 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2233 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2234 struct intel_overlay_error_state *error); 2235 2236 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2237 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2238 struct drm_device *dev, 2239 struct intel_display_error_state *error); 2240 2241 /* On SNB platform, before reading ring registers forcewake bit 2242 * must be set to prevent GT core from power down and stale values being 2243 * returned. 2244 */ 2245 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 2246 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 2247 2248 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2249 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2250 2251 /* intel_sideband.c */ 2252 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2253 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2254 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2255 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg); 2256 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val); 2257 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2258 enum intel_sbi_destination destination); 2259 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2260 enum intel_sbi_destination destination); 2261 2262 int vlv_gpu_freq(int ddr_freq, int val); 2263 int vlv_freq_opcode(int ddr_freq, int val); 2264 2265 #define __i915_read(x) \ 2266 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace); 2267 __i915_read(8) 2268 __i915_read(16) 2269 __i915_read(32) 2270 __i915_read(64) 2271 #undef __i915_read 2272 2273 #define __i915_write(x) \ 2274 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace); 2275 __i915_write(8) 2276 __i915_write(16) 2277 __i915_write(32) 2278 __i915_write(64) 2279 #undef __i915_write 2280 2281 #define I915_READ8(reg) i915_read8(dev_priv, (reg), true) 2282 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true) 2283 2284 #define I915_READ16(reg) i915_read16(dev_priv, (reg), true) 2285 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true) 2286 #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false) 2287 #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false) 2288 2289 #define I915_READ(reg) i915_read32(dev_priv, (reg), true) 2290 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true) 2291 #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false) 2292 #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false) 2293 2294 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true) 2295 #define I915_READ64(reg) i915_read64(dev_priv, (reg), true) 2296 2297 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2298 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2299 2300 /* "Broadcast RGB" property */ 2301 #define INTEL_BROADCAST_RGB_AUTO 0 2302 #define INTEL_BROADCAST_RGB_FULL 1 2303 #define INTEL_BROADCAST_RGB_LIMITED 2 2304 2305 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2306 { 2307 if (HAS_PCH_SPLIT(dev)) 2308 return CPU_VGACNTRL; 2309 else if (IS_VALLEYVIEW(dev)) 2310 return VLV_VGACNTRL; 2311 else 2312 return VGACNTRL; 2313 } 2314 2315 static inline void __user *to_user_ptr(u64 address) 2316 { 2317 return (void __user *)(uintptr_t)address; 2318 } 2319 2320 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2321 { 2322 unsigned long j = msecs_to_jiffies(m); 2323 2324 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2325 } 2326 2327 static inline unsigned long 2328 timespec_to_jiffies_timeout(const struct timespec *value) 2329 { 2330 unsigned long j = timespec_to_jiffies(value); 2331 2332 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2333 } 2334 2335 #endif 2336