1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi/drm/i915_drm.h> 34 #include <uapi/drm/drm_fourcc.h> 35 36 #include <asm/hypervisor.h> 37 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <linux/i2c-algo-bit.h> 41 #include <linux/backlight.h> 42 #include <linux/hash.h> 43 #include <linux/intel-iommu.h> 44 #include <linux/kref.h> 45 #include <linux/mm_types.h> 46 #include <linux/perf_event.h> 47 #include <linux/pm_qos.h> 48 #include <linux/dma-resv.h> 49 #include <linux/shmem_fs.h> 50 #include <linux/stackdepot.h> 51 #include <linux/xarray.h> 52 53 #include <drm/intel-gtt.h> 54 #include <drm/drm_gem.h> 55 #include <drm/drm_auth.h> 56 #include <drm/drm_cache.h> 57 #include <drm/drm_util.h> 58 #include <drm/drm_dsc.h> 59 #include <drm/drm_atomic.h> 60 #include <drm/drm_connector.h> 61 #include <drm/i915_mei_hdcp_interface.h> 62 #include <drm/ttm/ttm_device.h> 63 64 #include "i915_params.h" 65 #include "i915_reg.h" 66 #include "i915_utils.h" 67 68 #include "display/intel_bios.h" 69 #include "display/intel_display.h" 70 #include "display/intel_display_power.h" 71 #include "display/intel_dmc.h" 72 #include "display/intel_dpll_mgr.h" 73 #include "display/intel_dsb.h" 74 #include "display/intel_frontbuffer.h" 75 #include "display/intel_global_state.h" 76 #include "display/intel_gmbus.h" 77 #include "display/intel_opregion.h" 78 79 #include "gem/i915_gem_context_types.h" 80 #include "gem/i915_gem_shrinker.h" 81 #include "gem/i915_gem_stolen.h" 82 #include "gem/i915_gem_lmem.h" 83 84 #include "gt/intel_engine.h" 85 #include "gt/intel_gt_types.h" 86 #include "gt/intel_region_lmem.h" 87 #include "gt/intel_workarounds.h" 88 #include "gt/uc/intel_uc.h" 89 90 #include "intel_device_info.h" 91 #include "intel_memory_region.h" 92 #include "intel_pch.h" 93 #include "intel_runtime_pm.h" 94 #include "intel_step.h" 95 #include "intel_uncore.h" 96 #include "intel_wakeref.h" 97 #include "intel_wopcm.h" 98 99 #include "i915_gem.h" 100 #include "i915_gem_gtt.h" 101 #include "i915_gpu_error.h" 102 #include "i915_perf_types.h" 103 #include "i915_request.h" 104 #include "i915_scheduler.h" 105 #include "gt/intel_timeline.h" 106 #include "i915_vma.h" 107 #include "i915_irq.h" 108 109 110 /* General customization: 111 */ 112 113 #define DRIVER_NAME "i915" 114 #define DRIVER_DESC "Intel Graphics" 115 #define DRIVER_DATE "20201103" 116 #define DRIVER_TIMESTAMP 1604406085 117 118 struct drm_i915_gem_object; 119 120 enum hpd_pin { 121 HPD_NONE = 0, 122 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 123 HPD_CRT, 124 HPD_SDVO_B, 125 HPD_SDVO_C, 126 HPD_PORT_A, 127 HPD_PORT_B, 128 HPD_PORT_C, 129 HPD_PORT_D, 130 HPD_PORT_E, 131 HPD_PORT_TC1, 132 HPD_PORT_TC2, 133 HPD_PORT_TC3, 134 HPD_PORT_TC4, 135 HPD_PORT_TC5, 136 HPD_PORT_TC6, 137 138 HPD_NUM_PINS 139 }; 140 141 #define for_each_hpd_pin(__pin) \ 142 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) 143 144 /* Threshold == 5 for long IRQs, 50 for short */ 145 #define HPD_STORM_DEFAULT_THRESHOLD 50 146 147 struct i915_hotplug { 148 struct delayed_work hotplug_work; 149 150 const u32 *hpd, *pch_hpd; 151 152 struct { 153 unsigned long last_jiffies; 154 int count; 155 enum { 156 HPD_ENABLED = 0, 157 HPD_DISABLED = 1, 158 HPD_MARK_DISABLED = 2 159 } state; 160 } stats[HPD_NUM_PINS]; 161 u32 event_bits; 162 u32 retry_bits; 163 struct delayed_work reenable_work; 164 165 u32 long_port_mask; 166 u32 short_port_mask; 167 struct work_struct dig_port_work; 168 169 struct work_struct poll_init_work; 170 bool poll_enabled; 171 172 unsigned int hpd_storm_threshold; 173 /* Whether or not to count short HPD IRQs in HPD storms */ 174 u8 hpd_short_storm_enabled; 175 176 /* 177 * if we get a HPD irq from DP and a HPD irq from non-DP 178 * the non-DP HPD could block the workqueue on a mode config 179 * mutex getting, that userspace may have taken. However 180 * userspace is waiting on the DP workqueue to run which is 181 * blocked behind the non-DP one. 182 */ 183 struct workqueue_struct *dp_wq; 184 }; 185 186 #define I915_GEM_GPU_DOMAINS \ 187 (I915_GEM_DOMAIN_RENDER | \ 188 I915_GEM_DOMAIN_SAMPLER | \ 189 I915_GEM_DOMAIN_COMMAND | \ 190 I915_GEM_DOMAIN_INSTRUCTION | \ 191 I915_GEM_DOMAIN_VERTEX) 192 193 struct drm_i915_private; 194 struct i915_mm_struct; 195 struct i915_mmu_object; 196 197 struct drm_i915_file_private { 198 struct drm_i915_private *dev_priv; 199 200 union { 201 struct drm_file *file; 202 struct rcu_head rcu; 203 }; 204 205 struct xarray context_xa; 206 struct xarray vm_xa; 207 208 unsigned int bsd_engine; 209 210 /* 211 * Every context ban increments per client ban score. Also 212 * hangs in short succession increments ban score. If ban threshold 213 * is reached, client is considered banned and submitting more work 214 * will fail. This is a stop gap measure to limit the badly behaving 215 * clients access to gpu. Note that unbannable contexts never increment 216 * the client ban score. 217 */ 218 #define I915_CLIENT_SCORE_HANG_FAST 1 219 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ) 220 #define I915_CLIENT_SCORE_CONTEXT_BAN 3 221 #define I915_CLIENT_SCORE_BANNED 9 222 /** ban_score: Accumulated score of all ctx bans and fast hangs. */ 223 atomic_t ban_score; 224 unsigned long hang_timestamp; 225 }; 226 227 /* Interface history: 228 * 229 * 1.1: Original. 230 * 1.2: Add Power Management 231 * 1.3: Add vblank support 232 * 1.4: Fix cmdbuffer path, add heap destroy 233 * 1.5: Add vblank pipe configuration 234 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 235 * - Support vertical blank on secondary display pipe 236 */ 237 #define DRIVER_MAJOR 1 238 #define DRIVER_MINOR 6 239 #define DRIVER_PATCHLEVEL 0 240 241 struct intel_overlay; 242 struct intel_overlay_error_state; 243 244 struct sdvo_device_mapping { 245 u8 initialized; 246 u8 dvo_port; 247 u8 slave_addr; 248 u8 dvo_wiring; 249 u8 i2c_pin; 250 u8 ddc_pin; 251 }; 252 253 struct intel_connector; 254 struct intel_encoder; 255 struct intel_atomic_state; 256 struct intel_cdclk_config; 257 struct intel_cdclk_state; 258 struct intel_cdclk_vals; 259 struct intel_initial_plane_config; 260 struct intel_crtc; 261 struct intel_limit; 262 struct dpll; 263 264 struct drm_i915_display_funcs { 265 void (*get_cdclk)(struct drm_i915_private *dev_priv, 266 struct intel_cdclk_config *cdclk_config); 267 void (*set_cdclk)(struct drm_i915_private *dev_priv, 268 const struct intel_cdclk_config *cdclk_config, 269 enum pipe pipe); 270 int (*bw_calc_min_cdclk)(struct intel_atomic_state *state); 271 int (*get_fifo_size)(struct drm_i915_private *dev_priv, 272 enum i9xx_plane_id i9xx_plane); 273 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state); 274 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state); 275 void (*initial_watermarks)(struct intel_atomic_state *state, 276 struct intel_crtc *crtc); 277 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 278 struct intel_crtc *crtc); 279 void (*optimize_watermarks)(struct intel_atomic_state *state, 280 struct intel_crtc *crtc); 281 int (*compute_global_watermarks)(struct intel_atomic_state *state); 282 void (*update_wm)(struct intel_crtc *crtc); 283 int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); 284 u8 (*calc_voltage_level)(int cdclk); 285 /* Returns the active state of the crtc, and if the crtc is active, 286 * fills out the pipe-config with the hw state. */ 287 bool (*get_pipe_config)(struct intel_crtc *, 288 struct intel_crtc_state *); 289 void (*get_initial_plane_config)(struct intel_crtc *, 290 struct intel_initial_plane_config *); 291 int (*crtc_compute_clock)(struct intel_crtc *crtc, 292 struct intel_crtc_state *crtc_state); 293 void (*crtc_enable)(struct intel_atomic_state *state, 294 struct intel_crtc *crtc); 295 void (*crtc_disable)(struct intel_atomic_state *state, 296 struct intel_crtc *crtc); 297 void (*commit_modeset_enables)(struct intel_atomic_state *state); 298 void (*commit_modeset_disables)(struct intel_atomic_state *state); 299 void (*audio_codec_enable)(struct intel_encoder *encoder, 300 const struct intel_crtc_state *crtc_state, 301 const struct drm_connector_state *conn_state); 302 void (*audio_codec_disable)(struct intel_encoder *encoder, 303 const struct intel_crtc_state *old_crtc_state, 304 const struct drm_connector_state *old_conn_state); 305 void (*fdi_link_train)(struct intel_crtc *crtc, 306 const struct intel_crtc_state *crtc_state); 307 void (*init_clock_gating)(struct drm_i915_private *dev_priv); 308 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); 309 /* clock updates for mode set */ 310 /* cursor updates */ 311 /* render clock increase/decrease */ 312 /* display clock increase/decrease */ 313 /* pll clock increase/decrease */ 314 315 int (*color_check)(struct intel_crtc_state *crtc_state); 316 /* 317 * Program double buffered color management registers during 318 * vblank evasion. The registers should then latch during the 319 * next vblank start, alongside any other double buffered registers 320 * involved with the same commit. 321 */ 322 void (*color_commit)(const struct intel_crtc_state *crtc_state); 323 /* 324 * Load LUTs (and other single buffered color management 325 * registers). Will (hopefully) be called during the vblank 326 * following the latching of any double buffered registers 327 * involved with the same commit. 328 */ 329 void (*load_luts)(const struct intel_crtc_state *crtc_state); 330 void (*read_luts)(struct intel_crtc_state *crtc_state); 331 }; 332 333 enum i915_cache_level { 334 I915_CACHE_NONE = 0, 335 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 336 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 337 caches, eg sampler/render caches, and the 338 large Last-Level-Cache. LLC is coherent with 339 the CPU, but L3 is only visible to the GPU. */ 340 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 341 }; 342 343 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ 344 345 struct intel_fbc { 346 /* This is always the inner lock when overlapping with struct_mutex and 347 * it's the outer lock when overlapping with stolen_lock. */ 348 struct mutex lock; 349 unsigned threshold; 350 unsigned int possible_framebuffer_bits; 351 unsigned int busy_bits; 352 struct intel_crtc *crtc; 353 354 struct drm_mm_node compressed_fb; 355 struct drm_mm_node *compressed_llb; 356 357 bool false_color; 358 359 bool active; 360 bool activated; 361 bool flip_pending; 362 363 bool underrun_detected; 364 struct work_struct underrun_work; 365 366 /* 367 * Due to the atomic rules we can't access some structures without the 368 * appropriate locking, so we cache information here in order to avoid 369 * these problems. 370 */ 371 struct intel_fbc_state_cache { 372 struct { 373 unsigned int mode_flags; 374 u32 hsw_bdw_pixel_rate; 375 } crtc; 376 377 struct { 378 unsigned int rotation; 379 int src_w; 380 int src_h; 381 bool visible; 382 /* 383 * Display surface base address adjustement for 384 * pageflips. Note that on gen4+ this only adjusts up 385 * to a tile, offsets within a tile are handled in 386 * the hw itself (with the TILEOFF register). 387 */ 388 int adjusted_x; 389 int adjusted_y; 390 391 u16 pixel_blend_mode; 392 } plane; 393 394 struct { 395 const struct drm_format_info *format; 396 unsigned int stride; 397 u64 modifier; 398 } fb; 399 400 unsigned int fence_y_offset; 401 u16 gen9_wa_cfb_stride; 402 u16 interval; 403 s8 fence_id; 404 bool psr2_active; 405 } state_cache; 406 407 /* 408 * This structure contains everything that's relevant to program the 409 * hardware registers. When we want to figure out if we need to disable 410 * and re-enable FBC for a new configuration we just check if there's 411 * something different in the struct. The genx_fbc_activate functions 412 * are supposed to read from it in order to program the registers. 413 */ 414 struct intel_fbc_reg_params { 415 struct { 416 enum pipe pipe; 417 enum i9xx_plane_id i9xx_plane; 418 } crtc; 419 420 struct { 421 const struct drm_format_info *format; 422 unsigned int stride; 423 u64 modifier; 424 } fb; 425 426 int cfb_size; 427 unsigned int fence_y_offset; 428 u16 gen9_wa_cfb_stride; 429 u16 interval; 430 s8 fence_id; 431 bool plane_visible; 432 } params; 433 434 const char *no_fbc_reason; 435 }; 436 437 /* 438 * HIGH_RR is the highest eDP panel refresh rate read from EDID 439 * LOW_RR is the lowest eDP panel refresh rate found from EDID 440 * parsing for same resolution. 441 */ 442 enum drrs_refresh_rate_type { 443 DRRS_HIGH_RR, 444 DRRS_LOW_RR, 445 DRRS_MAX_RR, /* RR count */ 446 }; 447 448 enum drrs_support_type { 449 DRRS_NOT_SUPPORTED = 0, 450 STATIC_DRRS_SUPPORT = 1, 451 SEAMLESS_DRRS_SUPPORT = 2 452 }; 453 454 struct intel_dp; 455 struct i915_drrs { 456 struct mutex mutex; 457 struct delayed_work work; 458 struct intel_dp *dp; 459 unsigned busy_frontbuffer_bits; 460 enum drrs_refresh_rate_type refresh_rate_type; 461 enum drrs_support_type type; 462 }; 463 464 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 465 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 466 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 467 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) 468 #define QUIRK_INCREASE_T12_DELAY (1<<6) 469 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7) 470 471 struct intel_fbdev; 472 struct intel_fbc_work; 473 474 struct intel_gmbus { 475 struct i2c_adapter adapter; 476 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 477 u32 force_bit; 478 u32 reg0; 479 i915_reg_t gpio_reg; 480 struct i2c_algo_bit_data bit_algo; 481 struct drm_i915_private *dev_priv; 482 }; 483 484 struct i915_suspend_saved_registers { 485 u32 saveDSPARB; 486 u32 saveSWF0[16]; 487 u32 saveSWF1[16]; 488 u32 saveSWF3[3]; 489 u16 saveGCDGMBUS; 490 }; 491 492 struct vlv_s0ix_state; 493 494 #define MAX_L3_SLICES 2 495 struct intel_l3_parity { 496 u32 *remap_info[MAX_L3_SLICES]; 497 struct work_struct error_work; 498 int which_slice; 499 }; 500 501 struct i915_gem_mm { 502 /* 503 * Shortcut for the stolen region. This points to either 504 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 505 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 506 * support stolen. 507 */ 508 struct intel_memory_region *stolen_region; 509 /** Memory allocator for GTT stolen memory */ 510 struct drm_mm stolen; 511 /** Protects the usage of the GTT stolen memory allocator. This is 512 * always the inner lock when overlapping with struct_mutex. */ 513 struct mutex stolen_lock; 514 515 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 516 spinlock_t obj_lock; 517 518 /** 519 * List of objects which are purgeable. 520 */ 521 struct list_head purge_list; 522 523 /** 524 * List of objects which have allocated pages and are shrinkable. 525 */ 526 struct list_head shrink_list; 527 528 /** 529 * List of objects which are pending destruction. 530 */ 531 struct llist_head free_list; 532 struct work_struct free_work; 533 /** 534 * Count of objects pending destructions. Used to skip needlessly 535 * waiting on an RCU barrier if no objects are waiting to be freed. 536 */ 537 atomic_t free_count; 538 539 /** 540 * tmpfs instance used for shmem backed objects 541 */ 542 struct vfsmount *gemfs; 543 544 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 545 546 struct notifier_block oom_notifier; 547 struct notifier_block vmap_notifier; 548 struct shrinker shrinker; 549 550 #ifdef CONFIG_MMU_NOTIFIER 551 /** 552 * notifier_lock for mmu notifiers, memory may not be allocated 553 * while holding this lock. 554 */ 555 spinlock_t notifier_lock; 556 #endif 557 558 /* shrinker accounting, also useful for userland debugging */ 559 u64 shrink_memory; 560 u32 shrink_count; 561 }; 562 563 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ 564 565 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915, 566 u64 context); 567 568 static inline unsigned long 569 i915_fence_timeout(const struct drm_i915_private *i915) 570 { 571 return i915_fence_context_timeout(i915, U64_MAX); 572 } 573 574 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 575 #define I915_NUM_QGV_POINTS 8 576 577 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 578 579 struct ddi_vbt_port_info { 580 /* Non-NULL if port present. */ 581 struct intel_bios_encoder_data *devdata; 582 583 int max_tmds_clock; 584 585 /* This is an index in the HDMI/DVI DDI buffer translation table. */ 586 u8 hdmi_level_shift; 587 u8 hdmi_level_shift_set:1; 588 589 u8 alternate_aux_channel; 590 u8 alternate_ddc_pin; 591 592 int dp_max_link_rate; /* 0 for not limited by VBT */ 593 }; 594 595 enum psr_lines_to_wait { 596 PSR_0_LINES_TO_WAIT = 0, 597 PSR_1_LINE_TO_WAIT, 598 PSR_4_LINES_TO_WAIT, 599 PSR_8_LINES_TO_WAIT 600 }; 601 602 struct intel_vbt_data { 603 /* bdb version */ 604 u16 version; 605 606 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 607 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 608 609 /* Feature bits */ 610 unsigned int int_tv_support:1; 611 unsigned int lvds_dither:1; 612 unsigned int int_crt_support:1; 613 unsigned int lvds_use_ssc:1; 614 unsigned int int_lvds_support:1; 615 unsigned int display_clock_mode:1; 616 unsigned int fdi_rx_polarity_inverted:1; 617 unsigned int panel_type:4; 618 int lvds_ssc_freq; 619 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 620 enum drm_panel_orientation orientation; 621 622 enum drrs_support_type drrs_type; 623 624 struct { 625 int rate; 626 int lanes; 627 int preemphasis; 628 int vswing; 629 bool low_vswing; 630 bool initialized; 631 int bpp; 632 struct edp_power_seq pps; 633 bool hobl; 634 } edp; 635 636 struct { 637 bool enable; 638 bool full_link; 639 bool require_aux_wakeup; 640 int idle_frames; 641 enum psr_lines_to_wait lines_to_wait; 642 int tp1_wakeup_time_us; 643 int tp2_tp3_wakeup_time_us; 644 int psr2_tp2_tp3_wakeup_time_us; 645 } psr; 646 647 struct { 648 u16 pwm_freq_hz; 649 bool present; 650 bool active_low_pwm; 651 u8 min_brightness; /* min_brightness/255 of max */ 652 u8 controller; /* brightness controller number */ 653 enum intel_backlight_type type; 654 } backlight; 655 656 /* MIPI DSI */ 657 struct { 658 u16 panel_id; 659 struct mipi_config *config; 660 struct mipi_pps_data *pps; 661 u16 bl_ports; 662 u16 cabc_ports; 663 u8 seq_version; 664 u32 size; 665 u8 *data; 666 const u8 *sequence[MIPI_SEQ_MAX]; 667 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ 668 enum drm_panel_orientation orientation; 669 } dsi; 670 671 int crt_ddc_pin; 672 673 struct list_head display_devices; 674 675 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 676 struct sdvo_device_mapping sdvo_mappings[2]; 677 }; 678 679 enum intel_ddb_partitioning { 680 INTEL_DDB_PART_1_2, 681 INTEL_DDB_PART_5_6, /* IVB+ */ 682 }; 683 684 struct ilk_wm_values { 685 u32 wm_pipe[3]; 686 u32 wm_lp[3]; 687 u32 wm_lp_spr[3]; 688 bool enable_fbc_wm; 689 enum intel_ddb_partitioning partitioning; 690 }; 691 692 struct g4x_pipe_wm { 693 u16 plane[I915_MAX_PLANES]; 694 u16 fbc; 695 }; 696 697 struct g4x_sr_wm { 698 u16 plane; 699 u16 cursor; 700 u16 fbc; 701 }; 702 703 struct vlv_wm_ddl_values { 704 u8 plane[I915_MAX_PLANES]; 705 }; 706 707 struct vlv_wm_values { 708 struct g4x_pipe_wm pipe[3]; 709 struct g4x_sr_wm sr; 710 struct vlv_wm_ddl_values ddl[3]; 711 u8 level; 712 bool cxsr; 713 }; 714 715 struct g4x_wm_values { 716 struct g4x_pipe_wm pipe[2]; 717 struct g4x_sr_wm sr; 718 struct g4x_sr_wm hpll; 719 bool cxsr; 720 bool hpll_en; 721 bool fbc_en; 722 }; 723 724 struct skl_ddb_entry { 725 u16 start, end; /* in number of blocks, 'end' is exclusive */ 726 }; 727 728 static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry) 729 { 730 return entry->end - entry->start; 731 } 732 733 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, 734 const struct skl_ddb_entry *e2) 735 { 736 if (e1->start == e2->start && e1->end == e2->end) 737 return true; 738 739 return false; 740 } 741 742 struct i915_frontbuffer_tracking { 743 spinlock_t lock; 744 745 /* 746 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 747 * scheduled flips. 748 */ 749 unsigned busy_bits; 750 unsigned flip_bits; 751 }; 752 753 struct i915_virtual_gpu { 754 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 755 bool active; 756 u32 caps; 757 }; 758 759 struct intel_cdclk_config { 760 unsigned int cdclk, vco, ref, bypass; 761 u8 voltage_level; 762 }; 763 764 struct i915_selftest_stash { 765 atomic_t counter; 766 struct ida mock_region_instances; 767 }; 768 769 struct drm_i915_private { 770 struct drm_device drm; 771 772 /* FIXME: Device release actions should all be moved to drmm_ */ 773 bool do_release; 774 775 /* i915 device parameters */ 776 struct i915_params params; 777 778 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */ 779 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 780 struct intel_driver_caps caps; 781 782 /** 783 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and 784 * end of stolen which we can optionally use to create GEM objects 785 * backed by stolen memory. Note that stolen_usable_size tells us 786 * exactly how much of this we are actually allowed to use, given that 787 * some portion of it is in fact reserved for use by hardware functions. 788 */ 789 struct resource dsm; 790 /** 791 * Reseved portion of Data Stolen Memory 792 */ 793 struct resource dsm_reserved; 794 795 /* 796 * Stolen memory is segmented in hardware with different portions 797 * offlimits to certain functions. 798 * 799 * The drm_mm is initialised to the total accessible range, as found 800 * from the PCI config. On Broadwell+, this is further restricted to 801 * avoid the first page! The upper end of stolen memory is reserved for 802 * hardware functions and similarly removed from the accessible range. 803 */ 804 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ 805 806 struct intel_uncore uncore; 807 struct intel_uncore_mmio_debug mmio_debug; 808 809 struct i915_virtual_gpu vgpu; 810 811 struct intel_gvt *gvt; 812 813 struct intel_wopcm wopcm; 814 815 struct intel_dmc dmc; 816 817 struct intel_gmbus gmbus[GMBUS_NUM_PINS]; 818 819 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 820 * controller on different i2c buses. */ 821 struct mutex gmbus_mutex; 822 823 /** 824 * Base address of where the gmbus and gpio blocks are located (either 825 * on PCH or on SoC for platforms without PCH). 826 */ 827 u32 gpio_mmio_base; 828 829 u32 hsw_psr_mmio_adjust; 830 831 /* MMIO base address for MIPI regs */ 832 u32 mipi_mmio_base; 833 834 u32 pps_mmio_base; 835 836 wait_queue_head_t gmbus_wait_queue; 837 838 struct pci_dev *bridge_dev; 839 840 struct rb_root uabi_engines; 841 842 struct resource mch_res; 843 844 /* protects the irq masks */ 845 spinlock_t irq_lock; 846 847 bool display_irqs_enabled; 848 849 /* Sideband mailbox protection */ 850 struct mutex sb_lock; 851 struct pm_qos_request sb_qos; 852 853 /** Cached value of IMR to avoid reads in updating the bitfield */ 854 union { 855 u32 irq_mask; 856 u32 de_irq_mask[I915_MAX_PIPES]; 857 }; 858 u32 pipestat_irq_mask[I915_MAX_PIPES]; 859 860 struct i915_hotplug hotplug; 861 struct intel_fbc fbc; 862 struct i915_drrs drrs; 863 struct intel_opregion opregion; 864 struct intel_vbt_data vbt; 865 866 bool preserve_bios_swizzle; 867 868 /* overlay */ 869 struct intel_overlay *overlay; 870 871 /* backlight registers and fields in struct intel_panel */ 872 struct mutex backlight_lock; 873 874 /* protects panel power sequencer state */ 875 struct mutex pps_mutex; 876 877 unsigned int fsb_freq, mem_freq, is_ddr3; 878 unsigned int skl_preferred_vco_freq; 879 unsigned int max_cdclk_freq; 880 881 unsigned int max_dotclk_freq; 882 unsigned int hpll_freq; 883 unsigned int fdi_pll_freq; 884 unsigned int czclk_freq; 885 886 struct { 887 /* The current hardware cdclk configuration */ 888 struct intel_cdclk_config hw; 889 890 /* cdclk, divider, and ratio table from bspec */ 891 const struct intel_cdclk_vals *table; 892 893 struct intel_global_obj obj; 894 } cdclk; 895 896 struct { 897 /* The current hardware dbuf configuration */ 898 u8 enabled_slices; 899 900 struct intel_global_obj obj; 901 } dbuf; 902 903 /** 904 * wq - Driver workqueue for GEM. 905 * 906 * NOTE: Work items scheduled here are not allowed to grab any modeset 907 * locks, for otherwise the flushing done in the pageflip code will 908 * result in deadlocks. 909 */ 910 struct workqueue_struct *wq; 911 912 /* ordered wq for modesets */ 913 struct workqueue_struct *modeset_wq; 914 /* unbound hipri wq for page flips/plane updates */ 915 struct workqueue_struct *flip_wq; 916 917 /* Display functions */ 918 struct drm_i915_display_funcs display; 919 920 /* PCH chipset type */ 921 enum intel_pch pch_type; 922 unsigned short pch_id; 923 924 unsigned long quirks; 925 926 struct drm_atomic_state *modeset_restore_state; 927 struct drm_modeset_acquire_ctx reset_ctx; 928 929 struct i915_ggtt ggtt; /* VM representing the global address space */ 930 931 struct i915_gem_mm mm; 932 933 /* Kernel Modesetting */ 934 935 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 936 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 937 938 /** 939 * dpll and cdclk state is protected by connection_mutex 940 * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll. 941 * Must be global rather than per dpll, because on some platforms plls 942 * share registers. 943 */ 944 struct { 945 struct mutex lock; 946 947 int num_shared_dpll; 948 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 949 const struct intel_dpll_mgr *mgr; 950 951 struct { 952 int nssc; 953 int ssc; 954 } ref_clks; 955 } dpll; 956 957 struct list_head global_obj_list; 958 959 /* 960 * For reading active_pipes holding any crtc lock is 961 * sufficient, for writing must hold all of them. 962 */ 963 u8 active_pipes; 964 965 struct i915_wa_list gt_wa_list; 966 967 struct i915_frontbuffer_tracking fb_tracking; 968 969 struct intel_atomic_helper { 970 struct llist_head free_list; 971 struct work_struct free_work; 972 } atomic_helper; 973 974 bool mchbar_need_disable; 975 976 struct intel_l3_parity l3_parity; 977 978 /* 979 * HTI (aka HDPORT) state read during initial hw readout. Most 980 * platforms don't have HTI, so this will just stay 0. Those that do 981 * will use this later to figure out which PLLs and PHYs are unavailable 982 * for driver usage. 983 */ 984 u32 hti_state; 985 986 /* 987 * edram size in MB. 988 * Cannot be determined by PCIID. You must always read a register. 989 */ 990 u32 edram_size_mb; 991 992 struct i915_power_domains power_domains; 993 994 struct i915_gpu_error gpu_error; 995 996 struct drm_i915_gem_object *vlv_pctx; 997 998 /* list of fbdev register on this device */ 999 struct intel_fbdev *fbdev; 1000 struct work_struct fbdev_suspend_work; 1001 1002 struct drm_property *broadcast_rgb_property; 1003 struct drm_property *force_audio_property; 1004 1005 /* hda/i915 audio component */ 1006 struct i915_audio_component *audio_component; 1007 bool audio_component_registered; 1008 /** 1009 * av_mutex - mutex for audio/video sync 1010 * 1011 */ 1012 struct mutex av_mutex; 1013 int audio_power_refcount; 1014 u32 audio_freq_cntrl; 1015 1016 u32 fdi_rx_config; 1017 1018 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 1019 u32 chv_phy_control; 1020 /* 1021 * Shadows for CHV DPLL_MD regs to keep the state 1022 * checker somewhat working in the presence hardware 1023 * crappiness (can't read out DPLL_MD for pipes B & C). 1024 */ 1025 u32 chv_dpll_md[I915_MAX_PIPES]; 1026 u32 bxt_phy_grc; 1027 1028 u32 suspend_count; 1029 bool power_domains_suspended; 1030 struct i915_suspend_saved_registers regfile; 1031 struct vlv_s0ix_state *vlv_s0ix_state; 1032 1033 enum { 1034 I915_SAGV_UNKNOWN = 0, 1035 I915_SAGV_DISABLED, 1036 I915_SAGV_ENABLED, 1037 I915_SAGV_NOT_CONTROLLED 1038 } sagv_status; 1039 1040 u32 sagv_block_time_us; 1041 1042 struct { 1043 /* 1044 * Raw watermark latency values: 1045 * in 0.1us units for WM0, 1046 * in 0.5us units for WM1+. 1047 */ 1048 /* primary */ 1049 u16 pri_latency[5]; 1050 /* sprite */ 1051 u16 spr_latency[5]; 1052 /* cursor */ 1053 u16 cur_latency[5]; 1054 /* 1055 * Raw watermark memory latency values 1056 * for SKL for all 8 levels 1057 * in 1us units. 1058 */ 1059 u16 skl_latency[8]; 1060 1061 /* current hardware state */ 1062 union { 1063 struct ilk_wm_values hw; 1064 struct vlv_wm_values vlv; 1065 struct g4x_wm_values g4x; 1066 }; 1067 1068 u8 max_level; 1069 1070 /* 1071 * Should be held around atomic WM register writing; also 1072 * protects * intel_crtc->wm.active and 1073 * crtc_state->wm.need_postvbl_update. 1074 */ 1075 struct mutex wm_mutex; 1076 } wm; 1077 1078 struct dram_info { 1079 bool wm_lv_0_adjust_needed; 1080 u8 num_channels; 1081 bool symmetric_memory; 1082 enum intel_dram_type { 1083 INTEL_DRAM_UNKNOWN, 1084 INTEL_DRAM_DDR3, 1085 INTEL_DRAM_DDR4, 1086 INTEL_DRAM_LPDDR3, 1087 INTEL_DRAM_LPDDR4, 1088 INTEL_DRAM_DDR5, 1089 INTEL_DRAM_LPDDR5, 1090 } type; 1091 u8 num_qgv_points; 1092 } dram_info; 1093 1094 struct intel_bw_info { 1095 /* for each QGV point */ 1096 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 1097 u8 num_qgv_points; 1098 u8 num_planes; 1099 } max_bw[6]; 1100 1101 struct intel_global_obj bw_obj; 1102 1103 struct intel_runtime_pm runtime_pm; 1104 1105 struct i915_perf perf; 1106 1107 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1108 struct intel_gt gt; 1109 1110 struct { 1111 struct i915_gem_contexts { 1112 spinlock_t lock; /* locks list */ 1113 struct list_head list; 1114 } contexts; 1115 1116 /* 1117 * We replace the local file with a global mappings as the 1118 * backing storage for the mmap is on the device and not 1119 * on the struct file, and we do not want to prolong the 1120 * lifetime of the local fd. To minimise the number of 1121 * anonymous inodes we create, we use a global singleton to 1122 * share the global mapping. 1123 */ 1124 struct file *mmap_singleton; 1125 } gem; 1126 1127 u8 framestart_delay; 1128 1129 /* Window2 specifies time required to program DSB (Window2) in number of scan lines */ 1130 u8 window2_delay; 1131 1132 u8 pch_ssc_use; 1133 1134 /* For i915gm/i945gm vblank irq workaround */ 1135 u8 vblank_enabled; 1136 1137 /* perform PHY state sanity checks? */ 1138 bool chv_phy_assert[2]; 1139 1140 bool ipc_enabled; 1141 1142 /* Used to save the pipe-to-encoder mapping for audio */ 1143 struct intel_encoder *av_enc_map[I915_MAX_PIPES]; 1144 1145 /* necessary resource sharing with HDMI LPE audio driver. */ 1146 struct { 1147 struct platform_device *platdev; 1148 int irq; 1149 } lpe_audio; 1150 1151 struct i915_pmu pmu; 1152 1153 struct i915_hdcp_comp_master *hdcp_master; 1154 bool hdcp_comp_added; 1155 1156 /* Mutex to protect the above hdcp component related values. */ 1157 struct mutex hdcp_comp_mutex; 1158 1159 /* The TTM device structure. */ 1160 struct ttm_device bdev; 1161 1162 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 1163 1164 /* 1165 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1166 * will be rejected. Instead look for a better place. 1167 */ 1168 }; 1169 1170 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1171 { 1172 return container_of(dev, struct drm_i915_private, drm); 1173 } 1174 1175 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 1176 { 1177 return dev_get_drvdata(kdev); 1178 } 1179 1180 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 1181 { 1182 return pci_get_drvdata(pdev); 1183 } 1184 1185 /* Simple iterator over all initialised engines */ 1186 #define for_each_engine(engine__, dev_priv__, id__) \ 1187 for ((id__) = 0; \ 1188 (id__) < I915_NUM_ENGINES; \ 1189 (id__)++) \ 1190 for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) 1191 1192 /* Iterator over subset of engines selected by mask */ 1193 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \ 1194 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \ 1195 (tmp__) ? \ 1196 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \ 1197 0;) 1198 1199 #define rb_to_uabi_engine(rb) \ 1200 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 1201 1202 #define for_each_uabi_engine(engine__, i915__) \ 1203 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 1204 (engine__); \ 1205 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1206 1207 #define for_each_uabi_class_engine(engine__, class__, i915__) \ 1208 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \ 1209 (engine__) && (engine__)->uabi_class == (class__); \ 1210 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 1211 1212 #define I915_GTT_OFFSET_NONE ((u32)-1) 1213 1214 /* 1215 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1216 * considered to be the frontbuffer for the given plane interface-wise. This 1217 * doesn't mean that the hw necessarily already scans it out, but that any 1218 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1219 * 1220 * We have one bit per pipe and per scanout plane type. 1221 */ 1222 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 1223 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ 1224 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ 1225 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ 1226 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ 1227 }) 1228 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1229 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1230 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1231 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ 1232 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) 1233 1234 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) 1235 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime) 1236 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) 1237 1238 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id) 1239 1240 /* 1241 * Deprecated: this will be replaced by individual IP checks: 1242 * GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() 1243 */ 1244 #define INTEL_GEN(dev_priv) GRAPHICS_VER(dev_priv) 1245 /* 1246 * Deprecated: use IS_GRAPHICS_VER(), IS_MEDIA_VER() and IS_DISPLAY_VER() as 1247 * appropriate. 1248 */ 1249 #define IS_GEN_RANGE(dev_priv, s, e) IS_GRAPHICS_VER(dev_priv, (s), (e)) 1250 /* 1251 * Deprecated: use GRAPHICS_VER(), MEDIA_VER() and DISPLAY_VER() as appropriate. 1252 */ 1253 #define IS_GEN(dev_priv, n) (GRAPHICS_VER(dev_priv) == (n)) 1254 1255 #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics_ver) 1256 #define IS_GRAPHICS_VER(i915, from, until) \ 1257 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 1258 1259 #define MEDIA_VER(i915) (INTEL_INFO(i915)->media_ver) 1260 #define IS_MEDIA_VER(i915, from, until) \ 1261 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 1262 1263 #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver) 1264 #define IS_DISPLAY_VER(i915, from, until) \ 1265 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 1266 1267 #define REVID_FOREVER 0xff 1268 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision) 1269 1270 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb) 1271 1272 /* 1273 * Return true if revision is in range [since,until] inclusive. 1274 * 1275 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. 1276 */ 1277 #define IS_REVID(p, since, until) \ 1278 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) 1279 1280 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 1281 #define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step) 1282 1283 #define IS_DISPLAY_STEP(__i915, since, until) \ 1284 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 1285 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until)) 1286 1287 #define IS_GT_STEP(__i915, since, until) \ 1288 (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ 1289 INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until)) 1290 1291 static __always_inline unsigned int 1292 __platform_mask_index(const struct intel_runtime_info *info, 1293 enum intel_platform p) 1294 { 1295 const unsigned int pbits = 1296 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1297 1298 /* Expand the platform_mask array if this fails. */ 1299 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 1300 pbits * ARRAY_SIZE(info->platform_mask)); 1301 1302 return p / pbits; 1303 } 1304 1305 static __always_inline unsigned int 1306 __platform_mask_bit(const struct intel_runtime_info *info, 1307 enum intel_platform p) 1308 { 1309 const unsigned int pbits = 1310 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 1311 1312 return p % pbits + INTEL_SUBPLATFORM_BITS; 1313 } 1314 1315 static inline u32 1316 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 1317 { 1318 const unsigned int pi = __platform_mask_index(info, p); 1319 1320 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 1321 } 1322 1323 static __always_inline bool 1324 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 1325 { 1326 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1327 const unsigned int pi = __platform_mask_index(info, p); 1328 const unsigned int pb = __platform_mask_bit(info, p); 1329 1330 BUILD_BUG_ON(!__builtin_constant_p(p)); 1331 1332 return info->platform_mask[pi] & BIT(pb); 1333 } 1334 1335 static __always_inline bool 1336 IS_SUBPLATFORM(const struct drm_i915_private *i915, 1337 enum intel_platform p, unsigned int s) 1338 { 1339 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 1340 const unsigned int pi = __platform_mask_index(info, p); 1341 const unsigned int pb = __platform_mask_bit(info, p); 1342 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 1343 const u32 mask = info->platform_mask[pi]; 1344 1345 BUILD_BUG_ON(!__builtin_constant_p(p)); 1346 BUILD_BUG_ON(!__builtin_constant_p(s)); 1347 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 1348 1349 /* Shift and test on the MSB position so sign flag can be used. */ 1350 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 1351 } 1352 1353 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) 1354 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) 1355 1356 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) 1357 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) 1358 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) 1359 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) 1360 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) 1361 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) 1362 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) 1363 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) 1364 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) 1365 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) 1366 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) 1367 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) 1368 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) 1369 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) 1370 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) 1371 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) 1372 #define IS_IRONLAKE_M(dev_priv) \ 1373 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) 1374 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) 1375 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) 1376 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ 1377 INTEL_INFO(dev_priv)->gt == 1) 1378 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) 1379 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) 1380 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) 1381 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) 1382 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) 1383 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) 1384 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) 1385 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) 1386 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) 1387 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) 1388 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) 1389 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) 1390 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ 1391 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) 1392 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) 1393 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) 1394 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) 1395 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) 1396 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) 1397 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ 1398 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) 1399 #define IS_BDW_ULT(dev_priv) \ 1400 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 1401 #define IS_BDW_ULX(dev_priv) \ 1402 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 1403 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ 1404 INTEL_INFO(dev_priv)->gt == 3) 1405 #define IS_HSW_ULT(dev_priv) \ 1406 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 1407 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ 1408 INTEL_INFO(dev_priv)->gt == 3) 1409 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ 1410 INTEL_INFO(dev_priv)->gt == 1) 1411 /* ULX machines are also considered ULT. */ 1412 #define IS_HSW_ULX(dev_priv) \ 1413 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 1414 #define IS_SKL_ULT(dev_priv) \ 1415 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 1416 #define IS_SKL_ULX(dev_priv) \ 1417 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 1418 #define IS_KBL_ULT(dev_priv) \ 1419 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 1420 #define IS_KBL_ULX(dev_priv) \ 1421 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 1422 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1423 INTEL_INFO(dev_priv)->gt == 2) 1424 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1425 INTEL_INFO(dev_priv)->gt == 3) 1426 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ 1427 INTEL_INFO(dev_priv)->gt == 4) 1428 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1429 INTEL_INFO(dev_priv)->gt == 2) 1430 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ 1431 INTEL_INFO(dev_priv)->gt == 3) 1432 #define IS_CFL_ULT(dev_priv) \ 1433 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 1434 #define IS_CFL_ULX(dev_priv) \ 1435 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 1436 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1437 INTEL_INFO(dev_priv)->gt == 2) 1438 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ 1439 INTEL_INFO(dev_priv)->gt == 3) 1440 1441 #define IS_CML_ULT(dev_priv) \ 1442 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 1443 #define IS_CML_ULX(dev_priv) \ 1444 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 1445 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ 1446 INTEL_INFO(dev_priv)->gt == 2) 1447 1448 #define IS_CNL_WITH_PORT_F(dev_priv) \ 1449 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF) 1450 #define IS_ICL_WITH_PORT_F(dev_priv) \ 1451 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 1452 1453 #define IS_TGL_U(dev_priv) \ 1454 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) 1455 1456 #define IS_TGL_Y(dev_priv) \ 1457 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) 1458 1459 #define SKL_REVID_A0 0x0 1460 #define SKL_REVID_B0 0x1 1461 #define SKL_REVID_C0 0x2 1462 #define SKL_REVID_D0 0x3 1463 #define SKL_REVID_E0 0x4 1464 #define SKL_REVID_F0 0x5 1465 #define SKL_REVID_G0 0x6 1466 #define SKL_REVID_H0 0x7 1467 1468 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) 1469 1470 #define BXT_REVID_A0 0x0 1471 #define BXT_REVID_A1 0x1 1472 #define BXT_REVID_B0 0x3 1473 #define BXT_REVID_B_LAST 0x8 1474 #define BXT_REVID_C0 0x9 1475 1476 #define IS_BXT_REVID(dev_priv, since, until) \ 1477 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) 1478 1479 #define IS_KBL_GT_STEP(dev_priv, since, until) \ 1480 (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until)) 1481 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ 1482 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) 1483 1484 #define GLK_REVID_A0 0x0 1485 #define GLK_REVID_A1 0x1 1486 #define GLK_REVID_A2 0x2 1487 #define GLK_REVID_B0 0x3 1488 1489 #define IS_GLK_REVID(dev_priv, since, until) \ 1490 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) 1491 1492 #define CNL_REVID_A0 0x0 1493 #define CNL_REVID_B0 0x1 1494 #define CNL_REVID_C0 0x2 1495 1496 #define IS_CNL_REVID(p, since, until) \ 1497 (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) 1498 1499 #define ICL_REVID_A0 0x0 1500 #define ICL_REVID_A2 0x1 1501 #define ICL_REVID_B0 0x3 1502 #define ICL_REVID_B2 0x4 1503 #define ICL_REVID_C0 0x5 1504 1505 #define IS_ICL_REVID(p, since, until) \ 1506 (IS_ICELAKE(p) && IS_REVID(p, since, until)) 1507 1508 #define EHL_REVID_A0 0x0 1509 #define EHL_REVID_B0 0x1 1510 1511 #define IS_JSL_EHL_REVID(p, since, until) \ 1512 (IS_JSL_EHL(p) && IS_REVID(p, since, until)) 1513 1514 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \ 1515 (IS_TIGERLAKE(__i915) && \ 1516 IS_DISPLAY_STEP(__i915, since, until)) 1517 1518 #define IS_TGL_UY_GT_STEP(__i915, since, until) \ 1519 ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1520 IS_GT_STEP(__i915, since, until)) 1521 1522 #define IS_TGL_GT_STEP(__i915, since, until) \ 1523 (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ 1524 IS_GT_STEP(__i915, since, until)) 1525 1526 #define RKL_REVID_A0 0x0 1527 #define RKL_REVID_B0 0x1 1528 #define RKL_REVID_C0 0x4 1529 1530 #define IS_RKL_REVID(p, since, until) \ 1531 (IS_ROCKETLAKE(p) && IS_REVID(p, since, until)) 1532 1533 #define DG1_REVID_A0 0x0 1534 #define DG1_REVID_B0 0x1 1535 1536 #define IS_DG1_REVID(p, since, until) \ 1537 (IS_DG1(p) && IS_REVID(p, since, until)) 1538 1539 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ 1540 (IS_ALDERLAKE_S(__i915) && \ 1541 IS_DISPLAY_STEP(__i915, since, until)) 1542 1543 #define IS_ADLS_GT_STEP(__i915, since, until) \ 1544 (IS_ALDERLAKE_S(__i915) && \ 1545 IS_GT_STEP(__i915, since, until)) 1546 1547 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \ 1548 (IS_ALDERLAKE_P(__i915) && \ 1549 IS_DISPLAY_STEP(__i915, since, until)) 1550 1551 #define IS_ADLP_GT_STEP(__i915, since, until) \ 1552 (IS_ALDERLAKE_P(__i915) && \ 1553 IS_GT_STEP(__i915, since, until)) 1554 1555 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) 1556 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) 1557 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) 1558 1559 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 1560 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 1561 1562 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \ 1563 unsigned int first__ = (first); \ 1564 unsigned int count__ = (count); \ 1565 ((gt)->info.engine_mask & \ 1566 GENMASK(first__ + count__ - 1, first__)) >> first__; \ 1567 }) 1568 #define VDBOX_MASK(gt) \ 1569 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 1570 #define VEBOX_MASK(gt) \ 1571 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 1572 1573 /* 1574 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 1575 * All later gens can run the final buffer from the ppgtt 1576 */ 1577 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7) 1578 1579 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc) 1580 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop) 1581 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb) 1582 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6) 1583 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) 1584 1585 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical) 1586 1587 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ 1588 (INTEL_INFO(dev_priv)->has_logical_ring_contexts) 1589 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ 1590 (INTEL_INFO(dev_priv)->has_logical_ring_elsq) 1591 1592 #define HAS_MASTER_UNIT_IRQ(dev_priv) (INTEL_INFO(dev_priv)->has_master_unit_irq) 1593 1594 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) 1595 1596 #define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type) 1597 #define HAS_PPGTT(dev_priv) \ 1598 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE) 1599 #define HAS_FULL_PPGTT(dev_priv) \ 1600 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL) 1601 1602 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ 1603 GEM_BUG_ON((sizes) == 0); \ 1604 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \ 1605 }) 1606 1607 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay) 1608 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 1609 (INTEL_INFO(dev_priv)->display.overlay_needs_physical) 1610 1611 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1612 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1613 1614 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \ 1615 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9) 1616 1617 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1618 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1619 (IS_CANNONLAKE(dev_priv) || \ 1620 IS_SKL_GT3(dev_priv) || \ 1621 IS_SKL_GT4(dev_priv)) 1622 1623 #define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4) 1624 #define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \ 1625 IS_GEMINILAKE(dev_priv) || \ 1626 IS_KABYLAKE(dev_priv)) 1627 1628 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1629 * rows, which changed the alignment requirements and fence programming. 1630 */ 1631 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \ 1632 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv))) 1633 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv) 1634 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug) 1635 1636 #define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2) 1637 #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc) 1638 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7) 1639 1640 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 1641 1642 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst) 1643 1644 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi) 1645 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg) 1646 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) 1647 #define HAS_PSR_HW_TRACKING(dev_priv) \ 1648 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) 1649 #define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12) 1650 #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0) 1651 1652 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) 1653 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p) 1654 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 1655 1656 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) 1657 1658 #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) 1659 1660 #define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12) 1661 1662 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) 1663 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) 1664 1665 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc) 1666 1667 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 1668 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 1669 1670 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) 1671 1672 #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) 1673 1674 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs) 1675 1676 1677 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) 1678 1679 #define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10)) 1680 1681 /* DPF == dynamic parity feature */ 1682 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) 1683 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ 1684 2 : HAS_L3_DPF(dev_priv)) 1685 1686 #define GT_FREQUENCY_MULTIPLIER 50 1687 #define GEN9_FREQ_SCALER 3 1688 1689 #define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask)) 1690 1691 #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0) 1692 1693 #define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 12) 1694 1695 /* Only valid when HAS_DISPLAY() is true */ 1696 #define INTEL_DISPLAY_ENABLED(dev_priv) \ 1697 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display) 1698 1699 static inline bool run_as_guest(void) 1700 { 1701 return !hypervisor_is_type(X86_HYPER_NATIVE); 1702 } 1703 1704 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \ 1705 IS_ALDERLAKE_S(dev_priv)) 1706 1707 static inline bool intel_vtd_active(void) 1708 { 1709 #ifdef CONFIG_INTEL_IOMMU 1710 if (intel_iommu_gfx_mapped) 1711 return true; 1712 #endif 1713 1714 /* Running as a guest, we assume the host is enforcing VT'd */ 1715 return run_as_guest(); 1716 } 1717 1718 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) 1719 { 1720 return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(); 1721 } 1722 1723 static inline bool 1724 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 1725 { 1726 return IS_BROXTON(i915) && intel_vtd_active(); 1727 } 1728 1729 static inline bool 1730 intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 1731 { 1732 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 1733 } 1734 1735 /* i915_drv.c */ 1736 extern const struct dev_pm_ops i915_pm_ops; 1737 1738 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 1739 void i915_driver_remove(struct drm_i915_private *i915); 1740 void i915_driver_shutdown(struct drm_i915_private *i915); 1741 1742 int i915_resume_switcheroo(struct drm_i915_private *i915); 1743 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state); 1744 1745 int i915_getparam_ioctl(struct drm_device *dev, void *data, 1746 struct drm_file *file_priv); 1747 1748 /* i915_gem.c */ 1749 int i915_gem_init_userptr(struct drm_i915_private *dev_priv); 1750 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); 1751 void i915_gem_init_early(struct drm_i915_private *dev_priv); 1752 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); 1753 1754 struct intel_memory_region *i915_gem_shmem_setup(struct drm_i915_private *i915, 1755 u16 type, u16 instance); 1756 1757 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) 1758 { 1759 /* 1760 * A single pass should suffice to release all the freed objects (along 1761 * most call paths) , but be a little more paranoid in that freeing 1762 * the objects does take a little amount of time, during which the rcu 1763 * callbacks could have added new objects into the freed list, and 1764 * armed the work again. 1765 */ 1766 while (atomic_read(&i915->mm.free_count)) { 1767 flush_work(&i915->mm.free_work); 1768 rcu_barrier(); 1769 } 1770 } 1771 1772 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) 1773 { 1774 /* 1775 * Similar to objects above (see i915_gem_drain_freed-objects), in 1776 * general we have workers that are armed by RCU and then rearm 1777 * themselves in their callbacks. To be paranoid, we need to 1778 * drain the workqueue a second time after waiting for the RCU 1779 * grace period so that we catch work queued via RCU from the first 1780 * pass. As neither drain_workqueue() nor flush_workqueue() report 1781 * a result, we make an assumption that we only don't require more 1782 * than 3 passes to catch all _recursive_ RCU delayed work. 1783 * 1784 */ 1785 int pass = 3; 1786 do { 1787 flush_workqueue(i915->wq); 1788 rcu_barrier(); 1789 i915_gem_drain_freed_objects(i915); 1790 } while (--pass); 1791 drain_workqueue(i915->wq); 1792 } 1793 1794 struct i915_vma * __must_check 1795 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, 1796 struct i915_gem_ww_ctx *ww, 1797 const struct i915_ggtt_view *view, 1798 u64 size, u64 alignment, u64 flags); 1799 1800 static inline struct i915_vma * __must_check 1801 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 1802 const struct i915_ggtt_view *view, 1803 u64 size, u64 alignment, u64 flags) 1804 { 1805 return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment, flags); 1806 } 1807 1808 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, 1809 unsigned long flags); 1810 #define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) 1811 #define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) 1812 #define I915_GEM_OBJECT_UNBIND_TEST BIT(2) 1813 #define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) 1814 1815 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); 1816 1817 int i915_gem_dumb_create(struct drm_file *file_priv, 1818 struct drm_device *dev, 1819 struct drm_mode_create_dumb *args); 1820 1821 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); 1822 1823 static inline u32 i915_reset_count(struct i915_gpu_error *error) 1824 { 1825 return atomic_read(&error->reset_count); 1826 } 1827 1828 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, 1829 const struct intel_engine_cs *engine) 1830 { 1831 return atomic_read(&error->reset_engine_count[engine->uabi_class]); 1832 } 1833 1834 int __must_check i915_gem_init(struct drm_i915_private *dev_priv); 1835 void i915_gem_driver_register(struct drm_i915_private *i915); 1836 void i915_gem_driver_unregister(struct drm_i915_private *i915); 1837 void i915_gem_driver_remove(struct drm_i915_private *dev_priv); 1838 void i915_gem_driver_release(struct drm_i915_private *dev_priv); 1839 void i915_gem_suspend(struct drm_i915_private *dev_priv); 1840 void i915_gem_suspend_late(struct drm_i915_private *dev_priv); 1841 void i915_gem_resume(struct drm_i915_private *dev_priv); 1842 1843 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); 1844 1845 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1846 enum i915_cache_level cache_level); 1847 1848 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 1849 struct dma_buf *dma_buf); 1850 1851 struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags); 1852 1853 static inline struct i915_gem_context * 1854 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) 1855 { 1856 return xa_load(&file_priv->context_xa, id); 1857 } 1858 1859 static inline struct i915_gem_context * 1860 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) 1861 { 1862 struct i915_gem_context *ctx; 1863 1864 rcu_read_lock(); 1865 ctx = __i915_gem_context_lookup_rcu(file_priv, id); 1866 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1867 ctx = NULL; 1868 rcu_read_unlock(); 1869 1870 return ctx; 1871 } 1872 1873 /* i915_gem_evict.c */ 1874 int __must_check i915_gem_evict_something(struct i915_address_space *vm, 1875 u64 min_size, u64 alignment, 1876 unsigned long color, 1877 u64 start, u64 end, 1878 unsigned flags); 1879 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, 1880 struct drm_mm_node *node, 1881 unsigned int flags); 1882 int i915_gem_evict_vm(struct i915_address_space *vm); 1883 1884 /* i915_gem_internal.c */ 1885 struct drm_i915_gem_object * 1886 i915_gem_object_create_internal(struct drm_i915_private *dev_priv, 1887 phys_addr_t size); 1888 1889 /* i915_gem_tiling.c */ 1890 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 1891 { 1892 struct drm_i915_private *i915 = to_i915(obj->base.dev); 1893 1894 return i915->ggtt.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 1895 i915_gem_object_is_tiled(obj); 1896 } 1897 1898 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, 1899 unsigned int tiling, unsigned int stride); 1900 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, 1901 unsigned int tiling, unsigned int stride); 1902 1903 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 1904 1905 /* i915_cmd_parser.c */ 1906 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); 1907 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine); 1908 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); 1909 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1910 struct i915_vma *batch, 1911 unsigned long batch_offset, 1912 unsigned long batch_length, 1913 struct i915_vma *shadow, 1914 bool trampoline); 1915 #define I915_CMD_PARSER_TRAMPOLINE_SIZE 8 1916 1917 /* intel_device_info.c */ 1918 static inline struct intel_device_info * 1919 mkwrite_device_info(struct drm_i915_private *dev_priv) 1920 { 1921 return (struct intel_device_info *)INTEL_INFO(dev_priv); 1922 } 1923 1924 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 1925 struct drm_file *file); 1926 1927 /* i915_mm.c */ 1928 int remap_io_mapping(struct vm_area_struct *vma, 1929 unsigned long addr, unsigned long pfn, unsigned long size, 1930 struct io_mapping *iomap); 1931 int remap_io_sg(struct vm_area_struct *vma, 1932 unsigned long addr, unsigned long size, 1933 struct scatterlist *sgl, resource_size_t iobase); 1934 1935 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) 1936 { 1937 if (GRAPHICS_VER(i915) >= 10) 1938 return CNL_HWS_CSB_WRITE_INDEX; 1939 else 1940 return I915_HWS_CSB_WRITE_INDEX; 1941 } 1942 1943 static inline enum i915_map_type 1944 i915_coherent_map_type(struct drm_i915_private *i915, 1945 struct drm_i915_gem_object *obj, bool always_coherent) 1946 { 1947 if (i915_gem_object_is_lmem(obj)) 1948 return I915_MAP_WC; 1949 if (HAS_LLC(i915) || always_coherent) 1950 return I915_MAP_WB; 1951 else 1952 return I915_MAP_WC; 1953 } 1954 1955 #endif 1956