1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/slab.h> 38 #include <linux/string_helpers.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_types.h" 52 #include "display/intel_dmc.h" 53 #include "display/intel_dp.h" 54 #include "display/intel_dpt.h" 55 #include "display/intel_fbdev.h" 56 #include "display/intel_hotplug.h" 57 #include "display/intel_overlay.h" 58 #include "display/intel_pch_refclk.h" 59 #include "display/intel_pipe_crc.h" 60 #include "display/intel_pps.h" 61 #include "display/intel_sprite.h" 62 #include "display/intel_vga.h" 63 #include "display/skl_watermark.h" 64 65 #include "gem/i915_gem_context.h" 66 #include "gem/i915_gem_create.h" 67 #include "gem/i915_gem_dmabuf.h" 68 #include "gem/i915_gem_ioctls.h" 69 #include "gem/i915_gem_mman.h" 70 #include "gem/i915_gem_pm.h" 71 #include "gt/intel_gt.h" 72 #include "gt/intel_gt_pm.h" 73 #include "gt/intel_rc6.h" 74 75 #include "pxp/intel_pxp.h" 76 #include "pxp/intel_pxp_debugfs.h" 77 #include "pxp/intel_pxp_pm.h" 78 79 #include "soc/intel_dram.h" 80 #include "soc/intel_gmch.h" 81 82 #include "i915_debugfs.h" 83 #include "i915_driver.h" 84 #include "i915_drm_client.h" 85 #include "i915_drv.h" 86 #include "i915_file_private.h" 87 #include "i915_getparam.h" 88 #include "i915_hwmon.h" 89 #include "i915_ioc32.h" 90 #include "i915_ioctl.h" 91 #include "i915_irq.h" 92 #include "i915_memcpy.h" 93 #include "i915_perf.h" 94 #include "i915_query.h" 95 #include "i915_suspend.h" 96 #include "i915_switcheroo.h" 97 #include "i915_sysfs.h" 98 #include "i915_utils.h" 99 #include "i915_vgpu.h" 100 #include "intel_clock_gating.h" 101 #include "intel_gvt.h" 102 #include "intel_memory_region.h" 103 #include "intel_pci_config.h" 104 #include "intel_pcode.h" 105 #include "intel_region_ttm.h" 106 #include "vlv_suspend.h" 107 108 static const struct drm_driver i915_drm_driver; 109 110 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 111 { 112 /* 113 * The i915 workqueue is primarily used for batched retirement of 114 * requests (and thus managing bo) once the task has been completed 115 * by the GPU. i915_retire_requests() is called directly when we 116 * need high-priority retirement, such as waiting for an explicit 117 * bo. 118 * 119 * It is also used for periodic low-priority events, such as 120 * idle-timers and recording error state. 121 * 122 * All tasks on the workqueue are expected to acquire the dev mutex 123 * so there is no point in running more than one instance of the 124 * workqueue at any time. Use an ordered one. 125 */ 126 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 127 if (dev_priv->wq == NULL) 128 goto out_err; 129 130 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 131 if (dev_priv->display.hotplug.dp_wq == NULL) 132 goto out_free_wq; 133 134 return 0; 135 136 out_free_wq: 137 destroy_workqueue(dev_priv->wq); 138 out_err: 139 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 140 141 return -ENOMEM; 142 } 143 144 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 145 { 146 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 147 destroy_workqueue(dev_priv->wq); 148 } 149 150 /* 151 * We don't keep the workarounds for pre-production hardware, so we expect our 152 * driver to fail on these machines in one way or another. A little warning on 153 * dmesg may help both the user and the bug triagers. 154 * 155 * Our policy for removing pre-production workarounds is to keep the 156 * current gen workarounds as a guide to the bring-up of the next gen 157 * (workarounds have a habit of persisting!). Anything older than that 158 * should be removed along with the complications they introduce. 159 */ 160 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 161 { 162 bool pre = false; 163 164 pre |= IS_HSW_EARLY_SDV(dev_priv); 165 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 166 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 167 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 168 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 169 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 170 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 171 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 172 173 if (pre) { 174 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 175 "It may not be fully functional.\n"); 176 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 177 } 178 } 179 180 static void sanitize_gpu(struct drm_i915_private *i915) 181 { 182 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 183 struct intel_gt *gt; 184 unsigned int i; 185 186 for_each_gt(gt, i915, i) 187 __intel_gt_reset(gt, ALL_ENGINES); 188 } 189 } 190 191 /** 192 * i915_driver_early_probe - setup state not requiring device access 193 * @dev_priv: device private 194 * 195 * Initialize everything that is a "SW-only" state, that is state not 196 * requiring accessing the device or exposing the driver via kernel internal 197 * or userspace interfaces. Example steps belonging here: lock initialization, 198 * system memory allocation, setting up device specific attributes and 199 * function hooks not requiring accessing the device. 200 */ 201 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 202 { 203 int ret = 0; 204 205 if (i915_inject_probe_failure(dev_priv)) 206 return -ENODEV; 207 208 intel_device_info_runtime_init_early(dev_priv); 209 210 intel_step_init(dev_priv); 211 212 intel_uncore_mmio_debug_init_early(dev_priv); 213 214 spin_lock_init(&dev_priv->irq_lock); 215 spin_lock_init(&dev_priv->gpu_error.lock); 216 mutex_init(&dev_priv->display.backlight.lock); 217 218 mutex_init(&dev_priv->sb_lock); 219 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 220 221 mutex_init(&dev_priv->display.audio.mutex); 222 mutex_init(&dev_priv->display.wm.wm_mutex); 223 mutex_init(&dev_priv->display.pps.mutex); 224 mutex_init(&dev_priv->display.hdcp.comp_mutex); 225 spin_lock_init(&dev_priv->display.dkl.phy_lock); 226 227 i915_memcpy_init_early(dev_priv); 228 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 229 230 ret = i915_workqueues_init(dev_priv); 231 if (ret < 0) 232 return ret; 233 234 ret = vlv_suspend_init(dev_priv); 235 if (ret < 0) 236 goto err_workqueues; 237 238 ret = intel_region_ttm_device_init(dev_priv); 239 if (ret) 240 goto err_ttm; 241 242 ret = intel_root_gt_init_early(dev_priv); 243 if (ret < 0) 244 goto err_rootgt; 245 246 i915_drm_clients_init(&dev_priv->clients, dev_priv); 247 248 i915_gem_init_early(dev_priv); 249 250 /* This must be called before any calls to HAS_PCH_* */ 251 intel_detect_pch(dev_priv); 252 253 intel_irq_init(dev_priv); 254 intel_init_display_hooks(dev_priv); 255 intel_clock_gating_hooks_init(dev_priv); 256 257 intel_detect_preproduction_hw(dev_priv); 258 259 return 0; 260 261 err_rootgt: 262 intel_region_ttm_device_fini(dev_priv); 263 err_ttm: 264 vlv_suspend_cleanup(dev_priv); 265 err_workqueues: 266 i915_workqueues_cleanup(dev_priv); 267 return ret; 268 } 269 270 /** 271 * i915_driver_late_release - cleanup the setup done in 272 * i915_driver_early_probe() 273 * @dev_priv: device private 274 */ 275 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 276 { 277 intel_irq_fini(dev_priv); 278 intel_power_domains_cleanup(dev_priv); 279 i915_gem_cleanup_early(dev_priv); 280 intel_gt_driver_late_release_all(dev_priv); 281 i915_drm_clients_fini(&dev_priv->clients); 282 intel_region_ttm_device_fini(dev_priv); 283 vlv_suspend_cleanup(dev_priv); 284 i915_workqueues_cleanup(dev_priv); 285 286 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 287 mutex_destroy(&dev_priv->sb_lock); 288 289 i915_params_free(&dev_priv->params); 290 } 291 292 /** 293 * i915_driver_mmio_probe - setup device MMIO 294 * @dev_priv: device private 295 * 296 * Setup minimal device state necessary for MMIO accesses later in the 297 * initialization sequence. The setup here should avoid any other device-wide 298 * side effects or exposing the driver via kernel internal or user space 299 * interfaces. 300 */ 301 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 302 { 303 struct intel_gt *gt; 304 int ret, i; 305 306 if (i915_inject_probe_failure(dev_priv)) 307 return -ENODEV; 308 309 ret = intel_gmch_bridge_setup(dev_priv); 310 if (ret < 0) 311 return ret; 312 313 for_each_gt(gt, dev_priv, i) { 314 ret = intel_uncore_init_mmio(gt->uncore); 315 if (ret) 316 return ret; 317 318 ret = drmm_add_action_or_reset(&dev_priv->drm, 319 intel_uncore_fini_mmio, 320 gt->uncore); 321 if (ret) 322 return ret; 323 } 324 325 /* Try to make sure MCHBAR is enabled before poking at it */ 326 intel_gmch_bar_setup(dev_priv); 327 intel_device_info_runtime_init(dev_priv); 328 329 for_each_gt(gt, dev_priv, i) { 330 ret = intel_gt_init_mmio(gt); 331 if (ret) 332 goto err_uncore; 333 } 334 335 /* As early as possible, scrub existing GPU state before clobbering */ 336 sanitize_gpu(dev_priv); 337 338 return 0; 339 340 err_uncore: 341 intel_gmch_bar_teardown(dev_priv); 342 343 return ret; 344 } 345 346 /** 347 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 348 * @dev_priv: device private 349 */ 350 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 351 { 352 intel_gmch_bar_teardown(dev_priv); 353 } 354 355 /** 356 * i915_set_dma_info - set all relevant PCI dma info as configured for the 357 * platform 358 * @i915: valid i915 instance 359 * 360 * Set the dma max segment size, device and coherent masks. The dma mask set 361 * needs to occur before i915_ggtt_probe_hw. 362 * 363 * A couple of platforms have special needs. Address them as well. 364 * 365 */ 366 static int i915_set_dma_info(struct drm_i915_private *i915) 367 { 368 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 369 int ret; 370 371 GEM_BUG_ON(!mask_size); 372 373 /* 374 * We don't have a max segment size, so set it to the max so sg's 375 * debugging layer doesn't complain 376 */ 377 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 378 379 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 380 if (ret) 381 goto mask_err; 382 383 /* overlay on gen2 is broken and can't address above 1G */ 384 if (GRAPHICS_VER(i915) == 2) 385 mask_size = 30; 386 387 /* 388 * 965GM sometimes incorrectly writes to hardware status page (HWS) 389 * using 32bit addressing, overwriting memory if HWS is located 390 * above 4GB. 391 * 392 * The documentation also mentions an issue with undefined 393 * behaviour if any general state is accessed within a page above 4GB, 394 * which also needs to be handled carefully. 395 */ 396 if (IS_I965G(i915) || IS_I965GM(i915)) 397 mask_size = 32; 398 399 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 400 if (ret) 401 goto mask_err; 402 403 return 0; 404 405 mask_err: 406 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 407 return ret; 408 } 409 410 static int i915_pcode_init(struct drm_i915_private *i915) 411 { 412 struct intel_gt *gt; 413 int id, ret; 414 415 for_each_gt(gt, i915, id) { 416 ret = intel_pcode_init(gt->uncore); 417 if (ret) { 418 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 419 return ret; 420 } 421 } 422 423 return 0; 424 } 425 426 /** 427 * i915_driver_hw_probe - setup state requiring device access 428 * @dev_priv: device private 429 * 430 * Setup state that requires accessing the device, but doesn't require 431 * exposing the driver via kernel internal or userspace interfaces. 432 */ 433 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 434 { 435 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 436 struct pci_dev *root_pdev; 437 int ret; 438 439 if (i915_inject_probe_failure(dev_priv)) 440 return -ENODEV; 441 442 if (HAS_PPGTT(dev_priv)) { 443 if (intel_vgpu_active(dev_priv) && 444 !intel_vgpu_has_full_ppgtt(dev_priv)) { 445 i915_report_error(dev_priv, 446 "incompatible vGPU found, support for isolated ppGTT required\n"); 447 return -ENXIO; 448 } 449 } 450 451 if (HAS_EXECLISTS(dev_priv)) { 452 /* 453 * Older GVT emulation depends upon intercepting CSB mmio, 454 * which we no longer use, preferring to use the HWSP cache 455 * instead. 456 */ 457 if (intel_vgpu_active(dev_priv) && 458 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 459 i915_report_error(dev_priv, 460 "old vGPU host found, support for HWSP emulation required\n"); 461 return -ENXIO; 462 } 463 } 464 465 /* needs to be done before ggtt probe */ 466 intel_dram_edram_detect(dev_priv); 467 468 ret = i915_set_dma_info(dev_priv); 469 if (ret) 470 return ret; 471 472 ret = i915_perf_init(dev_priv); 473 if (ret) 474 return ret; 475 476 ret = i915_ggtt_probe_hw(dev_priv); 477 if (ret) 478 goto err_perf; 479 480 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 481 if (ret) 482 goto err_ggtt; 483 484 ret = i915_ggtt_init_hw(dev_priv); 485 if (ret) 486 goto err_ggtt; 487 488 /* 489 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 490 * might be different due to bar resizing. 491 */ 492 ret = intel_gt_tiles_init(dev_priv); 493 if (ret) 494 goto err_ggtt; 495 496 ret = intel_memory_regions_hw_probe(dev_priv); 497 if (ret) 498 goto err_ggtt; 499 500 ret = i915_ggtt_enable_hw(dev_priv); 501 if (ret) { 502 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 503 goto err_mem_regions; 504 } 505 506 pci_set_master(pdev); 507 508 /* On the 945G/GM, the chipset reports the MSI capability on the 509 * integrated graphics even though the support isn't actually there 510 * according to the published specs. It doesn't appear to function 511 * correctly in testing on 945G. 512 * This may be a side effect of MSI having been made available for PEG 513 * and the registers being closely associated. 514 * 515 * According to chipset errata, on the 965GM, MSI interrupts may 516 * be lost or delayed, and was defeatured. MSI interrupts seem to 517 * get lost on g4x as well, and interrupt delivery seems to stay 518 * properly dead afterwards. So we'll just disable them for all 519 * pre-gen5 chipsets. 520 * 521 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 522 * interrupts even when in MSI mode. This results in spurious 523 * interrupt warnings if the legacy irq no. is shared with another 524 * device. The kernel then disables that interrupt source and so 525 * prevents the other device from working properly. 526 */ 527 if (GRAPHICS_VER(dev_priv) >= 5) { 528 if (pci_enable_msi(pdev) < 0) 529 drm_dbg(&dev_priv->drm, "can't enable MSI"); 530 } 531 532 ret = intel_gvt_init(dev_priv); 533 if (ret) 534 goto err_msi; 535 536 intel_opregion_setup(dev_priv); 537 538 ret = i915_pcode_init(dev_priv); 539 if (ret) 540 goto err_opregion; 541 542 /* 543 * Fill the dram structure to get the system dram info. This will be 544 * used for memory latency calculation. 545 */ 546 intel_dram_detect(dev_priv); 547 548 intel_bw_init_hw(dev_priv); 549 550 /* 551 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 552 * This should be totally removed when we handle the pci states properly 553 * on runtime PM and on s2idle cases. 554 */ 555 root_pdev = pcie_find_root_port(pdev); 556 if (root_pdev) 557 pci_d3cold_disable(root_pdev); 558 559 return 0; 560 561 err_opregion: 562 intel_opregion_cleanup(dev_priv); 563 err_msi: 564 if (pdev->msi_enabled) 565 pci_disable_msi(pdev); 566 err_mem_regions: 567 intel_memory_regions_driver_release(dev_priv); 568 err_ggtt: 569 i915_ggtt_driver_release(dev_priv); 570 i915_gem_drain_freed_objects(dev_priv); 571 i915_ggtt_driver_late_release(dev_priv); 572 err_perf: 573 i915_perf_fini(dev_priv); 574 return ret; 575 } 576 577 /** 578 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 579 * @dev_priv: device private 580 */ 581 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 582 { 583 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 584 struct pci_dev *root_pdev; 585 586 i915_perf_fini(dev_priv); 587 588 intel_opregion_cleanup(dev_priv); 589 590 if (pdev->msi_enabled) 591 pci_disable_msi(pdev); 592 593 root_pdev = pcie_find_root_port(pdev); 594 if (root_pdev) 595 pci_d3cold_enable(root_pdev); 596 } 597 598 /** 599 * i915_driver_register - register the driver with the rest of the system 600 * @dev_priv: device private 601 * 602 * Perform any steps necessary to make the driver available via kernel 603 * internal or userspace interfaces. 604 */ 605 static void i915_driver_register(struct drm_i915_private *dev_priv) 606 { 607 struct intel_gt *gt; 608 unsigned int i; 609 610 i915_gem_driver_register(dev_priv); 611 i915_pmu_register(dev_priv); 612 613 intel_vgpu_register(dev_priv); 614 615 /* Reveal our presence to userspace */ 616 if (drm_dev_register(&dev_priv->drm, 0)) { 617 drm_err(&dev_priv->drm, 618 "Failed to register driver for userspace access!\n"); 619 return; 620 } 621 622 i915_debugfs_register(dev_priv); 623 i915_setup_sysfs(dev_priv); 624 625 /* Depends on sysfs having been initialized */ 626 i915_perf_register(dev_priv); 627 628 for_each_gt(gt, dev_priv, i) 629 intel_gt_driver_register(gt); 630 631 intel_pxp_debugfs_register(dev_priv->pxp); 632 633 i915_hwmon_register(dev_priv); 634 635 intel_display_driver_register(dev_priv); 636 637 intel_power_domains_enable(dev_priv); 638 intel_runtime_pm_enable(&dev_priv->runtime_pm); 639 640 intel_register_dsm_handler(); 641 642 if (i915_switcheroo_register(dev_priv)) 643 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 644 } 645 646 /** 647 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 648 * @dev_priv: device private 649 */ 650 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 651 { 652 struct intel_gt *gt; 653 unsigned int i; 654 655 i915_switcheroo_unregister(dev_priv); 656 657 intel_unregister_dsm_handler(); 658 659 intel_runtime_pm_disable(&dev_priv->runtime_pm); 660 intel_power_domains_disable(dev_priv); 661 662 intel_display_driver_unregister(dev_priv); 663 664 intel_pxp_fini(dev_priv); 665 666 for_each_gt(gt, dev_priv, i) 667 intel_gt_driver_unregister(gt); 668 669 i915_hwmon_unregister(dev_priv); 670 671 i915_perf_unregister(dev_priv); 672 i915_pmu_unregister(dev_priv); 673 674 i915_teardown_sysfs(dev_priv); 675 drm_dev_unplug(&dev_priv->drm); 676 677 i915_gem_driver_unregister(dev_priv); 678 } 679 680 void 681 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 682 { 683 drm_printf(p, "iommu: %s\n", 684 str_enabled_disabled(i915_vtd_active(i915))); 685 } 686 687 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 688 { 689 if (drm_debug_enabled(DRM_UT_DRIVER)) { 690 struct drm_printer p = drm_debug_printer("i915 device info:"); 691 struct intel_gt *gt; 692 unsigned int i; 693 694 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 695 INTEL_DEVID(dev_priv), 696 INTEL_REVID(dev_priv), 697 intel_platform_name(INTEL_INFO(dev_priv)->platform), 698 intel_subplatform(RUNTIME_INFO(dev_priv), 699 INTEL_INFO(dev_priv)->platform), 700 GRAPHICS_VER(dev_priv)); 701 702 intel_device_info_print(INTEL_INFO(dev_priv), 703 RUNTIME_INFO(dev_priv), &p); 704 i915_print_iommu_status(dev_priv, &p); 705 for_each_gt(gt, dev_priv, i) 706 intel_gt_info_print(>->info, &p); 707 } 708 709 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 710 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 711 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 712 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 713 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 714 drm_info(&dev_priv->drm, 715 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 716 } 717 718 static struct drm_i915_private * 719 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 720 { 721 const struct intel_device_info *match_info = 722 (struct intel_device_info *)ent->driver_data; 723 struct intel_device_info *device_info; 724 struct intel_runtime_info *runtime; 725 struct drm_i915_private *i915; 726 727 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 728 struct drm_i915_private, drm); 729 if (IS_ERR(i915)) 730 return i915; 731 732 pci_set_drvdata(pdev, i915); 733 734 /* Device parameters start as a copy of module parameters. */ 735 i915_params_copy(&i915->params, &i915_modparams); 736 737 /* Setup the write-once "constant" device info */ 738 device_info = mkwrite_device_info(i915); 739 memcpy(device_info, match_info, sizeof(*device_info)); 740 741 /* Initialize initial runtime info from static const data and pdev. */ 742 runtime = RUNTIME_INFO(i915); 743 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 744 runtime->device_id = pdev->device; 745 746 return i915; 747 } 748 749 /** 750 * i915_driver_probe - setup chip and create an initial config 751 * @pdev: PCI device 752 * @ent: matching PCI ID entry 753 * 754 * The driver probe routine has to do several things: 755 * - drive output discovery via intel_modeset_init() 756 * - initialize the memory manager 757 * - allocate initial config memory 758 * - setup the DRM framebuffer with the allocated memory 759 */ 760 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 761 { 762 struct drm_i915_private *i915; 763 int ret; 764 765 i915 = i915_driver_create(pdev, ent); 766 if (IS_ERR(i915)) 767 return PTR_ERR(i915); 768 769 ret = pci_enable_device(pdev); 770 if (ret) 771 goto out_fini; 772 773 ret = i915_driver_early_probe(i915); 774 if (ret < 0) 775 goto out_pci_disable; 776 777 disable_rpm_wakeref_asserts(&i915->runtime_pm); 778 779 intel_vgpu_detect(i915); 780 781 ret = intel_gt_probe_all(i915); 782 if (ret < 0) 783 goto out_runtime_pm_put; 784 785 ret = i915_driver_mmio_probe(i915); 786 if (ret < 0) 787 goto out_tiles_cleanup; 788 789 ret = i915_driver_hw_probe(i915); 790 if (ret < 0) 791 goto out_cleanup_mmio; 792 793 ret = intel_modeset_init_noirq(i915); 794 if (ret < 0) 795 goto out_cleanup_hw; 796 797 ret = intel_irq_install(i915); 798 if (ret) 799 goto out_cleanup_modeset; 800 801 ret = intel_modeset_init_nogem(i915); 802 if (ret) 803 goto out_cleanup_irq; 804 805 ret = i915_gem_init(i915); 806 if (ret) 807 goto out_cleanup_modeset2; 808 809 intel_pxp_init(i915); 810 811 ret = intel_modeset_init(i915); 812 if (ret) 813 goto out_cleanup_gem; 814 815 i915_driver_register(i915); 816 817 enable_rpm_wakeref_asserts(&i915->runtime_pm); 818 819 i915_welcome_messages(i915); 820 821 i915->do_release = true; 822 823 return 0; 824 825 out_cleanup_gem: 826 i915_gem_suspend(i915); 827 i915_gem_driver_remove(i915); 828 i915_gem_driver_release(i915); 829 out_cleanup_modeset2: 830 /* FIXME clean up the error path */ 831 intel_modeset_driver_remove(i915); 832 intel_irq_uninstall(i915); 833 intel_modeset_driver_remove_noirq(i915); 834 goto out_cleanup_modeset; 835 out_cleanup_irq: 836 intel_irq_uninstall(i915); 837 out_cleanup_modeset: 838 intel_modeset_driver_remove_nogem(i915); 839 out_cleanup_hw: 840 i915_driver_hw_remove(i915); 841 intel_memory_regions_driver_release(i915); 842 i915_ggtt_driver_release(i915); 843 i915_gem_drain_freed_objects(i915); 844 i915_ggtt_driver_late_release(i915); 845 out_cleanup_mmio: 846 i915_driver_mmio_release(i915); 847 out_tiles_cleanup: 848 intel_gt_release_all(i915); 849 out_runtime_pm_put: 850 enable_rpm_wakeref_asserts(&i915->runtime_pm); 851 i915_driver_late_release(i915); 852 out_pci_disable: 853 pci_disable_device(pdev); 854 out_fini: 855 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 856 return ret; 857 } 858 859 void i915_driver_remove(struct drm_i915_private *i915) 860 { 861 intel_wakeref_t wakeref; 862 863 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 864 865 i915_driver_unregister(i915); 866 867 /* Flush any external code that still may be under the RCU lock */ 868 synchronize_rcu(); 869 870 i915_gem_suspend(i915); 871 872 intel_gvt_driver_remove(i915); 873 874 intel_modeset_driver_remove(i915); 875 876 intel_irq_uninstall(i915); 877 878 intel_modeset_driver_remove_noirq(i915); 879 880 i915_reset_error_state(i915); 881 i915_gem_driver_remove(i915); 882 883 intel_modeset_driver_remove_nogem(i915); 884 885 i915_driver_hw_remove(i915); 886 887 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 888 } 889 890 static void i915_driver_release(struct drm_device *dev) 891 { 892 struct drm_i915_private *dev_priv = to_i915(dev); 893 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 894 intel_wakeref_t wakeref; 895 896 if (!dev_priv->do_release) 897 return; 898 899 wakeref = intel_runtime_pm_get(rpm); 900 901 i915_gem_driver_release(dev_priv); 902 903 intel_memory_regions_driver_release(dev_priv); 904 i915_ggtt_driver_release(dev_priv); 905 i915_gem_drain_freed_objects(dev_priv); 906 i915_ggtt_driver_late_release(dev_priv); 907 908 i915_driver_mmio_release(dev_priv); 909 910 intel_runtime_pm_put(rpm, wakeref); 911 912 intel_runtime_pm_driver_release(rpm); 913 914 i915_driver_late_release(dev_priv); 915 } 916 917 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 918 { 919 struct drm_i915_private *i915 = to_i915(dev); 920 int ret; 921 922 ret = i915_gem_open(i915, file); 923 if (ret) 924 return ret; 925 926 return 0; 927 } 928 929 /** 930 * i915_driver_lastclose - clean up after all DRM clients have exited 931 * @dev: DRM device 932 * 933 * Take care of cleaning up after all DRM clients have exited. In the 934 * mode setting case, we want to restore the kernel's initial mode (just 935 * in case the last client left us in a bad state). 936 * 937 * Additionally, in the non-mode setting case, we'll tear down the GTT 938 * and DMA structures, since the kernel won't be using them, and clea 939 * up any GEM state. 940 */ 941 static void i915_driver_lastclose(struct drm_device *dev) 942 { 943 struct drm_i915_private *i915 = to_i915(dev); 944 945 intel_fbdev_restore_mode(i915); 946 947 vga_switcheroo_process_delayed_switch(); 948 } 949 950 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 951 { 952 struct drm_i915_file_private *file_priv = file->driver_priv; 953 954 i915_gem_context_close(file); 955 i915_drm_client_put(file_priv->client); 956 957 kfree_rcu(file_priv, rcu); 958 959 /* Catch up with all the deferred frees from "this" client */ 960 i915_gem_flush_free_objects(to_i915(dev)); 961 } 962 963 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 964 { 965 struct intel_encoder *encoder; 966 967 if (!HAS_DISPLAY(dev_priv)) 968 return; 969 970 drm_modeset_lock_all(&dev_priv->drm); 971 for_each_intel_encoder(&dev_priv->drm, encoder) 972 if (encoder->suspend) 973 encoder->suspend(encoder); 974 drm_modeset_unlock_all(&dev_priv->drm); 975 } 976 977 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 978 { 979 struct intel_encoder *encoder; 980 981 if (!HAS_DISPLAY(dev_priv)) 982 return; 983 984 drm_modeset_lock_all(&dev_priv->drm); 985 for_each_intel_encoder(&dev_priv->drm, encoder) 986 if (encoder->shutdown) 987 encoder->shutdown(encoder); 988 drm_modeset_unlock_all(&dev_priv->drm); 989 } 990 991 void i915_driver_shutdown(struct drm_i915_private *i915) 992 { 993 disable_rpm_wakeref_asserts(&i915->runtime_pm); 994 intel_runtime_pm_disable(&i915->runtime_pm); 995 intel_power_domains_disable(i915); 996 997 if (HAS_DISPLAY(i915)) { 998 drm_kms_helper_poll_disable(&i915->drm); 999 1000 drm_atomic_helper_shutdown(&i915->drm); 1001 } 1002 1003 intel_dp_mst_suspend(i915); 1004 1005 intel_runtime_pm_disable_interrupts(i915); 1006 intel_hpd_cancel_work(i915); 1007 1008 intel_suspend_encoders(i915); 1009 intel_shutdown_encoders(i915); 1010 1011 intel_dmc_suspend(i915); 1012 1013 i915_gem_suspend(i915); 1014 1015 /* 1016 * The only requirement is to reboot with display DC states disabled, 1017 * for now leaving all display power wells in the INIT power domain 1018 * enabled. 1019 * 1020 * TODO: 1021 * - unify the pci_driver::shutdown sequence here with the 1022 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1023 * - unify the driver remove and system/runtime suspend sequences with 1024 * the above unified shutdown/poweroff sequence. 1025 */ 1026 intel_power_domains_driver_remove(i915); 1027 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1028 1029 intel_runtime_pm_driver_release(&i915->runtime_pm); 1030 } 1031 1032 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1033 { 1034 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1035 if (acpi_target_system_state() < ACPI_STATE_S3) 1036 return true; 1037 #endif 1038 return false; 1039 } 1040 1041 static void i915_drm_complete(struct drm_device *dev) 1042 { 1043 struct drm_i915_private *i915 = to_i915(dev); 1044 1045 intel_pxp_resume_complete(i915->pxp); 1046 } 1047 1048 static int i915_drm_prepare(struct drm_device *dev) 1049 { 1050 struct drm_i915_private *i915 = to_i915(dev); 1051 1052 intel_pxp_suspend_prepare(i915->pxp); 1053 1054 /* 1055 * NB intel_display_suspend() may issue new requests after we've 1056 * ostensibly marked the GPU as ready-to-sleep here. We need to 1057 * split out that work and pull it forward so that after point, 1058 * the GPU is not woken again. 1059 */ 1060 return i915_gem_backup_suspend(i915); 1061 } 1062 1063 static int i915_drm_suspend(struct drm_device *dev) 1064 { 1065 struct drm_i915_private *dev_priv = to_i915(dev); 1066 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1067 pci_power_t opregion_target_state; 1068 1069 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1070 1071 /* We do a lot of poking in a lot of registers, make sure they work 1072 * properly. */ 1073 intel_power_domains_disable(dev_priv); 1074 if (HAS_DISPLAY(dev_priv)) 1075 drm_kms_helper_poll_disable(dev); 1076 1077 pci_save_state(pdev); 1078 1079 intel_display_suspend(dev); 1080 1081 intel_dp_mst_suspend(dev_priv); 1082 1083 intel_runtime_pm_disable_interrupts(dev_priv); 1084 intel_hpd_cancel_work(dev_priv); 1085 1086 intel_suspend_encoders(dev_priv); 1087 1088 /* Must be called before GGTT is suspended. */ 1089 intel_dpt_suspend(dev_priv); 1090 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1091 1092 i915_save_display(dev_priv); 1093 1094 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1095 intel_opregion_suspend(dev_priv, opregion_target_state); 1096 1097 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1098 1099 dev_priv->suspend_count++; 1100 1101 intel_dmc_suspend(dev_priv); 1102 1103 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1104 1105 i915_gem_drain_freed_objects(dev_priv); 1106 1107 return 0; 1108 } 1109 1110 static enum i915_drm_suspend_mode 1111 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1112 { 1113 if (hibernate) 1114 return I915_DRM_SUSPEND_HIBERNATE; 1115 1116 if (suspend_to_idle(dev_priv)) 1117 return I915_DRM_SUSPEND_IDLE; 1118 1119 return I915_DRM_SUSPEND_MEM; 1120 } 1121 1122 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1123 { 1124 struct drm_i915_private *dev_priv = to_i915(dev); 1125 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1126 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1127 struct intel_gt *gt; 1128 int ret, i; 1129 1130 disable_rpm_wakeref_asserts(rpm); 1131 1132 intel_pxp_suspend(dev_priv->pxp); 1133 1134 i915_gem_suspend_late(dev_priv); 1135 1136 for_each_gt(gt, dev_priv, i) 1137 intel_uncore_suspend(gt->uncore); 1138 1139 intel_power_domains_suspend(dev_priv, 1140 get_suspend_mode(dev_priv, hibernation)); 1141 1142 intel_display_power_suspend_late(dev_priv); 1143 1144 ret = vlv_suspend_complete(dev_priv); 1145 if (ret) { 1146 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1147 intel_power_domains_resume(dev_priv); 1148 1149 goto out; 1150 } 1151 1152 pci_disable_device(pdev); 1153 /* 1154 * During hibernation on some platforms the BIOS may try to access 1155 * the device even though it's already in D3 and hang the machine. So 1156 * leave the device in D0 on those platforms and hope the BIOS will 1157 * power down the device properly. The issue was seen on multiple old 1158 * GENs with different BIOS vendors, so having an explicit blacklist 1159 * is inpractical; apply the workaround on everything pre GEN6. The 1160 * platforms where the issue was seen: 1161 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1162 * Fujitsu FSC S7110 1163 * Acer Aspire 1830T 1164 */ 1165 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1166 pci_set_power_state(pdev, PCI_D3hot); 1167 1168 out: 1169 enable_rpm_wakeref_asserts(rpm); 1170 if (!dev_priv->uncore.user_forcewake_count) 1171 intel_runtime_pm_driver_release(rpm); 1172 1173 return ret; 1174 } 1175 1176 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1177 pm_message_t state) 1178 { 1179 int error; 1180 1181 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1182 state.event != PM_EVENT_FREEZE)) 1183 return -EINVAL; 1184 1185 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1186 return 0; 1187 1188 error = i915_drm_suspend(&i915->drm); 1189 if (error) 1190 return error; 1191 1192 return i915_drm_suspend_late(&i915->drm, false); 1193 } 1194 1195 static int i915_drm_resume(struct drm_device *dev) 1196 { 1197 struct drm_i915_private *dev_priv = to_i915(dev); 1198 struct intel_gt *gt; 1199 int ret, i; 1200 1201 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1202 1203 ret = i915_pcode_init(dev_priv); 1204 if (ret) 1205 return ret; 1206 1207 sanitize_gpu(dev_priv); 1208 1209 ret = i915_ggtt_enable_hw(dev_priv); 1210 if (ret) 1211 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1212 1213 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1214 1215 for_each_gt(gt, dev_priv, i) 1216 if (GRAPHICS_VER(gt->i915) >= 8) 1217 setup_private_pat(gt); 1218 1219 /* Must be called after GGTT is resumed. */ 1220 intel_dpt_resume(dev_priv); 1221 1222 intel_dmc_resume(dev_priv); 1223 1224 i915_restore_display(dev_priv); 1225 intel_pps_unlock_regs_wa(dev_priv); 1226 1227 intel_init_pch_refclk(dev_priv); 1228 1229 /* 1230 * Interrupts have to be enabled before any batches are run. If not the 1231 * GPU will hang. i915_gem_init_hw() will initiate batches to 1232 * update/restore the context. 1233 * 1234 * drm_mode_config_reset() needs AUX interrupts. 1235 * 1236 * Modeset enabling in intel_modeset_init_hw() also needs working 1237 * interrupts. 1238 */ 1239 intel_runtime_pm_enable_interrupts(dev_priv); 1240 1241 if (HAS_DISPLAY(dev_priv)) 1242 drm_mode_config_reset(dev); 1243 1244 i915_gem_resume(dev_priv); 1245 1246 intel_modeset_init_hw(dev_priv); 1247 intel_clock_gating_init(dev_priv); 1248 intel_hpd_init(dev_priv); 1249 1250 /* MST sideband requires HPD interrupts enabled */ 1251 intel_dp_mst_resume(dev_priv); 1252 intel_display_resume(dev); 1253 1254 intel_hpd_poll_disable(dev_priv); 1255 if (HAS_DISPLAY(dev_priv)) 1256 drm_kms_helper_poll_enable(dev); 1257 1258 intel_opregion_resume(dev_priv); 1259 1260 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1261 1262 intel_power_domains_enable(dev_priv); 1263 1264 intel_gvt_resume(dev_priv); 1265 1266 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1267 1268 return 0; 1269 } 1270 1271 static int i915_drm_resume_early(struct drm_device *dev) 1272 { 1273 struct drm_i915_private *dev_priv = to_i915(dev); 1274 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1275 struct intel_gt *gt; 1276 int ret, i; 1277 1278 /* 1279 * We have a resume ordering issue with the snd-hda driver also 1280 * requiring our device to be power up. Due to the lack of a 1281 * parent/child relationship we currently solve this with an early 1282 * resume hook. 1283 * 1284 * FIXME: This should be solved with a special hdmi sink device or 1285 * similar so that power domains can be employed. 1286 */ 1287 1288 /* 1289 * Note that we need to set the power state explicitly, since we 1290 * powered off the device during freeze and the PCI core won't power 1291 * it back up for us during thaw. Powering off the device during 1292 * freeze is not a hard requirement though, and during the 1293 * suspend/resume phases the PCI core makes sure we get here with the 1294 * device powered on. So in case we change our freeze logic and keep 1295 * the device powered we can also remove the following set power state 1296 * call. 1297 */ 1298 ret = pci_set_power_state(pdev, PCI_D0); 1299 if (ret) { 1300 drm_err(&dev_priv->drm, 1301 "failed to set PCI D0 power state (%d)\n", ret); 1302 return ret; 1303 } 1304 1305 /* 1306 * Note that pci_enable_device() first enables any parent bridge 1307 * device and only then sets the power state for this device. The 1308 * bridge enabling is a nop though, since bridge devices are resumed 1309 * first. The order of enabling power and enabling the device is 1310 * imposed by the PCI core as described above, so here we preserve the 1311 * same order for the freeze/thaw phases. 1312 * 1313 * TODO: eventually we should remove pci_disable_device() / 1314 * pci_enable_enable_device() from suspend/resume. Due to how they 1315 * depend on the device enable refcount we can't anyway depend on them 1316 * disabling/enabling the device. 1317 */ 1318 if (pci_enable_device(pdev)) 1319 return -EIO; 1320 1321 pci_set_master(pdev); 1322 1323 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1324 1325 ret = vlv_resume_prepare(dev_priv, false); 1326 if (ret) 1327 drm_err(&dev_priv->drm, 1328 "Resume prepare failed: %d, continuing anyway\n", ret); 1329 1330 for_each_gt(gt, dev_priv, i) { 1331 intel_uncore_resume_early(gt->uncore); 1332 intel_gt_check_and_clear_faults(gt); 1333 } 1334 1335 intel_display_power_resume_early(dev_priv); 1336 1337 intel_power_domains_resume(dev_priv); 1338 1339 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1340 1341 return ret; 1342 } 1343 1344 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1345 { 1346 int ret; 1347 1348 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1349 return 0; 1350 1351 ret = i915_drm_resume_early(&i915->drm); 1352 if (ret) 1353 return ret; 1354 1355 return i915_drm_resume(&i915->drm); 1356 } 1357 1358 static int i915_pm_prepare(struct device *kdev) 1359 { 1360 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1361 1362 if (!i915) { 1363 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1364 return -ENODEV; 1365 } 1366 1367 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1368 return 0; 1369 1370 return i915_drm_prepare(&i915->drm); 1371 } 1372 1373 static int i915_pm_suspend(struct device *kdev) 1374 { 1375 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1376 1377 if (!i915) { 1378 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1379 return -ENODEV; 1380 } 1381 1382 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1383 return 0; 1384 1385 return i915_drm_suspend(&i915->drm); 1386 } 1387 1388 static int i915_pm_suspend_late(struct device *kdev) 1389 { 1390 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1391 1392 /* 1393 * We have a suspend ordering issue with the snd-hda driver also 1394 * requiring our device to be power up. Due to the lack of a 1395 * parent/child relationship we currently solve this with an late 1396 * suspend hook. 1397 * 1398 * FIXME: This should be solved with a special hdmi sink device or 1399 * similar so that power domains can be employed. 1400 */ 1401 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1402 return 0; 1403 1404 return i915_drm_suspend_late(&i915->drm, false); 1405 } 1406 1407 static int i915_pm_poweroff_late(struct device *kdev) 1408 { 1409 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1410 1411 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1412 return 0; 1413 1414 return i915_drm_suspend_late(&i915->drm, true); 1415 } 1416 1417 static int i915_pm_resume_early(struct device *kdev) 1418 { 1419 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1420 1421 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1422 return 0; 1423 1424 return i915_drm_resume_early(&i915->drm); 1425 } 1426 1427 static int i915_pm_resume(struct device *kdev) 1428 { 1429 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1430 1431 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1432 return 0; 1433 1434 return i915_drm_resume(&i915->drm); 1435 } 1436 1437 static void i915_pm_complete(struct device *kdev) 1438 { 1439 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1440 1441 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1442 return; 1443 1444 i915_drm_complete(&i915->drm); 1445 } 1446 1447 /* freeze: before creating the hibernation_image */ 1448 static int i915_pm_freeze(struct device *kdev) 1449 { 1450 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1451 int ret; 1452 1453 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1454 ret = i915_drm_suspend(&i915->drm); 1455 if (ret) 1456 return ret; 1457 } 1458 1459 ret = i915_gem_freeze(i915); 1460 if (ret) 1461 return ret; 1462 1463 return 0; 1464 } 1465 1466 static int i915_pm_freeze_late(struct device *kdev) 1467 { 1468 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1469 int ret; 1470 1471 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1472 ret = i915_drm_suspend_late(&i915->drm, true); 1473 if (ret) 1474 return ret; 1475 } 1476 1477 ret = i915_gem_freeze_late(i915); 1478 if (ret) 1479 return ret; 1480 1481 return 0; 1482 } 1483 1484 /* thaw: called after creating the hibernation image, but before turning off. */ 1485 static int i915_pm_thaw_early(struct device *kdev) 1486 { 1487 return i915_pm_resume_early(kdev); 1488 } 1489 1490 static int i915_pm_thaw(struct device *kdev) 1491 { 1492 return i915_pm_resume(kdev); 1493 } 1494 1495 /* restore: called after loading the hibernation image. */ 1496 static int i915_pm_restore_early(struct device *kdev) 1497 { 1498 return i915_pm_resume_early(kdev); 1499 } 1500 1501 static int i915_pm_restore(struct device *kdev) 1502 { 1503 return i915_pm_resume(kdev); 1504 } 1505 1506 static int intel_runtime_suspend(struct device *kdev) 1507 { 1508 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1509 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1510 struct intel_gt *gt; 1511 int ret, i; 1512 1513 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1514 return -ENODEV; 1515 1516 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1517 1518 disable_rpm_wakeref_asserts(rpm); 1519 1520 /* 1521 * We are safe here against re-faults, since the fault handler takes 1522 * an RPM reference. 1523 */ 1524 i915_gem_runtime_suspend(dev_priv); 1525 1526 intel_pxp_runtime_suspend(dev_priv->pxp); 1527 1528 for_each_gt(gt, dev_priv, i) 1529 intel_gt_runtime_suspend(gt); 1530 1531 intel_runtime_pm_disable_interrupts(dev_priv); 1532 1533 for_each_gt(gt, dev_priv, i) 1534 intel_uncore_suspend(gt->uncore); 1535 1536 intel_display_power_suspend(dev_priv); 1537 1538 ret = vlv_suspend_complete(dev_priv); 1539 if (ret) { 1540 drm_err(&dev_priv->drm, 1541 "Runtime suspend failed, disabling it (%d)\n", ret); 1542 intel_uncore_runtime_resume(&dev_priv->uncore); 1543 1544 intel_runtime_pm_enable_interrupts(dev_priv); 1545 1546 for_each_gt(gt, dev_priv, i) 1547 intel_gt_runtime_resume(gt); 1548 1549 enable_rpm_wakeref_asserts(rpm); 1550 1551 return ret; 1552 } 1553 1554 enable_rpm_wakeref_asserts(rpm); 1555 intel_runtime_pm_driver_release(rpm); 1556 1557 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1558 drm_err(&dev_priv->drm, 1559 "Unclaimed access detected prior to suspending\n"); 1560 1561 rpm->suspended = true; 1562 1563 /* 1564 * FIXME: We really should find a document that references the arguments 1565 * used below! 1566 */ 1567 if (IS_BROADWELL(dev_priv)) { 1568 /* 1569 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1570 * being detected, and the call we do at intel_runtime_resume() 1571 * won't be able to restore them. Since PCI_D3hot matches the 1572 * actual specification and appears to be working, use it. 1573 */ 1574 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1575 } else { 1576 /* 1577 * current versions of firmware which depend on this opregion 1578 * notification have repurposed the D1 definition to mean 1579 * "runtime suspended" vs. what you would normally expect (D3) 1580 * to distinguish it from notifications that might be sent via 1581 * the suspend path. 1582 */ 1583 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1584 } 1585 1586 assert_forcewakes_inactive(&dev_priv->uncore); 1587 1588 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1589 intel_hpd_poll_enable(dev_priv); 1590 1591 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1592 return 0; 1593 } 1594 1595 static int intel_runtime_resume(struct device *kdev) 1596 { 1597 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1598 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1599 struct intel_gt *gt; 1600 int ret, i; 1601 1602 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1603 return -ENODEV; 1604 1605 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1606 1607 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1608 disable_rpm_wakeref_asserts(rpm); 1609 1610 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1611 rpm->suspended = false; 1612 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1613 drm_dbg(&dev_priv->drm, 1614 "Unclaimed access during suspend, bios?\n"); 1615 1616 intel_display_power_resume(dev_priv); 1617 1618 ret = vlv_resume_prepare(dev_priv, true); 1619 1620 for_each_gt(gt, dev_priv, i) 1621 intel_uncore_runtime_resume(gt->uncore); 1622 1623 intel_runtime_pm_enable_interrupts(dev_priv); 1624 1625 /* 1626 * No point of rolling back things in case of an error, as the best 1627 * we can do is to hope that things will still work (and disable RPM). 1628 */ 1629 for_each_gt(gt, dev_priv, i) 1630 intel_gt_runtime_resume(gt); 1631 1632 intel_pxp_runtime_resume(dev_priv->pxp); 1633 1634 /* 1635 * On VLV/CHV display interrupts are part of the display 1636 * power well, so hpd is reinitialized from there. For 1637 * everyone else do it here. 1638 */ 1639 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1640 intel_hpd_init(dev_priv); 1641 intel_hpd_poll_disable(dev_priv); 1642 } 1643 1644 skl_watermark_ipc_update(dev_priv); 1645 1646 enable_rpm_wakeref_asserts(rpm); 1647 1648 if (ret) 1649 drm_err(&dev_priv->drm, 1650 "Runtime resume failed, disabling it (%d)\n", ret); 1651 else 1652 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1653 1654 return ret; 1655 } 1656 1657 const struct dev_pm_ops i915_pm_ops = { 1658 /* 1659 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1660 * PMSG_RESUME] 1661 */ 1662 .prepare = i915_pm_prepare, 1663 .suspend = i915_pm_suspend, 1664 .suspend_late = i915_pm_suspend_late, 1665 .resume_early = i915_pm_resume_early, 1666 .resume = i915_pm_resume, 1667 .complete = i915_pm_complete, 1668 1669 /* 1670 * S4 event handlers 1671 * @freeze, @freeze_late : called (1) before creating the 1672 * hibernation image [PMSG_FREEZE] and 1673 * (2) after rebooting, before restoring 1674 * the image [PMSG_QUIESCE] 1675 * @thaw, @thaw_early : called (1) after creating the hibernation 1676 * image, before writing it [PMSG_THAW] 1677 * and (2) after failing to create or 1678 * restore the image [PMSG_RECOVER] 1679 * @poweroff, @poweroff_late: called after writing the hibernation 1680 * image, before rebooting [PMSG_HIBERNATE] 1681 * @restore, @restore_early : called after rebooting and restoring the 1682 * hibernation image [PMSG_RESTORE] 1683 */ 1684 .freeze = i915_pm_freeze, 1685 .freeze_late = i915_pm_freeze_late, 1686 .thaw_early = i915_pm_thaw_early, 1687 .thaw = i915_pm_thaw, 1688 .poweroff = i915_pm_suspend, 1689 .poweroff_late = i915_pm_poweroff_late, 1690 .restore_early = i915_pm_restore_early, 1691 .restore = i915_pm_restore, 1692 1693 /* S0ix (via runtime suspend) event handlers */ 1694 .runtime_suspend = intel_runtime_suspend, 1695 .runtime_resume = intel_runtime_resume, 1696 }; 1697 1698 static const struct file_operations i915_driver_fops = { 1699 .owner = THIS_MODULE, 1700 .open = drm_open, 1701 .release = drm_release_noglobal, 1702 .unlocked_ioctl = drm_ioctl, 1703 .mmap = i915_gem_mmap, 1704 .poll = drm_poll, 1705 .read = drm_read, 1706 .compat_ioctl = i915_ioc32_compat_ioctl, 1707 .llseek = noop_llseek, 1708 #ifdef CONFIG_PROC_FS 1709 .show_fdinfo = i915_drm_client_fdinfo, 1710 #endif 1711 }; 1712 1713 static int 1714 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1715 struct drm_file *file) 1716 { 1717 return -ENODEV; 1718 } 1719 1720 static const struct drm_ioctl_desc i915_ioctls[] = { 1721 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1722 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1723 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1724 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1725 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1726 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1727 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1728 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1729 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1730 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1731 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1732 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1733 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1734 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1735 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1736 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1737 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1738 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1739 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1740 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1742 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1743 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1744 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1745 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1746 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1747 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1749 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1750 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1751 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1752 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1753 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1754 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1755 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1756 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1757 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1758 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1759 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1760 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1761 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1762 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1763 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1764 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1765 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1766 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1767 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1768 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1771 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1772 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1773 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1774 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1775 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1776 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1777 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1779 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1780 }; 1781 1782 /* 1783 * Interface history: 1784 * 1785 * 1.1: Original. 1786 * 1.2: Add Power Management 1787 * 1.3: Add vblank support 1788 * 1.4: Fix cmdbuffer path, add heap destroy 1789 * 1.5: Add vblank pipe configuration 1790 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1791 * - Support vertical blank on secondary display pipe 1792 */ 1793 #define DRIVER_MAJOR 1 1794 #define DRIVER_MINOR 6 1795 #define DRIVER_PATCHLEVEL 0 1796 1797 static const struct drm_driver i915_drm_driver = { 1798 /* Don't use MTRRs here; the Xserver or userspace app should 1799 * deal with them for Intel hardware. 1800 */ 1801 .driver_features = 1802 DRIVER_GEM | 1803 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1804 DRIVER_SYNCOBJ_TIMELINE, 1805 .release = i915_driver_release, 1806 .open = i915_driver_open, 1807 .lastclose = i915_driver_lastclose, 1808 .postclose = i915_driver_postclose, 1809 1810 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1811 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1812 .gem_prime_import = i915_gem_prime_import, 1813 1814 .dumb_create = i915_gem_dumb_create, 1815 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1816 1817 .ioctls = i915_ioctls, 1818 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1819 .fops = &i915_driver_fops, 1820 .name = DRIVER_NAME, 1821 .desc = DRIVER_DESC, 1822 .date = DRIVER_DATE, 1823 .major = DRIVER_MAJOR, 1824 .minor = DRIVER_MINOR, 1825 .patchlevel = DRIVER_PATCHLEVEL, 1826 }; 1827