1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_types.h" 52 #include "display/intel_dmc.h" 53 #include "display/intel_dp.h" 54 #include "display/intel_dpt.h" 55 #include "display/intel_fbdev.h" 56 #include "display/intel_hotplug.h" 57 #include "display/intel_overlay.h" 58 #include "display/intel_pch_refclk.h" 59 #include "display/intel_pipe_crc.h" 60 #include "display/intel_pps.h" 61 #include "display/intel_sprite.h" 62 #include "display/intel_vga.h" 63 64 #include "gem/i915_gem_context.h" 65 #include "gem/i915_gem_create.h" 66 #include "gem/i915_gem_dmabuf.h" 67 #include "gem/i915_gem_ioctls.h" 68 #include "gem/i915_gem_mman.h" 69 #include "gem/i915_gem_pm.h" 70 #include "gt/intel_gt.h" 71 #include "gt/intel_gt_pm.h" 72 #include "gt/intel_rc6.h" 73 74 #include "pxp/intel_pxp_pm.h" 75 76 #include "i915_file_private.h" 77 #include "i915_debugfs.h" 78 #include "i915_driver.h" 79 #include "i915_drv.h" 80 #include "i915_getparam.h" 81 #include "i915_ioc32.h" 82 #include "i915_ioctl.h" 83 #include "i915_irq.h" 84 #include "i915_memcpy.h" 85 #include "i915_perf.h" 86 #include "i915_query.h" 87 #include "i915_suspend.h" 88 #include "i915_switcheroo.h" 89 #include "i915_sysfs.h" 90 #include "i915_vgpu.h" 91 #include "intel_dram.h" 92 #include "intel_gvt.h" 93 #include "intel_memory_region.h" 94 #include "intel_pci_config.h" 95 #include "intel_pcode.h" 96 #include "intel_pm.h" 97 #include "intel_region_ttm.h" 98 #include "vlv_suspend.h" 99 100 static const struct drm_driver i915_drm_driver; 101 102 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 103 { 104 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 105 106 dev_priv->bridge_dev = 107 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 108 if (!dev_priv->bridge_dev) { 109 drm_err(&dev_priv->drm, "bridge device not found\n"); 110 return -EIO; 111 } 112 return 0; 113 } 114 115 /* Allocate space for the MCH regs if needed, return nonzero on error */ 116 static int 117 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 118 { 119 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 120 u32 temp_lo, temp_hi = 0; 121 u64 mchbar_addr; 122 int ret; 123 124 if (GRAPHICS_VER(dev_priv) >= 4) 125 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 126 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 127 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 128 129 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 130 #ifdef CONFIG_PNP 131 if (mchbar_addr && 132 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 133 return 0; 134 #endif 135 136 /* Get some space for it */ 137 dev_priv->mch_res.name = "i915 MCHBAR"; 138 dev_priv->mch_res.flags = IORESOURCE_MEM; 139 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 140 &dev_priv->mch_res, 141 MCHBAR_SIZE, MCHBAR_SIZE, 142 PCIBIOS_MIN_MEM, 143 0, pcibios_align_resource, 144 dev_priv->bridge_dev); 145 if (ret) { 146 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 147 dev_priv->mch_res.start = 0; 148 return ret; 149 } 150 151 if (GRAPHICS_VER(dev_priv) >= 4) 152 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 153 upper_32_bits(dev_priv->mch_res.start)); 154 155 pci_write_config_dword(dev_priv->bridge_dev, reg, 156 lower_32_bits(dev_priv->mch_res.start)); 157 return 0; 158 } 159 160 /* Setup MCHBAR if possible, return true if we should disable it again */ 161 static void 162 intel_setup_mchbar(struct drm_i915_private *dev_priv) 163 { 164 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 165 u32 temp; 166 bool enabled; 167 168 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 169 return; 170 171 dev_priv->mchbar_need_disable = false; 172 173 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 174 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 175 enabled = !!(temp & DEVEN_MCHBAR_EN); 176 } else { 177 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 178 enabled = temp & 1; 179 } 180 181 /* If it's already enabled, don't have to do anything */ 182 if (enabled) 183 return; 184 185 if (intel_alloc_mchbar_resource(dev_priv)) 186 return; 187 188 dev_priv->mchbar_need_disable = true; 189 190 /* Space is allocated or reserved, so enable it. */ 191 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 192 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 193 temp | DEVEN_MCHBAR_EN); 194 } else { 195 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 196 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 197 } 198 } 199 200 static void 201 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 202 { 203 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 204 205 if (dev_priv->mchbar_need_disable) { 206 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 207 u32 deven_val; 208 209 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 210 &deven_val); 211 deven_val &= ~DEVEN_MCHBAR_EN; 212 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 213 deven_val); 214 } else { 215 u32 mchbar_val; 216 217 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 218 &mchbar_val); 219 mchbar_val &= ~1; 220 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 221 mchbar_val); 222 } 223 } 224 225 if (dev_priv->mch_res.start) 226 release_resource(&dev_priv->mch_res); 227 } 228 229 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 230 { 231 /* 232 * The i915 workqueue is primarily used for batched retirement of 233 * requests (and thus managing bo) once the task has been completed 234 * by the GPU. i915_retire_requests() is called directly when we 235 * need high-priority retirement, such as waiting for an explicit 236 * bo. 237 * 238 * It is also used for periodic low-priority events, such as 239 * idle-timers and recording error state. 240 * 241 * All tasks on the workqueue are expected to acquire the dev mutex 242 * so there is no point in running more than one instance of the 243 * workqueue at any time. Use an ordered one. 244 */ 245 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 246 if (dev_priv->wq == NULL) 247 goto out_err; 248 249 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 250 if (dev_priv->hotplug.dp_wq == NULL) 251 goto out_free_wq; 252 253 return 0; 254 255 out_free_wq: 256 destroy_workqueue(dev_priv->wq); 257 out_err: 258 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 259 260 return -ENOMEM; 261 } 262 263 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 264 { 265 destroy_workqueue(dev_priv->hotplug.dp_wq); 266 destroy_workqueue(dev_priv->wq); 267 } 268 269 /* 270 * We don't keep the workarounds for pre-production hardware, so we expect our 271 * driver to fail on these machines in one way or another. A little warning on 272 * dmesg may help both the user and the bug triagers. 273 * 274 * Our policy for removing pre-production workarounds is to keep the 275 * current gen workarounds as a guide to the bring-up of the next gen 276 * (workarounds have a habit of persisting!). Anything older than that 277 * should be removed along with the complications they introduce. 278 */ 279 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 280 { 281 bool pre = false; 282 283 pre |= IS_HSW_EARLY_SDV(dev_priv); 284 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 285 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 286 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 287 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 288 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 289 290 if (pre) { 291 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 292 "It may not be fully functional.\n"); 293 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 294 } 295 } 296 297 static void sanitize_gpu(struct drm_i915_private *i915) 298 { 299 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 300 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 301 } 302 303 /** 304 * i915_driver_early_probe - setup state not requiring device access 305 * @dev_priv: device private 306 * 307 * Initialize everything that is a "SW-only" state, that is state not 308 * requiring accessing the device or exposing the driver via kernel internal 309 * or userspace interfaces. Example steps belonging here: lock initialization, 310 * system memory allocation, setting up device specific attributes and 311 * function hooks not requiring accessing the device. 312 */ 313 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 314 { 315 int ret = 0; 316 317 if (i915_inject_probe_failure(dev_priv)) 318 return -ENODEV; 319 320 intel_device_info_subplatform_init(dev_priv); 321 intel_step_init(dev_priv); 322 323 intel_gt_init_early(to_gt(dev_priv), dev_priv); 324 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 325 intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv)); 326 327 spin_lock_init(&dev_priv->irq_lock); 328 spin_lock_init(&dev_priv->gpu_error.lock); 329 mutex_init(&dev_priv->backlight_lock); 330 331 mutex_init(&dev_priv->sb_lock); 332 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 333 334 mutex_init(&dev_priv->audio.mutex); 335 mutex_init(&dev_priv->wm.wm_mutex); 336 mutex_init(&dev_priv->pps_mutex); 337 mutex_init(&dev_priv->hdcp_comp_mutex); 338 339 i915_memcpy_init_early(dev_priv); 340 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 341 342 ret = i915_workqueues_init(dev_priv); 343 if (ret < 0) 344 return ret; 345 346 ret = vlv_suspend_init(dev_priv); 347 if (ret < 0) 348 goto err_workqueues; 349 350 ret = intel_region_ttm_device_init(dev_priv); 351 if (ret) 352 goto err_ttm; 353 354 intel_wopcm_init_early(&dev_priv->wopcm); 355 356 __intel_gt_init_early(to_gt(dev_priv), dev_priv); 357 358 i915_gem_init_early(dev_priv); 359 360 /* This must be called before any calls to HAS_PCH_* */ 361 intel_detect_pch(dev_priv); 362 363 intel_pm_setup(dev_priv); 364 ret = intel_power_domains_init(dev_priv); 365 if (ret < 0) 366 goto err_gem; 367 intel_irq_init(dev_priv); 368 intel_init_display_hooks(dev_priv); 369 intel_init_clock_gating_hooks(dev_priv); 370 371 intel_detect_preproduction_hw(dev_priv); 372 373 return 0; 374 375 err_gem: 376 i915_gem_cleanup_early(dev_priv); 377 intel_gt_driver_late_release(to_gt(dev_priv)); 378 intel_region_ttm_device_fini(dev_priv); 379 err_ttm: 380 vlv_suspend_cleanup(dev_priv); 381 err_workqueues: 382 i915_workqueues_cleanup(dev_priv); 383 return ret; 384 } 385 386 /** 387 * i915_driver_late_release - cleanup the setup done in 388 * i915_driver_early_probe() 389 * @dev_priv: device private 390 */ 391 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 392 { 393 intel_irq_fini(dev_priv); 394 intel_power_domains_cleanup(dev_priv); 395 i915_gem_cleanup_early(dev_priv); 396 intel_gt_driver_late_release(to_gt(dev_priv)); 397 intel_region_ttm_device_fini(dev_priv); 398 vlv_suspend_cleanup(dev_priv); 399 i915_workqueues_cleanup(dev_priv); 400 401 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 402 mutex_destroy(&dev_priv->sb_lock); 403 404 i915_params_free(&dev_priv->params); 405 } 406 407 /** 408 * i915_driver_mmio_probe - setup device MMIO 409 * @dev_priv: device private 410 * 411 * Setup minimal device state necessary for MMIO accesses later in the 412 * initialization sequence. The setup here should avoid any other device-wide 413 * side effects or exposing the driver via kernel internal or user space 414 * interfaces. 415 */ 416 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 417 { 418 int ret; 419 420 if (i915_inject_probe_failure(dev_priv)) 421 return -ENODEV; 422 423 ret = i915_get_bridge_dev(dev_priv); 424 if (ret < 0) 425 return ret; 426 427 ret = intel_uncore_setup_mmio(&dev_priv->uncore); 428 if (ret < 0) 429 goto err_bridge; 430 431 ret = intel_uncore_init_mmio(&dev_priv->uncore); 432 if (ret) 433 goto err_mmio; 434 435 /* Try to make sure MCHBAR is enabled before poking at it */ 436 intel_setup_mchbar(dev_priv); 437 intel_device_info_runtime_init(dev_priv); 438 439 ret = intel_gt_init_mmio(to_gt(dev_priv)); 440 if (ret) 441 goto err_uncore; 442 443 /* As early as possible, scrub existing GPU state before clobbering */ 444 sanitize_gpu(dev_priv); 445 446 return 0; 447 448 err_uncore: 449 intel_teardown_mchbar(dev_priv); 450 intel_uncore_fini_mmio(&dev_priv->uncore); 451 err_mmio: 452 intel_uncore_cleanup_mmio(&dev_priv->uncore); 453 err_bridge: 454 pci_dev_put(dev_priv->bridge_dev); 455 456 return ret; 457 } 458 459 /** 460 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 461 * @dev_priv: device private 462 */ 463 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 464 { 465 intel_teardown_mchbar(dev_priv); 466 intel_uncore_fini_mmio(&dev_priv->uncore); 467 intel_uncore_cleanup_mmio(&dev_priv->uncore); 468 pci_dev_put(dev_priv->bridge_dev); 469 } 470 471 /** 472 * i915_set_dma_info - set all relevant PCI dma info as configured for the 473 * platform 474 * @i915: valid i915 instance 475 * 476 * Set the dma max segment size, device and coherent masks. The dma mask set 477 * needs to occur before i915_ggtt_probe_hw. 478 * 479 * A couple of platforms have special needs. Address them as well. 480 * 481 */ 482 static int i915_set_dma_info(struct drm_i915_private *i915) 483 { 484 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 485 int ret; 486 487 GEM_BUG_ON(!mask_size); 488 489 /* 490 * We don't have a max segment size, so set it to the max so sg's 491 * debugging layer doesn't complain 492 */ 493 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 494 495 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 496 if (ret) 497 goto mask_err; 498 499 /* overlay on gen2 is broken and can't address above 1G */ 500 if (GRAPHICS_VER(i915) == 2) 501 mask_size = 30; 502 503 /* 504 * 965GM sometimes incorrectly writes to hardware status page (HWS) 505 * using 32bit addressing, overwriting memory if HWS is located 506 * above 4GB. 507 * 508 * The documentation also mentions an issue with undefined 509 * behaviour if any general state is accessed within a page above 4GB, 510 * which also needs to be handled carefully. 511 */ 512 if (IS_I965G(i915) || IS_I965GM(i915)) 513 mask_size = 32; 514 515 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 516 if (ret) 517 goto mask_err; 518 519 return 0; 520 521 mask_err: 522 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 523 return ret; 524 } 525 526 /** 527 * i915_driver_hw_probe - setup state requiring device access 528 * @dev_priv: device private 529 * 530 * Setup state that requires accessing the device, but doesn't require 531 * exposing the driver via kernel internal or userspace interfaces. 532 */ 533 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 534 { 535 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 536 int ret; 537 538 if (i915_inject_probe_failure(dev_priv)) 539 return -ENODEV; 540 541 if (HAS_PPGTT(dev_priv)) { 542 if (intel_vgpu_active(dev_priv) && 543 !intel_vgpu_has_full_ppgtt(dev_priv)) { 544 i915_report_error(dev_priv, 545 "incompatible vGPU found, support for isolated ppGTT required\n"); 546 return -ENXIO; 547 } 548 } 549 550 if (HAS_EXECLISTS(dev_priv)) { 551 /* 552 * Older GVT emulation depends upon intercepting CSB mmio, 553 * which we no longer use, preferring to use the HWSP cache 554 * instead. 555 */ 556 if (intel_vgpu_active(dev_priv) && 557 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 558 i915_report_error(dev_priv, 559 "old vGPU host found, support for HWSP emulation required\n"); 560 return -ENXIO; 561 } 562 } 563 564 /* needs to be done before ggtt probe */ 565 intel_dram_edram_detect(dev_priv); 566 567 ret = i915_set_dma_info(dev_priv); 568 if (ret) 569 return ret; 570 571 i915_perf_init(dev_priv); 572 573 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 574 if (ret) 575 goto err_perf; 576 577 ret = i915_ggtt_probe_hw(dev_priv); 578 if (ret) 579 goto err_perf; 580 581 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 582 if (ret) 583 goto err_ggtt; 584 585 ret = i915_ggtt_init_hw(dev_priv); 586 if (ret) 587 goto err_ggtt; 588 589 ret = intel_memory_regions_hw_probe(dev_priv); 590 if (ret) 591 goto err_ggtt; 592 593 ret = intel_gt_probe_lmem(to_gt(dev_priv)); 594 if (ret) 595 goto err_mem_regions; 596 597 ret = i915_ggtt_enable_hw(dev_priv); 598 if (ret) { 599 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 600 goto err_mem_regions; 601 } 602 603 pci_set_master(pdev); 604 605 /* On the 945G/GM, the chipset reports the MSI capability on the 606 * integrated graphics even though the support isn't actually there 607 * according to the published specs. It doesn't appear to function 608 * correctly in testing on 945G. 609 * This may be a side effect of MSI having been made available for PEG 610 * and the registers being closely associated. 611 * 612 * According to chipset errata, on the 965GM, MSI interrupts may 613 * be lost or delayed, and was defeatured. MSI interrupts seem to 614 * get lost on g4x as well, and interrupt delivery seems to stay 615 * properly dead afterwards. So we'll just disable them for all 616 * pre-gen5 chipsets. 617 * 618 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 619 * interrupts even when in MSI mode. This results in spurious 620 * interrupt warnings if the legacy irq no. is shared with another 621 * device. The kernel then disables that interrupt source and so 622 * prevents the other device from working properly. 623 */ 624 if (GRAPHICS_VER(dev_priv) >= 5) { 625 if (pci_enable_msi(pdev) < 0) 626 drm_dbg(&dev_priv->drm, "can't enable MSI"); 627 } 628 629 ret = intel_gvt_init(dev_priv); 630 if (ret) 631 goto err_msi; 632 633 intel_opregion_setup(dev_priv); 634 635 ret = intel_pcode_init(dev_priv); 636 if (ret) 637 goto err_msi; 638 639 /* 640 * Fill the dram structure to get the system dram info. This will be 641 * used for memory latency calculation. 642 */ 643 intel_dram_detect(dev_priv); 644 645 intel_bw_init_hw(dev_priv); 646 647 return 0; 648 649 err_msi: 650 if (pdev->msi_enabled) 651 pci_disable_msi(pdev); 652 err_mem_regions: 653 intel_memory_regions_driver_release(dev_priv); 654 err_ggtt: 655 i915_ggtt_driver_release(dev_priv); 656 i915_gem_drain_freed_objects(dev_priv); 657 i915_ggtt_driver_late_release(dev_priv); 658 err_perf: 659 i915_perf_fini(dev_priv); 660 return ret; 661 } 662 663 /** 664 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 665 * @dev_priv: device private 666 */ 667 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 668 { 669 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 670 671 i915_perf_fini(dev_priv); 672 673 if (pdev->msi_enabled) 674 pci_disable_msi(pdev); 675 } 676 677 /** 678 * i915_driver_register - register the driver with the rest of the system 679 * @dev_priv: device private 680 * 681 * Perform any steps necessary to make the driver available via kernel 682 * internal or userspace interfaces. 683 */ 684 static void i915_driver_register(struct drm_i915_private *dev_priv) 685 { 686 struct drm_device *dev = &dev_priv->drm; 687 688 i915_gem_driver_register(dev_priv); 689 i915_pmu_register(dev_priv); 690 691 intel_vgpu_register(dev_priv); 692 693 /* Reveal our presence to userspace */ 694 if (drm_dev_register(dev, 0)) { 695 drm_err(&dev_priv->drm, 696 "Failed to register driver for userspace access!\n"); 697 return; 698 } 699 700 i915_debugfs_register(dev_priv); 701 i915_setup_sysfs(dev_priv); 702 703 /* Depends on sysfs having been initialized */ 704 i915_perf_register(dev_priv); 705 706 intel_gt_driver_register(to_gt(dev_priv)); 707 708 intel_display_driver_register(dev_priv); 709 710 intel_power_domains_enable(dev_priv); 711 intel_runtime_pm_enable(&dev_priv->runtime_pm); 712 713 intel_register_dsm_handler(); 714 715 if (i915_switcheroo_register(dev_priv)) 716 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 717 } 718 719 /** 720 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 721 * @dev_priv: device private 722 */ 723 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 724 { 725 i915_switcheroo_unregister(dev_priv); 726 727 intel_unregister_dsm_handler(); 728 729 intel_runtime_pm_disable(&dev_priv->runtime_pm); 730 intel_power_domains_disable(dev_priv); 731 732 intel_display_driver_unregister(dev_priv); 733 734 intel_gt_driver_unregister(to_gt(dev_priv)); 735 736 i915_perf_unregister(dev_priv); 737 i915_pmu_unregister(dev_priv); 738 739 i915_teardown_sysfs(dev_priv); 740 drm_dev_unplug(&dev_priv->drm); 741 742 i915_gem_driver_unregister(dev_priv); 743 } 744 745 void 746 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 747 { 748 drm_printf(p, "iommu: %s\n", enableddisabled(intel_vtd_active(i915))); 749 } 750 751 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 752 { 753 if (drm_debug_enabled(DRM_UT_DRIVER)) { 754 struct drm_printer p = drm_debug_printer("i915 device info:"); 755 756 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 757 INTEL_DEVID(dev_priv), 758 INTEL_REVID(dev_priv), 759 intel_platform_name(INTEL_INFO(dev_priv)->platform), 760 intel_subplatform(RUNTIME_INFO(dev_priv), 761 INTEL_INFO(dev_priv)->platform), 762 GRAPHICS_VER(dev_priv)); 763 764 intel_device_info_print_static(INTEL_INFO(dev_priv), &p); 765 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); 766 i915_print_iommu_status(dev_priv, &p); 767 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 768 } 769 770 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 771 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 772 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 773 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 774 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 775 drm_info(&dev_priv->drm, 776 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 777 } 778 779 static struct drm_i915_private * 780 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 781 { 782 const struct intel_device_info *match_info = 783 (struct intel_device_info *)ent->driver_data; 784 struct intel_device_info *device_info; 785 struct drm_i915_private *i915; 786 787 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 788 struct drm_i915_private, drm); 789 if (IS_ERR(i915)) 790 return i915; 791 792 pci_set_drvdata(pdev, i915); 793 794 /* Device parameters start as a copy of module parameters. */ 795 i915_params_copy(&i915->params, &i915_modparams); 796 797 /* Setup the write-once "constant" device info */ 798 device_info = mkwrite_device_info(i915); 799 memcpy(device_info, match_info, sizeof(*device_info)); 800 RUNTIME_INFO(i915)->device_id = pdev->device; 801 802 return i915; 803 } 804 805 /** 806 * i915_driver_probe - setup chip and create an initial config 807 * @pdev: PCI device 808 * @ent: matching PCI ID entry 809 * 810 * The driver probe routine has to do several things: 811 * - drive output discovery via intel_modeset_init() 812 * - initialize the memory manager 813 * - allocate initial config memory 814 * - setup the DRM framebuffer with the allocated memory 815 */ 816 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 817 { 818 const struct intel_device_info *match_info = 819 (struct intel_device_info *)ent->driver_data; 820 struct drm_i915_private *i915; 821 int ret; 822 823 i915 = i915_driver_create(pdev, ent); 824 if (IS_ERR(i915)) 825 return PTR_ERR(i915); 826 827 /* Disable nuclear pageflip by default on pre-ILK */ 828 if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5) 829 i915->drm.driver_features &= ~DRIVER_ATOMIC; 830 831 ret = pci_enable_device(pdev); 832 if (ret) 833 goto out_fini; 834 835 ret = i915_driver_early_probe(i915); 836 if (ret < 0) 837 goto out_pci_disable; 838 839 disable_rpm_wakeref_asserts(&i915->runtime_pm); 840 841 intel_vgpu_detect(i915); 842 843 ret = i915_driver_mmio_probe(i915); 844 if (ret < 0) 845 goto out_runtime_pm_put; 846 847 ret = i915_driver_hw_probe(i915); 848 if (ret < 0) 849 goto out_cleanup_mmio; 850 851 ret = intel_modeset_init_noirq(i915); 852 if (ret < 0) 853 goto out_cleanup_hw; 854 855 ret = intel_irq_install(i915); 856 if (ret) 857 goto out_cleanup_modeset; 858 859 ret = intel_modeset_init_nogem(i915); 860 if (ret) 861 goto out_cleanup_irq; 862 863 ret = i915_gem_init(i915); 864 if (ret) 865 goto out_cleanup_modeset2; 866 867 ret = intel_modeset_init(i915); 868 if (ret) 869 goto out_cleanup_gem; 870 871 i915_driver_register(i915); 872 873 enable_rpm_wakeref_asserts(&i915->runtime_pm); 874 875 i915_welcome_messages(i915); 876 877 i915->do_release = true; 878 879 return 0; 880 881 out_cleanup_gem: 882 i915_gem_suspend(i915); 883 i915_gem_driver_remove(i915); 884 i915_gem_driver_release(i915); 885 out_cleanup_modeset2: 886 /* FIXME clean up the error path */ 887 intel_modeset_driver_remove(i915); 888 intel_irq_uninstall(i915); 889 intel_modeset_driver_remove_noirq(i915); 890 goto out_cleanup_modeset; 891 out_cleanup_irq: 892 intel_irq_uninstall(i915); 893 out_cleanup_modeset: 894 intel_modeset_driver_remove_nogem(i915); 895 out_cleanup_hw: 896 i915_driver_hw_remove(i915); 897 intel_memory_regions_driver_release(i915); 898 i915_ggtt_driver_release(i915); 899 i915_gem_drain_freed_objects(i915); 900 i915_ggtt_driver_late_release(i915); 901 out_cleanup_mmio: 902 i915_driver_mmio_release(i915); 903 out_runtime_pm_put: 904 enable_rpm_wakeref_asserts(&i915->runtime_pm); 905 i915_driver_late_release(i915); 906 out_pci_disable: 907 pci_disable_device(pdev); 908 out_fini: 909 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 910 return ret; 911 } 912 913 void i915_driver_remove(struct drm_i915_private *i915) 914 { 915 disable_rpm_wakeref_asserts(&i915->runtime_pm); 916 917 i915_driver_unregister(i915); 918 919 /* Flush any external code that still may be under the RCU lock */ 920 synchronize_rcu(); 921 922 i915_gem_suspend(i915); 923 924 intel_gvt_driver_remove(i915); 925 926 intel_modeset_driver_remove(i915); 927 928 intel_irq_uninstall(i915); 929 930 intel_modeset_driver_remove_noirq(i915); 931 932 i915_reset_error_state(i915); 933 i915_gem_driver_remove(i915); 934 935 intel_modeset_driver_remove_nogem(i915); 936 937 i915_driver_hw_remove(i915); 938 939 enable_rpm_wakeref_asserts(&i915->runtime_pm); 940 } 941 942 static void i915_driver_release(struct drm_device *dev) 943 { 944 struct drm_i915_private *dev_priv = to_i915(dev); 945 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 946 947 if (!dev_priv->do_release) 948 return; 949 950 disable_rpm_wakeref_asserts(rpm); 951 952 i915_gem_driver_release(dev_priv); 953 954 intel_memory_regions_driver_release(dev_priv); 955 i915_ggtt_driver_release(dev_priv); 956 i915_gem_drain_freed_objects(dev_priv); 957 i915_ggtt_driver_late_release(dev_priv); 958 959 i915_driver_mmio_release(dev_priv); 960 961 enable_rpm_wakeref_asserts(rpm); 962 intel_runtime_pm_driver_release(rpm); 963 964 i915_driver_late_release(dev_priv); 965 } 966 967 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 968 { 969 struct drm_i915_private *i915 = to_i915(dev); 970 int ret; 971 972 ret = i915_gem_open(i915, file); 973 if (ret) 974 return ret; 975 976 return 0; 977 } 978 979 /** 980 * i915_driver_lastclose - clean up after all DRM clients have exited 981 * @dev: DRM device 982 * 983 * Take care of cleaning up after all DRM clients have exited. In the 984 * mode setting case, we want to restore the kernel's initial mode (just 985 * in case the last client left us in a bad state). 986 * 987 * Additionally, in the non-mode setting case, we'll tear down the GTT 988 * and DMA structures, since the kernel won't be using them, and clea 989 * up any GEM state. 990 */ 991 static void i915_driver_lastclose(struct drm_device *dev) 992 { 993 struct drm_i915_private *i915 = to_i915(dev); 994 995 intel_fbdev_restore_mode(dev); 996 997 if (HAS_DISPLAY(i915)) 998 vga_switcheroo_process_delayed_switch(); 999 } 1000 1001 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1002 { 1003 struct drm_i915_file_private *file_priv = file->driver_priv; 1004 1005 i915_gem_context_close(file); 1006 1007 kfree_rcu(file_priv, rcu); 1008 1009 /* Catch up with all the deferred frees from "this" client */ 1010 i915_gem_flush_free_objects(to_i915(dev)); 1011 } 1012 1013 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1014 { 1015 struct drm_device *dev = &dev_priv->drm; 1016 struct intel_encoder *encoder; 1017 1018 if (!HAS_DISPLAY(dev_priv)) 1019 return; 1020 1021 drm_modeset_lock_all(dev); 1022 for_each_intel_encoder(dev, encoder) 1023 if (encoder->suspend) 1024 encoder->suspend(encoder); 1025 drm_modeset_unlock_all(dev); 1026 } 1027 1028 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1029 { 1030 struct drm_device *dev = &dev_priv->drm; 1031 struct intel_encoder *encoder; 1032 1033 if (!HAS_DISPLAY(dev_priv)) 1034 return; 1035 1036 drm_modeset_lock_all(dev); 1037 for_each_intel_encoder(dev, encoder) 1038 if (encoder->shutdown) 1039 encoder->shutdown(encoder); 1040 drm_modeset_unlock_all(dev); 1041 } 1042 1043 void i915_driver_shutdown(struct drm_i915_private *i915) 1044 { 1045 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1046 intel_runtime_pm_disable(&i915->runtime_pm); 1047 intel_power_domains_disable(i915); 1048 1049 i915_gem_suspend(i915); 1050 1051 if (HAS_DISPLAY(i915)) { 1052 drm_kms_helper_poll_disable(&i915->drm); 1053 1054 drm_atomic_helper_shutdown(&i915->drm); 1055 } 1056 1057 intel_dp_mst_suspend(i915); 1058 1059 intel_runtime_pm_disable_interrupts(i915); 1060 intel_hpd_cancel_work(i915); 1061 1062 intel_suspend_encoders(i915); 1063 intel_shutdown_encoders(i915); 1064 1065 intel_dmc_ucode_suspend(i915); 1066 1067 /* 1068 * The only requirement is to reboot with display DC states disabled, 1069 * for now leaving all display power wells in the INIT power domain 1070 * enabled. 1071 * 1072 * TODO: 1073 * - unify the pci_driver::shutdown sequence here with the 1074 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1075 * - unify the driver remove and system/runtime suspend sequences with 1076 * the above unified shutdown/poweroff sequence. 1077 */ 1078 intel_power_domains_driver_remove(i915); 1079 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1080 1081 intel_runtime_pm_driver_release(&i915->runtime_pm); 1082 } 1083 1084 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1085 { 1086 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1087 if (acpi_target_system_state() < ACPI_STATE_S3) 1088 return true; 1089 #endif 1090 return false; 1091 } 1092 1093 static int i915_drm_prepare(struct drm_device *dev) 1094 { 1095 struct drm_i915_private *i915 = to_i915(dev); 1096 1097 /* 1098 * NB intel_display_suspend() may issue new requests after we've 1099 * ostensibly marked the GPU as ready-to-sleep here. We need to 1100 * split out that work and pull it forward so that after point, 1101 * the GPU is not woken again. 1102 */ 1103 return i915_gem_backup_suspend(i915); 1104 } 1105 1106 static int i915_drm_suspend(struct drm_device *dev) 1107 { 1108 struct drm_i915_private *dev_priv = to_i915(dev); 1109 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1110 pci_power_t opregion_target_state; 1111 1112 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1113 1114 /* We do a lot of poking in a lot of registers, make sure they work 1115 * properly. */ 1116 intel_power_domains_disable(dev_priv); 1117 if (HAS_DISPLAY(dev_priv)) 1118 drm_kms_helper_poll_disable(dev); 1119 1120 pci_save_state(pdev); 1121 1122 intel_display_suspend(dev); 1123 1124 intel_dp_mst_suspend(dev_priv); 1125 1126 intel_runtime_pm_disable_interrupts(dev_priv); 1127 intel_hpd_cancel_work(dev_priv); 1128 1129 intel_suspend_encoders(dev_priv); 1130 1131 intel_suspend_hw(dev_priv); 1132 1133 /* Must be called before GGTT is suspended. */ 1134 intel_dpt_suspend(dev_priv); 1135 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1136 1137 i915_save_display(dev_priv); 1138 1139 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1140 intel_opregion_suspend(dev_priv, opregion_target_state); 1141 1142 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1143 1144 dev_priv->suspend_count++; 1145 1146 intel_dmc_ucode_suspend(dev_priv); 1147 1148 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1149 1150 return 0; 1151 } 1152 1153 static enum i915_drm_suspend_mode 1154 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1155 { 1156 if (hibernate) 1157 return I915_DRM_SUSPEND_HIBERNATE; 1158 1159 if (suspend_to_idle(dev_priv)) 1160 return I915_DRM_SUSPEND_IDLE; 1161 1162 return I915_DRM_SUSPEND_MEM; 1163 } 1164 1165 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1166 { 1167 struct drm_i915_private *dev_priv = to_i915(dev); 1168 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1169 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1170 int ret; 1171 1172 disable_rpm_wakeref_asserts(rpm); 1173 1174 i915_gem_suspend_late(dev_priv); 1175 1176 intel_uncore_suspend(&dev_priv->uncore); 1177 1178 intel_power_domains_suspend(dev_priv, 1179 get_suspend_mode(dev_priv, hibernation)); 1180 1181 intel_display_power_suspend_late(dev_priv); 1182 1183 ret = vlv_suspend_complete(dev_priv); 1184 if (ret) { 1185 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1186 intel_power_domains_resume(dev_priv); 1187 1188 goto out; 1189 } 1190 1191 /* 1192 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1193 * This should be totally removed when we handle the pci states properly 1194 * on runtime PM and on s2idle cases. 1195 */ 1196 if (suspend_to_idle(dev_priv)) 1197 pci_d3cold_disable(pdev); 1198 1199 pci_disable_device(pdev); 1200 /* 1201 * During hibernation on some platforms the BIOS may try to access 1202 * the device even though it's already in D3 and hang the machine. So 1203 * leave the device in D0 on those platforms and hope the BIOS will 1204 * power down the device properly. The issue was seen on multiple old 1205 * GENs with different BIOS vendors, so having an explicit blacklist 1206 * is inpractical; apply the workaround on everything pre GEN6. The 1207 * platforms where the issue was seen: 1208 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1209 * Fujitsu FSC S7110 1210 * Acer Aspire 1830T 1211 */ 1212 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1213 pci_set_power_state(pdev, PCI_D3hot); 1214 1215 out: 1216 enable_rpm_wakeref_asserts(rpm); 1217 if (!dev_priv->uncore.user_forcewake_count) 1218 intel_runtime_pm_driver_release(rpm); 1219 1220 return ret; 1221 } 1222 1223 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1224 pm_message_t state) 1225 { 1226 int error; 1227 1228 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1229 state.event != PM_EVENT_FREEZE)) 1230 return -EINVAL; 1231 1232 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1233 return 0; 1234 1235 error = i915_drm_suspend(&i915->drm); 1236 if (error) 1237 return error; 1238 1239 return i915_drm_suspend_late(&i915->drm, false); 1240 } 1241 1242 static int i915_drm_resume(struct drm_device *dev) 1243 { 1244 struct drm_i915_private *dev_priv = to_i915(dev); 1245 int ret; 1246 1247 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1248 1249 ret = intel_pcode_init(dev_priv); 1250 if (ret) 1251 return ret; 1252 1253 sanitize_gpu(dev_priv); 1254 1255 ret = i915_ggtt_enable_hw(dev_priv); 1256 if (ret) 1257 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1258 1259 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1260 /* Must be called after GGTT is resumed. */ 1261 intel_dpt_resume(dev_priv); 1262 1263 intel_dmc_ucode_resume(dev_priv); 1264 1265 i915_restore_display(dev_priv); 1266 intel_pps_unlock_regs_wa(dev_priv); 1267 1268 intel_init_pch_refclk(dev_priv); 1269 1270 /* 1271 * Interrupts have to be enabled before any batches are run. If not the 1272 * GPU will hang. i915_gem_init_hw() will initiate batches to 1273 * update/restore the context. 1274 * 1275 * drm_mode_config_reset() needs AUX interrupts. 1276 * 1277 * Modeset enabling in intel_modeset_init_hw() also needs working 1278 * interrupts. 1279 */ 1280 intel_runtime_pm_enable_interrupts(dev_priv); 1281 1282 if (HAS_DISPLAY(dev_priv)) 1283 drm_mode_config_reset(dev); 1284 1285 i915_gem_resume(dev_priv); 1286 1287 intel_modeset_init_hw(dev_priv); 1288 intel_init_clock_gating(dev_priv); 1289 intel_hpd_init(dev_priv); 1290 1291 /* MST sideband requires HPD interrupts enabled */ 1292 intel_dp_mst_resume(dev_priv); 1293 intel_display_resume(dev); 1294 1295 intel_hpd_poll_disable(dev_priv); 1296 if (HAS_DISPLAY(dev_priv)) 1297 drm_kms_helper_poll_enable(dev); 1298 1299 intel_opregion_resume(dev_priv); 1300 1301 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1302 1303 intel_power_domains_enable(dev_priv); 1304 1305 intel_gvt_resume(dev_priv); 1306 1307 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1308 1309 return 0; 1310 } 1311 1312 static int i915_drm_resume_early(struct drm_device *dev) 1313 { 1314 struct drm_i915_private *dev_priv = to_i915(dev); 1315 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1316 int ret; 1317 1318 /* 1319 * We have a resume ordering issue with the snd-hda driver also 1320 * requiring our device to be power up. Due to the lack of a 1321 * parent/child relationship we currently solve this with an early 1322 * resume hook. 1323 * 1324 * FIXME: This should be solved with a special hdmi sink device or 1325 * similar so that power domains can be employed. 1326 */ 1327 1328 /* 1329 * Note that we need to set the power state explicitly, since we 1330 * powered off the device during freeze and the PCI core won't power 1331 * it back up for us during thaw. Powering off the device during 1332 * freeze is not a hard requirement though, and during the 1333 * suspend/resume phases the PCI core makes sure we get here with the 1334 * device powered on. So in case we change our freeze logic and keep 1335 * the device powered we can also remove the following set power state 1336 * call. 1337 */ 1338 ret = pci_set_power_state(pdev, PCI_D0); 1339 if (ret) { 1340 drm_err(&dev_priv->drm, 1341 "failed to set PCI D0 power state (%d)\n", ret); 1342 return ret; 1343 } 1344 1345 /* 1346 * Note that pci_enable_device() first enables any parent bridge 1347 * device and only then sets the power state for this device. The 1348 * bridge enabling is a nop though, since bridge devices are resumed 1349 * first. The order of enabling power and enabling the device is 1350 * imposed by the PCI core as described above, so here we preserve the 1351 * same order for the freeze/thaw phases. 1352 * 1353 * TODO: eventually we should remove pci_disable_device() / 1354 * pci_enable_enable_device() from suspend/resume. Due to how they 1355 * depend on the device enable refcount we can't anyway depend on them 1356 * disabling/enabling the device. 1357 */ 1358 if (pci_enable_device(pdev)) 1359 return -EIO; 1360 1361 pci_set_master(pdev); 1362 1363 pci_d3cold_enable(pdev); 1364 1365 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1366 1367 ret = vlv_resume_prepare(dev_priv, false); 1368 if (ret) 1369 drm_err(&dev_priv->drm, 1370 "Resume prepare failed: %d, continuing anyway\n", ret); 1371 1372 intel_uncore_resume_early(&dev_priv->uncore); 1373 1374 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1375 1376 intel_display_power_resume_early(dev_priv); 1377 1378 intel_power_domains_resume(dev_priv); 1379 1380 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1381 1382 return ret; 1383 } 1384 1385 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1386 { 1387 int ret; 1388 1389 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1390 return 0; 1391 1392 ret = i915_drm_resume_early(&i915->drm); 1393 if (ret) 1394 return ret; 1395 1396 return i915_drm_resume(&i915->drm); 1397 } 1398 1399 static int i915_pm_prepare(struct device *kdev) 1400 { 1401 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1402 1403 if (!i915) { 1404 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1405 return -ENODEV; 1406 } 1407 1408 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1409 return 0; 1410 1411 return i915_drm_prepare(&i915->drm); 1412 } 1413 1414 static int i915_pm_suspend(struct device *kdev) 1415 { 1416 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1417 1418 if (!i915) { 1419 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1420 return -ENODEV; 1421 } 1422 1423 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1424 return 0; 1425 1426 return i915_drm_suspend(&i915->drm); 1427 } 1428 1429 static int i915_pm_suspend_late(struct device *kdev) 1430 { 1431 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1432 1433 /* 1434 * We have a suspend ordering issue with the snd-hda driver also 1435 * requiring our device to be power up. Due to the lack of a 1436 * parent/child relationship we currently solve this with an late 1437 * suspend hook. 1438 * 1439 * FIXME: This should be solved with a special hdmi sink device or 1440 * similar so that power domains can be employed. 1441 */ 1442 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1443 return 0; 1444 1445 return i915_drm_suspend_late(&i915->drm, false); 1446 } 1447 1448 static int i915_pm_poweroff_late(struct device *kdev) 1449 { 1450 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1451 1452 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1453 return 0; 1454 1455 return i915_drm_suspend_late(&i915->drm, true); 1456 } 1457 1458 static int i915_pm_resume_early(struct device *kdev) 1459 { 1460 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1461 1462 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1463 return 0; 1464 1465 return i915_drm_resume_early(&i915->drm); 1466 } 1467 1468 static int i915_pm_resume(struct device *kdev) 1469 { 1470 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1471 1472 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1473 return 0; 1474 1475 return i915_drm_resume(&i915->drm); 1476 } 1477 1478 /* freeze: before creating the hibernation_image */ 1479 static int i915_pm_freeze(struct device *kdev) 1480 { 1481 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1482 int ret; 1483 1484 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1485 ret = i915_drm_suspend(&i915->drm); 1486 if (ret) 1487 return ret; 1488 } 1489 1490 ret = i915_gem_freeze(i915); 1491 if (ret) 1492 return ret; 1493 1494 return 0; 1495 } 1496 1497 static int i915_pm_freeze_late(struct device *kdev) 1498 { 1499 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1500 int ret; 1501 1502 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1503 ret = i915_drm_suspend_late(&i915->drm, true); 1504 if (ret) 1505 return ret; 1506 } 1507 1508 ret = i915_gem_freeze_late(i915); 1509 if (ret) 1510 return ret; 1511 1512 return 0; 1513 } 1514 1515 /* thaw: called after creating the hibernation image, but before turning off. */ 1516 static int i915_pm_thaw_early(struct device *kdev) 1517 { 1518 return i915_pm_resume_early(kdev); 1519 } 1520 1521 static int i915_pm_thaw(struct device *kdev) 1522 { 1523 return i915_pm_resume(kdev); 1524 } 1525 1526 /* restore: called after loading the hibernation image. */ 1527 static int i915_pm_restore_early(struct device *kdev) 1528 { 1529 return i915_pm_resume_early(kdev); 1530 } 1531 1532 static int i915_pm_restore(struct device *kdev) 1533 { 1534 return i915_pm_resume(kdev); 1535 } 1536 1537 static int intel_runtime_suspend(struct device *kdev) 1538 { 1539 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1540 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1541 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1542 int ret; 1543 1544 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1545 return -ENODEV; 1546 1547 drm_dbg_kms(&dev_priv->drm, "Suspending device\n"); 1548 1549 disable_rpm_wakeref_asserts(rpm); 1550 1551 /* 1552 * We are safe here against re-faults, since the fault handler takes 1553 * an RPM reference. 1554 */ 1555 i915_gem_runtime_suspend(dev_priv); 1556 1557 intel_gt_runtime_suspend(to_gt(dev_priv)); 1558 1559 intel_runtime_pm_disable_interrupts(dev_priv); 1560 1561 intel_uncore_suspend(&dev_priv->uncore); 1562 1563 intel_display_power_suspend(dev_priv); 1564 1565 ret = vlv_suspend_complete(dev_priv); 1566 if (ret) { 1567 drm_err(&dev_priv->drm, 1568 "Runtime suspend failed, disabling it (%d)\n", ret); 1569 intel_uncore_runtime_resume(&dev_priv->uncore); 1570 1571 intel_runtime_pm_enable_interrupts(dev_priv); 1572 1573 intel_gt_runtime_resume(to_gt(dev_priv)); 1574 1575 enable_rpm_wakeref_asserts(rpm); 1576 1577 return ret; 1578 } 1579 1580 enable_rpm_wakeref_asserts(rpm); 1581 intel_runtime_pm_driver_release(rpm); 1582 1583 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1584 drm_err(&dev_priv->drm, 1585 "Unclaimed access detected prior to suspending\n"); 1586 1587 /* 1588 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1589 * This should be totally removed when we handle the pci states properly 1590 * on runtime PM and on s2idle cases. 1591 */ 1592 pci_d3cold_disable(pdev); 1593 rpm->suspended = true; 1594 1595 /* 1596 * FIXME: We really should find a document that references the arguments 1597 * used below! 1598 */ 1599 if (IS_BROADWELL(dev_priv)) { 1600 /* 1601 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1602 * being detected, and the call we do at intel_runtime_resume() 1603 * won't be able to restore them. Since PCI_D3hot matches the 1604 * actual specification and appears to be working, use it. 1605 */ 1606 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1607 } else { 1608 /* 1609 * current versions of firmware which depend on this opregion 1610 * notification have repurposed the D1 definition to mean 1611 * "runtime suspended" vs. what you would normally expect (D3) 1612 * to distinguish it from notifications that might be sent via 1613 * the suspend path. 1614 */ 1615 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1616 } 1617 1618 assert_forcewakes_inactive(&dev_priv->uncore); 1619 1620 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1621 intel_hpd_poll_enable(dev_priv); 1622 1623 drm_dbg_kms(&dev_priv->drm, "Device suspended\n"); 1624 return 0; 1625 } 1626 1627 static int intel_runtime_resume(struct device *kdev) 1628 { 1629 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1630 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1631 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1632 int ret; 1633 1634 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1635 return -ENODEV; 1636 1637 drm_dbg_kms(&dev_priv->drm, "Resuming device\n"); 1638 1639 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1640 disable_rpm_wakeref_asserts(rpm); 1641 1642 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1643 rpm->suspended = false; 1644 pci_d3cold_enable(pdev); 1645 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1646 drm_dbg(&dev_priv->drm, 1647 "Unclaimed access during suspend, bios?\n"); 1648 1649 intel_display_power_resume(dev_priv); 1650 1651 ret = vlv_resume_prepare(dev_priv, true); 1652 1653 intel_uncore_runtime_resume(&dev_priv->uncore); 1654 1655 intel_runtime_pm_enable_interrupts(dev_priv); 1656 1657 /* 1658 * No point of rolling back things in case of an error, as the best 1659 * we can do is to hope that things will still work (and disable RPM). 1660 */ 1661 intel_gt_runtime_resume(to_gt(dev_priv)); 1662 1663 /* 1664 * On VLV/CHV display interrupts are part of the display 1665 * power well, so hpd is reinitialized from there. For 1666 * everyone else do it here. 1667 */ 1668 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1669 intel_hpd_init(dev_priv); 1670 intel_hpd_poll_disable(dev_priv); 1671 } 1672 1673 intel_enable_ipc(dev_priv); 1674 1675 enable_rpm_wakeref_asserts(rpm); 1676 1677 if (ret) 1678 drm_err(&dev_priv->drm, 1679 "Runtime resume failed, disabling it (%d)\n", ret); 1680 else 1681 drm_dbg_kms(&dev_priv->drm, "Device resumed\n"); 1682 1683 return ret; 1684 } 1685 1686 const struct dev_pm_ops i915_pm_ops = { 1687 /* 1688 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1689 * PMSG_RESUME] 1690 */ 1691 .prepare = i915_pm_prepare, 1692 .suspend = i915_pm_suspend, 1693 .suspend_late = i915_pm_suspend_late, 1694 .resume_early = i915_pm_resume_early, 1695 .resume = i915_pm_resume, 1696 1697 /* 1698 * S4 event handlers 1699 * @freeze, @freeze_late : called (1) before creating the 1700 * hibernation image [PMSG_FREEZE] and 1701 * (2) after rebooting, before restoring 1702 * the image [PMSG_QUIESCE] 1703 * @thaw, @thaw_early : called (1) after creating the hibernation 1704 * image, before writing it [PMSG_THAW] 1705 * and (2) after failing to create or 1706 * restore the image [PMSG_RECOVER] 1707 * @poweroff, @poweroff_late: called after writing the hibernation 1708 * image, before rebooting [PMSG_HIBERNATE] 1709 * @restore, @restore_early : called after rebooting and restoring the 1710 * hibernation image [PMSG_RESTORE] 1711 */ 1712 .freeze = i915_pm_freeze, 1713 .freeze_late = i915_pm_freeze_late, 1714 .thaw_early = i915_pm_thaw_early, 1715 .thaw = i915_pm_thaw, 1716 .poweroff = i915_pm_suspend, 1717 .poweroff_late = i915_pm_poweroff_late, 1718 .restore_early = i915_pm_restore_early, 1719 .restore = i915_pm_restore, 1720 1721 /* S0ix (via runtime suspend) event handlers */ 1722 .runtime_suspend = intel_runtime_suspend, 1723 .runtime_resume = intel_runtime_resume, 1724 }; 1725 1726 static const struct file_operations i915_driver_fops = { 1727 .owner = THIS_MODULE, 1728 .open = drm_open, 1729 .release = drm_release_noglobal, 1730 .unlocked_ioctl = drm_ioctl, 1731 .mmap = i915_gem_mmap, 1732 .poll = drm_poll, 1733 .read = drm_read, 1734 .compat_ioctl = i915_ioc32_compat_ioctl, 1735 .llseek = noop_llseek, 1736 }; 1737 1738 static int 1739 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1740 struct drm_file *file) 1741 { 1742 return -ENODEV; 1743 } 1744 1745 static const struct drm_ioctl_desc i915_ioctls[] = { 1746 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1747 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1748 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1749 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1750 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1751 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1752 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1753 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1754 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1755 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1756 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1757 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1758 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1759 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1760 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1761 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1762 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1763 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1764 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1765 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1766 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1767 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1768 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1771 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1772 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1773 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1774 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1775 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1776 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1777 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1779 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1780 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1782 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1783 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1784 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1786 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1788 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1789 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1790 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1791 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1792 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1794 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1795 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1796 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1797 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1798 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1799 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1800 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1801 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1802 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1804 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1805 }; 1806 1807 /* 1808 * Interface history: 1809 * 1810 * 1.1: Original. 1811 * 1.2: Add Power Management 1812 * 1.3: Add vblank support 1813 * 1.4: Fix cmdbuffer path, add heap destroy 1814 * 1.5: Add vblank pipe configuration 1815 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1816 * - Support vertical blank on secondary display pipe 1817 */ 1818 #define DRIVER_MAJOR 1 1819 #define DRIVER_MINOR 6 1820 #define DRIVER_PATCHLEVEL 0 1821 1822 static const struct drm_driver i915_drm_driver = { 1823 /* Don't use MTRRs here; the Xserver or userspace app should 1824 * deal with them for Intel hardware. 1825 */ 1826 .driver_features = 1827 DRIVER_GEM | 1828 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1829 DRIVER_SYNCOBJ_TIMELINE, 1830 .release = i915_driver_release, 1831 .open = i915_driver_open, 1832 .lastclose = i915_driver_lastclose, 1833 .postclose = i915_driver_postclose, 1834 1835 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1836 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1837 .gem_prime_import = i915_gem_prime_import, 1838 1839 .dumb_create = i915_gem_dumb_create, 1840 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1841 1842 .ioctls = i915_ioctls, 1843 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1844 .fops = &i915_driver_fops, 1845 .name = DRIVER_NAME, 1846 .desc = DRIVER_DESC, 1847 .date = DRIVER_DATE, 1848 .major = DRIVER_MAJOR, 1849 .minor = DRIVER_MINOR, 1850 .patchlevel = DRIVER_PATCHLEVEL, 1851 }; 1852