xref: /openbmc/linux/drivers/gpu/drm/i915/i915_driver.c (revision dba52960)
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29 
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/module.h>
33 #include <linux/oom.h>
34 #include <linux/pci.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vga_switcheroo.h>
40 #include <linux/vt.h>
41 
42 #include <drm/drm_aperture.h>
43 #include <drm/drm_atomic_helper.h>
44 #include <drm/drm_ioctl.h>
45 #include <drm/drm_managed.h>
46 #include <drm/drm_probe_helper.h>
47 
48 #include "display/intel_acpi.h"
49 #include "display/intel_bw.h"
50 #include "display/intel_cdclk.h"
51 #include "display/intel_display_types.h"
52 #include "display/intel_dmc.h"
53 #include "display/intel_dp.h"
54 #include "display/intel_dpt.h"
55 #include "display/intel_fbdev.h"
56 #include "display/intel_hotplug.h"
57 #include "display/intel_overlay.h"
58 #include "display/intel_pch_refclk.h"
59 #include "display/intel_pipe_crc.h"
60 #include "display/intel_pps.h"
61 #include "display/intel_sprite.h"
62 #include "display/intel_vga.h"
63 
64 #include "gem/i915_gem_context.h"
65 #include "gem/i915_gem_ioctls.h"
66 #include "gem/i915_gem_mman.h"
67 #include "gem/i915_gem_pm.h"
68 #include "gt/intel_gt.h"
69 #include "gt/intel_gt_pm.h"
70 #include "gt/intel_rc6.h"
71 
72 #include "pxp/intel_pxp_pm.h"
73 
74 #include "i915_debugfs.h"
75 #include "i915_driver.h"
76 #include "i915_drv.h"
77 #include "i915_ioc32.h"
78 #include "i915_irq.h"
79 #include "i915_memcpy.h"
80 #include "i915_perf.h"
81 #include "i915_query.h"
82 #include "i915_suspend.h"
83 #include "i915_switcheroo.h"
84 #include "i915_sysfs.h"
85 #include "i915_vgpu.h"
86 #include "intel_dram.h"
87 #include "intel_gvt.h"
88 #include "intel_memory_region.h"
89 #include "intel_pcode.h"
90 #include "intel_pm.h"
91 #include "intel_region_ttm.h"
92 #include "vlv_suspend.h"
93 
94 static const struct drm_driver i915_drm_driver;
95 
96 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
97 {
98 	int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
99 
100 	dev_priv->bridge_dev =
101 		pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
102 	if (!dev_priv->bridge_dev) {
103 		drm_err(&dev_priv->drm, "bridge device not found\n");
104 		return -EIO;
105 	}
106 	return 0;
107 }
108 
109 /* Allocate space for the MCH regs if needed, return nonzero on error */
110 static int
111 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
112 {
113 	int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
114 	u32 temp_lo, temp_hi = 0;
115 	u64 mchbar_addr;
116 	int ret;
117 
118 	if (GRAPHICS_VER(dev_priv) >= 4)
119 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
120 	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
121 	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
122 
123 	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
124 #ifdef CONFIG_PNP
125 	if (mchbar_addr &&
126 	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
127 		return 0;
128 #endif
129 
130 	/* Get some space for it */
131 	dev_priv->mch_res.name = "i915 MCHBAR";
132 	dev_priv->mch_res.flags = IORESOURCE_MEM;
133 	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
134 				     &dev_priv->mch_res,
135 				     MCHBAR_SIZE, MCHBAR_SIZE,
136 				     PCIBIOS_MIN_MEM,
137 				     0, pcibios_align_resource,
138 				     dev_priv->bridge_dev);
139 	if (ret) {
140 		drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
141 		dev_priv->mch_res.start = 0;
142 		return ret;
143 	}
144 
145 	if (GRAPHICS_VER(dev_priv) >= 4)
146 		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
147 				       upper_32_bits(dev_priv->mch_res.start));
148 
149 	pci_write_config_dword(dev_priv->bridge_dev, reg,
150 			       lower_32_bits(dev_priv->mch_res.start));
151 	return 0;
152 }
153 
154 /* Setup MCHBAR if possible, return true if we should disable it again */
155 static void
156 intel_setup_mchbar(struct drm_i915_private *dev_priv)
157 {
158 	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
159 	u32 temp;
160 	bool enabled;
161 
162 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
163 		return;
164 
165 	dev_priv->mchbar_need_disable = false;
166 
167 	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
168 		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
169 		enabled = !!(temp & DEVEN_MCHBAR_EN);
170 	} else {
171 		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
172 		enabled = temp & 1;
173 	}
174 
175 	/* If it's already enabled, don't have to do anything */
176 	if (enabled)
177 		return;
178 
179 	if (intel_alloc_mchbar_resource(dev_priv))
180 		return;
181 
182 	dev_priv->mchbar_need_disable = true;
183 
184 	/* Space is allocated or reserved, so enable it. */
185 	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
186 		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
187 				       temp | DEVEN_MCHBAR_EN);
188 	} else {
189 		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
190 		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
191 	}
192 }
193 
194 static void
195 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
196 {
197 	int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
198 
199 	if (dev_priv->mchbar_need_disable) {
200 		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
201 			u32 deven_val;
202 
203 			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
204 					      &deven_val);
205 			deven_val &= ~DEVEN_MCHBAR_EN;
206 			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
207 					       deven_val);
208 		} else {
209 			u32 mchbar_val;
210 
211 			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
212 					      &mchbar_val);
213 			mchbar_val &= ~1;
214 			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
215 					       mchbar_val);
216 		}
217 	}
218 
219 	if (dev_priv->mch_res.start)
220 		release_resource(&dev_priv->mch_res);
221 }
222 
223 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
224 {
225 	/*
226 	 * The i915 workqueue is primarily used for batched retirement of
227 	 * requests (and thus managing bo) once the task has been completed
228 	 * by the GPU. i915_retire_requests() is called directly when we
229 	 * need high-priority retirement, such as waiting for an explicit
230 	 * bo.
231 	 *
232 	 * It is also used for periodic low-priority events, such as
233 	 * idle-timers and recording error state.
234 	 *
235 	 * All tasks on the workqueue are expected to acquire the dev mutex
236 	 * so there is no point in running more than one instance of the
237 	 * workqueue at any time.  Use an ordered one.
238 	 */
239 	dev_priv->wq = alloc_ordered_workqueue("i915", 0);
240 	if (dev_priv->wq == NULL)
241 		goto out_err;
242 
243 	dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
244 	if (dev_priv->hotplug.dp_wq == NULL)
245 		goto out_free_wq;
246 
247 	return 0;
248 
249 out_free_wq:
250 	destroy_workqueue(dev_priv->wq);
251 out_err:
252 	drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
253 
254 	return -ENOMEM;
255 }
256 
257 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
258 {
259 	destroy_workqueue(dev_priv->hotplug.dp_wq);
260 	destroy_workqueue(dev_priv->wq);
261 }
262 
263 /*
264  * We don't keep the workarounds for pre-production hardware, so we expect our
265  * driver to fail on these machines in one way or another. A little warning on
266  * dmesg may help both the user and the bug triagers.
267  *
268  * Our policy for removing pre-production workarounds is to keep the
269  * current gen workarounds as a guide to the bring-up of the next gen
270  * (workarounds have a habit of persisting!). Anything older than that
271  * should be removed along with the complications they introduce.
272  */
273 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
274 {
275 	bool pre = false;
276 
277 	pre |= IS_HSW_EARLY_SDV(dev_priv);
278 	pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
279 	pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
280 	pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
281 	pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
282 	pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
283 
284 	if (pre) {
285 		drm_err(&dev_priv->drm, "This is a pre-production stepping. "
286 			  "It may not be fully functional.\n");
287 		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
288 	}
289 }
290 
291 static void sanitize_gpu(struct drm_i915_private *i915)
292 {
293 	if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
294 		__intel_gt_reset(to_gt(i915), ALL_ENGINES);
295 }
296 
297 /**
298  * i915_driver_early_probe - setup state not requiring device access
299  * @dev_priv: device private
300  *
301  * Initialize everything that is a "SW-only" state, that is state not
302  * requiring accessing the device or exposing the driver via kernel internal
303  * or userspace interfaces. Example steps belonging here: lock initialization,
304  * system memory allocation, setting up device specific attributes and
305  * function hooks not requiring accessing the device.
306  */
307 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
308 {
309 	int ret = 0;
310 
311 	if (i915_inject_probe_failure(dev_priv))
312 		return -ENODEV;
313 
314 	intel_device_info_subplatform_init(dev_priv);
315 	intel_step_init(dev_priv);
316 
317 	intel_gt_init_early(to_gt(dev_priv), dev_priv);
318 	intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
319 	intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
320 
321 	spin_lock_init(&dev_priv->irq_lock);
322 	spin_lock_init(&dev_priv->gpu_error.lock);
323 	mutex_init(&dev_priv->backlight_lock);
324 
325 	mutex_init(&dev_priv->sb_lock);
326 	cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
327 
328 	mutex_init(&dev_priv->audio.mutex);
329 	mutex_init(&dev_priv->wm.wm_mutex);
330 	mutex_init(&dev_priv->pps_mutex);
331 	mutex_init(&dev_priv->hdcp_comp_mutex);
332 
333 	i915_memcpy_init_early(dev_priv);
334 	intel_runtime_pm_init_early(&dev_priv->runtime_pm);
335 
336 	ret = i915_workqueues_init(dev_priv);
337 	if (ret < 0)
338 		return ret;
339 
340 	ret = vlv_suspend_init(dev_priv);
341 	if (ret < 0)
342 		goto err_workqueues;
343 
344 	ret = intel_region_ttm_device_init(dev_priv);
345 	if (ret)
346 		goto err_ttm;
347 
348 	intel_wopcm_init_early(&dev_priv->wopcm);
349 
350 	__intel_gt_init_early(to_gt(dev_priv), dev_priv);
351 
352 	i915_gem_init_early(dev_priv);
353 
354 	/* This must be called before any calls to HAS_PCH_* */
355 	intel_detect_pch(dev_priv);
356 
357 	intel_pm_setup(dev_priv);
358 	ret = intel_power_domains_init(dev_priv);
359 	if (ret < 0)
360 		goto err_gem;
361 	intel_irq_init(dev_priv);
362 	intel_init_display_hooks(dev_priv);
363 	intel_init_clock_gating_hooks(dev_priv);
364 
365 	intel_detect_preproduction_hw(dev_priv);
366 
367 	return 0;
368 
369 err_gem:
370 	i915_gem_cleanup_early(dev_priv);
371 	intel_gt_driver_late_release(to_gt(dev_priv));
372 	intel_region_ttm_device_fini(dev_priv);
373 err_ttm:
374 	vlv_suspend_cleanup(dev_priv);
375 err_workqueues:
376 	i915_workqueues_cleanup(dev_priv);
377 	return ret;
378 }
379 
380 /**
381  * i915_driver_late_release - cleanup the setup done in
382  *			       i915_driver_early_probe()
383  * @dev_priv: device private
384  */
385 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
386 {
387 	intel_irq_fini(dev_priv);
388 	intel_power_domains_cleanup(dev_priv);
389 	i915_gem_cleanup_early(dev_priv);
390 	intel_gt_driver_late_release(to_gt(dev_priv));
391 	intel_region_ttm_device_fini(dev_priv);
392 	vlv_suspend_cleanup(dev_priv);
393 	i915_workqueues_cleanup(dev_priv);
394 
395 	cpu_latency_qos_remove_request(&dev_priv->sb_qos);
396 	mutex_destroy(&dev_priv->sb_lock);
397 
398 	i915_params_free(&dev_priv->params);
399 }
400 
401 /**
402  * i915_driver_mmio_probe - setup device MMIO
403  * @dev_priv: device private
404  *
405  * Setup minimal device state necessary for MMIO accesses later in the
406  * initialization sequence. The setup here should avoid any other device-wide
407  * side effects or exposing the driver via kernel internal or user space
408  * interfaces.
409  */
410 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
411 {
412 	int ret;
413 
414 	if (i915_inject_probe_failure(dev_priv))
415 		return -ENODEV;
416 
417 	ret = i915_get_bridge_dev(dev_priv);
418 	if (ret < 0)
419 		return ret;
420 
421 	ret = intel_uncore_setup_mmio(&dev_priv->uncore);
422 	if (ret < 0)
423 		goto err_bridge;
424 
425 	ret = intel_uncore_init_mmio(&dev_priv->uncore);
426 	if (ret)
427 		goto err_mmio;
428 
429 	/* Try to make sure MCHBAR is enabled before poking at it */
430 	intel_setup_mchbar(dev_priv);
431 	intel_device_info_runtime_init(dev_priv);
432 
433 	ret = intel_gt_init_mmio(to_gt(dev_priv));
434 	if (ret)
435 		goto err_uncore;
436 
437 	/* As early as possible, scrub existing GPU state before clobbering */
438 	sanitize_gpu(dev_priv);
439 
440 	return 0;
441 
442 err_uncore:
443 	intel_teardown_mchbar(dev_priv);
444 	intel_uncore_fini_mmio(&dev_priv->uncore);
445 err_mmio:
446 	intel_uncore_cleanup_mmio(&dev_priv->uncore);
447 err_bridge:
448 	pci_dev_put(dev_priv->bridge_dev);
449 
450 	return ret;
451 }
452 
453 /**
454  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
455  * @dev_priv: device private
456  */
457 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
458 {
459 	intel_teardown_mchbar(dev_priv);
460 	intel_uncore_fini_mmio(&dev_priv->uncore);
461 	intel_uncore_cleanup_mmio(&dev_priv->uncore);
462 	pci_dev_put(dev_priv->bridge_dev);
463 }
464 
465 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
466 {
467 	intel_gvt_sanitize_options(dev_priv);
468 }
469 
470 /**
471  * i915_set_dma_info - set all relevant PCI dma info as configured for the
472  * platform
473  * @i915: valid i915 instance
474  *
475  * Set the dma max segment size, device and coherent masks.  The dma mask set
476  * needs to occur before i915_ggtt_probe_hw.
477  *
478  * A couple of platforms have special needs.  Address them as well.
479  *
480  */
481 static int i915_set_dma_info(struct drm_i915_private *i915)
482 {
483 	unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
484 	int ret;
485 
486 	GEM_BUG_ON(!mask_size);
487 
488 	/*
489 	 * We don't have a max segment size, so set it to the max so sg's
490 	 * debugging layer doesn't complain
491 	 */
492 	dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
493 
494 	ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
495 	if (ret)
496 		goto mask_err;
497 
498 	/* overlay on gen2 is broken and can't address above 1G */
499 	if (GRAPHICS_VER(i915) == 2)
500 		mask_size = 30;
501 
502 	/*
503 	 * 965GM sometimes incorrectly writes to hardware status page (HWS)
504 	 * using 32bit addressing, overwriting memory if HWS is located
505 	 * above 4GB.
506 	 *
507 	 * The documentation also mentions an issue with undefined
508 	 * behaviour if any general state is accessed within a page above 4GB,
509 	 * which also needs to be handled carefully.
510 	 */
511 	if (IS_I965G(i915) || IS_I965GM(i915))
512 		mask_size = 32;
513 
514 	ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
515 	if (ret)
516 		goto mask_err;
517 
518 	return 0;
519 
520 mask_err:
521 	drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
522 	return ret;
523 }
524 
525 /**
526  * i915_driver_hw_probe - setup state requiring device access
527  * @dev_priv: device private
528  *
529  * Setup state that requires accessing the device, but doesn't require
530  * exposing the driver via kernel internal or userspace interfaces.
531  */
532 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
533 {
534 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
535 	int ret;
536 
537 	if (i915_inject_probe_failure(dev_priv))
538 		return -ENODEV;
539 
540 	if (HAS_PPGTT(dev_priv)) {
541 		if (intel_vgpu_active(dev_priv) &&
542 		    !intel_vgpu_has_full_ppgtt(dev_priv)) {
543 			i915_report_error(dev_priv,
544 					  "incompatible vGPU found, support for isolated ppGTT required\n");
545 			return -ENXIO;
546 		}
547 	}
548 
549 	if (HAS_EXECLISTS(dev_priv)) {
550 		/*
551 		 * Older GVT emulation depends upon intercepting CSB mmio,
552 		 * which we no longer use, preferring to use the HWSP cache
553 		 * instead.
554 		 */
555 		if (intel_vgpu_active(dev_priv) &&
556 		    !intel_vgpu_has_hwsp_emulation(dev_priv)) {
557 			i915_report_error(dev_priv,
558 					  "old vGPU host found, support for HWSP emulation required\n");
559 			return -ENXIO;
560 		}
561 	}
562 
563 	intel_sanitize_options(dev_priv);
564 
565 	/* needs to be done before ggtt probe */
566 	intel_dram_edram_detect(dev_priv);
567 
568 	ret = i915_set_dma_info(dev_priv);
569 	if (ret)
570 		return ret;
571 
572 	i915_perf_init(dev_priv);
573 
574 	ret = i915_ggtt_probe_hw(dev_priv);
575 	if (ret)
576 		goto err_perf;
577 
578 	ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
579 	if (ret)
580 		goto err_ggtt;
581 
582 	ret = i915_ggtt_init_hw(dev_priv);
583 	if (ret)
584 		goto err_ggtt;
585 
586 	ret = intel_memory_regions_hw_probe(dev_priv);
587 	if (ret)
588 		goto err_ggtt;
589 
590 	intel_gt_init_hw_early(to_gt(dev_priv), &dev_priv->ggtt);
591 
592 	ret = intel_gt_probe_lmem(to_gt(dev_priv));
593 	if (ret)
594 		goto err_mem_regions;
595 
596 	ret = i915_ggtt_enable_hw(dev_priv);
597 	if (ret) {
598 		drm_err(&dev_priv->drm, "failed to enable GGTT\n");
599 		goto err_mem_regions;
600 	}
601 
602 	pci_set_master(pdev);
603 
604 	/* On the 945G/GM, the chipset reports the MSI capability on the
605 	 * integrated graphics even though the support isn't actually there
606 	 * according to the published specs.  It doesn't appear to function
607 	 * correctly in testing on 945G.
608 	 * This may be a side effect of MSI having been made available for PEG
609 	 * and the registers being closely associated.
610 	 *
611 	 * According to chipset errata, on the 965GM, MSI interrupts may
612 	 * be lost or delayed, and was defeatured. MSI interrupts seem to
613 	 * get lost on g4x as well, and interrupt delivery seems to stay
614 	 * properly dead afterwards. So we'll just disable them for all
615 	 * pre-gen5 chipsets.
616 	 *
617 	 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
618 	 * interrupts even when in MSI mode. This results in spurious
619 	 * interrupt warnings if the legacy irq no. is shared with another
620 	 * device. The kernel then disables that interrupt source and so
621 	 * prevents the other device from working properly.
622 	 */
623 	if (GRAPHICS_VER(dev_priv) >= 5) {
624 		if (pci_enable_msi(pdev) < 0)
625 			drm_dbg(&dev_priv->drm, "can't enable MSI");
626 	}
627 
628 	ret = intel_gvt_init(dev_priv);
629 	if (ret)
630 		goto err_msi;
631 
632 	intel_opregion_setup(dev_priv);
633 
634 	ret = intel_pcode_init(dev_priv);
635 	if (ret)
636 		goto err_msi;
637 
638 	/*
639 	 * Fill the dram structure to get the system dram info. This will be
640 	 * used for memory latency calculation.
641 	 */
642 	intel_dram_detect(dev_priv);
643 
644 	intel_bw_init_hw(dev_priv);
645 
646 	return 0;
647 
648 err_msi:
649 	if (pdev->msi_enabled)
650 		pci_disable_msi(pdev);
651 err_mem_regions:
652 	intel_memory_regions_driver_release(dev_priv);
653 err_ggtt:
654 	i915_ggtt_driver_release(dev_priv);
655 	i915_gem_drain_freed_objects(dev_priv);
656 	i915_ggtt_driver_late_release(dev_priv);
657 err_perf:
658 	i915_perf_fini(dev_priv);
659 	return ret;
660 }
661 
662 /**
663  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
664  * @dev_priv: device private
665  */
666 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
667 {
668 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
669 
670 	i915_perf_fini(dev_priv);
671 
672 	if (pdev->msi_enabled)
673 		pci_disable_msi(pdev);
674 }
675 
676 /**
677  * i915_driver_register - register the driver with the rest of the system
678  * @dev_priv: device private
679  *
680  * Perform any steps necessary to make the driver available via kernel
681  * internal or userspace interfaces.
682  */
683 static void i915_driver_register(struct drm_i915_private *dev_priv)
684 {
685 	struct drm_device *dev = &dev_priv->drm;
686 
687 	i915_gem_driver_register(dev_priv);
688 	i915_pmu_register(dev_priv);
689 
690 	intel_vgpu_register(dev_priv);
691 
692 	/* Reveal our presence to userspace */
693 	if (drm_dev_register(dev, 0)) {
694 		drm_err(&dev_priv->drm,
695 			"Failed to register driver for userspace access!\n");
696 		return;
697 	}
698 
699 	i915_debugfs_register(dev_priv);
700 	i915_setup_sysfs(dev_priv);
701 
702 	/* Depends on sysfs having been initialized */
703 	i915_perf_register(dev_priv);
704 
705 	intel_gt_driver_register(to_gt(dev_priv));
706 
707 	intel_display_driver_register(dev_priv);
708 
709 	intel_power_domains_enable(dev_priv);
710 	intel_runtime_pm_enable(&dev_priv->runtime_pm);
711 
712 	intel_register_dsm_handler();
713 
714 	if (i915_switcheroo_register(dev_priv))
715 		drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
716 }
717 
718 /**
719  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
720  * @dev_priv: device private
721  */
722 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
723 {
724 	i915_switcheroo_unregister(dev_priv);
725 
726 	intel_unregister_dsm_handler();
727 
728 	intel_runtime_pm_disable(&dev_priv->runtime_pm);
729 	intel_power_domains_disable(dev_priv);
730 
731 	intel_display_driver_unregister(dev_priv);
732 
733 	intel_gt_driver_unregister(to_gt(dev_priv));
734 
735 	i915_perf_unregister(dev_priv);
736 	i915_pmu_unregister(dev_priv);
737 
738 	i915_teardown_sysfs(dev_priv);
739 	drm_dev_unplug(&dev_priv->drm);
740 
741 	i915_gem_driver_unregister(dev_priv);
742 }
743 
744 void
745 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
746 {
747 	drm_printf(p, "iommu: %s\n", enableddisabled(intel_vtd_active(i915)));
748 }
749 
750 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
751 {
752 	if (drm_debug_enabled(DRM_UT_DRIVER)) {
753 		struct drm_printer p = drm_debug_printer("i915 device info:");
754 
755 		drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
756 			   INTEL_DEVID(dev_priv),
757 			   INTEL_REVID(dev_priv),
758 			   intel_platform_name(INTEL_INFO(dev_priv)->platform),
759 			   intel_subplatform(RUNTIME_INFO(dev_priv),
760 					     INTEL_INFO(dev_priv)->platform),
761 			   GRAPHICS_VER(dev_priv));
762 
763 		intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
764 		intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
765 		i915_print_iommu_status(dev_priv, &p);
766 		intel_gt_info_print(&to_gt(dev_priv)->info, &p);
767 	}
768 
769 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
770 		drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
771 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
772 		drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
773 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
774 		drm_info(&dev_priv->drm,
775 			 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
776 }
777 
778 static struct drm_i915_private *
779 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
780 {
781 	const struct intel_device_info *match_info =
782 		(struct intel_device_info *)ent->driver_data;
783 	struct intel_device_info *device_info;
784 	struct drm_i915_private *i915;
785 
786 	i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
787 				  struct drm_i915_private, drm);
788 	if (IS_ERR(i915))
789 		return i915;
790 
791 	pci_set_drvdata(pdev, i915);
792 
793 	/* Device parameters start as a copy of module parameters. */
794 	i915_params_copy(&i915->params, &i915_modparams);
795 
796 	/* Setup the write-once "constant" device info */
797 	device_info = mkwrite_device_info(i915);
798 	memcpy(device_info, match_info, sizeof(*device_info));
799 	RUNTIME_INFO(i915)->device_id = pdev->device;
800 
801 	return i915;
802 }
803 
804 /**
805  * i915_driver_probe - setup chip and create an initial config
806  * @pdev: PCI device
807  * @ent: matching PCI ID entry
808  *
809  * The driver probe routine has to do several things:
810  *   - drive output discovery via intel_modeset_init()
811  *   - initialize the memory manager
812  *   - allocate initial config memory
813  *   - setup the DRM framebuffer with the allocated memory
814  */
815 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
816 {
817 	const struct intel_device_info *match_info =
818 		(struct intel_device_info *)ent->driver_data;
819 	struct drm_i915_private *i915;
820 	int ret;
821 
822 	i915 = i915_driver_create(pdev, ent);
823 	if (IS_ERR(i915))
824 		return PTR_ERR(i915);
825 
826 	/* Disable nuclear pageflip by default on pre-ILK */
827 	if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
828 		i915->drm.driver_features &= ~DRIVER_ATOMIC;
829 
830 	/*
831 	 * Check if we support fake LMEM -- for now we only unleash this for
832 	 * the live selftests(test-and-exit).
833 	 */
834 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
835 	if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
836 		if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&
837 		    i915->params.fake_lmem_start) {
838 			mkwrite_device_info(i915)->memory_regions =
839 				REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
840 			GEM_BUG_ON(!HAS_LMEM(i915));
841 		}
842 	}
843 #endif
844 
845 	ret = pci_enable_device(pdev);
846 	if (ret)
847 		goto out_fini;
848 
849 	ret = i915_driver_early_probe(i915);
850 	if (ret < 0)
851 		goto out_pci_disable;
852 
853 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
854 
855 	intel_vgpu_detect(i915);
856 
857 	ret = i915_driver_mmio_probe(i915);
858 	if (ret < 0)
859 		goto out_runtime_pm_put;
860 
861 	ret = i915_driver_hw_probe(i915);
862 	if (ret < 0)
863 		goto out_cleanup_mmio;
864 
865 	ret = intel_modeset_init_noirq(i915);
866 	if (ret < 0)
867 		goto out_cleanup_hw;
868 
869 	ret = intel_irq_install(i915);
870 	if (ret)
871 		goto out_cleanup_modeset;
872 
873 	ret = intel_modeset_init_nogem(i915);
874 	if (ret)
875 		goto out_cleanup_irq;
876 
877 	ret = i915_gem_init(i915);
878 	if (ret)
879 		goto out_cleanup_modeset2;
880 
881 	ret = intel_modeset_init(i915);
882 	if (ret)
883 		goto out_cleanup_gem;
884 
885 	i915_driver_register(i915);
886 
887 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
888 
889 	i915_welcome_messages(i915);
890 
891 	i915->do_release = true;
892 
893 	return 0;
894 
895 out_cleanup_gem:
896 	i915_gem_suspend(i915);
897 	i915_gem_driver_remove(i915);
898 	i915_gem_driver_release(i915);
899 out_cleanup_modeset2:
900 	/* FIXME clean up the error path */
901 	intel_modeset_driver_remove(i915);
902 	intel_irq_uninstall(i915);
903 	intel_modeset_driver_remove_noirq(i915);
904 	goto out_cleanup_modeset;
905 out_cleanup_irq:
906 	intel_irq_uninstall(i915);
907 out_cleanup_modeset:
908 	intel_modeset_driver_remove_nogem(i915);
909 out_cleanup_hw:
910 	i915_driver_hw_remove(i915);
911 	intel_memory_regions_driver_release(i915);
912 	i915_ggtt_driver_release(i915);
913 	i915_gem_drain_freed_objects(i915);
914 	i915_ggtt_driver_late_release(i915);
915 out_cleanup_mmio:
916 	i915_driver_mmio_release(i915);
917 out_runtime_pm_put:
918 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
919 	i915_driver_late_release(i915);
920 out_pci_disable:
921 	pci_disable_device(pdev);
922 out_fini:
923 	i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
924 	return ret;
925 }
926 
927 void i915_driver_remove(struct drm_i915_private *i915)
928 {
929 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
930 
931 	i915_driver_unregister(i915);
932 
933 	/* Flush any external code that still may be under the RCU lock */
934 	synchronize_rcu();
935 
936 	i915_gem_suspend(i915);
937 
938 	intel_gvt_driver_remove(i915);
939 
940 	intel_modeset_driver_remove(i915);
941 
942 	intel_irq_uninstall(i915);
943 
944 	intel_modeset_driver_remove_noirq(i915);
945 
946 	i915_reset_error_state(i915);
947 	i915_gem_driver_remove(i915);
948 
949 	intel_modeset_driver_remove_nogem(i915);
950 
951 	i915_driver_hw_remove(i915);
952 
953 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
954 }
955 
956 static void i915_driver_release(struct drm_device *dev)
957 {
958 	struct drm_i915_private *dev_priv = to_i915(dev);
959 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
960 
961 	if (!dev_priv->do_release)
962 		return;
963 
964 	disable_rpm_wakeref_asserts(rpm);
965 
966 	i915_gem_driver_release(dev_priv);
967 
968 	intel_memory_regions_driver_release(dev_priv);
969 	i915_ggtt_driver_release(dev_priv);
970 	i915_gem_drain_freed_objects(dev_priv);
971 	i915_ggtt_driver_late_release(dev_priv);
972 
973 	i915_driver_mmio_release(dev_priv);
974 
975 	enable_rpm_wakeref_asserts(rpm);
976 	intel_runtime_pm_driver_release(rpm);
977 
978 	i915_driver_late_release(dev_priv);
979 }
980 
981 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
982 {
983 	struct drm_i915_private *i915 = to_i915(dev);
984 	int ret;
985 
986 	ret = i915_gem_open(i915, file);
987 	if (ret)
988 		return ret;
989 
990 	return 0;
991 }
992 
993 /**
994  * i915_driver_lastclose - clean up after all DRM clients have exited
995  * @dev: DRM device
996  *
997  * Take care of cleaning up after all DRM clients have exited.  In the
998  * mode setting case, we want to restore the kernel's initial mode (just
999  * in case the last client left us in a bad state).
1000  *
1001  * Additionally, in the non-mode setting case, we'll tear down the GTT
1002  * and DMA structures, since the kernel won't be using them, and clea
1003  * up any GEM state.
1004  */
1005 static void i915_driver_lastclose(struct drm_device *dev)
1006 {
1007 	struct drm_i915_private *i915 = to_i915(dev);
1008 
1009 	intel_fbdev_restore_mode(dev);
1010 
1011 	if (HAS_DISPLAY(i915))
1012 		vga_switcheroo_process_delayed_switch();
1013 }
1014 
1015 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1016 {
1017 	struct drm_i915_file_private *file_priv = file->driver_priv;
1018 
1019 	i915_gem_context_close(file);
1020 
1021 	kfree_rcu(file_priv, rcu);
1022 
1023 	/* Catch up with all the deferred frees from "this" client */
1024 	i915_gem_flush_free_objects(to_i915(dev));
1025 }
1026 
1027 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1028 {
1029 	struct drm_device *dev = &dev_priv->drm;
1030 	struct intel_encoder *encoder;
1031 
1032 	if (!HAS_DISPLAY(dev_priv))
1033 		return;
1034 
1035 	drm_modeset_lock_all(dev);
1036 	for_each_intel_encoder(dev, encoder)
1037 		if (encoder->suspend)
1038 			encoder->suspend(encoder);
1039 	drm_modeset_unlock_all(dev);
1040 }
1041 
1042 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1043 {
1044 	struct drm_device *dev = &dev_priv->drm;
1045 	struct intel_encoder *encoder;
1046 
1047 	if (!HAS_DISPLAY(dev_priv))
1048 		return;
1049 
1050 	drm_modeset_lock_all(dev);
1051 	for_each_intel_encoder(dev, encoder)
1052 		if (encoder->shutdown)
1053 			encoder->shutdown(encoder);
1054 	drm_modeset_unlock_all(dev);
1055 }
1056 
1057 void i915_driver_shutdown(struct drm_i915_private *i915)
1058 {
1059 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
1060 	intel_runtime_pm_disable(&i915->runtime_pm);
1061 	intel_power_domains_disable(i915);
1062 
1063 	i915_gem_suspend(i915);
1064 
1065 	if (HAS_DISPLAY(i915)) {
1066 		drm_kms_helper_poll_disable(&i915->drm);
1067 
1068 		drm_atomic_helper_shutdown(&i915->drm);
1069 	}
1070 
1071 	intel_dp_mst_suspend(i915);
1072 
1073 	intel_runtime_pm_disable_interrupts(i915);
1074 	intel_hpd_cancel_work(i915);
1075 
1076 	intel_suspend_encoders(i915);
1077 	intel_shutdown_encoders(i915);
1078 
1079 	intel_dmc_ucode_suspend(i915);
1080 
1081 	/*
1082 	 * The only requirement is to reboot with display DC states disabled,
1083 	 * for now leaving all display power wells in the INIT power domain
1084 	 * enabled.
1085 	 *
1086 	 * TODO:
1087 	 * - unify the pci_driver::shutdown sequence here with the
1088 	 *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1089 	 * - unify the driver remove and system/runtime suspend sequences with
1090 	 *   the above unified shutdown/poweroff sequence.
1091 	 */
1092 	intel_power_domains_driver_remove(i915);
1093 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
1094 
1095 	intel_runtime_pm_driver_release(&i915->runtime_pm);
1096 }
1097 
1098 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1099 {
1100 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1101 	if (acpi_target_system_state() < ACPI_STATE_S3)
1102 		return true;
1103 #endif
1104 	return false;
1105 }
1106 
1107 static int i915_drm_prepare(struct drm_device *dev)
1108 {
1109 	struct drm_i915_private *i915 = to_i915(dev);
1110 
1111 	/*
1112 	 * NB intel_display_suspend() may issue new requests after we've
1113 	 * ostensibly marked the GPU as ready-to-sleep here. We need to
1114 	 * split out that work and pull it forward so that after point,
1115 	 * the GPU is not woken again.
1116 	 */
1117 	return i915_gem_backup_suspend(i915);
1118 }
1119 
1120 static int i915_drm_suspend(struct drm_device *dev)
1121 {
1122 	struct drm_i915_private *dev_priv = to_i915(dev);
1123 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1124 	pci_power_t opregion_target_state;
1125 
1126 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1127 
1128 	/* We do a lot of poking in a lot of registers, make sure they work
1129 	 * properly. */
1130 	intel_power_domains_disable(dev_priv);
1131 	if (HAS_DISPLAY(dev_priv))
1132 		drm_kms_helper_poll_disable(dev);
1133 
1134 	pci_save_state(pdev);
1135 
1136 	intel_display_suspend(dev);
1137 
1138 	intel_dp_mst_suspend(dev_priv);
1139 
1140 	intel_runtime_pm_disable_interrupts(dev_priv);
1141 	intel_hpd_cancel_work(dev_priv);
1142 
1143 	intel_suspend_encoders(dev_priv);
1144 
1145 	intel_suspend_hw(dev_priv);
1146 
1147 	/* Must be called before GGTT is suspended. */
1148 	intel_dpt_suspend(dev_priv);
1149 	i915_ggtt_suspend(&dev_priv->ggtt);
1150 
1151 	i915_save_display(dev_priv);
1152 
1153 	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1154 	intel_opregion_suspend(dev_priv, opregion_target_state);
1155 
1156 	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1157 
1158 	dev_priv->suspend_count++;
1159 
1160 	intel_dmc_ucode_suspend(dev_priv);
1161 
1162 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1163 
1164 	return 0;
1165 }
1166 
1167 static enum i915_drm_suspend_mode
1168 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1169 {
1170 	if (hibernate)
1171 		return I915_DRM_SUSPEND_HIBERNATE;
1172 
1173 	if (suspend_to_idle(dev_priv))
1174 		return I915_DRM_SUSPEND_IDLE;
1175 
1176 	return I915_DRM_SUSPEND_MEM;
1177 }
1178 
1179 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1180 {
1181 	struct drm_i915_private *dev_priv = to_i915(dev);
1182 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1183 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1184 	int ret;
1185 
1186 	disable_rpm_wakeref_asserts(rpm);
1187 
1188 	i915_gem_suspend_late(dev_priv);
1189 
1190 	intel_uncore_suspend(&dev_priv->uncore);
1191 
1192 	intel_power_domains_suspend(dev_priv,
1193 				    get_suspend_mode(dev_priv, hibernation));
1194 
1195 	intel_display_power_suspend_late(dev_priv);
1196 
1197 	ret = vlv_suspend_complete(dev_priv);
1198 	if (ret) {
1199 		drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1200 		intel_power_domains_resume(dev_priv);
1201 
1202 		goto out;
1203 	}
1204 
1205 	/*
1206 	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1207 	 * This should be totally removed when we handle the pci states properly
1208 	 * on runtime PM and on s2idle cases.
1209 	 */
1210 	if (suspend_to_idle(dev_priv))
1211 		pci_d3cold_disable(pdev);
1212 
1213 	pci_disable_device(pdev);
1214 	/*
1215 	 * During hibernation on some platforms the BIOS may try to access
1216 	 * the device even though it's already in D3 and hang the machine. So
1217 	 * leave the device in D0 on those platforms and hope the BIOS will
1218 	 * power down the device properly. The issue was seen on multiple old
1219 	 * GENs with different BIOS vendors, so having an explicit blacklist
1220 	 * is inpractical; apply the workaround on everything pre GEN6. The
1221 	 * platforms where the issue was seen:
1222 	 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1223 	 * Fujitsu FSC S7110
1224 	 * Acer Aspire 1830T
1225 	 */
1226 	if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1227 		pci_set_power_state(pdev, PCI_D3hot);
1228 
1229 out:
1230 	enable_rpm_wakeref_asserts(rpm);
1231 	if (!dev_priv->uncore.user_forcewake_count)
1232 		intel_runtime_pm_driver_release(rpm);
1233 
1234 	return ret;
1235 }
1236 
1237 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1238 				   pm_message_t state)
1239 {
1240 	int error;
1241 
1242 	if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1243 			     state.event != PM_EVENT_FREEZE))
1244 		return -EINVAL;
1245 
1246 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1247 		return 0;
1248 
1249 	error = i915_drm_suspend(&i915->drm);
1250 	if (error)
1251 		return error;
1252 
1253 	return i915_drm_suspend_late(&i915->drm, false);
1254 }
1255 
1256 static int i915_drm_resume(struct drm_device *dev)
1257 {
1258 	struct drm_i915_private *dev_priv = to_i915(dev);
1259 	int ret;
1260 
1261 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1262 
1263 	ret = intel_pcode_init(dev_priv);
1264 	if (ret)
1265 		return ret;
1266 
1267 	sanitize_gpu(dev_priv);
1268 
1269 	ret = i915_ggtt_enable_hw(dev_priv);
1270 	if (ret)
1271 		drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1272 
1273 	i915_ggtt_resume(&dev_priv->ggtt);
1274 	/* Must be called after GGTT is resumed. */
1275 	intel_dpt_resume(dev_priv);
1276 
1277 	intel_dmc_ucode_resume(dev_priv);
1278 
1279 	i915_restore_display(dev_priv);
1280 	intel_pps_unlock_regs_wa(dev_priv);
1281 
1282 	intel_init_pch_refclk(dev_priv);
1283 
1284 	/*
1285 	 * Interrupts have to be enabled before any batches are run. If not the
1286 	 * GPU will hang. i915_gem_init_hw() will initiate batches to
1287 	 * update/restore the context.
1288 	 *
1289 	 * drm_mode_config_reset() needs AUX interrupts.
1290 	 *
1291 	 * Modeset enabling in intel_modeset_init_hw() also needs working
1292 	 * interrupts.
1293 	 */
1294 	intel_runtime_pm_enable_interrupts(dev_priv);
1295 
1296 	if (HAS_DISPLAY(dev_priv))
1297 		drm_mode_config_reset(dev);
1298 
1299 	i915_gem_resume(dev_priv);
1300 
1301 	intel_modeset_init_hw(dev_priv);
1302 	intel_init_clock_gating(dev_priv);
1303 	intel_hpd_init(dev_priv);
1304 
1305 	/* MST sideband requires HPD interrupts enabled */
1306 	intel_dp_mst_resume(dev_priv);
1307 	intel_display_resume(dev);
1308 
1309 	intel_hpd_poll_disable(dev_priv);
1310 	if (HAS_DISPLAY(dev_priv))
1311 		drm_kms_helper_poll_enable(dev);
1312 
1313 	intel_opregion_resume(dev_priv);
1314 
1315 	intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1316 
1317 	intel_power_domains_enable(dev_priv);
1318 
1319 	intel_gvt_resume(dev_priv);
1320 
1321 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1322 
1323 	return 0;
1324 }
1325 
1326 static int i915_drm_resume_early(struct drm_device *dev)
1327 {
1328 	struct drm_i915_private *dev_priv = to_i915(dev);
1329 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1330 	int ret;
1331 
1332 	/*
1333 	 * We have a resume ordering issue with the snd-hda driver also
1334 	 * requiring our device to be power up. Due to the lack of a
1335 	 * parent/child relationship we currently solve this with an early
1336 	 * resume hook.
1337 	 *
1338 	 * FIXME: This should be solved with a special hdmi sink device or
1339 	 * similar so that power domains can be employed.
1340 	 */
1341 
1342 	/*
1343 	 * Note that we need to set the power state explicitly, since we
1344 	 * powered off the device during freeze and the PCI core won't power
1345 	 * it back up for us during thaw. Powering off the device during
1346 	 * freeze is not a hard requirement though, and during the
1347 	 * suspend/resume phases the PCI core makes sure we get here with the
1348 	 * device powered on. So in case we change our freeze logic and keep
1349 	 * the device powered we can also remove the following set power state
1350 	 * call.
1351 	 */
1352 	ret = pci_set_power_state(pdev, PCI_D0);
1353 	if (ret) {
1354 		drm_err(&dev_priv->drm,
1355 			"failed to set PCI D0 power state (%d)\n", ret);
1356 		return ret;
1357 	}
1358 
1359 	/*
1360 	 * Note that pci_enable_device() first enables any parent bridge
1361 	 * device and only then sets the power state for this device. The
1362 	 * bridge enabling is a nop though, since bridge devices are resumed
1363 	 * first. The order of enabling power and enabling the device is
1364 	 * imposed by the PCI core as described above, so here we preserve the
1365 	 * same order for the freeze/thaw phases.
1366 	 *
1367 	 * TODO: eventually we should remove pci_disable_device() /
1368 	 * pci_enable_enable_device() from suspend/resume. Due to how they
1369 	 * depend on the device enable refcount we can't anyway depend on them
1370 	 * disabling/enabling the device.
1371 	 */
1372 	if (pci_enable_device(pdev))
1373 		return -EIO;
1374 
1375 	pci_set_master(pdev);
1376 
1377 	pci_d3cold_enable(pdev);
1378 
1379 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1380 
1381 	ret = vlv_resume_prepare(dev_priv, false);
1382 	if (ret)
1383 		drm_err(&dev_priv->drm,
1384 			"Resume prepare failed: %d, continuing anyway\n", ret);
1385 
1386 	intel_uncore_resume_early(&dev_priv->uncore);
1387 
1388 	intel_gt_check_and_clear_faults(to_gt(dev_priv));
1389 
1390 	intel_display_power_resume_early(dev_priv);
1391 
1392 	intel_power_domains_resume(dev_priv);
1393 
1394 	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1395 
1396 	return ret;
1397 }
1398 
1399 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1400 {
1401 	int ret;
1402 
1403 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1404 		return 0;
1405 
1406 	ret = i915_drm_resume_early(&i915->drm);
1407 	if (ret)
1408 		return ret;
1409 
1410 	return i915_drm_resume(&i915->drm);
1411 }
1412 
1413 static int i915_pm_prepare(struct device *kdev)
1414 {
1415 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1416 
1417 	if (!i915) {
1418 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1419 		return -ENODEV;
1420 	}
1421 
1422 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1423 		return 0;
1424 
1425 	return i915_drm_prepare(&i915->drm);
1426 }
1427 
1428 static int i915_pm_suspend(struct device *kdev)
1429 {
1430 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1431 
1432 	if (!i915) {
1433 		dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1434 		return -ENODEV;
1435 	}
1436 
1437 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1438 		return 0;
1439 
1440 	return i915_drm_suspend(&i915->drm);
1441 }
1442 
1443 static int i915_pm_suspend_late(struct device *kdev)
1444 {
1445 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1446 
1447 	/*
1448 	 * We have a suspend ordering issue with the snd-hda driver also
1449 	 * requiring our device to be power up. Due to the lack of a
1450 	 * parent/child relationship we currently solve this with an late
1451 	 * suspend hook.
1452 	 *
1453 	 * FIXME: This should be solved with a special hdmi sink device or
1454 	 * similar so that power domains can be employed.
1455 	 */
1456 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1457 		return 0;
1458 
1459 	return i915_drm_suspend_late(&i915->drm, false);
1460 }
1461 
1462 static int i915_pm_poweroff_late(struct device *kdev)
1463 {
1464 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1465 
1466 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1467 		return 0;
1468 
1469 	return i915_drm_suspend_late(&i915->drm, true);
1470 }
1471 
1472 static int i915_pm_resume_early(struct device *kdev)
1473 {
1474 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1475 
1476 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1477 		return 0;
1478 
1479 	return i915_drm_resume_early(&i915->drm);
1480 }
1481 
1482 static int i915_pm_resume(struct device *kdev)
1483 {
1484 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1485 
1486 	if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1487 		return 0;
1488 
1489 	return i915_drm_resume(&i915->drm);
1490 }
1491 
1492 /* freeze: before creating the hibernation_image */
1493 static int i915_pm_freeze(struct device *kdev)
1494 {
1495 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1496 	int ret;
1497 
1498 	if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1499 		ret = i915_drm_suspend(&i915->drm);
1500 		if (ret)
1501 			return ret;
1502 	}
1503 
1504 	ret = i915_gem_freeze(i915);
1505 	if (ret)
1506 		return ret;
1507 
1508 	return 0;
1509 }
1510 
1511 static int i915_pm_freeze_late(struct device *kdev)
1512 {
1513 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
1514 	int ret;
1515 
1516 	if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1517 		ret = i915_drm_suspend_late(&i915->drm, true);
1518 		if (ret)
1519 			return ret;
1520 	}
1521 
1522 	ret = i915_gem_freeze_late(i915);
1523 	if (ret)
1524 		return ret;
1525 
1526 	return 0;
1527 }
1528 
1529 /* thaw: called after creating the hibernation image, but before turning off. */
1530 static int i915_pm_thaw_early(struct device *kdev)
1531 {
1532 	return i915_pm_resume_early(kdev);
1533 }
1534 
1535 static int i915_pm_thaw(struct device *kdev)
1536 {
1537 	return i915_pm_resume(kdev);
1538 }
1539 
1540 /* restore: called after loading the hibernation image. */
1541 static int i915_pm_restore_early(struct device *kdev)
1542 {
1543 	return i915_pm_resume_early(kdev);
1544 }
1545 
1546 static int i915_pm_restore(struct device *kdev)
1547 {
1548 	return i915_pm_resume(kdev);
1549 }
1550 
1551 static int intel_runtime_suspend(struct device *kdev)
1552 {
1553 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1554 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1555 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1556 	int ret;
1557 
1558 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1559 		return -ENODEV;
1560 
1561 	drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1562 
1563 	disable_rpm_wakeref_asserts(rpm);
1564 
1565 	/*
1566 	 * We are safe here against re-faults, since the fault handler takes
1567 	 * an RPM reference.
1568 	 */
1569 	i915_gem_runtime_suspend(dev_priv);
1570 
1571 	intel_gt_runtime_suspend(to_gt(dev_priv));
1572 
1573 	intel_runtime_pm_disable_interrupts(dev_priv);
1574 
1575 	intel_uncore_suspend(&dev_priv->uncore);
1576 
1577 	intel_display_power_suspend(dev_priv);
1578 
1579 	ret = vlv_suspend_complete(dev_priv);
1580 	if (ret) {
1581 		drm_err(&dev_priv->drm,
1582 			"Runtime suspend failed, disabling it (%d)\n", ret);
1583 		intel_uncore_runtime_resume(&dev_priv->uncore);
1584 
1585 		intel_runtime_pm_enable_interrupts(dev_priv);
1586 
1587 		intel_gt_runtime_resume(to_gt(dev_priv));
1588 
1589 		enable_rpm_wakeref_asserts(rpm);
1590 
1591 		return ret;
1592 	}
1593 
1594 	enable_rpm_wakeref_asserts(rpm);
1595 	intel_runtime_pm_driver_release(rpm);
1596 
1597 	if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1598 		drm_err(&dev_priv->drm,
1599 			"Unclaimed access detected prior to suspending\n");
1600 
1601 	/*
1602 	 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1603 	 * This should be totally removed when we handle the pci states properly
1604 	 * on runtime PM and on s2idle cases.
1605 	 */
1606 	pci_d3cold_disable(pdev);
1607 	rpm->suspended = true;
1608 
1609 	/*
1610 	 * FIXME: We really should find a document that references the arguments
1611 	 * used below!
1612 	 */
1613 	if (IS_BROADWELL(dev_priv)) {
1614 		/*
1615 		 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1616 		 * being detected, and the call we do at intel_runtime_resume()
1617 		 * won't be able to restore them. Since PCI_D3hot matches the
1618 		 * actual specification and appears to be working, use it.
1619 		 */
1620 		intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1621 	} else {
1622 		/*
1623 		 * current versions of firmware which depend on this opregion
1624 		 * notification have repurposed the D1 definition to mean
1625 		 * "runtime suspended" vs. what you would normally expect (D3)
1626 		 * to distinguish it from notifications that might be sent via
1627 		 * the suspend path.
1628 		 */
1629 		intel_opregion_notify_adapter(dev_priv, PCI_D1);
1630 	}
1631 
1632 	assert_forcewakes_inactive(&dev_priv->uncore);
1633 
1634 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1635 		intel_hpd_poll_enable(dev_priv);
1636 
1637 	drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1638 	return 0;
1639 }
1640 
1641 static int intel_runtime_resume(struct device *kdev)
1642 {
1643 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1644 	struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1645 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1646 	int ret;
1647 
1648 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1649 		return -ENODEV;
1650 
1651 	drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1652 
1653 	drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1654 	disable_rpm_wakeref_asserts(rpm);
1655 
1656 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
1657 	rpm->suspended = false;
1658 	pci_d3cold_enable(pdev);
1659 	if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1660 		drm_dbg(&dev_priv->drm,
1661 			"Unclaimed access during suspend, bios?\n");
1662 
1663 	intel_display_power_resume(dev_priv);
1664 
1665 	ret = vlv_resume_prepare(dev_priv, true);
1666 
1667 	intel_uncore_runtime_resume(&dev_priv->uncore);
1668 
1669 	intel_runtime_pm_enable_interrupts(dev_priv);
1670 
1671 	/*
1672 	 * No point of rolling back things in case of an error, as the best
1673 	 * we can do is to hope that things will still work (and disable RPM).
1674 	 */
1675 	intel_gt_runtime_resume(to_gt(dev_priv));
1676 
1677 	/*
1678 	 * On VLV/CHV display interrupts are part of the display
1679 	 * power well, so hpd is reinitialized from there. For
1680 	 * everyone else do it here.
1681 	 */
1682 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1683 		intel_hpd_init(dev_priv);
1684 		intel_hpd_poll_disable(dev_priv);
1685 	}
1686 
1687 	intel_enable_ipc(dev_priv);
1688 
1689 	enable_rpm_wakeref_asserts(rpm);
1690 
1691 	if (ret)
1692 		drm_err(&dev_priv->drm,
1693 			"Runtime resume failed, disabling it (%d)\n", ret);
1694 	else
1695 		drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1696 
1697 	return ret;
1698 }
1699 
1700 const struct dev_pm_ops i915_pm_ops = {
1701 	/*
1702 	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1703 	 * PMSG_RESUME]
1704 	 */
1705 	.prepare = i915_pm_prepare,
1706 	.suspend = i915_pm_suspend,
1707 	.suspend_late = i915_pm_suspend_late,
1708 	.resume_early = i915_pm_resume_early,
1709 	.resume = i915_pm_resume,
1710 
1711 	/*
1712 	 * S4 event handlers
1713 	 * @freeze, @freeze_late    : called (1) before creating the
1714 	 *                            hibernation image [PMSG_FREEZE] and
1715 	 *                            (2) after rebooting, before restoring
1716 	 *                            the image [PMSG_QUIESCE]
1717 	 * @thaw, @thaw_early       : called (1) after creating the hibernation
1718 	 *                            image, before writing it [PMSG_THAW]
1719 	 *                            and (2) after failing to create or
1720 	 *                            restore the image [PMSG_RECOVER]
1721 	 * @poweroff, @poweroff_late: called after writing the hibernation
1722 	 *                            image, before rebooting [PMSG_HIBERNATE]
1723 	 * @restore, @restore_early : called after rebooting and restoring the
1724 	 *                            hibernation image [PMSG_RESTORE]
1725 	 */
1726 	.freeze = i915_pm_freeze,
1727 	.freeze_late = i915_pm_freeze_late,
1728 	.thaw_early = i915_pm_thaw_early,
1729 	.thaw = i915_pm_thaw,
1730 	.poweroff = i915_pm_suspend,
1731 	.poweroff_late = i915_pm_poweroff_late,
1732 	.restore_early = i915_pm_restore_early,
1733 	.restore = i915_pm_restore,
1734 
1735 	/* S0ix (via runtime suspend) event handlers */
1736 	.runtime_suspend = intel_runtime_suspend,
1737 	.runtime_resume = intel_runtime_resume,
1738 };
1739 
1740 static const struct file_operations i915_driver_fops = {
1741 	.owner = THIS_MODULE,
1742 	.open = drm_open,
1743 	.release = drm_release_noglobal,
1744 	.unlocked_ioctl = drm_ioctl,
1745 	.mmap = i915_gem_mmap,
1746 	.poll = drm_poll,
1747 	.read = drm_read,
1748 	.compat_ioctl = i915_ioc32_compat_ioctl,
1749 	.llseek = noop_llseek,
1750 };
1751 
1752 static int
1753 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1754 			  struct drm_file *file)
1755 {
1756 	return -ENODEV;
1757 }
1758 
1759 static const struct drm_ioctl_desc i915_ioctls[] = {
1760 	DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1761 	DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1762 	DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1763 	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1764 	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1765 	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1766 	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1767 	DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1768 	DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1769 	DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1770 	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1771 	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1772 	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773 	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1774 	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1775 	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1776 	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1777 	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1778 	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1779 	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1780 	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1781 	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1782 	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1783 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1784 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1785 	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1786 	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1787 	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1788 	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1789 	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1790 	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1791 	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1792 	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1793 	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1794 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1795 	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1796 	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1797 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1798 	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1799 	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1800 	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1801 	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1802 	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1803 	DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1804 	DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1805 	DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1806 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1807 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1808 	DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1809 	DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1810 	DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1811 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1812 	DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1813 	DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1814 	DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1815 	DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1816 	DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1817 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1818 	DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1819 };
1820 
1821 static const struct drm_driver i915_drm_driver = {
1822 	/* Don't use MTRRs here; the Xserver or userspace app should
1823 	 * deal with them for Intel hardware.
1824 	 */
1825 	.driver_features =
1826 	    DRIVER_GEM |
1827 	    DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1828 	    DRIVER_SYNCOBJ_TIMELINE,
1829 	.release = i915_driver_release,
1830 	.open = i915_driver_open,
1831 	.lastclose = i915_driver_lastclose,
1832 	.postclose = i915_driver_postclose,
1833 
1834 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1835 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1836 	.gem_prime_import = i915_gem_prime_import,
1837 
1838 	.dumb_create = i915_gem_dumb_create,
1839 	.dumb_map_offset = i915_gem_dumb_mmap_offset,
1840 
1841 	.ioctls = i915_ioctls,
1842 	.num_ioctls = ARRAY_SIZE(i915_ioctls),
1843 	.fops = &i915_driver_fops,
1844 	.name = DRIVER_NAME,
1845 	.desc = DRIVER_DESC,
1846 	.date = DRIVER_DATE,
1847 	.major = DRIVER_MAJOR,
1848 	.minor = DRIVER_MINOR,
1849 	.patchlevel = DRIVER_PATCHLEVEL,
1850 };
1851