1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 #include "display/skl_watermark.h" 65 66 #include "gem/i915_gem_context.h" 67 #include "gem/i915_gem_create.h" 68 #include "gem/i915_gem_dmabuf.h" 69 #include "gem/i915_gem_ioctls.h" 70 #include "gem/i915_gem_mman.h" 71 #include "gem/i915_gem_pm.h" 72 #include "gt/intel_gt.h" 73 #include "gt/intel_gt_pm.h" 74 #include "gt/intel_rc6.h" 75 76 #include "pxp/intel_pxp_pm.h" 77 78 #include "i915_file_private.h" 79 #include "i915_debugfs.h" 80 #include "i915_driver.h" 81 #include "i915_drm_client.h" 82 #include "i915_drv.h" 83 #include "i915_getparam.h" 84 #include "i915_ioc32.h" 85 #include "i915_ioctl.h" 86 #include "i915_irq.h" 87 #include "i915_memcpy.h" 88 #include "i915_perf.h" 89 #include "i915_query.h" 90 #include "i915_suspend.h" 91 #include "i915_switcheroo.h" 92 #include "i915_sysfs.h" 93 #include "i915_utils.h" 94 #include "i915_vgpu.h" 95 #include "intel_dram.h" 96 #include "intel_gvt.h" 97 #include "intel_memory_region.h" 98 #include "intel_pci_config.h" 99 #include "intel_pcode.h" 100 #include "intel_pm.h" 101 #include "intel_region_ttm.h" 102 #include "vlv_suspend.h" 103 104 /* Intel Rapid Start Technology ACPI device name */ 105 static const char irst_name[] = "INT3392"; 106 107 static const struct drm_driver i915_drm_driver; 108 109 static void i915_release_bridge_dev(struct drm_device *dev, 110 void *bridge) 111 { 112 pci_dev_put(bridge); 113 } 114 115 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 116 { 117 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 118 119 dev_priv->bridge_dev = 120 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 121 if (!dev_priv->bridge_dev) { 122 drm_err(&dev_priv->drm, "bridge device not found\n"); 123 return -EIO; 124 } 125 126 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev, 127 dev_priv->bridge_dev); 128 } 129 130 /* Allocate space for the MCH regs if needed, return nonzero on error */ 131 static int 132 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 133 { 134 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 135 u32 temp_lo, temp_hi = 0; 136 u64 mchbar_addr; 137 int ret; 138 139 if (GRAPHICS_VER(dev_priv) >= 4) 140 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 141 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 142 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 143 144 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 145 #ifdef CONFIG_PNP 146 if (mchbar_addr && 147 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 148 return 0; 149 #endif 150 151 /* Get some space for it */ 152 dev_priv->mch_res.name = "i915 MCHBAR"; 153 dev_priv->mch_res.flags = IORESOURCE_MEM; 154 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 155 &dev_priv->mch_res, 156 MCHBAR_SIZE, MCHBAR_SIZE, 157 PCIBIOS_MIN_MEM, 158 0, pcibios_align_resource, 159 dev_priv->bridge_dev); 160 if (ret) { 161 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 162 dev_priv->mch_res.start = 0; 163 return ret; 164 } 165 166 if (GRAPHICS_VER(dev_priv) >= 4) 167 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 168 upper_32_bits(dev_priv->mch_res.start)); 169 170 pci_write_config_dword(dev_priv->bridge_dev, reg, 171 lower_32_bits(dev_priv->mch_res.start)); 172 return 0; 173 } 174 175 /* Setup MCHBAR if possible, return true if we should disable it again */ 176 static void 177 intel_setup_mchbar(struct drm_i915_private *dev_priv) 178 { 179 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 180 u32 temp; 181 bool enabled; 182 183 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 184 return; 185 186 dev_priv->mchbar_need_disable = false; 187 188 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 189 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 190 enabled = !!(temp & DEVEN_MCHBAR_EN); 191 } else { 192 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 193 enabled = temp & 1; 194 } 195 196 /* If it's already enabled, don't have to do anything */ 197 if (enabled) 198 return; 199 200 if (intel_alloc_mchbar_resource(dev_priv)) 201 return; 202 203 dev_priv->mchbar_need_disable = true; 204 205 /* Space is allocated or reserved, so enable it. */ 206 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 207 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 208 temp | DEVEN_MCHBAR_EN); 209 } else { 210 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 211 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 212 } 213 } 214 215 static void 216 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 217 { 218 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 219 220 if (dev_priv->mchbar_need_disable) { 221 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 222 u32 deven_val; 223 224 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 225 &deven_val); 226 deven_val &= ~DEVEN_MCHBAR_EN; 227 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 228 deven_val); 229 } else { 230 u32 mchbar_val; 231 232 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 233 &mchbar_val); 234 mchbar_val &= ~1; 235 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 236 mchbar_val); 237 } 238 } 239 240 if (dev_priv->mch_res.start) 241 release_resource(&dev_priv->mch_res); 242 } 243 244 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 245 { 246 /* 247 * The i915 workqueue is primarily used for batched retirement of 248 * requests (and thus managing bo) once the task has been completed 249 * by the GPU. i915_retire_requests() is called directly when we 250 * need high-priority retirement, such as waiting for an explicit 251 * bo. 252 * 253 * It is also used for periodic low-priority events, such as 254 * idle-timers and recording error state. 255 * 256 * All tasks on the workqueue are expected to acquire the dev mutex 257 * so there is no point in running more than one instance of the 258 * workqueue at any time. Use an ordered one. 259 */ 260 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 261 if (dev_priv->wq == NULL) 262 goto out_err; 263 264 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 265 if (dev_priv->display.hotplug.dp_wq == NULL) 266 goto out_free_wq; 267 268 return 0; 269 270 out_free_wq: 271 destroy_workqueue(dev_priv->wq); 272 out_err: 273 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 274 275 return -ENOMEM; 276 } 277 278 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 279 { 280 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 281 destroy_workqueue(dev_priv->wq); 282 } 283 284 /* 285 * We don't keep the workarounds for pre-production hardware, so we expect our 286 * driver to fail on these machines in one way or another. A little warning on 287 * dmesg may help both the user and the bug triagers. 288 * 289 * Our policy for removing pre-production workarounds is to keep the 290 * current gen workarounds as a guide to the bring-up of the next gen 291 * (workarounds have a habit of persisting!). Anything older than that 292 * should be removed along with the complications they introduce. 293 */ 294 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 295 { 296 bool pre = false; 297 298 pre |= IS_HSW_EARLY_SDV(dev_priv); 299 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 300 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 301 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 302 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 303 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 304 305 if (pre) { 306 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 307 "It may not be fully functional.\n"); 308 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 309 } 310 } 311 312 static void sanitize_gpu(struct drm_i915_private *i915) 313 { 314 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 315 struct intel_gt *gt; 316 unsigned int i; 317 318 for_each_gt(gt, i915, i) 319 __intel_gt_reset(gt, ALL_ENGINES); 320 } 321 } 322 323 /** 324 * i915_driver_early_probe - setup state not requiring device access 325 * @dev_priv: device private 326 * 327 * Initialize everything that is a "SW-only" state, that is state not 328 * requiring accessing the device or exposing the driver via kernel internal 329 * or userspace interfaces. Example steps belonging here: lock initialization, 330 * system memory allocation, setting up device specific attributes and 331 * function hooks not requiring accessing the device. 332 */ 333 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 334 { 335 int ret = 0; 336 337 if (i915_inject_probe_failure(dev_priv)) 338 return -ENODEV; 339 340 intel_device_info_subplatform_init(dev_priv); 341 intel_step_init(dev_priv); 342 343 intel_uncore_mmio_debug_init_early(dev_priv); 344 345 spin_lock_init(&dev_priv->irq_lock); 346 spin_lock_init(&dev_priv->gpu_error.lock); 347 mutex_init(&dev_priv->display.backlight.lock); 348 349 mutex_init(&dev_priv->sb_lock); 350 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 351 352 mutex_init(&dev_priv->display.audio.mutex); 353 mutex_init(&dev_priv->display.wm.wm_mutex); 354 mutex_init(&dev_priv->display.pps.mutex); 355 mutex_init(&dev_priv->display.hdcp.comp_mutex); 356 spin_lock_init(&dev_priv->display.dkl.phy_lock); 357 358 i915_memcpy_init_early(dev_priv); 359 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 360 361 ret = i915_workqueues_init(dev_priv); 362 if (ret < 0) 363 return ret; 364 365 ret = vlv_suspend_init(dev_priv); 366 if (ret < 0) 367 goto err_workqueues; 368 369 ret = intel_region_ttm_device_init(dev_priv); 370 if (ret) 371 goto err_ttm; 372 373 intel_wopcm_init_early(&dev_priv->wopcm); 374 375 ret = intel_root_gt_init_early(dev_priv); 376 if (ret < 0) 377 goto err_rootgt; 378 379 i915_drm_clients_init(&dev_priv->clients, dev_priv); 380 381 i915_gem_init_early(dev_priv); 382 383 /* This must be called before any calls to HAS_PCH_* */ 384 intel_detect_pch(dev_priv); 385 386 intel_pm_setup(dev_priv); 387 ret = intel_power_domains_init(dev_priv); 388 if (ret < 0) 389 goto err_gem; 390 intel_irq_init(dev_priv); 391 intel_init_display_hooks(dev_priv); 392 intel_init_clock_gating_hooks(dev_priv); 393 394 intel_detect_preproduction_hw(dev_priv); 395 396 return 0; 397 398 err_gem: 399 i915_gem_cleanup_early(dev_priv); 400 intel_gt_driver_late_release_all(dev_priv); 401 i915_drm_clients_fini(&dev_priv->clients); 402 err_rootgt: 403 intel_region_ttm_device_fini(dev_priv); 404 err_ttm: 405 vlv_suspend_cleanup(dev_priv); 406 err_workqueues: 407 i915_workqueues_cleanup(dev_priv); 408 return ret; 409 } 410 411 /** 412 * i915_driver_late_release - cleanup the setup done in 413 * i915_driver_early_probe() 414 * @dev_priv: device private 415 */ 416 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 417 { 418 intel_irq_fini(dev_priv); 419 intel_power_domains_cleanup(dev_priv); 420 i915_gem_cleanup_early(dev_priv); 421 intel_gt_driver_late_release_all(dev_priv); 422 i915_drm_clients_fini(&dev_priv->clients); 423 intel_region_ttm_device_fini(dev_priv); 424 vlv_suspend_cleanup(dev_priv); 425 i915_workqueues_cleanup(dev_priv); 426 427 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 428 mutex_destroy(&dev_priv->sb_lock); 429 430 i915_params_free(&dev_priv->params); 431 } 432 433 /** 434 * i915_driver_mmio_probe - setup device MMIO 435 * @dev_priv: device private 436 * 437 * Setup minimal device state necessary for MMIO accesses later in the 438 * initialization sequence. The setup here should avoid any other device-wide 439 * side effects or exposing the driver via kernel internal or user space 440 * interfaces. 441 */ 442 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 443 { 444 struct intel_gt *gt; 445 int ret, i; 446 447 if (i915_inject_probe_failure(dev_priv)) 448 return -ENODEV; 449 450 ret = i915_get_bridge_dev(dev_priv); 451 if (ret < 0) 452 return ret; 453 454 for_each_gt(gt, dev_priv, i) { 455 ret = intel_uncore_init_mmio(gt->uncore); 456 if (ret) 457 return ret; 458 459 ret = drmm_add_action_or_reset(&dev_priv->drm, 460 intel_uncore_fini_mmio, 461 gt->uncore); 462 if (ret) 463 return ret; 464 } 465 466 /* Try to make sure MCHBAR is enabled before poking at it */ 467 intel_setup_mchbar(dev_priv); 468 intel_device_info_runtime_init(dev_priv); 469 470 for_each_gt(gt, dev_priv, i) { 471 ret = intel_gt_init_mmio(gt); 472 if (ret) 473 goto err_uncore; 474 } 475 476 /* As early as possible, scrub existing GPU state before clobbering */ 477 sanitize_gpu(dev_priv); 478 479 return 0; 480 481 err_uncore: 482 intel_teardown_mchbar(dev_priv); 483 484 return ret; 485 } 486 487 /** 488 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 489 * @dev_priv: device private 490 */ 491 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 492 { 493 intel_teardown_mchbar(dev_priv); 494 } 495 496 /** 497 * i915_set_dma_info - set all relevant PCI dma info as configured for the 498 * platform 499 * @i915: valid i915 instance 500 * 501 * Set the dma max segment size, device and coherent masks. The dma mask set 502 * needs to occur before i915_ggtt_probe_hw. 503 * 504 * A couple of platforms have special needs. Address them as well. 505 * 506 */ 507 static int i915_set_dma_info(struct drm_i915_private *i915) 508 { 509 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 510 int ret; 511 512 GEM_BUG_ON(!mask_size); 513 514 /* 515 * We don't have a max segment size, so set it to the max so sg's 516 * debugging layer doesn't complain 517 */ 518 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 519 520 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 521 if (ret) 522 goto mask_err; 523 524 /* overlay on gen2 is broken and can't address above 1G */ 525 if (GRAPHICS_VER(i915) == 2) 526 mask_size = 30; 527 528 /* 529 * 965GM sometimes incorrectly writes to hardware status page (HWS) 530 * using 32bit addressing, overwriting memory if HWS is located 531 * above 4GB. 532 * 533 * The documentation also mentions an issue with undefined 534 * behaviour if any general state is accessed within a page above 4GB, 535 * which also needs to be handled carefully. 536 */ 537 if (IS_I965G(i915) || IS_I965GM(i915)) 538 mask_size = 32; 539 540 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 541 if (ret) 542 goto mask_err; 543 544 return 0; 545 546 mask_err: 547 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 548 return ret; 549 } 550 551 static int i915_pcode_init(struct drm_i915_private *i915) 552 { 553 struct intel_gt *gt; 554 int id, ret; 555 556 for_each_gt(gt, i915, id) { 557 ret = intel_pcode_init(gt->uncore); 558 if (ret) { 559 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 560 return ret; 561 } 562 } 563 564 return 0; 565 } 566 567 /** 568 * i915_driver_hw_probe - setup state requiring device access 569 * @dev_priv: device private 570 * 571 * Setup state that requires accessing the device, but doesn't require 572 * exposing the driver via kernel internal or userspace interfaces. 573 */ 574 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 575 { 576 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 577 struct pci_dev *root_pdev; 578 int ret; 579 580 if (i915_inject_probe_failure(dev_priv)) 581 return -ENODEV; 582 583 if (HAS_PPGTT(dev_priv)) { 584 if (intel_vgpu_active(dev_priv) && 585 !intel_vgpu_has_full_ppgtt(dev_priv)) { 586 i915_report_error(dev_priv, 587 "incompatible vGPU found, support for isolated ppGTT required\n"); 588 return -ENXIO; 589 } 590 } 591 592 if (HAS_EXECLISTS(dev_priv)) { 593 /* 594 * Older GVT emulation depends upon intercepting CSB mmio, 595 * which we no longer use, preferring to use the HWSP cache 596 * instead. 597 */ 598 if (intel_vgpu_active(dev_priv) && 599 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 600 i915_report_error(dev_priv, 601 "old vGPU host found, support for HWSP emulation required\n"); 602 return -ENXIO; 603 } 604 } 605 606 /* needs to be done before ggtt probe */ 607 intel_dram_edram_detect(dev_priv); 608 609 ret = i915_set_dma_info(dev_priv); 610 if (ret) 611 return ret; 612 613 i915_perf_init(dev_priv); 614 615 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 616 if (ret) 617 goto err_perf; 618 619 ret = i915_ggtt_probe_hw(dev_priv); 620 if (ret) 621 goto err_perf; 622 623 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 624 if (ret) 625 goto err_ggtt; 626 627 ret = i915_ggtt_init_hw(dev_priv); 628 if (ret) 629 goto err_ggtt; 630 631 ret = intel_memory_regions_hw_probe(dev_priv); 632 if (ret) 633 goto err_ggtt; 634 635 ret = intel_gt_tiles_init(dev_priv); 636 if (ret) 637 goto err_mem_regions; 638 639 ret = i915_ggtt_enable_hw(dev_priv); 640 if (ret) { 641 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 642 goto err_mem_regions; 643 } 644 645 pci_set_master(pdev); 646 647 /* On the 945G/GM, the chipset reports the MSI capability on the 648 * integrated graphics even though the support isn't actually there 649 * according to the published specs. It doesn't appear to function 650 * correctly in testing on 945G. 651 * This may be a side effect of MSI having been made available for PEG 652 * and the registers being closely associated. 653 * 654 * According to chipset errata, on the 965GM, MSI interrupts may 655 * be lost or delayed, and was defeatured. MSI interrupts seem to 656 * get lost on g4x as well, and interrupt delivery seems to stay 657 * properly dead afterwards. So we'll just disable them for all 658 * pre-gen5 chipsets. 659 * 660 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 661 * interrupts even when in MSI mode. This results in spurious 662 * interrupt warnings if the legacy irq no. is shared with another 663 * device. The kernel then disables that interrupt source and so 664 * prevents the other device from working properly. 665 */ 666 if (GRAPHICS_VER(dev_priv) >= 5) { 667 if (pci_enable_msi(pdev) < 0) 668 drm_dbg(&dev_priv->drm, "can't enable MSI"); 669 } 670 671 ret = intel_gvt_init(dev_priv); 672 if (ret) 673 goto err_msi; 674 675 intel_opregion_setup(dev_priv); 676 677 ret = i915_pcode_init(dev_priv); 678 if (ret) 679 goto err_msi; 680 681 /* 682 * Fill the dram structure to get the system dram info. This will be 683 * used for memory latency calculation. 684 */ 685 intel_dram_detect(dev_priv); 686 687 intel_bw_init_hw(dev_priv); 688 689 /* 690 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 691 * This should be totally removed when we handle the pci states properly 692 * on runtime PM and on s2idle cases. 693 */ 694 root_pdev = pcie_find_root_port(pdev); 695 if (root_pdev) 696 pci_d3cold_disable(root_pdev); 697 698 return 0; 699 700 err_msi: 701 if (pdev->msi_enabled) 702 pci_disable_msi(pdev); 703 err_mem_regions: 704 intel_memory_regions_driver_release(dev_priv); 705 err_ggtt: 706 i915_ggtt_driver_release(dev_priv); 707 i915_gem_drain_freed_objects(dev_priv); 708 i915_ggtt_driver_late_release(dev_priv); 709 err_perf: 710 i915_perf_fini(dev_priv); 711 return ret; 712 } 713 714 /** 715 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 716 * @dev_priv: device private 717 */ 718 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 719 { 720 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 721 struct pci_dev *root_pdev; 722 723 i915_perf_fini(dev_priv); 724 725 if (pdev->msi_enabled) 726 pci_disable_msi(pdev); 727 728 root_pdev = pcie_find_root_port(pdev); 729 if (root_pdev) 730 pci_d3cold_enable(root_pdev); 731 } 732 733 /** 734 * i915_driver_register - register the driver with the rest of the system 735 * @dev_priv: device private 736 * 737 * Perform any steps necessary to make the driver available via kernel 738 * internal or userspace interfaces. 739 */ 740 static void i915_driver_register(struct drm_i915_private *dev_priv) 741 { 742 struct drm_device *dev = &dev_priv->drm; 743 struct intel_gt *gt; 744 unsigned int i; 745 746 i915_gem_driver_register(dev_priv); 747 i915_pmu_register(dev_priv); 748 749 intel_vgpu_register(dev_priv); 750 751 /* Reveal our presence to userspace */ 752 if (drm_dev_register(dev, 0)) { 753 drm_err(&dev_priv->drm, 754 "Failed to register driver for userspace access!\n"); 755 return; 756 } 757 758 i915_debugfs_register(dev_priv); 759 i915_setup_sysfs(dev_priv); 760 761 /* Depends on sysfs having been initialized */ 762 i915_perf_register(dev_priv); 763 764 for_each_gt(gt, dev_priv, i) 765 intel_gt_driver_register(gt); 766 767 intel_display_driver_register(dev_priv); 768 769 intel_power_domains_enable(dev_priv); 770 intel_runtime_pm_enable(&dev_priv->runtime_pm); 771 772 intel_register_dsm_handler(); 773 774 if (i915_switcheroo_register(dev_priv)) 775 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 776 } 777 778 /** 779 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 780 * @dev_priv: device private 781 */ 782 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 783 { 784 struct intel_gt *gt; 785 unsigned int i; 786 787 i915_switcheroo_unregister(dev_priv); 788 789 intel_unregister_dsm_handler(); 790 791 intel_runtime_pm_disable(&dev_priv->runtime_pm); 792 intel_power_domains_disable(dev_priv); 793 794 intel_display_driver_unregister(dev_priv); 795 796 for_each_gt(gt, dev_priv, i) 797 intel_gt_driver_unregister(gt); 798 799 i915_perf_unregister(dev_priv); 800 i915_pmu_unregister(dev_priv); 801 802 i915_teardown_sysfs(dev_priv); 803 drm_dev_unplug(&dev_priv->drm); 804 805 i915_gem_driver_unregister(dev_priv); 806 } 807 808 void 809 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 810 { 811 drm_printf(p, "iommu: %s\n", 812 str_enabled_disabled(i915_vtd_active(i915))); 813 } 814 815 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 816 { 817 if (drm_debug_enabled(DRM_UT_DRIVER)) { 818 struct drm_printer p = drm_debug_printer("i915 device info:"); 819 struct intel_gt *gt; 820 unsigned int i; 821 822 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 823 INTEL_DEVID(dev_priv), 824 INTEL_REVID(dev_priv), 825 intel_platform_name(INTEL_INFO(dev_priv)->platform), 826 intel_subplatform(RUNTIME_INFO(dev_priv), 827 INTEL_INFO(dev_priv)->platform), 828 GRAPHICS_VER(dev_priv)); 829 830 intel_device_info_print(INTEL_INFO(dev_priv), 831 RUNTIME_INFO(dev_priv), &p); 832 i915_print_iommu_status(dev_priv, &p); 833 for_each_gt(gt, dev_priv, i) 834 intel_gt_info_print(>->info, &p); 835 } 836 837 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 838 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 839 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 840 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 841 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 842 drm_info(&dev_priv->drm, 843 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 844 } 845 846 static struct drm_i915_private * 847 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 848 { 849 const struct intel_device_info *match_info = 850 (struct intel_device_info *)ent->driver_data; 851 struct intel_device_info *device_info; 852 struct intel_runtime_info *runtime; 853 struct drm_i915_private *i915; 854 855 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 856 struct drm_i915_private, drm); 857 if (IS_ERR(i915)) 858 return i915; 859 860 pci_set_drvdata(pdev, i915); 861 862 /* Device parameters start as a copy of module parameters. */ 863 i915_params_copy(&i915->params, &i915_modparams); 864 865 /* Setup the write-once "constant" device info */ 866 device_info = mkwrite_device_info(i915); 867 memcpy(device_info, match_info, sizeof(*device_info)); 868 869 /* Initialize initial runtime info from static const data and pdev. */ 870 runtime = RUNTIME_INFO(i915); 871 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 872 runtime->device_id = pdev->device; 873 874 return i915; 875 } 876 877 /** 878 * i915_driver_probe - setup chip and create an initial config 879 * @pdev: PCI device 880 * @ent: matching PCI ID entry 881 * 882 * The driver probe routine has to do several things: 883 * - drive output discovery via intel_modeset_init() 884 * - initialize the memory manager 885 * - allocate initial config memory 886 * - setup the DRM framebuffer with the allocated memory 887 */ 888 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 889 { 890 struct drm_i915_private *i915; 891 int ret; 892 893 i915 = i915_driver_create(pdev, ent); 894 if (IS_ERR(i915)) 895 return PTR_ERR(i915); 896 897 /* Disable nuclear pageflip by default on pre-ILK */ 898 if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5) 899 i915->drm.driver_features &= ~DRIVER_ATOMIC; 900 901 ret = pci_enable_device(pdev); 902 if (ret) 903 goto out_fini; 904 905 ret = i915_driver_early_probe(i915); 906 if (ret < 0) 907 goto out_pci_disable; 908 909 disable_rpm_wakeref_asserts(&i915->runtime_pm); 910 911 intel_vgpu_detect(i915); 912 913 ret = intel_gt_probe_all(i915); 914 if (ret < 0) 915 goto out_runtime_pm_put; 916 917 ret = i915_driver_mmio_probe(i915); 918 if (ret < 0) 919 goto out_tiles_cleanup; 920 921 ret = i915_driver_hw_probe(i915); 922 if (ret < 0) 923 goto out_cleanup_mmio; 924 925 ret = intel_modeset_init_noirq(i915); 926 if (ret < 0) 927 goto out_cleanup_hw; 928 929 ret = intel_irq_install(i915); 930 if (ret) 931 goto out_cleanup_modeset; 932 933 ret = intel_modeset_init_nogem(i915); 934 if (ret) 935 goto out_cleanup_irq; 936 937 ret = i915_gem_init(i915); 938 if (ret) 939 goto out_cleanup_modeset2; 940 941 ret = intel_modeset_init(i915); 942 if (ret) 943 goto out_cleanup_gem; 944 945 i915_driver_register(i915); 946 947 enable_rpm_wakeref_asserts(&i915->runtime_pm); 948 949 i915_welcome_messages(i915); 950 951 i915->do_release = true; 952 953 return 0; 954 955 out_cleanup_gem: 956 i915_gem_suspend(i915); 957 i915_gem_driver_remove(i915); 958 i915_gem_driver_release(i915); 959 out_cleanup_modeset2: 960 /* FIXME clean up the error path */ 961 intel_modeset_driver_remove(i915); 962 intel_irq_uninstall(i915); 963 intel_modeset_driver_remove_noirq(i915); 964 goto out_cleanup_modeset; 965 out_cleanup_irq: 966 intel_irq_uninstall(i915); 967 out_cleanup_modeset: 968 intel_modeset_driver_remove_nogem(i915); 969 out_cleanup_hw: 970 i915_driver_hw_remove(i915); 971 intel_memory_regions_driver_release(i915); 972 i915_ggtt_driver_release(i915); 973 i915_gem_drain_freed_objects(i915); 974 i915_ggtt_driver_late_release(i915); 975 out_cleanup_mmio: 976 i915_driver_mmio_release(i915); 977 out_tiles_cleanup: 978 intel_gt_release_all(i915); 979 out_runtime_pm_put: 980 enable_rpm_wakeref_asserts(&i915->runtime_pm); 981 i915_driver_late_release(i915); 982 out_pci_disable: 983 pci_disable_device(pdev); 984 out_fini: 985 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 986 return ret; 987 } 988 989 void i915_driver_remove(struct drm_i915_private *i915) 990 { 991 intel_wakeref_t wakeref; 992 993 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 994 995 i915_driver_unregister(i915); 996 997 /* Flush any external code that still may be under the RCU lock */ 998 synchronize_rcu(); 999 1000 i915_gem_suspend(i915); 1001 1002 intel_gvt_driver_remove(i915); 1003 1004 intel_modeset_driver_remove(i915); 1005 1006 intel_irq_uninstall(i915); 1007 1008 intel_modeset_driver_remove_noirq(i915); 1009 1010 i915_reset_error_state(i915); 1011 i915_gem_driver_remove(i915); 1012 1013 intel_modeset_driver_remove_nogem(i915); 1014 1015 i915_driver_hw_remove(i915); 1016 1017 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1018 } 1019 1020 static void i915_driver_release(struct drm_device *dev) 1021 { 1022 struct drm_i915_private *dev_priv = to_i915(dev); 1023 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1024 intel_wakeref_t wakeref; 1025 1026 if (!dev_priv->do_release) 1027 return; 1028 1029 wakeref = intel_runtime_pm_get(rpm); 1030 1031 i915_gem_driver_release(dev_priv); 1032 1033 intel_memory_regions_driver_release(dev_priv); 1034 i915_ggtt_driver_release(dev_priv); 1035 i915_gem_drain_freed_objects(dev_priv); 1036 i915_ggtt_driver_late_release(dev_priv); 1037 1038 i915_driver_mmio_release(dev_priv); 1039 1040 intel_runtime_pm_put(rpm, wakeref); 1041 1042 intel_runtime_pm_driver_release(rpm); 1043 1044 i915_driver_late_release(dev_priv); 1045 } 1046 1047 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1048 { 1049 struct drm_i915_private *i915 = to_i915(dev); 1050 int ret; 1051 1052 ret = i915_gem_open(i915, file); 1053 if (ret) 1054 return ret; 1055 1056 return 0; 1057 } 1058 1059 /** 1060 * i915_driver_lastclose - clean up after all DRM clients have exited 1061 * @dev: DRM device 1062 * 1063 * Take care of cleaning up after all DRM clients have exited. In the 1064 * mode setting case, we want to restore the kernel's initial mode (just 1065 * in case the last client left us in a bad state). 1066 * 1067 * Additionally, in the non-mode setting case, we'll tear down the GTT 1068 * and DMA structures, since the kernel won't be using them, and clea 1069 * up any GEM state. 1070 */ 1071 static void i915_driver_lastclose(struct drm_device *dev) 1072 { 1073 struct drm_i915_private *i915 = to_i915(dev); 1074 1075 intel_fbdev_restore_mode(dev); 1076 1077 if (HAS_DISPLAY(i915)) 1078 vga_switcheroo_process_delayed_switch(); 1079 } 1080 1081 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1082 { 1083 struct drm_i915_file_private *file_priv = file->driver_priv; 1084 1085 i915_gem_context_close(file); 1086 i915_drm_client_put(file_priv->client); 1087 1088 kfree_rcu(file_priv, rcu); 1089 1090 /* Catch up with all the deferred frees from "this" client */ 1091 i915_gem_flush_free_objects(to_i915(dev)); 1092 } 1093 1094 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1095 { 1096 struct drm_device *dev = &dev_priv->drm; 1097 struct intel_encoder *encoder; 1098 1099 if (!HAS_DISPLAY(dev_priv)) 1100 return; 1101 1102 drm_modeset_lock_all(dev); 1103 for_each_intel_encoder(dev, encoder) 1104 if (encoder->suspend) 1105 encoder->suspend(encoder); 1106 drm_modeset_unlock_all(dev); 1107 } 1108 1109 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1110 { 1111 struct drm_device *dev = &dev_priv->drm; 1112 struct intel_encoder *encoder; 1113 1114 if (!HAS_DISPLAY(dev_priv)) 1115 return; 1116 1117 drm_modeset_lock_all(dev); 1118 for_each_intel_encoder(dev, encoder) 1119 if (encoder->shutdown) 1120 encoder->shutdown(encoder); 1121 drm_modeset_unlock_all(dev); 1122 } 1123 1124 void i915_driver_shutdown(struct drm_i915_private *i915) 1125 { 1126 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1127 intel_runtime_pm_disable(&i915->runtime_pm); 1128 intel_power_domains_disable(i915); 1129 1130 if (HAS_DISPLAY(i915)) { 1131 drm_kms_helper_poll_disable(&i915->drm); 1132 1133 drm_atomic_helper_shutdown(&i915->drm); 1134 } 1135 1136 intel_dp_mst_suspend(i915); 1137 1138 intel_runtime_pm_disable_interrupts(i915); 1139 intel_hpd_cancel_work(i915); 1140 1141 intel_suspend_encoders(i915); 1142 intel_shutdown_encoders(i915); 1143 1144 intel_dmc_ucode_suspend(i915); 1145 1146 i915_gem_suspend(i915); 1147 1148 /* 1149 * The only requirement is to reboot with display DC states disabled, 1150 * for now leaving all display power wells in the INIT power domain 1151 * enabled. 1152 * 1153 * TODO: 1154 * - unify the pci_driver::shutdown sequence here with the 1155 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1156 * - unify the driver remove and system/runtime suspend sequences with 1157 * the above unified shutdown/poweroff sequence. 1158 */ 1159 intel_power_domains_driver_remove(i915); 1160 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1161 1162 intel_runtime_pm_driver_release(&i915->runtime_pm); 1163 } 1164 1165 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1166 { 1167 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1168 if (acpi_target_system_state() < ACPI_STATE_S3) 1169 return true; 1170 #endif 1171 return false; 1172 } 1173 1174 static int i915_drm_prepare(struct drm_device *dev) 1175 { 1176 struct drm_i915_private *i915 = to_i915(dev); 1177 1178 /* 1179 * NB intel_display_suspend() may issue new requests after we've 1180 * ostensibly marked the GPU as ready-to-sleep here. We need to 1181 * split out that work and pull it forward so that after point, 1182 * the GPU is not woken again. 1183 */ 1184 return i915_gem_backup_suspend(i915); 1185 } 1186 1187 static int i915_drm_suspend(struct drm_device *dev) 1188 { 1189 struct drm_i915_private *dev_priv = to_i915(dev); 1190 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1191 pci_power_t opregion_target_state; 1192 1193 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1194 1195 /* We do a lot of poking in a lot of registers, make sure they work 1196 * properly. */ 1197 intel_power_domains_disable(dev_priv); 1198 if (HAS_DISPLAY(dev_priv)) 1199 drm_kms_helper_poll_disable(dev); 1200 1201 pci_save_state(pdev); 1202 1203 intel_display_suspend(dev); 1204 1205 intel_dp_mst_suspend(dev_priv); 1206 1207 intel_runtime_pm_disable_interrupts(dev_priv); 1208 intel_hpd_cancel_work(dev_priv); 1209 1210 intel_suspend_encoders(dev_priv); 1211 1212 intel_suspend_hw(dev_priv); 1213 1214 /* Must be called before GGTT is suspended. */ 1215 intel_dpt_suspend(dev_priv); 1216 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1217 1218 i915_save_display(dev_priv); 1219 1220 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1221 intel_opregion_suspend(dev_priv, opregion_target_state); 1222 1223 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1224 1225 dev_priv->suspend_count++; 1226 1227 intel_dmc_ucode_suspend(dev_priv); 1228 1229 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1230 1231 i915_gem_drain_freed_objects(dev_priv); 1232 1233 return 0; 1234 } 1235 1236 static enum i915_drm_suspend_mode 1237 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1238 { 1239 if (hibernate) 1240 return I915_DRM_SUSPEND_HIBERNATE; 1241 1242 if (suspend_to_idle(dev_priv)) 1243 return I915_DRM_SUSPEND_IDLE; 1244 1245 return I915_DRM_SUSPEND_MEM; 1246 } 1247 1248 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1249 { 1250 struct drm_i915_private *dev_priv = to_i915(dev); 1251 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1252 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1253 struct intel_gt *gt; 1254 int ret, i; 1255 1256 disable_rpm_wakeref_asserts(rpm); 1257 1258 i915_gem_suspend_late(dev_priv); 1259 1260 for_each_gt(gt, dev_priv, i) 1261 intel_uncore_suspend(gt->uncore); 1262 1263 intel_power_domains_suspend(dev_priv, 1264 get_suspend_mode(dev_priv, hibernation)); 1265 1266 intel_display_power_suspend_late(dev_priv); 1267 1268 ret = vlv_suspend_complete(dev_priv); 1269 if (ret) { 1270 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1271 intel_power_domains_resume(dev_priv); 1272 1273 goto out; 1274 } 1275 1276 pci_disable_device(pdev); 1277 /* 1278 * During hibernation on some platforms the BIOS may try to access 1279 * the device even though it's already in D3 and hang the machine. So 1280 * leave the device in D0 on those platforms and hope the BIOS will 1281 * power down the device properly. The issue was seen on multiple old 1282 * GENs with different BIOS vendors, so having an explicit blacklist 1283 * is inpractical; apply the workaround on everything pre GEN6. The 1284 * platforms where the issue was seen: 1285 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1286 * Fujitsu FSC S7110 1287 * Acer Aspire 1830T 1288 */ 1289 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1290 pci_set_power_state(pdev, PCI_D3hot); 1291 1292 out: 1293 enable_rpm_wakeref_asserts(rpm); 1294 if (!dev_priv->uncore.user_forcewake_count) 1295 intel_runtime_pm_driver_release(rpm); 1296 1297 return ret; 1298 } 1299 1300 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1301 pm_message_t state) 1302 { 1303 int error; 1304 1305 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1306 state.event != PM_EVENT_FREEZE)) 1307 return -EINVAL; 1308 1309 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1310 return 0; 1311 1312 error = i915_drm_suspend(&i915->drm); 1313 if (error) 1314 return error; 1315 1316 return i915_drm_suspend_late(&i915->drm, false); 1317 } 1318 1319 static int i915_drm_resume(struct drm_device *dev) 1320 { 1321 struct drm_i915_private *dev_priv = to_i915(dev); 1322 int ret; 1323 1324 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1325 1326 ret = i915_pcode_init(dev_priv); 1327 if (ret) 1328 return ret; 1329 1330 sanitize_gpu(dev_priv); 1331 1332 ret = i915_ggtt_enable_hw(dev_priv); 1333 if (ret) 1334 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1335 1336 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1337 /* Must be called after GGTT is resumed. */ 1338 intel_dpt_resume(dev_priv); 1339 1340 intel_dmc_ucode_resume(dev_priv); 1341 1342 i915_restore_display(dev_priv); 1343 intel_pps_unlock_regs_wa(dev_priv); 1344 1345 intel_init_pch_refclk(dev_priv); 1346 1347 /* 1348 * Interrupts have to be enabled before any batches are run. If not the 1349 * GPU will hang. i915_gem_init_hw() will initiate batches to 1350 * update/restore the context. 1351 * 1352 * drm_mode_config_reset() needs AUX interrupts. 1353 * 1354 * Modeset enabling in intel_modeset_init_hw() also needs working 1355 * interrupts. 1356 */ 1357 intel_runtime_pm_enable_interrupts(dev_priv); 1358 1359 if (HAS_DISPLAY(dev_priv)) 1360 drm_mode_config_reset(dev); 1361 1362 i915_gem_resume(dev_priv); 1363 1364 intel_modeset_init_hw(dev_priv); 1365 intel_init_clock_gating(dev_priv); 1366 intel_hpd_init(dev_priv); 1367 1368 /* MST sideband requires HPD interrupts enabled */ 1369 intel_dp_mst_resume(dev_priv); 1370 intel_display_resume(dev); 1371 1372 intel_hpd_poll_disable(dev_priv); 1373 if (HAS_DISPLAY(dev_priv)) 1374 drm_kms_helper_poll_enable(dev); 1375 1376 intel_opregion_resume(dev_priv); 1377 1378 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1379 1380 intel_power_domains_enable(dev_priv); 1381 1382 intel_gvt_resume(dev_priv); 1383 1384 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1385 1386 return 0; 1387 } 1388 1389 static int i915_drm_resume_early(struct drm_device *dev) 1390 { 1391 struct drm_i915_private *dev_priv = to_i915(dev); 1392 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1393 struct intel_gt *gt; 1394 int ret, i; 1395 1396 /* 1397 * We have a resume ordering issue with the snd-hda driver also 1398 * requiring our device to be power up. Due to the lack of a 1399 * parent/child relationship we currently solve this with an early 1400 * resume hook. 1401 * 1402 * FIXME: This should be solved with a special hdmi sink device or 1403 * similar so that power domains can be employed. 1404 */ 1405 1406 /* 1407 * Note that we need to set the power state explicitly, since we 1408 * powered off the device during freeze and the PCI core won't power 1409 * it back up for us during thaw. Powering off the device during 1410 * freeze is not a hard requirement though, and during the 1411 * suspend/resume phases the PCI core makes sure we get here with the 1412 * device powered on. So in case we change our freeze logic and keep 1413 * the device powered we can also remove the following set power state 1414 * call. 1415 */ 1416 ret = pci_set_power_state(pdev, PCI_D0); 1417 if (ret) { 1418 drm_err(&dev_priv->drm, 1419 "failed to set PCI D0 power state (%d)\n", ret); 1420 return ret; 1421 } 1422 1423 /* 1424 * Note that pci_enable_device() first enables any parent bridge 1425 * device and only then sets the power state for this device. The 1426 * bridge enabling is a nop though, since bridge devices are resumed 1427 * first. The order of enabling power and enabling the device is 1428 * imposed by the PCI core as described above, so here we preserve the 1429 * same order for the freeze/thaw phases. 1430 * 1431 * TODO: eventually we should remove pci_disable_device() / 1432 * pci_enable_enable_device() from suspend/resume. Due to how they 1433 * depend on the device enable refcount we can't anyway depend on them 1434 * disabling/enabling the device. 1435 */ 1436 if (pci_enable_device(pdev)) 1437 return -EIO; 1438 1439 pci_set_master(pdev); 1440 1441 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1442 1443 ret = vlv_resume_prepare(dev_priv, false); 1444 if (ret) 1445 drm_err(&dev_priv->drm, 1446 "Resume prepare failed: %d, continuing anyway\n", ret); 1447 1448 for_each_gt(gt, dev_priv, i) { 1449 intel_uncore_resume_early(gt->uncore); 1450 intel_gt_check_and_clear_faults(gt); 1451 } 1452 1453 intel_display_power_resume_early(dev_priv); 1454 1455 intel_power_domains_resume(dev_priv); 1456 1457 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1458 1459 return ret; 1460 } 1461 1462 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1463 { 1464 int ret; 1465 1466 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1467 return 0; 1468 1469 ret = i915_drm_resume_early(&i915->drm); 1470 if (ret) 1471 return ret; 1472 1473 return i915_drm_resume(&i915->drm); 1474 } 1475 1476 static int i915_pm_prepare(struct device *kdev) 1477 { 1478 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1479 1480 if (!i915) { 1481 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1482 return -ENODEV; 1483 } 1484 1485 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1486 return 0; 1487 1488 return i915_drm_prepare(&i915->drm); 1489 } 1490 1491 static int i915_pm_suspend(struct device *kdev) 1492 { 1493 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1494 1495 if (!i915) { 1496 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1497 return -ENODEV; 1498 } 1499 1500 i915_ggtt_mark_pte_lost(i915, false); 1501 1502 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1503 return 0; 1504 1505 return i915_drm_suspend(&i915->drm); 1506 } 1507 1508 static int i915_pm_suspend_late(struct device *kdev) 1509 { 1510 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1511 1512 /* 1513 * We have a suspend ordering issue with the snd-hda driver also 1514 * requiring our device to be power up. Due to the lack of a 1515 * parent/child relationship we currently solve this with an late 1516 * suspend hook. 1517 * 1518 * FIXME: This should be solved with a special hdmi sink device or 1519 * similar so that power domains can be employed. 1520 */ 1521 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1522 return 0; 1523 1524 return i915_drm_suspend_late(&i915->drm, false); 1525 } 1526 1527 static int i915_pm_poweroff_late(struct device *kdev) 1528 { 1529 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1530 1531 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1532 return 0; 1533 1534 return i915_drm_suspend_late(&i915->drm, true); 1535 } 1536 1537 static int i915_pm_resume_early(struct device *kdev) 1538 { 1539 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1540 1541 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1542 return 0; 1543 1544 return i915_drm_resume_early(&i915->drm); 1545 } 1546 1547 static int i915_pm_resume(struct device *kdev) 1548 { 1549 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1550 1551 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1552 return 0; 1553 1554 /* 1555 * If IRST is enabled, or if we can't detect whether it's enabled, 1556 * then we must assume we lost the GGTT page table entries, since 1557 * they are not retained if IRST decided to enter S4. 1558 */ 1559 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1)) 1560 i915_ggtt_mark_pte_lost(i915, true); 1561 1562 return i915_drm_resume(&i915->drm); 1563 } 1564 1565 /* freeze: before creating the hibernation_image */ 1566 static int i915_pm_freeze(struct device *kdev) 1567 { 1568 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1569 int ret; 1570 1571 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1572 ret = i915_drm_suspend(&i915->drm); 1573 if (ret) 1574 return ret; 1575 } 1576 1577 ret = i915_gem_freeze(i915); 1578 if (ret) 1579 return ret; 1580 1581 return 0; 1582 } 1583 1584 static int i915_pm_freeze_late(struct device *kdev) 1585 { 1586 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1587 int ret; 1588 1589 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1590 ret = i915_drm_suspend_late(&i915->drm, true); 1591 if (ret) 1592 return ret; 1593 } 1594 1595 ret = i915_gem_freeze_late(i915); 1596 if (ret) 1597 return ret; 1598 1599 return 0; 1600 } 1601 1602 /* thaw: called after creating the hibernation image, but before turning off. */ 1603 static int i915_pm_thaw_early(struct device *kdev) 1604 { 1605 return i915_pm_resume_early(kdev); 1606 } 1607 1608 static int i915_pm_thaw(struct device *kdev) 1609 { 1610 return i915_pm_resume(kdev); 1611 } 1612 1613 /* restore: called after loading the hibernation image. */ 1614 static int i915_pm_restore_early(struct device *kdev) 1615 { 1616 return i915_pm_resume_early(kdev); 1617 } 1618 1619 static int i915_pm_restore(struct device *kdev) 1620 { 1621 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1622 1623 i915_ggtt_mark_pte_lost(i915, true); 1624 return i915_pm_resume(kdev); 1625 } 1626 1627 static int intel_runtime_suspend(struct device *kdev) 1628 { 1629 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1630 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1631 struct intel_gt *gt; 1632 int ret, i; 1633 1634 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1635 return -ENODEV; 1636 1637 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1638 1639 disable_rpm_wakeref_asserts(rpm); 1640 1641 /* 1642 * We are safe here against re-faults, since the fault handler takes 1643 * an RPM reference. 1644 */ 1645 i915_gem_runtime_suspend(dev_priv); 1646 1647 for_each_gt(gt, dev_priv, i) 1648 intel_gt_runtime_suspend(gt); 1649 1650 intel_runtime_pm_disable_interrupts(dev_priv); 1651 1652 for_each_gt(gt, dev_priv, i) 1653 intel_uncore_suspend(gt->uncore); 1654 1655 intel_display_power_suspend(dev_priv); 1656 1657 ret = vlv_suspend_complete(dev_priv); 1658 if (ret) { 1659 drm_err(&dev_priv->drm, 1660 "Runtime suspend failed, disabling it (%d)\n", ret); 1661 intel_uncore_runtime_resume(&dev_priv->uncore); 1662 1663 intel_runtime_pm_enable_interrupts(dev_priv); 1664 1665 intel_gt_runtime_resume(to_gt(dev_priv)); 1666 1667 enable_rpm_wakeref_asserts(rpm); 1668 1669 return ret; 1670 } 1671 1672 enable_rpm_wakeref_asserts(rpm); 1673 intel_runtime_pm_driver_release(rpm); 1674 1675 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1676 drm_err(&dev_priv->drm, 1677 "Unclaimed access detected prior to suspending\n"); 1678 1679 rpm->suspended = true; 1680 1681 /* 1682 * FIXME: We really should find a document that references the arguments 1683 * used below! 1684 */ 1685 if (IS_BROADWELL(dev_priv)) { 1686 /* 1687 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1688 * being detected, and the call we do at intel_runtime_resume() 1689 * won't be able to restore them. Since PCI_D3hot matches the 1690 * actual specification and appears to be working, use it. 1691 */ 1692 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1693 } else { 1694 /* 1695 * current versions of firmware which depend on this opregion 1696 * notification have repurposed the D1 definition to mean 1697 * "runtime suspended" vs. what you would normally expect (D3) 1698 * to distinguish it from notifications that might be sent via 1699 * the suspend path. 1700 */ 1701 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1702 } 1703 1704 assert_forcewakes_inactive(&dev_priv->uncore); 1705 1706 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1707 intel_hpd_poll_enable(dev_priv); 1708 1709 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1710 return 0; 1711 } 1712 1713 static int intel_runtime_resume(struct device *kdev) 1714 { 1715 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1716 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1717 struct intel_gt *gt; 1718 int ret, i; 1719 1720 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1721 return -ENODEV; 1722 1723 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1724 1725 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1726 disable_rpm_wakeref_asserts(rpm); 1727 1728 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1729 rpm->suspended = false; 1730 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1731 drm_dbg(&dev_priv->drm, 1732 "Unclaimed access during suspend, bios?\n"); 1733 1734 intel_display_power_resume(dev_priv); 1735 1736 ret = vlv_resume_prepare(dev_priv, true); 1737 1738 for_each_gt(gt, dev_priv, i) 1739 intel_uncore_runtime_resume(gt->uncore); 1740 1741 intel_runtime_pm_enable_interrupts(dev_priv); 1742 1743 /* 1744 * No point of rolling back things in case of an error, as the best 1745 * we can do is to hope that things will still work (and disable RPM). 1746 */ 1747 for_each_gt(gt, dev_priv, i) 1748 intel_gt_runtime_resume(gt); 1749 1750 /* 1751 * On VLV/CHV display interrupts are part of the display 1752 * power well, so hpd is reinitialized from there. For 1753 * everyone else do it here. 1754 */ 1755 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1756 intel_hpd_init(dev_priv); 1757 intel_hpd_poll_disable(dev_priv); 1758 } 1759 1760 skl_watermark_ipc_update(dev_priv); 1761 1762 enable_rpm_wakeref_asserts(rpm); 1763 1764 if (ret) 1765 drm_err(&dev_priv->drm, 1766 "Runtime resume failed, disabling it (%d)\n", ret); 1767 else 1768 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1769 1770 return ret; 1771 } 1772 1773 const struct dev_pm_ops i915_pm_ops = { 1774 /* 1775 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1776 * PMSG_RESUME] 1777 */ 1778 .prepare = i915_pm_prepare, 1779 .suspend = i915_pm_suspend, 1780 .suspend_late = i915_pm_suspend_late, 1781 .resume_early = i915_pm_resume_early, 1782 .resume = i915_pm_resume, 1783 1784 /* 1785 * S4 event handlers 1786 * @freeze, @freeze_late : called (1) before creating the 1787 * hibernation image [PMSG_FREEZE] and 1788 * (2) after rebooting, before restoring 1789 * the image [PMSG_QUIESCE] 1790 * @thaw, @thaw_early : called (1) after creating the hibernation 1791 * image, before writing it [PMSG_THAW] 1792 * and (2) after failing to create or 1793 * restore the image [PMSG_RECOVER] 1794 * @poweroff, @poweroff_late: called after writing the hibernation 1795 * image, before rebooting [PMSG_HIBERNATE] 1796 * @restore, @restore_early : called after rebooting and restoring the 1797 * hibernation image [PMSG_RESTORE] 1798 */ 1799 .freeze = i915_pm_freeze, 1800 .freeze_late = i915_pm_freeze_late, 1801 .thaw_early = i915_pm_thaw_early, 1802 .thaw = i915_pm_thaw, 1803 .poweroff = i915_pm_suspend, 1804 .poweroff_late = i915_pm_poweroff_late, 1805 .restore_early = i915_pm_restore_early, 1806 .restore = i915_pm_restore, 1807 1808 /* S0ix (via runtime suspend) event handlers */ 1809 .runtime_suspend = intel_runtime_suspend, 1810 .runtime_resume = intel_runtime_resume, 1811 }; 1812 1813 static const struct file_operations i915_driver_fops = { 1814 .owner = THIS_MODULE, 1815 .open = drm_open, 1816 .release = drm_release_noglobal, 1817 .unlocked_ioctl = drm_ioctl, 1818 .mmap = i915_gem_mmap, 1819 .poll = drm_poll, 1820 .read = drm_read, 1821 .compat_ioctl = i915_ioc32_compat_ioctl, 1822 .llseek = noop_llseek, 1823 #ifdef CONFIG_PROC_FS 1824 .show_fdinfo = i915_drm_client_fdinfo, 1825 #endif 1826 }; 1827 1828 static int 1829 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1830 struct drm_file *file) 1831 { 1832 return -ENODEV; 1833 } 1834 1835 static const struct drm_ioctl_desc i915_ioctls[] = { 1836 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1837 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1838 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1839 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1840 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1841 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1842 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1843 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1844 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1845 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1846 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1847 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1848 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1849 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1850 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1851 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1852 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1853 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1854 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1855 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1856 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1857 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1858 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1859 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1860 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1861 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1862 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1863 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1864 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1865 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1866 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1867 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1868 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1869 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1870 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1871 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1872 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1874 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1875 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1876 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1877 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1878 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1879 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1880 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1881 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1882 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1883 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1884 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1885 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1886 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1887 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1888 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1889 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1890 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1891 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1892 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1893 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1894 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1895 }; 1896 1897 /* 1898 * Interface history: 1899 * 1900 * 1.1: Original. 1901 * 1.2: Add Power Management 1902 * 1.3: Add vblank support 1903 * 1.4: Fix cmdbuffer path, add heap destroy 1904 * 1.5: Add vblank pipe configuration 1905 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1906 * - Support vertical blank on secondary display pipe 1907 */ 1908 #define DRIVER_MAJOR 1 1909 #define DRIVER_MINOR 6 1910 #define DRIVER_PATCHLEVEL 0 1911 1912 static const struct drm_driver i915_drm_driver = { 1913 /* Don't use MTRRs here; the Xserver or userspace app should 1914 * deal with them for Intel hardware. 1915 */ 1916 .driver_features = 1917 DRIVER_GEM | 1918 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1919 DRIVER_SYNCOBJ_TIMELINE, 1920 .release = i915_driver_release, 1921 .open = i915_driver_open, 1922 .lastclose = i915_driver_lastclose, 1923 .postclose = i915_driver_postclose, 1924 1925 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1926 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1927 .gem_prime_import = i915_gem_prime_import, 1928 1929 .dumb_create = i915_gem_dumb_create, 1930 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1931 1932 .ioctls = i915_ioctls, 1933 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1934 .fops = &i915_driver_fops, 1935 .name = DRIVER_NAME, 1936 .desc = DRIVER_DESC, 1937 .date = DRIVER_DATE, 1938 .major = DRIVER_MAJOR, 1939 .minor = DRIVER_MINOR, 1940 .patchlevel = DRIVER_PATCHLEVEL, 1941 }; 1942