1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/slab.h> 38 #include <linux/string_helpers.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_types.h" 52 #include "display/intel_dmc.h" 53 #include "display/intel_dp.h" 54 #include "display/intel_dpt.h" 55 #include "display/intel_fbdev.h" 56 #include "display/intel_hotplug.h" 57 #include "display/intel_overlay.h" 58 #include "display/intel_pch_refclk.h" 59 #include "display/intel_pipe_crc.h" 60 #include "display/intel_pps.h" 61 #include "display/intel_sprite.h" 62 #include "display/intel_vga.h" 63 #include "display/skl_watermark.h" 64 65 #include "gem/i915_gem_context.h" 66 #include "gem/i915_gem_create.h" 67 #include "gem/i915_gem_dmabuf.h" 68 #include "gem/i915_gem_ioctls.h" 69 #include "gem/i915_gem_mman.h" 70 #include "gem/i915_gem_pm.h" 71 #include "gt/intel_gt.h" 72 #include "gt/intel_gt_pm.h" 73 #include "gt/intel_rc6.h" 74 75 #include "pxp/intel_pxp.h" 76 #include "pxp/intel_pxp_debugfs.h" 77 #include "pxp/intel_pxp_pm.h" 78 79 #include "soc/intel_dram.h" 80 #include "soc/intel_gmch.h" 81 82 #include "i915_file_private.h" 83 #include "i915_debugfs.h" 84 #include "i915_driver.h" 85 #include "i915_drm_client.h" 86 #include "i915_drv.h" 87 #include "i915_getparam.h" 88 #include "i915_hwmon.h" 89 #include "i915_ioc32.h" 90 #include "i915_ioctl.h" 91 #include "i915_irq.h" 92 #include "i915_memcpy.h" 93 #include "i915_perf.h" 94 #include "i915_query.h" 95 #include "i915_suspend.h" 96 #include "i915_switcheroo.h" 97 #include "i915_sysfs.h" 98 #include "i915_utils.h" 99 #include "i915_vgpu.h" 100 #include "intel_gvt.h" 101 #include "intel_memory_region.h" 102 #include "intel_pci_config.h" 103 #include "intel_pcode.h" 104 #include "intel_pm.h" 105 #include "intel_region_ttm.h" 106 #include "vlv_suspend.h" 107 108 static const struct drm_driver i915_drm_driver; 109 110 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 111 { 112 /* 113 * The i915 workqueue is primarily used for batched retirement of 114 * requests (and thus managing bo) once the task has been completed 115 * by the GPU. i915_retire_requests() is called directly when we 116 * need high-priority retirement, such as waiting for an explicit 117 * bo. 118 * 119 * It is also used for periodic low-priority events, such as 120 * idle-timers and recording error state. 121 * 122 * All tasks on the workqueue are expected to acquire the dev mutex 123 * so there is no point in running more than one instance of the 124 * workqueue at any time. Use an ordered one. 125 */ 126 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 127 if (dev_priv->wq == NULL) 128 goto out_err; 129 130 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 131 if (dev_priv->display.hotplug.dp_wq == NULL) 132 goto out_free_wq; 133 134 return 0; 135 136 out_free_wq: 137 destroy_workqueue(dev_priv->wq); 138 out_err: 139 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 140 141 return -ENOMEM; 142 } 143 144 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 145 { 146 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 147 destroy_workqueue(dev_priv->wq); 148 } 149 150 /* 151 * We don't keep the workarounds for pre-production hardware, so we expect our 152 * driver to fail on these machines in one way or another. A little warning on 153 * dmesg may help both the user and the bug triagers. 154 * 155 * Our policy for removing pre-production workarounds is to keep the 156 * current gen workarounds as a guide to the bring-up of the next gen 157 * (workarounds have a habit of persisting!). Anything older than that 158 * should be removed along with the complications they introduce. 159 */ 160 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 161 { 162 bool pre = false; 163 164 pre |= IS_HSW_EARLY_SDV(dev_priv); 165 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 166 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 167 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 168 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 169 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 170 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 171 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 172 173 if (pre) { 174 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 175 "It may not be fully functional.\n"); 176 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 177 } 178 } 179 180 static void sanitize_gpu(struct drm_i915_private *i915) 181 { 182 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 183 struct intel_gt *gt; 184 unsigned int i; 185 186 for_each_gt(gt, i915, i) 187 __intel_gt_reset(gt, ALL_ENGINES); 188 } 189 } 190 191 /** 192 * i915_driver_early_probe - setup state not requiring device access 193 * @dev_priv: device private 194 * 195 * Initialize everything that is a "SW-only" state, that is state not 196 * requiring accessing the device or exposing the driver via kernel internal 197 * or userspace interfaces. Example steps belonging here: lock initialization, 198 * system memory allocation, setting up device specific attributes and 199 * function hooks not requiring accessing the device. 200 */ 201 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 202 { 203 int ret = 0; 204 205 if (i915_inject_probe_failure(dev_priv)) 206 return -ENODEV; 207 208 intel_device_info_runtime_init_early(dev_priv); 209 210 intel_step_init(dev_priv); 211 212 intel_uncore_mmio_debug_init_early(dev_priv); 213 214 spin_lock_init(&dev_priv->irq_lock); 215 spin_lock_init(&dev_priv->gpu_error.lock); 216 mutex_init(&dev_priv->display.backlight.lock); 217 218 mutex_init(&dev_priv->sb_lock); 219 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 220 221 mutex_init(&dev_priv->display.audio.mutex); 222 mutex_init(&dev_priv->display.wm.wm_mutex); 223 mutex_init(&dev_priv->display.pps.mutex); 224 mutex_init(&dev_priv->display.hdcp.comp_mutex); 225 spin_lock_init(&dev_priv->display.dkl.phy_lock); 226 227 i915_memcpy_init_early(dev_priv); 228 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 229 230 ret = i915_workqueues_init(dev_priv); 231 if (ret < 0) 232 return ret; 233 234 ret = vlv_suspend_init(dev_priv); 235 if (ret < 0) 236 goto err_workqueues; 237 238 ret = intel_region_ttm_device_init(dev_priv); 239 if (ret) 240 goto err_ttm; 241 242 ret = intel_root_gt_init_early(dev_priv); 243 if (ret < 0) 244 goto err_rootgt; 245 246 i915_drm_clients_init(&dev_priv->clients, dev_priv); 247 248 i915_gem_init_early(dev_priv); 249 250 /* This must be called before any calls to HAS_PCH_* */ 251 intel_detect_pch(dev_priv); 252 253 intel_irq_init(dev_priv); 254 intel_init_display_hooks(dev_priv); 255 intel_init_clock_gating_hooks(dev_priv); 256 257 intel_detect_preproduction_hw(dev_priv); 258 259 return 0; 260 261 err_rootgt: 262 intel_region_ttm_device_fini(dev_priv); 263 err_ttm: 264 vlv_suspend_cleanup(dev_priv); 265 err_workqueues: 266 i915_workqueues_cleanup(dev_priv); 267 return ret; 268 } 269 270 /** 271 * i915_driver_late_release - cleanup the setup done in 272 * i915_driver_early_probe() 273 * @dev_priv: device private 274 */ 275 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 276 { 277 intel_irq_fini(dev_priv); 278 intel_power_domains_cleanup(dev_priv); 279 i915_gem_cleanup_early(dev_priv); 280 intel_gt_driver_late_release_all(dev_priv); 281 i915_drm_clients_fini(&dev_priv->clients); 282 intel_region_ttm_device_fini(dev_priv); 283 vlv_suspend_cleanup(dev_priv); 284 i915_workqueues_cleanup(dev_priv); 285 286 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 287 mutex_destroy(&dev_priv->sb_lock); 288 289 i915_params_free(&dev_priv->params); 290 } 291 292 /** 293 * i915_driver_mmio_probe - setup device MMIO 294 * @dev_priv: device private 295 * 296 * Setup minimal device state necessary for MMIO accesses later in the 297 * initialization sequence. The setup here should avoid any other device-wide 298 * side effects or exposing the driver via kernel internal or user space 299 * interfaces. 300 */ 301 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 302 { 303 struct intel_gt *gt; 304 int ret, i; 305 306 if (i915_inject_probe_failure(dev_priv)) 307 return -ENODEV; 308 309 ret = intel_gmch_bridge_setup(dev_priv); 310 if (ret < 0) 311 return ret; 312 313 for_each_gt(gt, dev_priv, i) { 314 ret = intel_uncore_init_mmio(gt->uncore); 315 if (ret) 316 return ret; 317 318 ret = drmm_add_action_or_reset(&dev_priv->drm, 319 intel_uncore_fini_mmio, 320 gt->uncore); 321 if (ret) 322 return ret; 323 } 324 325 /* Try to make sure MCHBAR is enabled before poking at it */ 326 intel_gmch_bar_setup(dev_priv); 327 intel_device_info_runtime_init(dev_priv); 328 329 for_each_gt(gt, dev_priv, i) { 330 ret = intel_gt_init_mmio(gt); 331 if (ret) 332 goto err_uncore; 333 } 334 335 /* As early as possible, scrub existing GPU state before clobbering */ 336 sanitize_gpu(dev_priv); 337 338 return 0; 339 340 err_uncore: 341 intel_gmch_bar_teardown(dev_priv); 342 343 return ret; 344 } 345 346 /** 347 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 348 * @dev_priv: device private 349 */ 350 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 351 { 352 intel_gmch_bar_teardown(dev_priv); 353 } 354 355 /** 356 * i915_set_dma_info - set all relevant PCI dma info as configured for the 357 * platform 358 * @i915: valid i915 instance 359 * 360 * Set the dma max segment size, device and coherent masks. The dma mask set 361 * needs to occur before i915_ggtt_probe_hw. 362 * 363 * A couple of platforms have special needs. Address them as well. 364 * 365 */ 366 static int i915_set_dma_info(struct drm_i915_private *i915) 367 { 368 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 369 int ret; 370 371 GEM_BUG_ON(!mask_size); 372 373 /* 374 * We don't have a max segment size, so set it to the max so sg's 375 * debugging layer doesn't complain 376 */ 377 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 378 379 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 380 if (ret) 381 goto mask_err; 382 383 /* overlay on gen2 is broken and can't address above 1G */ 384 if (GRAPHICS_VER(i915) == 2) 385 mask_size = 30; 386 387 /* 388 * 965GM sometimes incorrectly writes to hardware status page (HWS) 389 * using 32bit addressing, overwriting memory if HWS is located 390 * above 4GB. 391 * 392 * The documentation also mentions an issue with undefined 393 * behaviour if any general state is accessed within a page above 4GB, 394 * which also needs to be handled carefully. 395 */ 396 if (IS_I965G(i915) || IS_I965GM(i915)) 397 mask_size = 32; 398 399 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 400 if (ret) 401 goto mask_err; 402 403 return 0; 404 405 mask_err: 406 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 407 return ret; 408 } 409 410 static int i915_pcode_init(struct drm_i915_private *i915) 411 { 412 struct intel_gt *gt; 413 int id, ret; 414 415 for_each_gt(gt, i915, id) { 416 ret = intel_pcode_init(gt->uncore); 417 if (ret) { 418 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 419 return ret; 420 } 421 } 422 423 return 0; 424 } 425 426 /** 427 * i915_driver_hw_probe - setup state requiring device access 428 * @dev_priv: device private 429 * 430 * Setup state that requires accessing the device, but doesn't require 431 * exposing the driver via kernel internal or userspace interfaces. 432 */ 433 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 434 { 435 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 436 struct pci_dev *root_pdev; 437 int ret; 438 439 if (i915_inject_probe_failure(dev_priv)) 440 return -ENODEV; 441 442 if (HAS_PPGTT(dev_priv)) { 443 if (intel_vgpu_active(dev_priv) && 444 !intel_vgpu_has_full_ppgtt(dev_priv)) { 445 i915_report_error(dev_priv, 446 "incompatible vGPU found, support for isolated ppGTT required\n"); 447 return -ENXIO; 448 } 449 } 450 451 if (HAS_EXECLISTS(dev_priv)) { 452 /* 453 * Older GVT emulation depends upon intercepting CSB mmio, 454 * which we no longer use, preferring to use the HWSP cache 455 * instead. 456 */ 457 if (intel_vgpu_active(dev_priv) && 458 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 459 i915_report_error(dev_priv, 460 "old vGPU host found, support for HWSP emulation required\n"); 461 return -ENXIO; 462 } 463 } 464 465 /* needs to be done before ggtt probe */ 466 intel_dram_edram_detect(dev_priv); 467 468 ret = i915_set_dma_info(dev_priv); 469 if (ret) 470 return ret; 471 472 i915_perf_init(dev_priv); 473 474 ret = i915_ggtt_probe_hw(dev_priv); 475 if (ret) 476 goto err_perf; 477 478 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 479 if (ret) 480 goto err_ggtt; 481 482 ret = i915_ggtt_init_hw(dev_priv); 483 if (ret) 484 goto err_ggtt; 485 486 /* 487 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 488 * might be different due to bar resizing. 489 */ 490 ret = intel_gt_tiles_init(dev_priv); 491 if (ret) 492 goto err_ggtt; 493 494 ret = intel_memory_regions_hw_probe(dev_priv); 495 if (ret) 496 goto err_ggtt; 497 498 ret = i915_ggtt_enable_hw(dev_priv); 499 if (ret) { 500 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 501 goto err_mem_regions; 502 } 503 504 pci_set_master(pdev); 505 506 /* On the 945G/GM, the chipset reports the MSI capability on the 507 * integrated graphics even though the support isn't actually there 508 * according to the published specs. It doesn't appear to function 509 * correctly in testing on 945G. 510 * This may be a side effect of MSI having been made available for PEG 511 * and the registers being closely associated. 512 * 513 * According to chipset errata, on the 965GM, MSI interrupts may 514 * be lost or delayed, and was defeatured. MSI interrupts seem to 515 * get lost on g4x as well, and interrupt delivery seems to stay 516 * properly dead afterwards. So we'll just disable them for all 517 * pre-gen5 chipsets. 518 * 519 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 520 * interrupts even when in MSI mode. This results in spurious 521 * interrupt warnings if the legacy irq no. is shared with another 522 * device. The kernel then disables that interrupt source and so 523 * prevents the other device from working properly. 524 */ 525 if (GRAPHICS_VER(dev_priv) >= 5) { 526 if (pci_enable_msi(pdev) < 0) 527 drm_dbg(&dev_priv->drm, "can't enable MSI"); 528 } 529 530 ret = intel_gvt_init(dev_priv); 531 if (ret) 532 goto err_msi; 533 534 intel_opregion_setup(dev_priv); 535 536 ret = i915_pcode_init(dev_priv); 537 if (ret) 538 goto err_msi; 539 540 /* 541 * Fill the dram structure to get the system dram info. This will be 542 * used for memory latency calculation. 543 */ 544 intel_dram_detect(dev_priv); 545 546 intel_bw_init_hw(dev_priv); 547 548 /* 549 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 550 * This should be totally removed when we handle the pci states properly 551 * on runtime PM and on s2idle cases. 552 */ 553 root_pdev = pcie_find_root_port(pdev); 554 if (root_pdev) 555 pci_d3cold_disable(root_pdev); 556 557 return 0; 558 559 err_msi: 560 if (pdev->msi_enabled) 561 pci_disable_msi(pdev); 562 err_mem_regions: 563 intel_memory_regions_driver_release(dev_priv); 564 err_ggtt: 565 i915_ggtt_driver_release(dev_priv); 566 i915_gem_drain_freed_objects(dev_priv); 567 i915_ggtt_driver_late_release(dev_priv); 568 err_perf: 569 i915_perf_fini(dev_priv); 570 return ret; 571 } 572 573 /** 574 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 575 * @dev_priv: device private 576 */ 577 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 578 { 579 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 580 struct pci_dev *root_pdev; 581 582 i915_perf_fini(dev_priv); 583 584 if (pdev->msi_enabled) 585 pci_disable_msi(pdev); 586 587 root_pdev = pcie_find_root_port(pdev); 588 if (root_pdev) 589 pci_d3cold_enable(root_pdev); 590 } 591 592 /** 593 * i915_driver_register - register the driver with the rest of the system 594 * @dev_priv: device private 595 * 596 * Perform any steps necessary to make the driver available via kernel 597 * internal or userspace interfaces. 598 */ 599 static void i915_driver_register(struct drm_i915_private *dev_priv) 600 { 601 struct intel_gt *gt; 602 unsigned int i; 603 604 i915_gem_driver_register(dev_priv); 605 i915_pmu_register(dev_priv); 606 607 intel_vgpu_register(dev_priv); 608 609 /* Reveal our presence to userspace */ 610 if (drm_dev_register(&dev_priv->drm, 0)) { 611 drm_err(&dev_priv->drm, 612 "Failed to register driver for userspace access!\n"); 613 return; 614 } 615 616 i915_debugfs_register(dev_priv); 617 i915_setup_sysfs(dev_priv); 618 619 /* Depends on sysfs having been initialized */ 620 i915_perf_register(dev_priv); 621 622 for_each_gt(gt, dev_priv, i) 623 intel_gt_driver_register(gt); 624 625 intel_pxp_debugfs_register(dev_priv->pxp); 626 627 i915_hwmon_register(dev_priv); 628 629 intel_display_driver_register(dev_priv); 630 631 intel_power_domains_enable(dev_priv); 632 intel_runtime_pm_enable(&dev_priv->runtime_pm); 633 634 intel_register_dsm_handler(); 635 636 if (i915_switcheroo_register(dev_priv)) 637 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 638 } 639 640 /** 641 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 642 * @dev_priv: device private 643 */ 644 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 645 { 646 struct intel_gt *gt; 647 unsigned int i; 648 649 i915_switcheroo_unregister(dev_priv); 650 651 intel_unregister_dsm_handler(); 652 653 intel_runtime_pm_disable(&dev_priv->runtime_pm); 654 intel_power_domains_disable(dev_priv); 655 656 intel_display_driver_unregister(dev_priv); 657 658 intel_pxp_fini(dev_priv); 659 660 for_each_gt(gt, dev_priv, i) 661 intel_gt_driver_unregister(gt); 662 663 i915_hwmon_unregister(dev_priv); 664 665 i915_perf_unregister(dev_priv); 666 i915_pmu_unregister(dev_priv); 667 668 i915_teardown_sysfs(dev_priv); 669 drm_dev_unplug(&dev_priv->drm); 670 671 i915_gem_driver_unregister(dev_priv); 672 } 673 674 void 675 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 676 { 677 drm_printf(p, "iommu: %s\n", 678 str_enabled_disabled(i915_vtd_active(i915))); 679 } 680 681 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 682 { 683 if (drm_debug_enabled(DRM_UT_DRIVER)) { 684 struct drm_printer p = drm_debug_printer("i915 device info:"); 685 struct intel_gt *gt; 686 unsigned int i; 687 688 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 689 INTEL_DEVID(dev_priv), 690 INTEL_REVID(dev_priv), 691 intel_platform_name(INTEL_INFO(dev_priv)->platform), 692 intel_subplatform(RUNTIME_INFO(dev_priv), 693 INTEL_INFO(dev_priv)->platform), 694 GRAPHICS_VER(dev_priv)); 695 696 intel_device_info_print(INTEL_INFO(dev_priv), 697 RUNTIME_INFO(dev_priv), &p); 698 i915_print_iommu_status(dev_priv, &p); 699 for_each_gt(gt, dev_priv, i) 700 intel_gt_info_print(>->info, &p); 701 } 702 703 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 704 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 705 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 706 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 707 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 708 drm_info(&dev_priv->drm, 709 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 710 } 711 712 static struct drm_i915_private * 713 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 714 { 715 const struct intel_device_info *match_info = 716 (struct intel_device_info *)ent->driver_data; 717 struct intel_device_info *device_info; 718 struct intel_runtime_info *runtime; 719 struct drm_i915_private *i915; 720 721 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 722 struct drm_i915_private, drm); 723 if (IS_ERR(i915)) 724 return i915; 725 726 pci_set_drvdata(pdev, i915); 727 728 /* Device parameters start as a copy of module parameters. */ 729 i915_params_copy(&i915->params, &i915_modparams); 730 731 /* Setup the write-once "constant" device info */ 732 device_info = mkwrite_device_info(i915); 733 memcpy(device_info, match_info, sizeof(*device_info)); 734 735 /* Initialize initial runtime info from static const data and pdev. */ 736 runtime = RUNTIME_INFO(i915); 737 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 738 runtime->device_id = pdev->device; 739 740 return i915; 741 } 742 743 /** 744 * i915_driver_probe - setup chip and create an initial config 745 * @pdev: PCI device 746 * @ent: matching PCI ID entry 747 * 748 * The driver probe routine has to do several things: 749 * - drive output discovery via intel_modeset_init() 750 * - initialize the memory manager 751 * - allocate initial config memory 752 * - setup the DRM framebuffer with the allocated memory 753 */ 754 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 755 { 756 struct drm_i915_private *i915; 757 int ret; 758 759 i915 = i915_driver_create(pdev, ent); 760 if (IS_ERR(i915)) 761 return PTR_ERR(i915); 762 763 ret = pci_enable_device(pdev); 764 if (ret) 765 goto out_fini; 766 767 ret = i915_driver_early_probe(i915); 768 if (ret < 0) 769 goto out_pci_disable; 770 771 disable_rpm_wakeref_asserts(&i915->runtime_pm); 772 773 intel_vgpu_detect(i915); 774 775 ret = intel_gt_probe_all(i915); 776 if (ret < 0) 777 goto out_runtime_pm_put; 778 779 ret = i915_driver_mmio_probe(i915); 780 if (ret < 0) 781 goto out_tiles_cleanup; 782 783 ret = i915_driver_hw_probe(i915); 784 if (ret < 0) 785 goto out_cleanup_mmio; 786 787 ret = intel_modeset_init_noirq(i915); 788 if (ret < 0) 789 goto out_cleanup_hw; 790 791 ret = intel_irq_install(i915); 792 if (ret) 793 goto out_cleanup_modeset; 794 795 ret = intel_modeset_init_nogem(i915); 796 if (ret) 797 goto out_cleanup_irq; 798 799 ret = i915_gem_init(i915); 800 if (ret) 801 goto out_cleanup_modeset2; 802 803 intel_pxp_init(i915); 804 805 ret = intel_modeset_init(i915); 806 if (ret) 807 goto out_cleanup_gem; 808 809 i915_driver_register(i915); 810 811 enable_rpm_wakeref_asserts(&i915->runtime_pm); 812 813 i915_welcome_messages(i915); 814 815 i915->do_release = true; 816 817 return 0; 818 819 out_cleanup_gem: 820 i915_gem_suspend(i915); 821 i915_gem_driver_remove(i915); 822 i915_gem_driver_release(i915); 823 out_cleanup_modeset2: 824 /* FIXME clean up the error path */ 825 intel_modeset_driver_remove(i915); 826 intel_irq_uninstall(i915); 827 intel_modeset_driver_remove_noirq(i915); 828 goto out_cleanup_modeset; 829 out_cleanup_irq: 830 intel_irq_uninstall(i915); 831 out_cleanup_modeset: 832 intel_modeset_driver_remove_nogem(i915); 833 out_cleanup_hw: 834 i915_driver_hw_remove(i915); 835 intel_memory_regions_driver_release(i915); 836 i915_ggtt_driver_release(i915); 837 i915_gem_drain_freed_objects(i915); 838 i915_ggtt_driver_late_release(i915); 839 out_cleanup_mmio: 840 i915_driver_mmio_release(i915); 841 out_tiles_cleanup: 842 intel_gt_release_all(i915); 843 out_runtime_pm_put: 844 enable_rpm_wakeref_asserts(&i915->runtime_pm); 845 i915_driver_late_release(i915); 846 out_pci_disable: 847 pci_disable_device(pdev); 848 out_fini: 849 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 850 return ret; 851 } 852 853 void i915_driver_remove(struct drm_i915_private *i915) 854 { 855 intel_wakeref_t wakeref; 856 857 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 858 859 i915_driver_unregister(i915); 860 861 /* Flush any external code that still may be under the RCU lock */ 862 synchronize_rcu(); 863 864 i915_gem_suspend(i915); 865 866 intel_gvt_driver_remove(i915); 867 868 intel_modeset_driver_remove(i915); 869 870 intel_irq_uninstall(i915); 871 872 intel_modeset_driver_remove_noirq(i915); 873 874 i915_reset_error_state(i915); 875 i915_gem_driver_remove(i915); 876 877 intel_modeset_driver_remove_nogem(i915); 878 879 i915_driver_hw_remove(i915); 880 881 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 882 } 883 884 static void i915_driver_release(struct drm_device *dev) 885 { 886 struct drm_i915_private *dev_priv = to_i915(dev); 887 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 888 intel_wakeref_t wakeref; 889 890 if (!dev_priv->do_release) 891 return; 892 893 wakeref = intel_runtime_pm_get(rpm); 894 895 i915_gem_driver_release(dev_priv); 896 897 intel_memory_regions_driver_release(dev_priv); 898 i915_ggtt_driver_release(dev_priv); 899 i915_gem_drain_freed_objects(dev_priv); 900 i915_ggtt_driver_late_release(dev_priv); 901 902 i915_driver_mmio_release(dev_priv); 903 904 intel_runtime_pm_put(rpm, wakeref); 905 906 intel_runtime_pm_driver_release(rpm); 907 908 i915_driver_late_release(dev_priv); 909 } 910 911 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 912 { 913 struct drm_i915_private *i915 = to_i915(dev); 914 int ret; 915 916 ret = i915_gem_open(i915, file); 917 if (ret) 918 return ret; 919 920 return 0; 921 } 922 923 /** 924 * i915_driver_lastclose - clean up after all DRM clients have exited 925 * @dev: DRM device 926 * 927 * Take care of cleaning up after all DRM clients have exited. In the 928 * mode setting case, we want to restore the kernel's initial mode (just 929 * in case the last client left us in a bad state). 930 * 931 * Additionally, in the non-mode setting case, we'll tear down the GTT 932 * and DMA structures, since the kernel won't be using them, and clea 933 * up any GEM state. 934 */ 935 static void i915_driver_lastclose(struct drm_device *dev) 936 { 937 struct drm_i915_private *i915 = to_i915(dev); 938 939 intel_fbdev_restore_mode(i915); 940 941 vga_switcheroo_process_delayed_switch(); 942 } 943 944 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 945 { 946 struct drm_i915_file_private *file_priv = file->driver_priv; 947 948 i915_gem_context_close(file); 949 i915_drm_client_put(file_priv->client); 950 951 kfree_rcu(file_priv, rcu); 952 953 /* Catch up with all the deferred frees from "this" client */ 954 i915_gem_flush_free_objects(to_i915(dev)); 955 } 956 957 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 958 { 959 struct intel_encoder *encoder; 960 961 if (!HAS_DISPLAY(dev_priv)) 962 return; 963 964 drm_modeset_lock_all(&dev_priv->drm); 965 for_each_intel_encoder(&dev_priv->drm, encoder) 966 if (encoder->suspend) 967 encoder->suspend(encoder); 968 drm_modeset_unlock_all(&dev_priv->drm); 969 } 970 971 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 972 { 973 struct intel_encoder *encoder; 974 975 if (!HAS_DISPLAY(dev_priv)) 976 return; 977 978 drm_modeset_lock_all(&dev_priv->drm); 979 for_each_intel_encoder(&dev_priv->drm, encoder) 980 if (encoder->shutdown) 981 encoder->shutdown(encoder); 982 drm_modeset_unlock_all(&dev_priv->drm); 983 } 984 985 void i915_driver_shutdown(struct drm_i915_private *i915) 986 { 987 disable_rpm_wakeref_asserts(&i915->runtime_pm); 988 intel_runtime_pm_disable(&i915->runtime_pm); 989 intel_power_domains_disable(i915); 990 991 if (HAS_DISPLAY(i915)) { 992 drm_kms_helper_poll_disable(&i915->drm); 993 994 drm_atomic_helper_shutdown(&i915->drm); 995 } 996 997 intel_dp_mst_suspend(i915); 998 999 intel_runtime_pm_disable_interrupts(i915); 1000 intel_hpd_cancel_work(i915); 1001 1002 intel_suspend_encoders(i915); 1003 intel_shutdown_encoders(i915); 1004 1005 intel_dmc_suspend(i915); 1006 1007 i915_gem_suspend(i915); 1008 1009 /* 1010 * The only requirement is to reboot with display DC states disabled, 1011 * for now leaving all display power wells in the INIT power domain 1012 * enabled. 1013 * 1014 * TODO: 1015 * - unify the pci_driver::shutdown sequence here with the 1016 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1017 * - unify the driver remove and system/runtime suspend sequences with 1018 * the above unified shutdown/poweroff sequence. 1019 */ 1020 intel_power_domains_driver_remove(i915); 1021 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1022 1023 intel_runtime_pm_driver_release(&i915->runtime_pm); 1024 } 1025 1026 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1027 { 1028 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1029 if (acpi_target_system_state() < ACPI_STATE_S3) 1030 return true; 1031 #endif 1032 return false; 1033 } 1034 1035 static void i915_drm_complete(struct drm_device *dev) 1036 { 1037 struct drm_i915_private *i915 = to_i915(dev); 1038 1039 intel_pxp_resume_complete(i915->pxp); 1040 } 1041 1042 static int i915_drm_prepare(struct drm_device *dev) 1043 { 1044 struct drm_i915_private *i915 = to_i915(dev); 1045 1046 intel_pxp_suspend_prepare(i915->pxp); 1047 1048 /* 1049 * NB intel_display_suspend() may issue new requests after we've 1050 * ostensibly marked the GPU as ready-to-sleep here. We need to 1051 * split out that work and pull it forward so that after point, 1052 * the GPU is not woken again. 1053 */ 1054 return i915_gem_backup_suspend(i915); 1055 } 1056 1057 static int i915_drm_suspend(struct drm_device *dev) 1058 { 1059 struct drm_i915_private *dev_priv = to_i915(dev); 1060 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1061 pci_power_t opregion_target_state; 1062 1063 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1064 1065 /* We do a lot of poking in a lot of registers, make sure they work 1066 * properly. */ 1067 intel_power_domains_disable(dev_priv); 1068 if (HAS_DISPLAY(dev_priv)) 1069 drm_kms_helper_poll_disable(dev); 1070 1071 pci_save_state(pdev); 1072 1073 intel_display_suspend(dev); 1074 1075 intel_dp_mst_suspend(dev_priv); 1076 1077 intel_runtime_pm_disable_interrupts(dev_priv); 1078 intel_hpd_cancel_work(dev_priv); 1079 1080 intel_suspend_encoders(dev_priv); 1081 1082 /* Must be called before GGTT is suspended. */ 1083 intel_dpt_suspend(dev_priv); 1084 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1085 1086 i915_save_display(dev_priv); 1087 1088 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1089 intel_opregion_suspend(dev_priv, opregion_target_state); 1090 1091 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1092 1093 dev_priv->suspend_count++; 1094 1095 intel_dmc_suspend(dev_priv); 1096 1097 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1098 1099 i915_gem_drain_freed_objects(dev_priv); 1100 1101 return 0; 1102 } 1103 1104 static enum i915_drm_suspend_mode 1105 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1106 { 1107 if (hibernate) 1108 return I915_DRM_SUSPEND_HIBERNATE; 1109 1110 if (suspend_to_idle(dev_priv)) 1111 return I915_DRM_SUSPEND_IDLE; 1112 1113 return I915_DRM_SUSPEND_MEM; 1114 } 1115 1116 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1117 { 1118 struct drm_i915_private *dev_priv = to_i915(dev); 1119 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1120 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1121 struct intel_gt *gt; 1122 int ret, i; 1123 1124 disable_rpm_wakeref_asserts(rpm); 1125 1126 intel_pxp_suspend(dev_priv->pxp); 1127 1128 i915_gem_suspend_late(dev_priv); 1129 1130 for_each_gt(gt, dev_priv, i) 1131 intel_uncore_suspend(gt->uncore); 1132 1133 intel_power_domains_suspend(dev_priv, 1134 get_suspend_mode(dev_priv, hibernation)); 1135 1136 intel_display_power_suspend_late(dev_priv); 1137 1138 ret = vlv_suspend_complete(dev_priv); 1139 if (ret) { 1140 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1141 intel_power_domains_resume(dev_priv); 1142 1143 goto out; 1144 } 1145 1146 pci_disable_device(pdev); 1147 /* 1148 * During hibernation on some platforms the BIOS may try to access 1149 * the device even though it's already in D3 and hang the machine. So 1150 * leave the device in D0 on those platforms and hope the BIOS will 1151 * power down the device properly. The issue was seen on multiple old 1152 * GENs with different BIOS vendors, so having an explicit blacklist 1153 * is inpractical; apply the workaround on everything pre GEN6. The 1154 * platforms where the issue was seen: 1155 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1156 * Fujitsu FSC S7110 1157 * Acer Aspire 1830T 1158 */ 1159 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1160 pci_set_power_state(pdev, PCI_D3hot); 1161 1162 out: 1163 enable_rpm_wakeref_asserts(rpm); 1164 if (!dev_priv->uncore.user_forcewake_count) 1165 intel_runtime_pm_driver_release(rpm); 1166 1167 return ret; 1168 } 1169 1170 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1171 pm_message_t state) 1172 { 1173 int error; 1174 1175 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1176 state.event != PM_EVENT_FREEZE)) 1177 return -EINVAL; 1178 1179 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1180 return 0; 1181 1182 error = i915_drm_suspend(&i915->drm); 1183 if (error) 1184 return error; 1185 1186 return i915_drm_suspend_late(&i915->drm, false); 1187 } 1188 1189 static int i915_drm_resume(struct drm_device *dev) 1190 { 1191 struct drm_i915_private *dev_priv = to_i915(dev); 1192 struct intel_gt *gt; 1193 int ret, i; 1194 1195 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1196 1197 ret = i915_pcode_init(dev_priv); 1198 if (ret) 1199 return ret; 1200 1201 sanitize_gpu(dev_priv); 1202 1203 ret = i915_ggtt_enable_hw(dev_priv); 1204 if (ret) 1205 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1206 1207 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1208 1209 for_each_gt(gt, dev_priv, i) 1210 if (GRAPHICS_VER(gt->i915) >= 8) 1211 setup_private_pat(gt); 1212 1213 /* Must be called after GGTT is resumed. */ 1214 intel_dpt_resume(dev_priv); 1215 1216 intel_dmc_resume(dev_priv); 1217 1218 i915_restore_display(dev_priv); 1219 intel_pps_unlock_regs_wa(dev_priv); 1220 1221 intel_init_pch_refclk(dev_priv); 1222 1223 /* 1224 * Interrupts have to be enabled before any batches are run. If not the 1225 * GPU will hang. i915_gem_init_hw() will initiate batches to 1226 * update/restore the context. 1227 * 1228 * drm_mode_config_reset() needs AUX interrupts. 1229 * 1230 * Modeset enabling in intel_modeset_init_hw() also needs working 1231 * interrupts. 1232 */ 1233 intel_runtime_pm_enable_interrupts(dev_priv); 1234 1235 if (HAS_DISPLAY(dev_priv)) 1236 drm_mode_config_reset(dev); 1237 1238 i915_gem_resume(dev_priv); 1239 1240 intel_modeset_init_hw(dev_priv); 1241 intel_init_clock_gating(dev_priv); 1242 intel_hpd_init(dev_priv); 1243 1244 /* MST sideband requires HPD interrupts enabled */ 1245 intel_dp_mst_resume(dev_priv); 1246 intel_display_resume(dev); 1247 1248 intel_hpd_poll_disable(dev_priv); 1249 if (HAS_DISPLAY(dev_priv)) 1250 drm_kms_helper_poll_enable(dev); 1251 1252 intel_opregion_resume(dev_priv); 1253 1254 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1255 1256 intel_power_domains_enable(dev_priv); 1257 1258 intel_gvt_resume(dev_priv); 1259 1260 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1261 1262 return 0; 1263 } 1264 1265 static int i915_drm_resume_early(struct drm_device *dev) 1266 { 1267 struct drm_i915_private *dev_priv = to_i915(dev); 1268 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1269 struct intel_gt *gt; 1270 int ret, i; 1271 1272 /* 1273 * We have a resume ordering issue with the snd-hda driver also 1274 * requiring our device to be power up. Due to the lack of a 1275 * parent/child relationship we currently solve this with an early 1276 * resume hook. 1277 * 1278 * FIXME: This should be solved with a special hdmi sink device or 1279 * similar so that power domains can be employed. 1280 */ 1281 1282 /* 1283 * Note that we need to set the power state explicitly, since we 1284 * powered off the device during freeze and the PCI core won't power 1285 * it back up for us during thaw. Powering off the device during 1286 * freeze is not a hard requirement though, and during the 1287 * suspend/resume phases the PCI core makes sure we get here with the 1288 * device powered on. So in case we change our freeze logic and keep 1289 * the device powered we can also remove the following set power state 1290 * call. 1291 */ 1292 ret = pci_set_power_state(pdev, PCI_D0); 1293 if (ret) { 1294 drm_err(&dev_priv->drm, 1295 "failed to set PCI D0 power state (%d)\n", ret); 1296 return ret; 1297 } 1298 1299 /* 1300 * Note that pci_enable_device() first enables any parent bridge 1301 * device and only then sets the power state for this device. The 1302 * bridge enabling is a nop though, since bridge devices are resumed 1303 * first. The order of enabling power and enabling the device is 1304 * imposed by the PCI core as described above, so here we preserve the 1305 * same order for the freeze/thaw phases. 1306 * 1307 * TODO: eventually we should remove pci_disable_device() / 1308 * pci_enable_enable_device() from suspend/resume. Due to how they 1309 * depend on the device enable refcount we can't anyway depend on them 1310 * disabling/enabling the device. 1311 */ 1312 if (pci_enable_device(pdev)) 1313 return -EIO; 1314 1315 pci_set_master(pdev); 1316 1317 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1318 1319 ret = vlv_resume_prepare(dev_priv, false); 1320 if (ret) 1321 drm_err(&dev_priv->drm, 1322 "Resume prepare failed: %d, continuing anyway\n", ret); 1323 1324 for_each_gt(gt, dev_priv, i) { 1325 intel_uncore_resume_early(gt->uncore); 1326 intel_gt_check_and_clear_faults(gt); 1327 } 1328 1329 intel_display_power_resume_early(dev_priv); 1330 1331 intel_power_domains_resume(dev_priv); 1332 1333 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1334 1335 return ret; 1336 } 1337 1338 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1339 { 1340 int ret; 1341 1342 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1343 return 0; 1344 1345 ret = i915_drm_resume_early(&i915->drm); 1346 if (ret) 1347 return ret; 1348 1349 return i915_drm_resume(&i915->drm); 1350 } 1351 1352 static int i915_pm_prepare(struct device *kdev) 1353 { 1354 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1355 1356 if (!i915) { 1357 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1358 return -ENODEV; 1359 } 1360 1361 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1362 return 0; 1363 1364 return i915_drm_prepare(&i915->drm); 1365 } 1366 1367 static int i915_pm_suspend(struct device *kdev) 1368 { 1369 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1370 1371 if (!i915) { 1372 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1373 return -ENODEV; 1374 } 1375 1376 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1377 return 0; 1378 1379 return i915_drm_suspend(&i915->drm); 1380 } 1381 1382 static int i915_pm_suspend_late(struct device *kdev) 1383 { 1384 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1385 1386 /* 1387 * We have a suspend ordering issue with the snd-hda driver also 1388 * requiring our device to be power up. Due to the lack of a 1389 * parent/child relationship we currently solve this with an late 1390 * suspend hook. 1391 * 1392 * FIXME: This should be solved with a special hdmi sink device or 1393 * similar so that power domains can be employed. 1394 */ 1395 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1396 return 0; 1397 1398 return i915_drm_suspend_late(&i915->drm, false); 1399 } 1400 1401 static int i915_pm_poweroff_late(struct device *kdev) 1402 { 1403 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1404 1405 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1406 return 0; 1407 1408 return i915_drm_suspend_late(&i915->drm, true); 1409 } 1410 1411 static int i915_pm_resume_early(struct device *kdev) 1412 { 1413 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1414 1415 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1416 return 0; 1417 1418 return i915_drm_resume_early(&i915->drm); 1419 } 1420 1421 static int i915_pm_resume(struct device *kdev) 1422 { 1423 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1424 1425 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1426 return 0; 1427 1428 return i915_drm_resume(&i915->drm); 1429 } 1430 1431 static void i915_pm_complete(struct device *kdev) 1432 { 1433 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1434 1435 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1436 return; 1437 1438 i915_drm_complete(&i915->drm); 1439 } 1440 1441 /* freeze: before creating the hibernation_image */ 1442 static int i915_pm_freeze(struct device *kdev) 1443 { 1444 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1445 int ret; 1446 1447 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1448 ret = i915_drm_suspend(&i915->drm); 1449 if (ret) 1450 return ret; 1451 } 1452 1453 ret = i915_gem_freeze(i915); 1454 if (ret) 1455 return ret; 1456 1457 return 0; 1458 } 1459 1460 static int i915_pm_freeze_late(struct device *kdev) 1461 { 1462 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1463 int ret; 1464 1465 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1466 ret = i915_drm_suspend_late(&i915->drm, true); 1467 if (ret) 1468 return ret; 1469 } 1470 1471 ret = i915_gem_freeze_late(i915); 1472 if (ret) 1473 return ret; 1474 1475 return 0; 1476 } 1477 1478 /* thaw: called after creating the hibernation image, but before turning off. */ 1479 static int i915_pm_thaw_early(struct device *kdev) 1480 { 1481 return i915_pm_resume_early(kdev); 1482 } 1483 1484 static int i915_pm_thaw(struct device *kdev) 1485 { 1486 return i915_pm_resume(kdev); 1487 } 1488 1489 /* restore: called after loading the hibernation image. */ 1490 static int i915_pm_restore_early(struct device *kdev) 1491 { 1492 return i915_pm_resume_early(kdev); 1493 } 1494 1495 static int i915_pm_restore(struct device *kdev) 1496 { 1497 return i915_pm_resume(kdev); 1498 } 1499 1500 static int intel_runtime_suspend(struct device *kdev) 1501 { 1502 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1503 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1504 struct intel_gt *gt; 1505 int ret, i; 1506 1507 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1508 return -ENODEV; 1509 1510 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1511 1512 disable_rpm_wakeref_asserts(rpm); 1513 1514 /* 1515 * We are safe here against re-faults, since the fault handler takes 1516 * an RPM reference. 1517 */ 1518 i915_gem_runtime_suspend(dev_priv); 1519 1520 intel_pxp_runtime_suspend(dev_priv->pxp); 1521 1522 for_each_gt(gt, dev_priv, i) 1523 intel_gt_runtime_suspend(gt); 1524 1525 intel_runtime_pm_disable_interrupts(dev_priv); 1526 1527 for_each_gt(gt, dev_priv, i) 1528 intel_uncore_suspend(gt->uncore); 1529 1530 intel_display_power_suspend(dev_priv); 1531 1532 ret = vlv_suspend_complete(dev_priv); 1533 if (ret) { 1534 drm_err(&dev_priv->drm, 1535 "Runtime suspend failed, disabling it (%d)\n", ret); 1536 intel_uncore_runtime_resume(&dev_priv->uncore); 1537 1538 intel_runtime_pm_enable_interrupts(dev_priv); 1539 1540 for_each_gt(gt, dev_priv, i) 1541 intel_gt_runtime_resume(gt); 1542 1543 enable_rpm_wakeref_asserts(rpm); 1544 1545 return ret; 1546 } 1547 1548 enable_rpm_wakeref_asserts(rpm); 1549 intel_runtime_pm_driver_release(rpm); 1550 1551 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1552 drm_err(&dev_priv->drm, 1553 "Unclaimed access detected prior to suspending\n"); 1554 1555 rpm->suspended = true; 1556 1557 /* 1558 * FIXME: We really should find a document that references the arguments 1559 * used below! 1560 */ 1561 if (IS_BROADWELL(dev_priv)) { 1562 /* 1563 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1564 * being detected, and the call we do at intel_runtime_resume() 1565 * won't be able to restore them. Since PCI_D3hot matches the 1566 * actual specification and appears to be working, use it. 1567 */ 1568 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1569 } else { 1570 /* 1571 * current versions of firmware which depend on this opregion 1572 * notification have repurposed the D1 definition to mean 1573 * "runtime suspended" vs. what you would normally expect (D3) 1574 * to distinguish it from notifications that might be sent via 1575 * the suspend path. 1576 */ 1577 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1578 } 1579 1580 assert_forcewakes_inactive(&dev_priv->uncore); 1581 1582 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1583 intel_hpd_poll_enable(dev_priv); 1584 1585 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1586 return 0; 1587 } 1588 1589 static int intel_runtime_resume(struct device *kdev) 1590 { 1591 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1592 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1593 struct intel_gt *gt; 1594 int ret, i; 1595 1596 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1597 return -ENODEV; 1598 1599 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1600 1601 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1602 disable_rpm_wakeref_asserts(rpm); 1603 1604 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1605 rpm->suspended = false; 1606 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1607 drm_dbg(&dev_priv->drm, 1608 "Unclaimed access during suspend, bios?\n"); 1609 1610 intel_display_power_resume(dev_priv); 1611 1612 ret = vlv_resume_prepare(dev_priv, true); 1613 1614 for_each_gt(gt, dev_priv, i) 1615 intel_uncore_runtime_resume(gt->uncore); 1616 1617 intel_runtime_pm_enable_interrupts(dev_priv); 1618 1619 /* 1620 * No point of rolling back things in case of an error, as the best 1621 * we can do is to hope that things will still work (and disable RPM). 1622 */ 1623 for_each_gt(gt, dev_priv, i) 1624 intel_gt_runtime_resume(gt); 1625 1626 intel_pxp_runtime_resume(dev_priv->pxp); 1627 1628 /* 1629 * On VLV/CHV display interrupts are part of the display 1630 * power well, so hpd is reinitialized from there. For 1631 * everyone else do it here. 1632 */ 1633 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1634 intel_hpd_init(dev_priv); 1635 intel_hpd_poll_disable(dev_priv); 1636 } 1637 1638 skl_watermark_ipc_update(dev_priv); 1639 1640 enable_rpm_wakeref_asserts(rpm); 1641 1642 if (ret) 1643 drm_err(&dev_priv->drm, 1644 "Runtime resume failed, disabling it (%d)\n", ret); 1645 else 1646 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1647 1648 return ret; 1649 } 1650 1651 const struct dev_pm_ops i915_pm_ops = { 1652 /* 1653 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1654 * PMSG_RESUME] 1655 */ 1656 .prepare = i915_pm_prepare, 1657 .suspend = i915_pm_suspend, 1658 .suspend_late = i915_pm_suspend_late, 1659 .resume_early = i915_pm_resume_early, 1660 .resume = i915_pm_resume, 1661 .complete = i915_pm_complete, 1662 1663 /* 1664 * S4 event handlers 1665 * @freeze, @freeze_late : called (1) before creating the 1666 * hibernation image [PMSG_FREEZE] and 1667 * (2) after rebooting, before restoring 1668 * the image [PMSG_QUIESCE] 1669 * @thaw, @thaw_early : called (1) after creating the hibernation 1670 * image, before writing it [PMSG_THAW] 1671 * and (2) after failing to create or 1672 * restore the image [PMSG_RECOVER] 1673 * @poweroff, @poweroff_late: called after writing the hibernation 1674 * image, before rebooting [PMSG_HIBERNATE] 1675 * @restore, @restore_early : called after rebooting and restoring the 1676 * hibernation image [PMSG_RESTORE] 1677 */ 1678 .freeze = i915_pm_freeze, 1679 .freeze_late = i915_pm_freeze_late, 1680 .thaw_early = i915_pm_thaw_early, 1681 .thaw = i915_pm_thaw, 1682 .poweroff = i915_pm_suspend, 1683 .poweroff_late = i915_pm_poweroff_late, 1684 .restore_early = i915_pm_restore_early, 1685 .restore = i915_pm_restore, 1686 1687 /* S0ix (via runtime suspend) event handlers */ 1688 .runtime_suspend = intel_runtime_suspend, 1689 .runtime_resume = intel_runtime_resume, 1690 }; 1691 1692 static const struct file_operations i915_driver_fops = { 1693 .owner = THIS_MODULE, 1694 .open = drm_open, 1695 .release = drm_release_noglobal, 1696 .unlocked_ioctl = drm_ioctl, 1697 .mmap = i915_gem_mmap, 1698 .poll = drm_poll, 1699 .read = drm_read, 1700 .compat_ioctl = i915_ioc32_compat_ioctl, 1701 .llseek = noop_llseek, 1702 #ifdef CONFIG_PROC_FS 1703 .show_fdinfo = i915_drm_client_fdinfo, 1704 #endif 1705 }; 1706 1707 static int 1708 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1709 struct drm_file *file) 1710 { 1711 return -ENODEV; 1712 } 1713 1714 static const struct drm_ioctl_desc i915_ioctls[] = { 1715 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1716 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1717 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1718 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1719 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1720 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1721 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1722 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1723 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1724 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1725 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1726 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1727 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1728 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1729 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1730 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1731 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1732 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1733 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1734 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1735 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1736 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1737 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1739 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1740 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1741 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1742 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1743 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1744 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1745 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1746 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1747 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1749 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1750 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1751 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1752 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1753 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1754 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1755 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1756 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1757 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1758 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1759 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1760 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1761 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1762 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1763 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1764 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1765 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1766 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1767 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1768 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1771 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1772 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1773 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1774 }; 1775 1776 /* 1777 * Interface history: 1778 * 1779 * 1.1: Original. 1780 * 1.2: Add Power Management 1781 * 1.3: Add vblank support 1782 * 1.4: Fix cmdbuffer path, add heap destroy 1783 * 1.5: Add vblank pipe configuration 1784 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1785 * - Support vertical blank on secondary display pipe 1786 */ 1787 #define DRIVER_MAJOR 1 1788 #define DRIVER_MINOR 6 1789 #define DRIVER_PATCHLEVEL 0 1790 1791 static const struct drm_driver i915_drm_driver = { 1792 /* Don't use MTRRs here; the Xserver or userspace app should 1793 * deal with them for Intel hardware. 1794 */ 1795 .driver_features = 1796 DRIVER_GEM | 1797 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1798 DRIVER_SYNCOBJ_TIMELINE, 1799 .release = i915_driver_release, 1800 .open = i915_driver_open, 1801 .lastclose = i915_driver_lastclose, 1802 .postclose = i915_driver_postclose, 1803 1804 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1805 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1806 .gem_prime_import = i915_gem_prime_import, 1807 1808 .dumb_create = i915_gem_dumb_create, 1809 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1810 1811 .ioctls = i915_ioctls, 1812 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1813 .fops = &i915_driver_fops, 1814 .name = DRIVER_NAME, 1815 .desc = DRIVER_DESC, 1816 .date = DRIVER_DATE, 1817 .major = DRIVER_MAJOR, 1818 .minor = DRIVER_MINOR, 1819 .patchlevel = DRIVER_PATCHLEVEL, 1820 }; 1821