1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 #include "display/skl_watermark.h" 65 66 #include "gem/i915_gem_context.h" 67 #include "gem/i915_gem_create.h" 68 #include "gem/i915_gem_dmabuf.h" 69 #include "gem/i915_gem_ioctls.h" 70 #include "gem/i915_gem_mman.h" 71 #include "gem/i915_gem_pm.h" 72 #include "gt/intel_gt.h" 73 #include "gt/intel_gt_pm.h" 74 #include "gt/intel_rc6.h" 75 76 #include "pxp/intel_pxp_pm.h" 77 78 #include "i915_file_private.h" 79 #include "i915_debugfs.h" 80 #include "i915_driver.h" 81 #include "i915_drm_client.h" 82 #include "i915_drv.h" 83 #include "i915_getparam.h" 84 #include "i915_hwmon.h" 85 #include "i915_ioc32.h" 86 #include "i915_ioctl.h" 87 #include "i915_irq.h" 88 #include "i915_memcpy.h" 89 #include "i915_perf.h" 90 #include "i915_query.h" 91 #include "i915_suspend.h" 92 #include "i915_switcheroo.h" 93 #include "i915_sysfs.h" 94 #include "i915_utils.h" 95 #include "i915_vgpu.h" 96 #include "intel_dram.h" 97 #include "intel_gvt.h" 98 #include "intel_memory_region.h" 99 #include "intel_pci_config.h" 100 #include "intel_pcode.h" 101 #include "intel_pm.h" 102 #include "intel_region_ttm.h" 103 #include "vlv_suspend.h" 104 105 /* Intel Rapid Start Technology ACPI device name */ 106 static const char irst_name[] = "INT3392"; 107 108 static const struct drm_driver i915_drm_driver; 109 110 static void i915_release_bridge_dev(struct drm_device *dev, 111 void *bridge) 112 { 113 pci_dev_put(bridge); 114 } 115 116 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 117 { 118 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 119 120 dev_priv->bridge_dev = 121 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 122 if (!dev_priv->bridge_dev) { 123 drm_err(&dev_priv->drm, "bridge device not found\n"); 124 return -EIO; 125 } 126 127 return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev, 128 dev_priv->bridge_dev); 129 } 130 131 /* Allocate space for the MCH regs if needed, return nonzero on error */ 132 static int 133 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 134 { 135 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 136 u32 temp_lo, temp_hi = 0; 137 u64 mchbar_addr; 138 int ret; 139 140 if (GRAPHICS_VER(dev_priv) >= 4) 141 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 142 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 143 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 144 145 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 146 #ifdef CONFIG_PNP 147 if (mchbar_addr && 148 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 149 return 0; 150 #endif 151 152 /* Get some space for it */ 153 dev_priv->mch_res.name = "i915 MCHBAR"; 154 dev_priv->mch_res.flags = IORESOURCE_MEM; 155 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 156 &dev_priv->mch_res, 157 MCHBAR_SIZE, MCHBAR_SIZE, 158 PCIBIOS_MIN_MEM, 159 0, pcibios_align_resource, 160 dev_priv->bridge_dev); 161 if (ret) { 162 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 163 dev_priv->mch_res.start = 0; 164 return ret; 165 } 166 167 if (GRAPHICS_VER(dev_priv) >= 4) 168 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 169 upper_32_bits(dev_priv->mch_res.start)); 170 171 pci_write_config_dword(dev_priv->bridge_dev, reg, 172 lower_32_bits(dev_priv->mch_res.start)); 173 return 0; 174 } 175 176 /* Setup MCHBAR if possible, return true if we should disable it again */ 177 static void 178 intel_setup_mchbar(struct drm_i915_private *dev_priv) 179 { 180 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 181 u32 temp; 182 bool enabled; 183 184 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 185 return; 186 187 dev_priv->mchbar_need_disable = false; 188 189 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 190 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 191 enabled = !!(temp & DEVEN_MCHBAR_EN); 192 } else { 193 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 194 enabled = temp & 1; 195 } 196 197 /* If it's already enabled, don't have to do anything */ 198 if (enabled) 199 return; 200 201 if (intel_alloc_mchbar_resource(dev_priv)) 202 return; 203 204 dev_priv->mchbar_need_disable = true; 205 206 /* Space is allocated or reserved, so enable it. */ 207 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 208 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 209 temp | DEVEN_MCHBAR_EN); 210 } else { 211 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 212 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 213 } 214 } 215 216 static void 217 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 218 { 219 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 220 221 if (dev_priv->mchbar_need_disable) { 222 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 223 u32 deven_val; 224 225 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 226 &deven_val); 227 deven_val &= ~DEVEN_MCHBAR_EN; 228 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 229 deven_val); 230 } else { 231 u32 mchbar_val; 232 233 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 234 &mchbar_val); 235 mchbar_val &= ~1; 236 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 237 mchbar_val); 238 } 239 } 240 241 if (dev_priv->mch_res.start) 242 release_resource(&dev_priv->mch_res); 243 } 244 245 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 246 { 247 /* 248 * The i915 workqueue is primarily used for batched retirement of 249 * requests (and thus managing bo) once the task has been completed 250 * by the GPU. i915_retire_requests() is called directly when we 251 * need high-priority retirement, such as waiting for an explicit 252 * bo. 253 * 254 * It is also used for periodic low-priority events, such as 255 * idle-timers and recording error state. 256 * 257 * All tasks on the workqueue are expected to acquire the dev mutex 258 * so there is no point in running more than one instance of the 259 * workqueue at any time. Use an ordered one. 260 */ 261 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 262 if (dev_priv->wq == NULL) 263 goto out_err; 264 265 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 266 if (dev_priv->display.hotplug.dp_wq == NULL) 267 goto out_free_wq; 268 269 return 0; 270 271 out_free_wq: 272 destroy_workqueue(dev_priv->wq); 273 out_err: 274 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 275 276 return -ENOMEM; 277 } 278 279 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 280 { 281 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 282 destroy_workqueue(dev_priv->wq); 283 } 284 285 /* 286 * We don't keep the workarounds for pre-production hardware, so we expect our 287 * driver to fail on these machines in one way or another. A little warning on 288 * dmesg may help both the user and the bug triagers. 289 * 290 * Our policy for removing pre-production workarounds is to keep the 291 * current gen workarounds as a guide to the bring-up of the next gen 292 * (workarounds have a habit of persisting!). Anything older than that 293 * should be removed along with the complications they introduce. 294 */ 295 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 296 { 297 bool pre = false; 298 299 pre |= IS_HSW_EARLY_SDV(dev_priv); 300 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 301 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 302 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 303 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 304 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 305 306 if (pre) { 307 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 308 "It may not be fully functional.\n"); 309 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 310 } 311 } 312 313 static void sanitize_gpu(struct drm_i915_private *i915) 314 { 315 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 316 struct intel_gt *gt; 317 unsigned int i; 318 319 for_each_gt(gt, i915, i) 320 __intel_gt_reset(gt, ALL_ENGINES); 321 } 322 } 323 324 /** 325 * i915_driver_early_probe - setup state not requiring device access 326 * @dev_priv: device private 327 * 328 * Initialize everything that is a "SW-only" state, that is state not 329 * requiring accessing the device or exposing the driver via kernel internal 330 * or userspace interfaces. Example steps belonging here: lock initialization, 331 * system memory allocation, setting up device specific attributes and 332 * function hooks not requiring accessing the device. 333 */ 334 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 335 { 336 int ret = 0; 337 338 if (i915_inject_probe_failure(dev_priv)) 339 return -ENODEV; 340 341 intel_device_info_runtime_init_early(dev_priv); 342 343 intel_step_init(dev_priv); 344 345 intel_uncore_mmio_debug_init_early(dev_priv); 346 347 spin_lock_init(&dev_priv->irq_lock); 348 spin_lock_init(&dev_priv->gpu_error.lock); 349 mutex_init(&dev_priv->display.backlight.lock); 350 351 mutex_init(&dev_priv->sb_lock); 352 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 353 354 mutex_init(&dev_priv->display.audio.mutex); 355 mutex_init(&dev_priv->display.wm.wm_mutex); 356 mutex_init(&dev_priv->display.pps.mutex); 357 mutex_init(&dev_priv->display.hdcp.comp_mutex); 358 spin_lock_init(&dev_priv->display.dkl.phy_lock); 359 360 i915_memcpy_init_early(dev_priv); 361 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 362 363 ret = i915_workqueues_init(dev_priv); 364 if (ret < 0) 365 return ret; 366 367 ret = vlv_suspend_init(dev_priv); 368 if (ret < 0) 369 goto err_workqueues; 370 371 ret = intel_region_ttm_device_init(dev_priv); 372 if (ret) 373 goto err_ttm; 374 375 ret = intel_root_gt_init_early(dev_priv); 376 if (ret < 0) 377 goto err_rootgt; 378 379 i915_drm_clients_init(&dev_priv->clients, dev_priv); 380 381 i915_gem_init_early(dev_priv); 382 383 /* This must be called before any calls to HAS_PCH_* */ 384 intel_detect_pch(dev_priv); 385 386 intel_pm_setup(dev_priv); 387 ret = intel_power_domains_init(dev_priv); 388 if (ret < 0) 389 goto err_gem; 390 intel_irq_init(dev_priv); 391 intel_init_display_hooks(dev_priv); 392 intel_init_clock_gating_hooks(dev_priv); 393 394 intel_detect_preproduction_hw(dev_priv); 395 396 return 0; 397 398 err_gem: 399 i915_gem_cleanup_early(dev_priv); 400 intel_gt_driver_late_release_all(dev_priv); 401 i915_drm_clients_fini(&dev_priv->clients); 402 err_rootgt: 403 intel_region_ttm_device_fini(dev_priv); 404 err_ttm: 405 vlv_suspend_cleanup(dev_priv); 406 err_workqueues: 407 i915_workqueues_cleanup(dev_priv); 408 return ret; 409 } 410 411 /** 412 * i915_driver_late_release - cleanup the setup done in 413 * i915_driver_early_probe() 414 * @dev_priv: device private 415 */ 416 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 417 { 418 intel_irq_fini(dev_priv); 419 intel_power_domains_cleanup(dev_priv); 420 i915_gem_cleanup_early(dev_priv); 421 intel_gt_driver_late_release_all(dev_priv); 422 i915_drm_clients_fini(&dev_priv->clients); 423 intel_region_ttm_device_fini(dev_priv); 424 vlv_suspend_cleanup(dev_priv); 425 i915_workqueues_cleanup(dev_priv); 426 427 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 428 mutex_destroy(&dev_priv->sb_lock); 429 430 i915_params_free(&dev_priv->params); 431 } 432 433 /** 434 * i915_driver_mmio_probe - setup device MMIO 435 * @dev_priv: device private 436 * 437 * Setup minimal device state necessary for MMIO accesses later in the 438 * initialization sequence. The setup here should avoid any other device-wide 439 * side effects or exposing the driver via kernel internal or user space 440 * interfaces. 441 */ 442 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 443 { 444 struct intel_gt *gt; 445 int ret, i; 446 447 if (i915_inject_probe_failure(dev_priv)) 448 return -ENODEV; 449 450 ret = i915_get_bridge_dev(dev_priv); 451 if (ret < 0) 452 return ret; 453 454 for_each_gt(gt, dev_priv, i) { 455 ret = intel_uncore_init_mmio(gt->uncore); 456 if (ret) 457 return ret; 458 459 ret = drmm_add_action_or_reset(&dev_priv->drm, 460 intel_uncore_fini_mmio, 461 gt->uncore); 462 if (ret) 463 return ret; 464 } 465 466 /* Try to make sure MCHBAR is enabled before poking at it */ 467 intel_setup_mchbar(dev_priv); 468 intel_device_info_runtime_init(dev_priv); 469 470 for_each_gt(gt, dev_priv, i) { 471 ret = intel_gt_init_mmio(gt); 472 if (ret) 473 goto err_uncore; 474 } 475 476 /* As early as possible, scrub existing GPU state before clobbering */ 477 sanitize_gpu(dev_priv); 478 479 return 0; 480 481 err_uncore: 482 intel_teardown_mchbar(dev_priv); 483 484 return ret; 485 } 486 487 /** 488 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 489 * @dev_priv: device private 490 */ 491 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 492 { 493 intel_teardown_mchbar(dev_priv); 494 } 495 496 /** 497 * i915_set_dma_info - set all relevant PCI dma info as configured for the 498 * platform 499 * @i915: valid i915 instance 500 * 501 * Set the dma max segment size, device and coherent masks. The dma mask set 502 * needs to occur before i915_ggtt_probe_hw. 503 * 504 * A couple of platforms have special needs. Address them as well. 505 * 506 */ 507 static int i915_set_dma_info(struct drm_i915_private *i915) 508 { 509 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 510 int ret; 511 512 GEM_BUG_ON(!mask_size); 513 514 /* 515 * We don't have a max segment size, so set it to the max so sg's 516 * debugging layer doesn't complain 517 */ 518 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 519 520 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 521 if (ret) 522 goto mask_err; 523 524 /* overlay on gen2 is broken and can't address above 1G */ 525 if (GRAPHICS_VER(i915) == 2) 526 mask_size = 30; 527 528 /* 529 * 965GM sometimes incorrectly writes to hardware status page (HWS) 530 * using 32bit addressing, overwriting memory if HWS is located 531 * above 4GB. 532 * 533 * The documentation also mentions an issue with undefined 534 * behaviour if any general state is accessed within a page above 4GB, 535 * which also needs to be handled carefully. 536 */ 537 if (IS_I965G(i915) || IS_I965GM(i915)) 538 mask_size = 32; 539 540 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 541 if (ret) 542 goto mask_err; 543 544 return 0; 545 546 mask_err: 547 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 548 return ret; 549 } 550 551 static int i915_pcode_init(struct drm_i915_private *i915) 552 { 553 struct intel_gt *gt; 554 int id, ret; 555 556 for_each_gt(gt, i915, id) { 557 ret = intel_pcode_init(gt->uncore); 558 if (ret) { 559 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 560 return ret; 561 } 562 } 563 564 return 0; 565 } 566 567 /** 568 * i915_driver_hw_probe - setup state requiring device access 569 * @dev_priv: device private 570 * 571 * Setup state that requires accessing the device, but doesn't require 572 * exposing the driver via kernel internal or userspace interfaces. 573 */ 574 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 575 { 576 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 577 struct pci_dev *root_pdev; 578 int ret; 579 580 if (i915_inject_probe_failure(dev_priv)) 581 return -ENODEV; 582 583 if (HAS_PPGTT(dev_priv)) { 584 if (intel_vgpu_active(dev_priv) && 585 !intel_vgpu_has_full_ppgtt(dev_priv)) { 586 i915_report_error(dev_priv, 587 "incompatible vGPU found, support for isolated ppGTT required\n"); 588 return -ENXIO; 589 } 590 } 591 592 if (HAS_EXECLISTS(dev_priv)) { 593 /* 594 * Older GVT emulation depends upon intercepting CSB mmio, 595 * which we no longer use, preferring to use the HWSP cache 596 * instead. 597 */ 598 if (intel_vgpu_active(dev_priv) && 599 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 600 i915_report_error(dev_priv, 601 "old vGPU host found, support for HWSP emulation required\n"); 602 return -ENXIO; 603 } 604 } 605 606 /* needs to be done before ggtt probe */ 607 intel_dram_edram_detect(dev_priv); 608 609 ret = i915_set_dma_info(dev_priv); 610 if (ret) 611 return ret; 612 613 i915_perf_init(dev_priv); 614 615 ret = i915_ggtt_probe_hw(dev_priv); 616 if (ret) 617 goto err_perf; 618 619 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 620 if (ret) 621 goto err_ggtt; 622 623 ret = i915_ggtt_init_hw(dev_priv); 624 if (ret) 625 goto err_ggtt; 626 627 ret = intel_memory_regions_hw_probe(dev_priv); 628 if (ret) 629 goto err_ggtt; 630 631 ret = intel_gt_tiles_init(dev_priv); 632 if (ret) 633 goto err_mem_regions; 634 635 ret = i915_ggtt_enable_hw(dev_priv); 636 if (ret) { 637 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 638 goto err_mem_regions; 639 } 640 641 pci_set_master(pdev); 642 643 /* On the 945G/GM, the chipset reports the MSI capability on the 644 * integrated graphics even though the support isn't actually there 645 * according to the published specs. It doesn't appear to function 646 * correctly in testing on 945G. 647 * This may be a side effect of MSI having been made available for PEG 648 * and the registers being closely associated. 649 * 650 * According to chipset errata, on the 965GM, MSI interrupts may 651 * be lost or delayed, and was defeatured. MSI interrupts seem to 652 * get lost on g4x as well, and interrupt delivery seems to stay 653 * properly dead afterwards. So we'll just disable them for all 654 * pre-gen5 chipsets. 655 * 656 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 657 * interrupts even when in MSI mode. This results in spurious 658 * interrupt warnings if the legacy irq no. is shared with another 659 * device. The kernel then disables that interrupt source and so 660 * prevents the other device from working properly. 661 */ 662 if (GRAPHICS_VER(dev_priv) >= 5) { 663 if (pci_enable_msi(pdev) < 0) 664 drm_dbg(&dev_priv->drm, "can't enable MSI"); 665 } 666 667 ret = intel_gvt_init(dev_priv); 668 if (ret) 669 goto err_msi; 670 671 intel_opregion_setup(dev_priv); 672 673 ret = i915_pcode_init(dev_priv); 674 if (ret) 675 goto err_msi; 676 677 /* 678 * Fill the dram structure to get the system dram info. This will be 679 * used for memory latency calculation. 680 */ 681 intel_dram_detect(dev_priv); 682 683 intel_bw_init_hw(dev_priv); 684 685 /* 686 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 687 * This should be totally removed when we handle the pci states properly 688 * on runtime PM and on s2idle cases. 689 */ 690 root_pdev = pcie_find_root_port(pdev); 691 if (root_pdev) 692 pci_d3cold_disable(root_pdev); 693 694 return 0; 695 696 err_msi: 697 if (pdev->msi_enabled) 698 pci_disable_msi(pdev); 699 err_mem_regions: 700 intel_memory_regions_driver_release(dev_priv); 701 err_ggtt: 702 i915_ggtt_driver_release(dev_priv); 703 i915_gem_drain_freed_objects(dev_priv); 704 i915_ggtt_driver_late_release(dev_priv); 705 err_perf: 706 i915_perf_fini(dev_priv); 707 return ret; 708 } 709 710 /** 711 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 712 * @dev_priv: device private 713 */ 714 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 715 { 716 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 717 struct pci_dev *root_pdev; 718 719 i915_perf_fini(dev_priv); 720 721 if (pdev->msi_enabled) 722 pci_disable_msi(pdev); 723 724 root_pdev = pcie_find_root_port(pdev); 725 if (root_pdev) 726 pci_d3cold_enable(root_pdev); 727 } 728 729 /** 730 * i915_driver_register - register the driver with the rest of the system 731 * @dev_priv: device private 732 * 733 * Perform any steps necessary to make the driver available via kernel 734 * internal or userspace interfaces. 735 */ 736 static void i915_driver_register(struct drm_i915_private *dev_priv) 737 { 738 struct intel_gt *gt; 739 unsigned int i; 740 741 i915_gem_driver_register(dev_priv); 742 i915_pmu_register(dev_priv); 743 744 intel_vgpu_register(dev_priv); 745 746 /* Reveal our presence to userspace */ 747 if (drm_dev_register(&dev_priv->drm, 0)) { 748 drm_err(&dev_priv->drm, 749 "Failed to register driver for userspace access!\n"); 750 return; 751 } 752 753 i915_debugfs_register(dev_priv); 754 i915_setup_sysfs(dev_priv); 755 756 /* Depends on sysfs having been initialized */ 757 i915_perf_register(dev_priv); 758 759 for_each_gt(gt, dev_priv, i) 760 intel_gt_driver_register(gt); 761 762 i915_hwmon_register(dev_priv); 763 764 intel_display_driver_register(dev_priv); 765 766 intel_power_domains_enable(dev_priv); 767 intel_runtime_pm_enable(&dev_priv->runtime_pm); 768 769 intel_register_dsm_handler(); 770 771 if (i915_switcheroo_register(dev_priv)) 772 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 773 } 774 775 /** 776 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 777 * @dev_priv: device private 778 */ 779 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 780 { 781 struct intel_gt *gt; 782 unsigned int i; 783 784 i915_switcheroo_unregister(dev_priv); 785 786 intel_unregister_dsm_handler(); 787 788 intel_runtime_pm_disable(&dev_priv->runtime_pm); 789 intel_power_domains_disable(dev_priv); 790 791 intel_display_driver_unregister(dev_priv); 792 793 for_each_gt(gt, dev_priv, i) 794 intel_gt_driver_unregister(gt); 795 796 i915_hwmon_unregister(dev_priv); 797 798 i915_perf_unregister(dev_priv); 799 i915_pmu_unregister(dev_priv); 800 801 i915_teardown_sysfs(dev_priv); 802 drm_dev_unplug(&dev_priv->drm); 803 804 i915_gem_driver_unregister(dev_priv); 805 } 806 807 void 808 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 809 { 810 drm_printf(p, "iommu: %s\n", 811 str_enabled_disabled(i915_vtd_active(i915))); 812 } 813 814 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 815 { 816 if (drm_debug_enabled(DRM_UT_DRIVER)) { 817 struct drm_printer p = drm_debug_printer("i915 device info:"); 818 struct intel_gt *gt; 819 unsigned int i; 820 821 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 822 INTEL_DEVID(dev_priv), 823 INTEL_REVID(dev_priv), 824 intel_platform_name(INTEL_INFO(dev_priv)->platform), 825 intel_subplatform(RUNTIME_INFO(dev_priv), 826 INTEL_INFO(dev_priv)->platform), 827 GRAPHICS_VER(dev_priv)); 828 829 intel_device_info_print(INTEL_INFO(dev_priv), 830 RUNTIME_INFO(dev_priv), &p); 831 i915_print_iommu_status(dev_priv, &p); 832 for_each_gt(gt, dev_priv, i) 833 intel_gt_info_print(>->info, &p); 834 } 835 836 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 837 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 838 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 839 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 840 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 841 drm_info(&dev_priv->drm, 842 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 843 } 844 845 static struct drm_i915_private * 846 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 847 { 848 const struct intel_device_info *match_info = 849 (struct intel_device_info *)ent->driver_data; 850 struct intel_device_info *device_info; 851 struct intel_runtime_info *runtime; 852 struct drm_i915_private *i915; 853 854 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 855 struct drm_i915_private, drm); 856 if (IS_ERR(i915)) 857 return i915; 858 859 pci_set_drvdata(pdev, i915); 860 861 /* Device parameters start as a copy of module parameters. */ 862 i915_params_copy(&i915->params, &i915_modparams); 863 864 /* Setup the write-once "constant" device info */ 865 device_info = mkwrite_device_info(i915); 866 memcpy(device_info, match_info, sizeof(*device_info)); 867 868 /* Initialize initial runtime info from static const data and pdev. */ 869 runtime = RUNTIME_INFO(i915); 870 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 871 runtime->device_id = pdev->device; 872 873 return i915; 874 } 875 876 /** 877 * i915_driver_probe - setup chip and create an initial config 878 * @pdev: PCI device 879 * @ent: matching PCI ID entry 880 * 881 * The driver probe routine has to do several things: 882 * - drive output discovery via intel_modeset_init() 883 * - initialize the memory manager 884 * - allocate initial config memory 885 * - setup the DRM framebuffer with the allocated memory 886 */ 887 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 888 { 889 struct drm_i915_private *i915; 890 int ret; 891 892 i915 = i915_driver_create(pdev, ent); 893 if (IS_ERR(i915)) 894 return PTR_ERR(i915); 895 896 ret = pci_enable_device(pdev); 897 if (ret) 898 goto out_fini; 899 900 ret = i915_driver_early_probe(i915); 901 if (ret < 0) 902 goto out_pci_disable; 903 904 disable_rpm_wakeref_asserts(&i915->runtime_pm); 905 906 intel_vgpu_detect(i915); 907 908 ret = intel_gt_probe_all(i915); 909 if (ret < 0) 910 goto out_runtime_pm_put; 911 912 ret = i915_driver_mmio_probe(i915); 913 if (ret < 0) 914 goto out_tiles_cleanup; 915 916 ret = i915_driver_hw_probe(i915); 917 if (ret < 0) 918 goto out_cleanup_mmio; 919 920 ret = intel_modeset_init_noirq(i915); 921 if (ret < 0) 922 goto out_cleanup_hw; 923 924 ret = intel_irq_install(i915); 925 if (ret) 926 goto out_cleanup_modeset; 927 928 ret = intel_modeset_init_nogem(i915); 929 if (ret) 930 goto out_cleanup_irq; 931 932 ret = i915_gem_init(i915); 933 if (ret) 934 goto out_cleanup_modeset2; 935 936 ret = intel_modeset_init(i915); 937 if (ret) 938 goto out_cleanup_gem; 939 940 i915_driver_register(i915); 941 942 enable_rpm_wakeref_asserts(&i915->runtime_pm); 943 944 i915_welcome_messages(i915); 945 946 i915->do_release = true; 947 948 return 0; 949 950 out_cleanup_gem: 951 i915_gem_suspend(i915); 952 i915_gem_driver_remove(i915); 953 i915_gem_driver_release(i915); 954 out_cleanup_modeset2: 955 /* FIXME clean up the error path */ 956 intel_modeset_driver_remove(i915); 957 intel_irq_uninstall(i915); 958 intel_modeset_driver_remove_noirq(i915); 959 goto out_cleanup_modeset; 960 out_cleanup_irq: 961 intel_irq_uninstall(i915); 962 out_cleanup_modeset: 963 intel_modeset_driver_remove_nogem(i915); 964 out_cleanup_hw: 965 i915_driver_hw_remove(i915); 966 intel_memory_regions_driver_release(i915); 967 i915_ggtt_driver_release(i915); 968 i915_gem_drain_freed_objects(i915); 969 i915_ggtt_driver_late_release(i915); 970 out_cleanup_mmio: 971 i915_driver_mmio_release(i915); 972 out_tiles_cleanup: 973 intel_gt_release_all(i915); 974 out_runtime_pm_put: 975 enable_rpm_wakeref_asserts(&i915->runtime_pm); 976 i915_driver_late_release(i915); 977 out_pci_disable: 978 pci_disable_device(pdev); 979 out_fini: 980 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 981 return ret; 982 } 983 984 void i915_driver_remove(struct drm_i915_private *i915) 985 { 986 intel_wakeref_t wakeref; 987 988 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 989 990 i915_driver_unregister(i915); 991 992 /* Flush any external code that still may be under the RCU lock */ 993 synchronize_rcu(); 994 995 i915_gem_suspend(i915); 996 997 intel_gvt_driver_remove(i915); 998 999 intel_modeset_driver_remove(i915); 1000 1001 intel_irq_uninstall(i915); 1002 1003 intel_modeset_driver_remove_noirq(i915); 1004 1005 i915_reset_error_state(i915); 1006 i915_gem_driver_remove(i915); 1007 1008 intel_modeset_driver_remove_nogem(i915); 1009 1010 i915_driver_hw_remove(i915); 1011 1012 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 1013 } 1014 1015 static void i915_driver_release(struct drm_device *dev) 1016 { 1017 struct drm_i915_private *dev_priv = to_i915(dev); 1018 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1019 intel_wakeref_t wakeref; 1020 1021 if (!dev_priv->do_release) 1022 return; 1023 1024 wakeref = intel_runtime_pm_get(rpm); 1025 1026 i915_gem_driver_release(dev_priv); 1027 1028 intel_memory_regions_driver_release(dev_priv); 1029 i915_ggtt_driver_release(dev_priv); 1030 i915_gem_drain_freed_objects(dev_priv); 1031 i915_ggtt_driver_late_release(dev_priv); 1032 1033 i915_driver_mmio_release(dev_priv); 1034 1035 intel_runtime_pm_put(rpm, wakeref); 1036 1037 intel_runtime_pm_driver_release(rpm); 1038 1039 i915_driver_late_release(dev_priv); 1040 } 1041 1042 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1043 { 1044 struct drm_i915_private *i915 = to_i915(dev); 1045 int ret; 1046 1047 ret = i915_gem_open(i915, file); 1048 if (ret) 1049 return ret; 1050 1051 return 0; 1052 } 1053 1054 /** 1055 * i915_driver_lastclose - clean up after all DRM clients have exited 1056 * @dev: DRM device 1057 * 1058 * Take care of cleaning up after all DRM clients have exited. In the 1059 * mode setting case, we want to restore the kernel's initial mode (just 1060 * in case the last client left us in a bad state). 1061 * 1062 * Additionally, in the non-mode setting case, we'll tear down the GTT 1063 * and DMA structures, since the kernel won't be using them, and clea 1064 * up any GEM state. 1065 */ 1066 static void i915_driver_lastclose(struct drm_device *dev) 1067 { 1068 struct drm_i915_private *i915 = to_i915(dev); 1069 1070 intel_fbdev_restore_mode(dev); 1071 1072 if (HAS_DISPLAY(i915)) 1073 vga_switcheroo_process_delayed_switch(); 1074 } 1075 1076 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1077 { 1078 struct drm_i915_file_private *file_priv = file->driver_priv; 1079 1080 i915_gem_context_close(file); 1081 i915_drm_client_put(file_priv->client); 1082 1083 kfree_rcu(file_priv, rcu); 1084 1085 /* Catch up with all the deferred frees from "this" client */ 1086 i915_gem_flush_free_objects(to_i915(dev)); 1087 } 1088 1089 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1090 { 1091 struct intel_encoder *encoder; 1092 1093 if (!HAS_DISPLAY(dev_priv)) 1094 return; 1095 1096 drm_modeset_lock_all(&dev_priv->drm); 1097 for_each_intel_encoder(&dev_priv->drm, encoder) 1098 if (encoder->suspend) 1099 encoder->suspend(encoder); 1100 drm_modeset_unlock_all(&dev_priv->drm); 1101 } 1102 1103 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1104 { 1105 struct intel_encoder *encoder; 1106 1107 if (!HAS_DISPLAY(dev_priv)) 1108 return; 1109 1110 drm_modeset_lock_all(&dev_priv->drm); 1111 for_each_intel_encoder(&dev_priv->drm, encoder) 1112 if (encoder->shutdown) 1113 encoder->shutdown(encoder); 1114 drm_modeset_unlock_all(&dev_priv->drm); 1115 } 1116 1117 void i915_driver_shutdown(struct drm_i915_private *i915) 1118 { 1119 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1120 intel_runtime_pm_disable(&i915->runtime_pm); 1121 intel_power_domains_disable(i915); 1122 1123 if (HAS_DISPLAY(i915)) { 1124 drm_kms_helper_poll_disable(&i915->drm); 1125 1126 drm_atomic_helper_shutdown(&i915->drm); 1127 } 1128 1129 intel_dp_mst_suspend(i915); 1130 1131 intel_runtime_pm_disable_interrupts(i915); 1132 intel_hpd_cancel_work(i915); 1133 1134 intel_suspend_encoders(i915); 1135 intel_shutdown_encoders(i915); 1136 1137 intel_dmc_ucode_suspend(i915); 1138 1139 i915_gem_suspend(i915); 1140 1141 /* 1142 * The only requirement is to reboot with display DC states disabled, 1143 * for now leaving all display power wells in the INIT power domain 1144 * enabled. 1145 * 1146 * TODO: 1147 * - unify the pci_driver::shutdown sequence here with the 1148 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1149 * - unify the driver remove and system/runtime suspend sequences with 1150 * the above unified shutdown/poweroff sequence. 1151 */ 1152 intel_power_domains_driver_remove(i915); 1153 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1154 1155 intel_runtime_pm_driver_release(&i915->runtime_pm); 1156 } 1157 1158 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1159 { 1160 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1161 if (acpi_target_system_state() < ACPI_STATE_S3) 1162 return true; 1163 #endif 1164 return false; 1165 } 1166 1167 static int i915_drm_prepare(struct drm_device *dev) 1168 { 1169 struct drm_i915_private *i915 = to_i915(dev); 1170 1171 /* 1172 * NB intel_display_suspend() may issue new requests after we've 1173 * ostensibly marked the GPU as ready-to-sleep here. We need to 1174 * split out that work and pull it forward so that after point, 1175 * the GPU is not woken again. 1176 */ 1177 return i915_gem_backup_suspend(i915); 1178 } 1179 1180 static int i915_drm_suspend(struct drm_device *dev) 1181 { 1182 struct drm_i915_private *dev_priv = to_i915(dev); 1183 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1184 pci_power_t opregion_target_state; 1185 1186 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1187 1188 /* We do a lot of poking in a lot of registers, make sure they work 1189 * properly. */ 1190 intel_power_domains_disable(dev_priv); 1191 if (HAS_DISPLAY(dev_priv)) 1192 drm_kms_helper_poll_disable(dev); 1193 1194 pci_save_state(pdev); 1195 1196 intel_display_suspend(dev); 1197 1198 intel_dp_mst_suspend(dev_priv); 1199 1200 intel_runtime_pm_disable_interrupts(dev_priv); 1201 intel_hpd_cancel_work(dev_priv); 1202 1203 intel_suspend_encoders(dev_priv); 1204 1205 intel_suspend_hw(dev_priv); 1206 1207 /* Must be called before GGTT is suspended. */ 1208 intel_dpt_suspend(dev_priv); 1209 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1210 1211 i915_save_display(dev_priv); 1212 1213 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1214 intel_opregion_suspend(dev_priv, opregion_target_state); 1215 1216 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1217 1218 dev_priv->suspend_count++; 1219 1220 intel_dmc_ucode_suspend(dev_priv); 1221 1222 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1223 1224 i915_gem_drain_freed_objects(dev_priv); 1225 1226 return 0; 1227 } 1228 1229 static enum i915_drm_suspend_mode 1230 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1231 { 1232 if (hibernate) 1233 return I915_DRM_SUSPEND_HIBERNATE; 1234 1235 if (suspend_to_idle(dev_priv)) 1236 return I915_DRM_SUSPEND_IDLE; 1237 1238 return I915_DRM_SUSPEND_MEM; 1239 } 1240 1241 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1242 { 1243 struct drm_i915_private *dev_priv = to_i915(dev); 1244 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1245 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1246 struct intel_gt *gt; 1247 int ret, i; 1248 1249 disable_rpm_wakeref_asserts(rpm); 1250 1251 i915_gem_suspend_late(dev_priv); 1252 1253 for_each_gt(gt, dev_priv, i) 1254 intel_uncore_suspend(gt->uncore); 1255 1256 intel_power_domains_suspend(dev_priv, 1257 get_suspend_mode(dev_priv, hibernation)); 1258 1259 intel_display_power_suspend_late(dev_priv); 1260 1261 ret = vlv_suspend_complete(dev_priv); 1262 if (ret) { 1263 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1264 intel_power_domains_resume(dev_priv); 1265 1266 goto out; 1267 } 1268 1269 pci_disable_device(pdev); 1270 /* 1271 * During hibernation on some platforms the BIOS may try to access 1272 * the device even though it's already in D3 and hang the machine. So 1273 * leave the device in D0 on those platforms and hope the BIOS will 1274 * power down the device properly. The issue was seen on multiple old 1275 * GENs with different BIOS vendors, so having an explicit blacklist 1276 * is inpractical; apply the workaround on everything pre GEN6. The 1277 * platforms where the issue was seen: 1278 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1279 * Fujitsu FSC S7110 1280 * Acer Aspire 1830T 1281 */ 1282 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1283 pci_set_power_state(pdev, PCI_D3hot); 1284 1285 out: 1286 enable_rpm_wakeref_asserts(rpm); 1287 if (!dev_priv->uncore.user_forcewake_count) 1288 intel_runtime_pm_driver_release(rpm); 1289 1290 return ret; 1291 } 1292 1293 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1294 pm_message_t state) 1295 { 1296 int error; 1297 1298 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1299 state.event != PM_EVENT_FREEZE)) 1300 return -EINVAL; 1301 1302 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1303 return 0; 1304 1305 error = i915_drm_suspend(&i915->drm); 1306 if (error) 1307 return error; 1308 1309 return i915_drm_suspend_late(&i915->drm, false); 1310 } 1311 1312 static int i915_drm_resume(struct drm_device *dev) 1313 { 1314 struct drm_i915_private *dev_priv = to_i915(dev); 1315 struct intel_gt *gt; 1316 int ret, i; 1317 1318 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1319 1320 ret = i915_pcode_init(dev_priv); 1321 if (ret) 1322 return ret; 1323 1324 sanitize_gpu(dev_priv); 1325 1326 ret = i915_ggtt_enable_hw(dev_priv); 1327 if (ret) 1328 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1329 1330 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1331 1332 for_each_gt(gt, dev_priv, i) 1333 if (GRAPHICS_VER(gt->i915) >= 8) 1334 setup_private_pat(gt); 1335 1336 /* Must be called after GGTT is resumed. */ 1337 intel_dpt_resume(dev_priv); 1338 1339 intel_dmc_ucode_resume(dev_priv); 1340 1341 i915_restore_display(dev_priv); 1342 intel_pps_unlock_regs_wa(dev_priv); 1343 1344 intel_init_pch_refclk(dev_priv); 1345 1346 /* 1347 * Interrupts have to be enabled before any batches are run. If not the 1348 * GPU will hang. i915_gem_init_hw() will initiate batches to 1349 * update/restore the context. 1350 * 1351 * drm_mode_config_reset() needs AUX interrupts. 1352 * 1353 * Modeset enabling in intel_modeset_init_hw() also needs working 1354 * interrupts. 1355 */ 1356 intel_runtime_pm_enable_interrupts(dev_priv); 1357 1358 if (HAS_DISPLAY(dev_priv)) 1359 drm_mode_config_reset(dev); 1360 1361 i915_gem_resume(dev_priv); 1362 1363 intel_modeset_init_hw(dev_priv); 1364 intel_init_clock_gating(dev_priv); 1365 intel_hpd_init(dev_priv); 1366 1367 /* MST sideband requires HPD interrupts enabled */ 1368 intel_dp_mst_resume(dev_priv); 1369 intel_display_resume(dev); 1370 1371 intel_hpd_poll_disable(dev_priv); 1372 if (HAS_DISPLAY(dev_priv)) 1373 drm_kms_helper_poll_enable(dev); 1374 1375 intel_opregion_resume(dev_priv); 1376 1377 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1378 1379 intel_power_domains_enable(dev_priv); 1380 1381 intel_gvt_resume(dev_priv); 1382 1383 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1384 1385 return 0; 1386 } 1387 1388 static int i915_drm_resume_early(struct drm_device *dev) 1389 { 1390 struct drm_i915_private *dev_priv = to_i915(dev); 1391 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1392 struct intel_gt *gt; 1393 int ret, i; 1394 1395 /* 1396 * We have a resume ordering issue with the snd-hda driver also 1397 * requiring our device to be power up. Due to the lack of a 1398 * parent/child relationship we currently solve this with an early 1399 * resume hook. 1400 * 1401 * FIXME: This should be solved with a special hdmi sink device or 1402 * similar so that power domains can be employed. 1403 */ 1404 1405 /* 1406 * Note that we need to set the power state explicitly, since we 1407 * powered off the device during freeze and the PCI core won't power 1408 * it back up for us during thaw. Powering off the device during 1409 * freeze is not a hard requirement though, and during the 1410 * suspend/resume phases the PCI core makes sure we get here with the 1411 * device powered on. So in case we change our freeze logic and keep 1412 * the device powered we can also remove the following set power state 1413 * call. 1414 */ 1415 ret = pci_set_power_state(pdev, PCI_D0); 1416 if (ret) { 1417 drm_err(&dev_priv->drm, 1418 "failed to set PCI D0 power state (%d)\n", ret); 1419 return ret; 1420 } 1421 1422 /* 1423 * Note that pci_enable_device() first enables any parent bridge 1424 * device and only then sets the power state for this device. The 1425 * bridge enabling is a nop though, since bridge devices are resumed 1426 * first. The order of enabling power and enabling the device is 1427 * imposed by the PCI core as described above, so here we preserve the 1428 * same order for the freeze/thaw phases. 1429 * 1430 * TODO: eventually we should remove pci_disable_device() / 1431 * pci_enable_enable_device() from suspend/resume. Due to how they 1432 * depend on the device enable refcount we can't anyway depend on them 1433 * disabling/enabling the device. 1434 */ 1435 if (pci_enable_device(pdev)) 1436 return -EIO; 1437 1438 pci_set_master(pdev); 1439 1440 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1441 1442 ret = vlv_resume_prepare(dev_priv, false); 1443 if (ret) 1444 drm_err(&dev_priv->drm, 1445 "Resume prepare failed: %d, continuing anyway\n", ret); 1446 1447 for_each_gt(gt, dev_priv, i) { 1448 intel_uncore_resume_early(gt->uncore); 1449 intel_gt_check_and_clear_faults(gt); 1450 } 1451 1452 intel_display_power_resume_early(dev_priv); 1453 1454 intel_power_domains_resume(dev_priv); 1455 1456 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1457 1458 return ret; 1459 } 1460 1461 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1462 { 1463 int ret; 1464 1465 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1466 return 0; 1467 1468 ret = i915_drm_resume_early(&i915->drm); 1469 if (ret) 1470 return ret; 1471 1472 return i915_drm_resume(&i915->drm); 1473 } 1474 1475 static int i915_pm_prepare(struct device *kdev) 1476 { 1477 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1478 1479 if (!i915) { 1480 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1481 return -ENODEV; 1482 } 1483 1484 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1485 return 0; 1486 1487 return i915_drm_prepare(&i915->drm); 1488 } 1489 1490 static int i915_pm_suspend(struct device *kdev) 1491 { 1492 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1493 1494 if (!i915) { 1495 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1496 return -ENODEV; 1497 } 1498 1499 i915_ggtt_mark_pte_lost(i915, false); 1500 1501 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1502 return 0; 1503 1504 return i915_drm_suspend(&i915->drm); 1505 } 1506 1507 static int i915_pm_suspend_late(struct device *kdev) 1508 { 1509 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1510 1511 /* 1512 * We have a suspend ordering issue with the snd-hda driver also 1513 * requiring our device to be power up. Due to the lack of a 1514 * parent/child relationship we currently solve this with an late 1515 * suspend hook. 1516 * 1517 * FIXME: This should be solved with a special hdmi sink device or 1518 * similar so that power domains can be employed. 1519 */ 1520 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1521 return 0; 1522 1523 return i915_drm_suspend_late(&i915->drm, false); 1524 } 1525 1526 static int i915_pm_poweroff_late(struct device *kdev) 1527 { 1528 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1529 1530 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1531 return 0; 1532 1533 return i915_drm_suspend_late(&i915->drm, true); 1534 } 1535 1536 static int i915_pm_resume_early(struct device *kdev) 1537 { 1538 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1539 1540 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1541 return 0; 1542 1543 return i915_drm_resume_early(&i915->drm); 1544 } 1545 1546 static int i915_pm_resume(struct device *kdev) 1547 { 1548 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1549 1550 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1551 return 0; 1552 1553 /* 1554 * If IRST is enabled, or if we can't detect whether it's enabled, 1555 * then we must assume we lost the GGTT page table entries, since 1556 * they are not retained if IRST decided to enter S4. 1557 */ 1558 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1)) 1559 i915_ggtt_mark_pte_lost(i915, true); 1560 1561 return i915_drm_resume(&i915->drm); 1562 } 1563 1564 /* freeze: before creating the hibernation_image */ 1565 static int i915_pm_freeze(struct device *kdev) 1566 { 1567 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1568 int ret; 1569 1570 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1571 ret = i915_drm_suspend(&i915->drm); 1572 if (ret) 1573 return ret; 1574 } 1575 1576 ret = i915_gem_freeze(i915); 1577 if (ret) 1578 return ret; 1579 1580 return 0; 1581 } 1582 1583 static int i915_pm_freeze_late(struct device *kdev) 1584 { 1585 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1586 int ret; 1587 1588 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1589 ret = i915_drm_suspend_late(&i915->drm, true); 1590 if (ret) 1591 return ret; 1592 } 1593 1594 ret = i915_gem_freeze_late(i915); 1595 if (ret) 1596 return ret; 1597 1598 return 0; 1599 } 1600 1601 /* thaw: called after creating the hibernation image, but before turning off. */ 1602 static int i915_pm_thaw_early(struct device *kdev) 1603 { 1604 return i915_pm_resume_early(kdev); 1605 } 1606 1607 static int i915_pm_thaw(struct device *kdev) 1608 { 1609 return i915_pm_resume(kdev); 1610 } 1611 1612 /* restore: called after loading the hibernation image. */ 1613 static int i915_pm_restore_early(struct device *kdev) 1614 { 1615 return i915_pm_resume_early(kdev); 1616 } 1617 1618 static int i915_pm_restore(struct device *kdev) 1619 { 1620 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1621 1622 i915_ggtt_mark_pte_lost(i915, true); 1623 return i915_pm_resume(kdev); 1624 } 1625 1626 static int intel_runtime_suspend(struct device *kdev) 1627 { 1628 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1629 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1630 struct intel_gt *gt; 1631 int ret, i; 1632 1633 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1634 return -ENODEV; 1635 1636 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1637 1638 disable_rpm_wakeref_asserts(rpm); 1639 1640 /* 1641 * We are safe here against re-faults, since the fault handler takes 1642 * an RPM reference. 1643 */ 1644 i915_gem_runtime_suspend(dev_priv); 1645 1646 for_each_gt(gt, dev_priv, i) 1647 intel_gt_runtime_suspend(gt); 1648 1649 intel_runtime_pm_disable_interrupts(dev_priv); 1650 1651 for_each_gt(gt, dev_priv, i) 1652 intel_uncore_suspend(gt->uncore); 1653 1654 intel_display_power_suspend(dev_priv); 1655 1656 ret = vlv_suspend_complete(dev_priv); 1657 if (ret) { 1658 drm_err(&dev_priv->drm, 1659 "Runtime suspend failed, disabling it (%d)\n", ret); 1660 intel_uncore_runtime_resume(&dev_priv->uncore); 1661 1662 intel_runtime_pm_enable_interrupts(dev_priv); 1663 1664 for_each_gt(gt, dev_priv, i) 1665 intel_gt_runtime_resume(gt); 1666 1667 enable_rpm_wakeref_asserts(rpm); 1668 1669 return ret; 1670 } 1671 1672 enable_rpm_wakeref_asserts(rpm); 1673 intel_runtime_pm_driver_release(rpm); 1674 1675 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1676 drm_err(&dev_priv->drm, 1677 "Unclaimed access detected prior to suspending\n"); 1678 1679 rpm->suspended = true; 1680 1681 /* 1682 * FIXME: We really should find a document that references the arguments 1683 * used below! 1684 */ 1685 if (IS_BROADWELL(dev_priv)) { 1686 /* 1687 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1688 * being detected, and the call we do at intel_runtime_resume() 1689 * won't be able to restore them. Since PCI_D3hot matches the 1690 * actual specification and appears to be working, use it. 1691 */ 1692 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1693 } else { 1694 /* 1695 * current versions of firmware which depend on this opregion 1696 * notification have repurposed the D1 definition to mean 1697 * "runtime suspended" vs. what you would normally expect (D3) 1698 * to distinguish it from notifications that might be sent via 1699 * the suspend path. 1700 */ 1701 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1702 } 1703 1704 assert_forcewakes_inactive(&dev_priv->uncore); 1705 1706 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1707 intel_hpd_poll_enable(dev_priv); 1708 1709 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1710 return 0; 1711 } 1712 1713 static int intel_runtime_resume(struct device *kdev) 1714 { 1715 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1716 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1717 struct intel_gt *gt; 1718 int ret, i; 1719 1720 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1721 return -ENODEV; 1722 1723 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1724 1725 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1726 disable_rpm_wakeref_asserts(rpm); 1727 1728 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1729 rpm->suspended = false; 1730 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1731 drm_dbg(&dev_priv->drm, 1732 "Unclaimed access during suspend, bios?\n"); 1733 1734 intel_display_power_resume(dev_priv); 1735 1736 ret = vlv_resume_prepare(dev_priv, true); 1737 1738 for_each_gt(gt, dev_priv, i) 1739 intel_uncore_runtime_resume(gt->uncore); 1740 1741 intel_runtime_pm_enable_interrupts(dev_priv); 1742 1743 /* 1744 * No point of rolling back things in case of an error, as the best 1745 * we can do is to hope that things will still work (and disable RPM). 1746 */ 1747 for_each_gt(gt, dev_priv, i) 1748 intel_gt_runtime_resume(gt); 1749 1750 /* 1751 * On VLV/CHV display interrupts are part of the display 1752 * power well, so hpd is reinitialized from there. For 1753 * everyone else do it here. 1754 */ 1755 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1756 intel_hpd_init(dev_priv); 1757 intel_hpd_poll_disable(dev_priv); 1758 } 1759 1760 skl_watermark_ipc_update(dev_priv); 1761 1762 enable_rpm_wakeref_asserts(rpm); 1763 1764 if (ret) 1765 drm_err(&dev_priv->drm, 1766 "Runtime resume failed, disabling it (%d)\n", ret); 1767 else 1768 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1769 1770 return ret; 1771 } 1772 1773 const struct dev_pm_ops i915_pm_ops = { 1774 /* 1775 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1776 * PMSG_RESUME] 1777 */ 1778 .prepare = i915_pm_prepare, 1779 .suspend = i915_pm_suspend, 1780 .suspend_late = i915_pm_suspend_late, 1781 .resume_early = i915_pm_resume_early, 1782 .resume = i915_pm_resume, 1783 1784 /* 1785 * S4 event handlers 1786 * @freeze, @freeze_late : called (1) before creating the 1787 * hibernation image [PMSG_FREEZE] and 1788 * (2) after rebooting, before restoring 1789 * the image [PMSG_QUIESCE] 1790 * @thaw, @thaw_early : called (1) after creating the hibernation 1791 * image, before writing it [PMSG_THAW] 1792 * and (2) after failing to create or 1793 * restore the image [PMSG_RECOVER] 1794 * @poweroff, @poweroff_late: called after writing the hibernation 1795 * image, before rebooting [PMSG_HIBERNATE] 1796 * @restore, @restore_early : called after rebooting and restoring the 1797 * hibernation image [PMSG_RESTORE] 1798 */ 1799 .freeze = i915_pm_freeze, 1800 .freeze_late = i915_pm_freeze_late, 1801 .thaw_early = i915_pm_thaw_early, 1802 .thaw = i915_pm_thaw, 1803 .poweroff = i915_pm_suspend, 1804 .poweroff_late = i915_pm_poweroff_late, 1805 .restore_early = i915_pm_restore_early, 1806 .restore = i915_pm_restore, 1807 1808 /* S0ix (via runtime suspend) event handlers */ 1809 .runtime_suspend = intel_runtime_suspend, 1810 .runtime_resume = intel_runtime_resume, 1811 }; 1812 1813 static const struct file_operations i915_driver_fops = { 1814 .owner = THIS_MODULE, 1815 .open = drm_open, 1816 .release = drm_release_noglobal, 1817 .unlocked_ioctl = drm_ioctl, 1818 .mmap = i915_gem_mmap, 1819 .poll = drm_poll, 1820 .read = drm_read, 1821 .compat_ioctl = i915_ioc32_compat_ioctl, 1822 .llseek = noop_llseek, 1823 #ifdef CONFIG_PROC_FS 1824 .show_fdinfo = i915_drm_client_fdinfo, 1825 #endif 1826 }; 1827 1828 static int 1829 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1830 struct drm_file *file) 1831 { 1832 return -ENODEV; 1833 } 1834 1835 static const struct drm_ioctl_desc i915_ioctls[] = { 1836 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1837 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1838 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1839 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1840 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1841 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1842 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1843 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1844 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1845 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1846 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1847 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1848 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1849 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1850 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1851 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1852 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1853 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1854 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1855 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1856 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1857 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1858 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1859 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1860 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1861 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1862 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1863 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1864 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1865 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1866 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1867 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1868 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1869 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1870 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1871 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1872 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1874 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1875 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1876 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1877 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1878 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1879 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1880 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1881 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1882 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1883 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1884 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1885 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1886 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1887 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1888 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1889 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1890 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1891 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1892 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1893 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1894 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1895 }; 1896 1897 /* 1898 * Interface history: 1899 * 1900 * 1.1: Original. 1901 * 1.2: Add Power Management 1902 * 1.3: Add vblank support 1903 * 1.4: Fix cmdbuffer path, add heap destroy 1904 * 1.5: Add vblank pipe configuration 1905 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1906 * - Support vertical blank on secondary display pipe 1907 */ 1908 #define DRIVER_MAJOR 1 1909 #define DRIVER_MINOR 6 1910 #define DRIVER_PATCHLEVEL 0 1911 1912 static const struct drm_driver i915_drm_driver = { 1913 /* Don't use MTRRs here; the Xserver or userspace app should 1914 * deal with them for Intel hardware. 1915 */ 1916 .driver_features = 1917 DRIVER_GEM | 1918 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1919 DRIVER_SYNCOBJ_TIMELINE, 1920 .release = i915_driver_release, 1921 .open = i915_driver_open, 1922 .lastclose = i915_driver_lastclose, 1923 .postclose = i915_driver_postclose, 1924 1925 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1926 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1927 .gem_prime_import = i915_gem_prime_import, 1928 1929 .dumb_create = i915_gem_dumb_create, 1930 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1931 1932 .ioctls = i915_ioctls, 1933 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1934 .fops = &i915_driver_fops, 1935 .name = DRIVER_NAME, 1936 .desc = DRIVER_DESC, 1937 .date = DRIVER_DATE, 1938 .major = DRIVER_MAJOR, 1939 .minor = DRIVER_MINOR, 1940 .patchlevel = DRIVER_PATCHLEVEL, 1941 }; 1942