1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 #include "display/skl_watermark.h" 65 66 #include "gem/i915_gem_context.h" 67 #include "gem/i915_gem_create.h" 68 #include "gem/i915_gem_dmabuf.h" 69 #include "gem/i915_gem_ioctls.h" 70 #include "gem/i915_gem_mman.h" 71 #include "gem/i915_gem_pm.h" 72 #include "gt/intel_gt.h" 73 #include "gt/intel_gt_pm.h" 74 #include "gt/intel_rc6.h" 75 76 #include "pxp/intel_pxp_pm.h" 77 78 #include "i915_file_private.h" 79 #include "i915_debugfs.h" 80 #include "i915_driver.h" 81 #include "i915_drm_client.h" 82 #include "i915_drv.h" 83 #include "i915_getparam.h" 84 #include "i915_ioc32.h" 85 #include "i915_ioctl.h" 86 #include "i915_irq.h" 87 #include "i915_memcpy.h" 88 #include "i915_perf.h" 89 #include "i915_query.h" 90 #include "i915_suspend.h" 91 #include "i915_switcheroo.h" 92 #include "i915_sysfs.h" 93 #include "i915_utils.h" 94 #include "i915_vgpu.h" 95 #include "intel_dram.h" 96 #include "intel_gvt.h" 97 #include "intel_memory_region.h" 98 #include "intel_pci_config.h" 99 #include "intel_pcode.h" 100 #include "intel_pm.h" 101 #include "intel_region_ttm.h" 102 #include "vlv_suspend.h" 103 104 /* Intel Rapid Start Technology ACPI device name */ 105 static const char irst_name[] = "INT3392"; 106 107 static const struct drm_driver i915_drm_driver; 108 109 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 110 { 111 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 112 113 dev_priv->bridge_dev = 114 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 115 if (!dev_priv->bridge_dev) { 116 drm_err(&dev_priv->drm, "bridge device not found\n"); 117 return -EIO; 118 } 119 return 0; 120 } 121 122 /* Allocate space for the MCH regs if needed, return nonzero on error */ 123 static int 124 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 125 { 126 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 127 u32 temp_lo, temp_hi = 0; 128 u64 mchbar_addr; 129 int ret; 130 131 if (GRAPHICS_VER(dev_priv) >= 4) 132 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 133 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 134 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 135 136 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 137 #ifdef CONFIG_PNP 138 if (mchbar_addr && 139 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 140 return 0; 141 #endif 142 143 /* Get some space for it */ 144 dev_priv->mch_res.name = "i915 MCHBAR"; 145 dev_priv->mch_res.flags = IORESOURCE_MEM; 146 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 147 &dev_priv->mch_res, 148 MCHBAR_SIZE, MCHBAR_SIZE, 149 PCIBIOS_MIN_MEM, 150 0, pcibios_align_resource, 151 dev_priv->bridge_dev); 152 if (ret) { 153 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 154 dev_priv->mch_res.start = 0; 155 return ret; 156 } 157 158 if (GRAPHICS_VER(dev_priv) >= 4) 159 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 160 upper_32_bits(dev_priv->mch_res.start)); 161 162 pci_write_config_dword(dev_priv->bridge_dev, reg, 163 lower_32_bits(dev_priv->mch_res.start)); 164 return 0; 165 } 166 167 /* Setup MCHBAR if possible, return true if we should disable it again */ 168 static void 169 intel_setup_mchbar(struct drm_i915_private *dev_priv) 170 { 171 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 172 u32 temp; 173 bool enabled; 174 175 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 176 return; 177 178 dev_priv->mchbar_need_disable = false; 179 180 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 181 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 182 enabled = !!(temp & DEVEN_MCHBAR_EN); 183 } else { 184 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 185 enabled = temp & 1; 186 } 187 188 /* If it's already enabled, don't have to do anything */ 189 if (enabled) 190 return; 191 192 if (intel_alloc_mchbar_resource(dev_priv)) 193 return; 194 195 dev_priv->mchbar_need_disable = true; 196 197 /* Space is allocated or reserved, so enable it. */ 198 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 199 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 200 temp | DEVEN_MCHBAR_EN); 201 } else { 202 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 203 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 204 } 205 } 206 207 static void 208 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 209 { 210 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 211 212 if (dev_priv->mchbar_need_disable) { 213 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 214 u32 deven_val; 215 216 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 217 &deven_val); 218 deven_val &= ~DEVEN_MCHBAR_EN; 219 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 220 deven_val); 221 } else { 222 u32 mchbar_val; 223 224 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 225 &mchbar_val); 226 mchbar_val &= ~1; 227 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 228 mchbar_val); 229 } 230 } 231 232 if (dev_priv->mch_res.start) 233 release_resource(&dev_priv->mch_res); 234 } 235 236 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 237 { 238 /* 239 * The i915 workqueue is primarily used for batched retirement of 240 * requests (and thus managing bo) once the task has been completed 241 * by the GPU. i915_retire_requests() is called directly when we 242 * need high-priority retirement, such as waiting for an explicit 243 * bo. 244 * 245 * It is also used for periodic low-priority events, such as 246 * idle-timers and recording error state. 247 * 248 * All tasks on the workqueue are expected to acquire the dev mutex 249 * so there is no point in running more than one instance of the 250 * workqueue at any time. Use an ordered one. 251 */ 252 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 253 if (dev_priv->wq == NULL) 254 goto out_err; 255 256 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 257 if (dev_priv->display.hotplug.dp_wq == NULL) 258 goto out_free_wq; 259 260 return 0; 261 262 out_free_wq: 263 destroy_workqueue(dev_priv->wq); 264 out_err: 265 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 266 267 return -ENOMEM; 268 } 269 270 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 271 { 272 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 273 destroy_workqueue(dev_priv->wq); 274 } 275 276 /* 277 * We don't keep the workarounds for pre-production hardware, so we expect our 278 * driver to fail on these machines in one way or another. A little warning on 279 * dmesg may help both the user and the bug triagers. 280 * 281 * Our policy for removing pre-production workarounds is to keep the 282 * current gen workarounds as a guide to the bring-up of the next gen 283 * (workarounds have a habit of persisting!). Anything older than that 284 * should be removed along with the complications they introduce. 285 */ 286 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 287 { 288 bool pre = false; 289 290 pre |= IS_HSW_EARLY_SDV(dev_priv); 291 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 292 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 293 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 294 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 295 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 296 297 if (pre) { 298 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 299 "It may not be fully functional.\n"); 300 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 301 } 302 } 303 304 static void sanitize_gpu(struct drm_i915_private *i915) 305 { 306 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 307 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 308 } 309 310 /** 311 * i915_driver_early_probe - setup state not requiring device access 312 * @dev_priv: device private 313 * 314 * Initialize everything that is a "SW-only" state, that is state not 315 * requiring accessing the device or exposing the driver via kernel internal 316 * or userspace interfaces. Example steps belonging here: lock initialization, 317 * system memory allocation, setting up device specific attributes and 318 * function hooks not requiring accessing the device. 319 */ 320 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 321 { 322 int ret = 0; 323 324 if (i915_inject_probe_failure(dev_priv)) 325 return -ENODEV; 326 327 intel_device_info_runtime_init_early(dev_priv); 328 329 intel_step_init(dev_priv); 330 331 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 332 333 spin_lock_init(&dev_priv->irq_lock); 334 spin_lock_init(&dev_priv->gpu_error.lock); 335 mutex_init(&dev_priv->display.backlight.lock); 336 337 mutex_init(&dev_priv->sb_lock); 338 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 339 340 mutex_init(&dev_priv->display.audio.mutex); 341 mutex_init(&dev_priv->display.wm.wm_mutex); 342 mutex_init(&dev_priv->display.pps.mutex); 343 mutex_init(&dev_priv->display.hdcp.comp_mutex); 344 spin_lock_init(&dev_priv->display.dkl.phy_lock); 345 346 i915_memcpy_init_early(dev_priv); 347 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 348 349 ret = i915_workqueues_init(dev_priv); 350 if (ret < 0) 351 return ret; 352 353 ret = vlv_suspend_init(dev_priv); 354 if (ret < 0) 355 goto err_workqueues; 356 357 ret = intel_region_ttm_device_init(dev_priv); 358 if (ret) 359 goto err_ttm; 360 361 intel_wopcm_init_early(&dev_priv->wopcm); 362 363 intel_root_gt_init_early(dev_priv); 364 365 i915_drm_clients_init(&dev_priv->clients, dev_priv); 366 367 i915_gem_init_early(dev_priv); 368 369 /* This must be called before any calls to HAS_PCH_* */ 370 intel_detect_pch(dev_priv); 371 372 intel_pm_setup(dev_priv); 373 ret = intel_power_domains_init(dev_priv); 374 if (ret < 0) 375 goto err_gem; 376 intel_irq_init(dev_priv); 377 intel_init_display_hooks(dev_priv); 378 intel_init_clock_gating_hooks(dev_priv); 379 380 intel_detect_preproduction_hw(dev_priv); 381 382 return 0; 383 384 err_gem: 385 i915_gem_cleanup_early(dev_priv); 386 intel_gt_driver_late_release_all(dev_priv); 387 i915_drm_clients_fini(&dev_priv->clients); 388 intel_region_ttm_device_fini(dev_priv); 389 err_ttm: 390 vlv_suspend_cleanup(dev_priv); 391 err_workqueues: 392 i915_workqueues_cleanup(dev_priv); 393 return ret; 394 } 395 396 /** 397 * i915_driver_late_release - cleanup the setup done in 398 * i915_driver_early_probe() 399 * @dev_priv: device private 400 */ 401 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 402 { 403 intel_irq_fini(dev_priv); 404 intel_power_domains_cleanup(dev_priv); 405 i915_gem_cleanup_early(dev_priv); 406 intel_gt_driver_late_release_all(dev_priv); 407 i915_drm_clients_fini(&dev_priv->clients); 408 intel_region_ttm_device_fini(dev_priv); 409 vlv_suspend_cleanup(dev_priv); 410 i915_workqueues_cleanup(dev_priv); 411 412 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 413 mutex_destroy(&dev_priv->sb_lock); 414 415 i915_params_free(&dev_priv->params); 416 } 417 418 /** 419 * i915_driver_mmio_probe - setup device MMIO 420 * @dev_priv: device private 421 * 422 * Setup minimal device state necessary for MMIO accesses later in the 423 * initialization sequence. The setup here should avoid any other device-wide 424 * side effects or exposing the driver via kernel internal or user space 425 * interfaces. 426 */ 427 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 428 { 429 int ret; 430 431 if (i915_inject_probe_failure(dev_priv)) 432 return -ENODEV; 433 434 ret = i915_get_bridge_dev(dev_priv); 435 if (ret < 0) 436 return ret; 437 438 ret = intel_uncore_init_mmio(&dev_priv->uncore); 439 if (ret) 440 return ret; 441 442 /* Try to make sure MCHBAR is enabled before poking at it */ 443 intel_setup_mchbar(dev_priv); 444 intel_device_info_runtime_init(dev_priv); 445 446 ret = intel_gt_init_mmio(to_gt(dev_priv)); 447 if (ret) 448 goto err_uncore; 449 450 /* As early as possible, scrub existing GPU state before clobbering */ 451 sanitize_gpu(dev_priv); 452 453 return 0; 454 455 err_uncore: 456 intel_teardown_mchbar(dev_priv); 457 intel_uncore_fini_mmio(&dev_priv->uncore); 458 pci_dev_put(dev_priv->bridge_dev); 459 460 return ret; 461 } 462 463 /** 464 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 465 * @dev_priv: device private 466 */ 467 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 468 { 469 intel_teardown_mchbar(dev_priv); 470 intel_uncore_fini_mmio(&dev_priv->uncore); 471 pci_dev_put(dev_priv->bridge_dev); 472 } 473 474 /** 475 * i915_set_dma_info - set all relevant PCI dma info as configured for the 476 * platform 477 * @i915: valid i915 instance 478 * 479 * Set the dma max segment size, device and coherent masks. The dma mask set 480 * needs to occur before i915_ggtt_probe_hw. 481 * 482 * A couple of platforms have special needs. Address them as well. 483 * 484 */ 485 static int i915_set_dma_info(struct drm_i915_private *i915) 486 { 487 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 488 int ret; 489 490 GEM_BUG_ON(!mask_size); 491 492 /* 493 * We don't have a max segment size, so set it to the max so sg's 494 * debugging layer doesn't complain 495 */ 496 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 497 498 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 499 if (ret) 500 goto mask_err; 501 502 /* overlay on gen2 is broken and can't address above 1G */ 503 if (GRAPHICS_VER(i915) == 2) 504 mask_size = 30; 505 506 /* 507 * 965GM sometimes incorrectly writes to hardware status page (HWS) 508 * using 32bit addressing, overwriting memory if HWS is located 509 * above 4GB. 510 * 511 * The documentation also mentions an issue with undefined 512 * behaviour if any general state is accessed within a page above 4GB, 513 * which also needs to be handled carefully. 514 */ 515 if (IS_I965G(i915) || IS_I965GM(i915)) 516 mask_size = 32; 517 518 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 519 if (ret) 520 goto mask_err; 521 522 return 0; 523 524 mask_err: 525 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 526 return ret; 527 } 528 529 static int i915_pcode_init(struct drm_i915_private *i915) 530 { 531 struct intel_gt *gt; 532 int id, ret; 533 534 for_each_gt(gt, i915, id) { 535 ret = intel_pcode_init(gt->uncore); 536 if (ret) { 537 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 538 return ret; 539 } 540 } 541 542 return 0; 543 } 544 545 /** 546 * i915_driver_hw_probe - setup state requiring device access 547 * @dev_priv: device private 548 * 549 * Setup state that requires accessing the device, but doesn't require 550 * exposing the driver via kernel internal or userspace interfaces. 551 */ 552 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 553 { 554 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 555 struct pci_dev *root_pdev; 556 int ret; 557 558 if (i915_inject_probe_failure(dev_priv)) 559 return -ENODEV; 560 561 if (HAS_PPGTT(dev_priv)) { 562 if (intel_vgpu_active(dev_priv) && 563 !intel_vgpu_has_full_ppgtt(dev_priv)) { 564 i915_report_error(dev_priv, 565 "incompatible vGPU found, support for isolated ppGTT required\n"); 566 return -ENXIO; 567 } 568 } 569 570 if (HAS_EXECLISTS(dev_priv)) { 571 /* 572 * Older GVT emulation depends upon intercepting CSB mmio, 573 * which we no longer use, preferring to use the HWSP cache 574 * instead. 575 */ 576 if (intel_vgpu_active(dev_priv) && 577 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 578 i915_report_error(dev_priv, 579 "old vGPU host found, support for HWSP emulation required\n"); 580 return -ENXIO; 581 } 582 } 583 584 /* needs to be done before ggtt probe */ 585 intel_dram_edram_detect(dev_priv); 586 587 ret = i915_set_dma_info(dev_priv); 588 if (ret) 589 return ret; 590 591 i915_perf_init(dev_priv); 592 593 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 594 if (ret) 595 goto err_perf; 596 597 ret = i915_ggtt_probe_hw(dev_priv); 598 if (ret) 599 goto err_perf; 600 601 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 602 if (ret) 603 goto err_ggtt; 604 605 ret = i915_ggtt_init_hw(dev_priv); 606 if (ret) 607 goto err_ggtt; 608 609 ret = intel_memory_regions_hw_probe(dev_priv); 610 if (ret) 611 goto err_ggtt; 612 613 ret = intel_gt_tiles_init(dev_priv); 614 if (ret) 615 goto err_mem_regions; 616 617 ret = i915_ggtt_enable_hw(dev_priv); 618 if (ret) { 619 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 620 goto err_mem_regions; 621 } 622 623 pci_set_master(pdev); 624 625 /* On the 945G/GM, the chipset reports the MSI capability on the 626 * integrated graphics even though the support isn't actually there 627 * according to the published specs. It doesn't appear to function 628 * correctly in testing on 945G. 629 * This may be a side effect of MSI having been made available for PEG 630 * and the registers being closely associated. 631 * 632 * According to chipset errata, on the 965GM, MSI interrupts may 633 * be lost or delayed, and was defeatured. MSI interrupts seem to 634 * get lost on g4x as well, and interrupt delivery seems to stay 635 * properly dead afterwards. So we'll just disable them for all 636 * pre-gen5 chipsets. 637 * 638 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 639 * interrupts even when in MSI mode. This results in spurious 640 * interrupt warnings if the legacy irq no. is shared with another 641 * device. The kernel then disables that interrupt source and so 642 * prevents the other device from working properly. 643 */ 644 if (GRAPHICS_VER(dev_priv) >= 5) { 645 if (pci_enable_msi(pdev) < 0) 646 drm_dbg(&dev_priv->drm, "can't enable MSI"); 647 } 648 649 ret = intel_gvt_init(dev_priv); 650 if (ret) 651 goto err_msi; 652 653 intel_opregion_setup(dev_priv); 654 655 ret = i915_pcode_init(dev_priv); 656 if (ret) 657 goto err_msi; 658 659 /* 660 * Fill the dram structure to get the system dram info. This will be 661 * used for memory latency calculation. 662 */ 663 intel_dram_detect(dev_priv); 664 665 intel_bw_init_hw(dev_priv); 666 667 /* 668 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 669 * This should be totally removed when we handle the pci states properly 670 * on runtime PM and on s2idle cases. 671 */ 672 root_pdev = pcie_find_root_port(pdev); 673 if (root_pdev) 674 pci_d3cold_disable(root_pdev); 675 676 return 0; 677 678 err_msi: 679 if (pdev->msi_enabled) 680 pci_disable_msi(pdev); 681 err_mem_regions: 682 intel_memory_regions_driver_release(dev_priv); 683 err_ggtt: 684 i915_ggtt_driver_release(dev_priv); 685 i915_gem_drain_freed_objects(dev_priv); 686 i915_ggtt_driver_late_release(dev_priv); 687 err_perf: 688 i915_perf_fini(dev_priv); 689 return ret; 690 } 691 692 /** 693 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 694 * @dev_priv: device private 695 */ 696 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 697 { 698 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 699 struct pci_dev *root_pdev; 700 701 i915_perf_fini(dev_priv); 702 703 if (pdev->msi_enabled) 704 pci_disable_msi(pdev); 705 706 root_pdev = pcie_find_root_port(pdev); 707 if (root_pdev) 708 pci_d3cold_enable(root_pdev); 709 } 710 711 /** 712 * i915_driver_register - register the driver with the rest of the system 713 * @dev_priv: device private 714 * 715 * Perform any steps necessary to make the driver available via kernel 716 * internal or userspace interfaces. 717 */ 718 static void i915_driver_register(struct drm_i915_private *dev_priv) 719 { 720 i915_gem_driver_register(dev_priv); 721 i915_pmu_register(dev_priv); 722 723 intel_vgpu_register(dev_priv); 724 725 /* Reveal our presence to userspace */ 726 if (drm_dev_register(&dev_priv->drm, 0)) { 727 drm_err(&dev_priv->drm, 728 "Failed to register driver for userspace access!\n"); 729 return; 730 } 731 732 i915_debugfs_register(dev_priv); 733 i915_setup_sysfs(dev_priv); 734 735 /* Depends on sysfs having been initialized */ 736 i915_perf_register(dev_priv); 737 738 intel_gt_driver_register(to_gt(dev_priv)); 739 740 intel_display_driver_register(dev_priv); 741 742 intel_power_domains_enable(dev_priv); 743 intel_runtime_pm_enable(&dev_priv->runtime_pm); 744 745 intel_register_dsm_handler(); 746 747 if (i915_switcheroo_register(dev_priv)) 748 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 749 } 750 751 /** 752 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 753 * @dev_priv: device private 754 */ 755 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 756 { 757 i915_switcheroo_unregister(dev_priv); 758 759 intel_unregister_dsm_handler(); 760 761 intel_runtime_pm_disable(&dev_priv->runtime_pm); 762 intel_power_domains_disable(dev_priv); 763 764 intel_display_driver_unregister(dev_priv); 765 766 intel_gt_driver_unregister(to_gt(dev_priv)); 767 768 i915_perf_unregister(dev_priv); 769 i915_pmu_unregister(dev_priv); 770 771 i915_teardown_sysfs(dev_priv); 772 drm_dev_unplug(&dev_priv->drm); 773 774 i915_gem_driver_unregister(dev_priv); 775 } 776 777 void 778 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 779 { 780 drm_printf(p, "iommu: %s\n", 781 str_enabled_disabled(i915_vtd_active(i915))); 782 } 783 784 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 785 { 786 if (drm_debug_enabled(DRM_UT_DRIVER)) { 787 struct drm_printer p = drm_debug_printer("i915 device info:"); 788 789 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 790 INTEL_DEVID(dev_priv), 791 INTEL_REVID(dev_priv), 792 intel_platform_name(INTEL_INFO(dev_priv)->platform), 793 intel_subplatform(RUNTIME_INFO(dev_priv), 794 INTEL_INFO(dev_priv)->platform), 795 GRAPHICS_VER(dev_priv)); 796 797 intel_device_info_print(INTEL_INFO(dev_priv), 798 RUNTIME_INFO(dev_priv), &p); 799 i915_print_iommu_status(dev_priv, &p); 800 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 801 } 802 803 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 804 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 805 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 806 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 807 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 808 drm_info(&dev_priv->drm, 809 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 810 } 811 812 static struct drm_i915_private * 813 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 814 { 815 const struct intel_device_info *match_info = 816 (struct intel_device_info *)ent->driver_data; 817 struct intel_device_info *device_info; 818 struct intel_runtime_info *runtime; 819 struct drm_i915_private *i915; 820 821 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 822 struct drm_i915_private, drm); 823 if (IS_ERR(i915)) 824 return i915; 825 826 pci_set_drvdata(pdev, i915); 827 828 /* Device parameters start as a copy of module parameters. */ 829 i915_params_copy(&i915->params, &i915_modparams); 830 831 /* Setup the write-once "constant" device info */ 832 device_info = mkwrite_device_info(i915); 833 memcpy(device_info, match_info, sizeof(*device_info)); 834 835 /* Initialize initial runtime info from static const data and pdev. */ 836 runtime = RUNTIME_INFO(i915); 837 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 838 runtime->device_id = pdev->device; 839 840 return i915; 841 } 842 843 /** 844 * i915_driver_probe - setup chip and create an initial config 845 * @pdev: PCI device 846 * @ent: matching PCI ID entry 847 * 848 * The driver probe routine has to do several things: 849 * - drive output discovery via intel_modeset_init() 850 * - initialize the memory manager 851 * - allocate initial config memory 852 * - setup the DRM framebuffer with the allocated memory 853 */ 854 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 855 { 856 struct drm_i915_private *i915; 857 int ret; 858 859 i915 = i915_driver_create(pdev, ent); 860 if (IS_ERR(i915)) 861 return PTR_ERR(i915); 862 863 ret = pci_enable_device(pdev); 864 if (ret) 865 goto out_fini; 866 867 ret = i915_driver_early_probe(i915); 868 if (ret < 0) 869 goto out_pci_disable; 870 871 disable_rpm_wakeref_asserts(&i915->runtime_pm); 872 873 intel_vgpu_detect(i915); 874 875 ret = intel_gt_probe_all(i915); 876 if (ret < 0) 877 goto out_runtime_pm_put; 878 879 ret = i915_driver_mmio_probe(i915); 880 if (ret < 0) 881 goto out_tiles_cleanup; 882 883 ret = i915_driver_hw_probe(i915); 884 if (ret < 0) 885 goto out_cleanup_mmio; 886 887 ret = intel_modeset_init_noirq(i915); 888 if (ret < 0) 889 goto out_cleanup_hw; 890 891 ret = intel_irq_install(i915); 892 if (ret) 893 goto out_cleanup_modeset; 894 895 ret = intel_modeset_init_nogem(i915); 896 if (ret) 897 goto out_cleanup_irq; 898 899 ret = i915_gem_init(i915); 900 if (ret) 901 goto out_cleanup_modeset2; 902 903 ret = intel_modeset_init(i915); 904 if (ret) 905 goto out_cleanup_gem; 906 907 i915_driver_register(i915); 908 909 enable_rpm_wakeref_asserts(&i915->runtime_pm); 910 911 i915_welcome_messages(i915); 912 913 i915->do_release = true; 914 915 return 0; 916 917 out_cleanup_gem: 918 i915_gem_suspend(i915); 919 i915_gem_driver_remove(i915); 920 i915_gem_driver_release(i915); 921 out_cleanup_modeset2: 922 /* FIXME clean up the error path */ 923 intel_modeset_driver_remove(i915); 924 intel_irq_uninstall(i915); 925 intel_modeset_driver_remove_noirq(i915); 926 goto out_cleanup_modeset; 927 out_cleanup_irq: 928 intel_irq_uninstall(i915); 929 out_cleanup_modeset: 930 intel_modeset_driver_remove_nogem(i915); 931 out_cleanup_hw: 932 i915_driver_hw_remove(i915); 933 intel_memory_regions_driver_release(i915); 934 i915_ggtt_driver_release(i915); 935 i915_gem_drain_freed_objects(i915); 936 i915_ggtt_driver_late_release(i915); 937 out_cleanup_mmio: 938 i915_driver_mmio_release(i915); 939 out_tiles_cleanup: 940 intel_gt_release_all(i915); 941 out_runtime_pm_put: 942 enable_rpm_wakeref_asserts(&i915->runtime_pm); 943 i915_driver_late_release(i915); 944 out_pci_disable: 945 pci_disable_device(pdev); 946 out_fini: 947 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 948 return ret; 949 } 950 951 void i915_driver_remove(struct drm_i915_private *i915) 952 { 953 intel_wakeref_t wakeref; 954 955 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 956 957 i915_driver_unregister(i915); 958 959 /* Flush any external code that still may be under the RCU lock */ 960 synchronize_rcu(); 961 962 i915_gem_suspend(i915); 963 964 intel_gvt_driver_remove(i915); 965 966 intel_modeset_driver_remove(i915); 967 968 intel_irq_uninstall(i915); 969 970 intel_modeset_driver_remove_noirq(i915); 971 972 i915_reset_error_state(i915); 973 i915_gem_driver_remove(i915); 974 975 intel_modeset_driver_remove_nogem(i915); 976 977 i915_driver_hw_remove(i915); 978 979 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 980 } 981 982 static void i915_driver_release(struct drm_device *dev) 983 { 984 struct drm_i915_private *dev_priv = to_i915(dev); 985 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 986 intel_wakeref_t wakeref; 987 988 if (!dev_priv->do_release) 989 return; 990 991 wakeref = intel_runtime_pm_get(rpm); 992 993 i915_gem_driver_release(dev_priv); 994 995 intel_memory_regions_driver_release(dev_priv); 996 i915_ggtt_driver_release(dev_priv); 997 i915_gem_drain_freed_objects(dev_priv); 998 i915_ggtt_driver_late_release(dev_priv); 999 1000 i915_driver_mmio_release(dev_priv); 1001 1002 intel_runtime_pm_put(rpm, wakeref); 1003 1004 intel_runtime_pm_driver_release(rpm); 1005 1006 i915_driver_late_release(dev_priv); 1007 } 1008 1009 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1010 { 1011 struct drm_i915_private *i915 = to_i915(dev); 1012 int ret; 1013 1014 ret = i915_gem_open(i915, file); 1015 if (ret) 1016 return ret; 1017 1018 return 0; 1019 } 1020 1021 /** 1022 * i915_driver_lastclose - clean up after all DRM clients have exited 1023 * @dev: DRM device 1024 * 1025 * Take care of cleaning up after all DRM clients have exited. In the 1026 * mode setting case, we want to restore the kernel's initial mode (just 1027 * in case the last client left us in a bad state). 1028 * 1029 * Additionally, in the non-mode setting case, we'll tear down the GTT 1030 * and DMA structures, since the kernel won't be using them, and clea 1031 * up any GEM state. 1032 */ 1033 static void i915_driver_lastclose(struct drm_device *dev) 1034 { 1035 struct drm_i915_private *i915 = to_i915(dev); 1036 1037 intel_fbdev_restore_mode(dev); 1038 1039 if (HAS_DISPLAY(i915)) 1040 vga_switcheroo_process_delayed_switch(); 1041 } 1042 1043 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1044 { 1045 struct drm_i915_file_private *file_priv = file->driver_priv; 1046 1047 i915_gem_context_close(file); 1048 i915_drm_client_put(file_priv->client); 1049 1050 kfree_rcu(file_priv, rcu); 1051 1052 /* Catch up with all the deferred frees from "this" client */ 1053 i915_gem_flush_free_objects(to_i915(dev)); 1054 } 1055 1056 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1057 { 1058 struct intel_encoder *encoder; 1059 1060 if (!HAS_DISPLAY(dev_priv)) 1061 return; 1062 1063 drm_modeset_lock_all(&dev_priv->drm); 1064 for_each_intel_encoder(&dev_priv->drm, encoder) 1065 if (encoder->suspend) 1066 encoder->suspend(encoder); 1067 drm_modeset_unlock_all(&dev_priv->drm); 1068 } 1069 1070 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1071 { 1072 struct intel_encoder *encoder; 1073 1074 if (!HAS_DISPLAY(dev_priv)) 1075 return; 1076 1077 drm_modeset_lock_all(&dev_priv->drm); 1078 for_each_intel_encoder(&dev_priv->drm, encoder) 1079 if (encoder->shutdown) 1080 encoder->shutdown(encoder); 1081 drm_modeset_unlock_all(&dev_priv->drm); 1082 } 1083 1084 void i915_driver_shutdown(struct drm_i915_private *i915) 1085 { 1086 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1087 intel_runtime_pm_disable(&i915->runtime_pm); 1088 intel_power_domains_disable(i915); 1089 1090 if (HAS_DISPLAY(i915)) { 1091 drm_kms_helper_poll_disable(&i915->drm); 1092 1093 drm_atomic_helper_shutdown(&i915->drm); 1094 } 1095 1096 intel_dp_mst_suspend(i915); 1097 1098 intel_runtime_pm_disable_interrupts(i915); 1099 intel_hpd_cancel_work(i915); 1100 1101 intel_suspend_encoders(i915); 1102 intel_shutdown_encoders(i915); 1103 1104 intel_dmc_ucode_suspend(i915); 1105 1106 i915_gem_suspend(i915); 1107 1108 /* 1109 * The only requirement is to reboot with display DC states disabled, 1110 * for now leaving all display power wells in the INIT power domain 1111 * enabled. 1112 * 1113 * TODO: 1114 * - unify the pci_driver::shutdown sequence here with the 1115 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1116 * - unify the driver remove and system/runtime suspend sequences with 1117 * the above unified shutdown/poweroff sequence. 1118 */ 1119 intel_power_domains_driver_remove(i915); 1120 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1121 1122 intel_runtime_pm_driver_release(&i915->runtime_pm); 1123 } 1124 1125 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1126 { 1127 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1128 if (acpi_target_system_state() < ACPI_STATE_S3) 1129 return true; 1130 #endif 1131 return false; 1132 } 1133 1134 static int i915_drm_prepare(struct drm_device *dev) 1135 { 1136 struct drm_i915_private *i915 = to_i915(dev); 1137 1138 /* 1139 * NB intel_display_suspend() may issue new requests after we've 1140 * ostensibly marked the GPU as ready-to-sleep here. We need to 1141 * split out that work and pull it forward so that after point, 1142 * the GPU is not woken again. 1143 */ 1144 return i915_gem_backup_suspend(i915); 1145 } 1146 1147 static int i915_drm_suspend(struct drm_device *dev) 1148 { 1149 struct drm_i915_private *dev_priv = to_i915(dev); 1150 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1151 pci_power_t opregion_target_state; 1152 1153 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1154 1155 /* We do a lot of poking in a lot of registers, make sure they work 1156 * properly. */ 1157 intel_power_domains_disable(dev_priv); 1158 if (HAS_DISPLAY(dev_priv)) 1159 drm_kms_helper_poll_disable(dev); 1160 1161 pci_save_state(pdev); 1162 1163 intel_display_suspend(dev); 1164 1165 intel_dp_mst_suspend(dev_priv); 1166 1167 intel_runtime_pm_disable_interrupts(dev_priv); 1168 intel_hpd_cancel_work(dev_priv); 1169 1170 intel_suspend_encoders(dev_priv); 1171 1172 intel_suspend_hw(dev_priv); 1173 1174 /* Must be called before GGTT is suspended. */ 1175 intel_dpt_suspend(dev_priv); 1176 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1177 1178 i915_save_display(dev_priv); 1179 1180 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1181 intel_opregion_suspend(dev_priv, opregion_target_state); 1182 1183 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1184 1185 dev_priv->suspend_count++; 1186 1187 intel_dmc_ucode_suspend(dev_priv); 1188 1189 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1190 1191 i915_gem_drain_freed_objects(dev_priv); 1192 1193 return 0; 1194 } 1195 1196 static enum i915_drm_suspend_mode 1197 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1198 { 1199 if (hibernate) 1200 return I915_DRM_SUSPEND_HIBERNATE; 1201 1202 if (suspend_to_idle(dev_priv)) 1203 return I915_DRM_SUSPEND_IDLE; 1204 1205 return I915_DRM_SUSPEND_MEM; 1206 } 1207 1208 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1209 { 1210 struct drm_i915_private *dev_priv = to_i915(dev); 1211 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1212 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1213 int ret; 1214 1215 disable_rpm_wakeref_asserts(rpm); 1216 1217 i915_gem_suspend_late(dev_priv); 1218 1219 intel_uncore_suspend(&dev_priv->uncore); 1220 1221 intel_power_domains_suspend(dev_priv, 1222 get_suspend_mode(dev_priv, hibernation)); 1223 1224 intel_display_power_suspend_late(dev_priv); 1225 1226 ret = vlv_suspend_complete(dev_priv); 1227 if (ret) { 1228 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1229 intel_power_domains_resume(dev_priv); 1230 1231 goto out; 1232 } 1233 1234 pci_disable_device(pdev); 1235 /* 1236 * During hibernation on some platforms the BIOS may try to access 1237 * the device even though it's already in D3 and hang the machine. So 1238 * leave the device in D0 on those platforms and hope the BIOS will 1239 * power down the device properly. The issue was seen on multiple old 1240 * GENs with different BIOS vendors, so having an explicit blacklist 1241 * is inpractical; apply the workaround on everything pre GEN6. The 1242 * platforms where the issue was seen: 1243 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1244 * Fujitsu FSC S7110 1245 * Acer Aspire 1830T 1246 */ 1247 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1248 pci_set_power_state(pdev, PCI_D3hot); 1249 1250 out: 1251 enable_rpm_wakeref_asserts(rpm); 1252 if (!dev_priv->uncore.user_forcewake_count) 1253 intel_runtime_pm_driver_release(rpm); 1254 1255 return ret; 1256 } 1257 1258 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1259 pm_message_t state) 1260 { 1261 int error; 1262 1263 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1264 state.event != PM_EVENT_FREEZE)) 1265 return -EINVAL; 1266 1267 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1268 return 0; 1269 1270 error = i915_drm_suspend(&i915->drm); 1271 if (error) 1272 return error; 1273 1274 return i915_drm_suspend_late(&i915->drm, false); 1275 } 1276 1277 static int i915_drm_resume(struct drm_device *dev) 1278 { 1279 struct drm_i915_private *dev_priv = to_i915(dev); 1280 int ret; 1281 1282 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1283 1284 ret = i915_pcode_init(dev_priv); 1285 if (ret) 1286 return ret; 1287 1288 sanitize_gpu(dev_priv); 1289 1290 ret = i915_ggtt_enable_hw(dev_priv); 1291 if (ret) 1292 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1293 1294 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1295 /* Must be called after GGTT is resumed. */ 1296 intel_dpt_resume(dev_priv); 1297 1298 intel_dmc_ucode_resume(dev_priv); 1299 1300 i915_restore_display(dev_priv); 1301 intel_pps_unlock_regs_wa(dev_priv); 1302 1303 intel_init_pch_refclk(dev_priv); 1304 1305 /* 1306 * Interrupts have to be enabled before any batches are run. If not the 1307 * GPU will hang. i915_gem_init_hw() will initiate batches to 1308 * update/restore the context. 1309 * 1310 * drm_mode_config_reset() needs AUX interrupts. 1311 * 1312 * Modeset enabling in intel_modeset_init_hw() also needs working 1313 * interrupts. 1314 */ 1315 intel_runtime_pm_enable_interrupts(dev_priv); 1316 1317 if (HAS_DISPLAY(dev_priv)) 1318 drm_mode_config_reset(dev); 1319 1320 i915_gem_resume(dev_priv); 1321 1322 intel_modeset_init_hw(dev_priv); 1323 intel_init_clock_gating(dev_priv); 1324 intel_hpd_init(dev_priv); 1325 1326 /* MST sideband requires HPD interrupts enabled */ 1327 intel_dp_mst_resume(dev_priv); 1328 intel_display_resume(dev); 1329 1330 intel_hpd_poll_disable(dev_priv); 1331 if (HAS_DISPLAY(dev_priv)) 1332 drm_kms_helper_poll_enable(dev); 1333 1334 intel_opregion_resume(dev_priv); 1335 1336 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1337 1338 intel_power_domains_enable(dev_priv); 1339 1340 intel_gvt_resume(dev_priv); 1341 1342 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1343 1344 return 0; 1345 } 1346 1347 static int i915_drm_resume_early(struct drm_device *dev) 1348 { 1349 struct drm_i915_private *dev_priv = to_i915(dev); 1350 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1351 int ret; 1352 1353 /* 1354 * We have a resume ordering issue with the snd-hda driver also 1355 * requiring our device to be power up. Due to the lack of a 1356 * parent/child relationship we currently solve this with an early 1357 * resume hook. 1358 * 1359 * FIXME: This should be solved with a special hdmi sink device or 1360 * similar so that power domains can be employed. 1361 */ 1362 1363 /* 1364 * Note that we need to set the power state explicitly, since we 1365 * powered off the device during freeze and the PCI core won't power 1366 * it back up for us during thaw. Powering off the device during 1367 * freeze is not a hard requirement though, and during the 1368 * suspend/resume phases the PCI core makes sure we get here with the 1369 * device powered on. So in case we change our freeze logic and keep 1370 * the device powered we can also remove the following set power state 1371 * call. 1372 */ 1373 ret = pci_set_power_state(pdev, PCI_D0); 1374 if (ret) { 1375 drm_err(&dev_priv->drm, 1376 "failed to set PCI D0 power state (%d)\n", ret); 1377 return ret; 1378 } 1379 1380 /* 1381 * Note that pci_enable_device() first enables any parent bridge 1382 * device and only then sets the power state for this device. The 1383 * bridge enabling is a nop though, since bridge devices are resumed 1384 * first. The order of enabling power and enabling the device is 1385 * imposed by the PCI core as described above, so here we preserve the 1386 * same order for the freeze/thaw phases. 1387 * 1388 * TODO: eventually we should remove pci_disable_device() / 1389 * pci_enable_enable_device() from suspend/resume. Due to how they 1390 * depend on the device enable refcount we can't anyway depend on them 1391 * disabling/enabling the device. 1392 */ 1393 if (pci_enable_device(pdev)) 1394 return -EIO; 1395 1396 pci_set_master(pdev); 1397 1398 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1399 1400 ret = vlv_resume_prepare(dev_priv, false); 1401 if (ret) 1402 drm_err(&dev_priv->drm, 1403 "Resume prepare failed: %d, continuing anyway\n", ret); 1404 1405 intel_uncore_resume_early(&dev_priv->uncore); 1406 1407 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1408 1409 intel_display_power_resume_early(dev_priv); 1410 1411 intel_power_domains_resume(dev_priv); 1412 1413 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1414 1415 return ret; 1416 } 1417 1418 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1419 { 1420 int ret; 1421 1422 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1423 return 0; 1424 1425 ret = i915_drm_resume_early(&i915->drm); 1426 if (ret) 1427 return ret; 1428 1429 return i915_drm_resume(&i915->drm); 1430 } 1431 1432 static int i915_pm_prepare(struct device *kdev) 1433 { 1434 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1435 1436 if (!i915) { 1437 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1438 return -ENODEV; 1439 } 1440 1441 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1442 return 0; 1443 1444 return i915_drm_prepare(&i915->drm); 1445 } 1446 1447 static int i915_pm_suspend(struct device *kdev) 1448 { 1449 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1450 1451 if (!i915) { 1452 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1453 return -ENODEV; 1454 } 1455 1456 i915_ggtt_mark_pte_lost(i915, false); 1457 1458 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1459 return 0; 1460 1461 return i915_drm_suspend(&i915->drm); 1462 } 1463 1464 static int i915_pm_suspend_late(struct device *kdev) 1465 { 1466 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1467 1468 /* 1469 * We have a suspend ordering issue with the snd-hda driver also 1470 * requiring our device to be power up. Due to the lack of a 1471 * parent/child relationship we currently solve this with an late 1472 * suspend hook. 1473 * 1474 * FIXME: This should be solved with a special hdmi sink device or 1475 * similar so that power domains can be employed. 1476 */ 1477 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1478 return 0; 1479 1480 return i915_drm_suspend_late(&i915->drm, false); 1481 } 1482 1483 static int i915_pm_poweroff_late(struct device *kdev) 1484 { 1485 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1486 1487 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1488 return 0; 1489 1490 return i915_drm_suspend_late(&i915->drm, true); 1491 } 1492 1493 static int i915_pm_resume_early(struct device *kdev) 1494 { 1495 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1496 1497 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1498 return 0; 1499 1500 return i915_drm_resume_early(&i915->drm); 1501 } 1502 1503 static int i915_pm_resume(struct device *kdev) 1504 { 1505 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1506 1507 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1508 return 0; 1509 1510 /* 1511 * If IRST is enabled, or if we can't detect whether it's enabled, 1512 * then we must assume we lost the GGTT page table entries, since 1513 * they are not retained if IRST decided to enter S4. 1514 */ 1515 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1)) 1516 i915_ggtt_mark_pte_lost(i915, true); 1517 1518 return i915_drm_resume(&i915->drm); 1519 } 1520 1521 /* freeze: before creating the hibernation_image */ 1522 static int i915_pm_freeze(struct device *kdev) 1523 { 1524 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1525 int ret; 1526 1527 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1528 ret = i915_drm_suspend(&i915->drm); 1529 if (ret) 1530 return ret; 1531 } 1532 1533 ret = i915_gem_freeze(i915); 1534 if (ret) 1535 return ret; 1536 1537 return 0; 1538 } 1539 1540 static int i915_pm_freeze_late(struct device *kdev) 1541 { 1542 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1543 int ret; 1544 1545 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1546 ret = i915_drm_suspend_late(&i915->drm, true); 1547 if (ret) 1548 return ret; 1549 } 1550 1551 ret = i915_gem_freeze_late(i915); 1552 if (ret) 1553 return ret; 1554 1555 return 0; 1556 } 1557 1558 /* thaw: called after creating the hibernation image, but before turning off. */ 1559 static int i915_pm_thaw_early(struct device *kdev) 1560 { 1561 return i915_pm_resume_early(kdev); 1562 } 1563 1564 static int i915_pm_thaw(struct device *kdev) 1565 { 1566 return i915_pm_resume(kdev); 1567 } 1568 1569 /* restore: called after loading the hibernation image. */ 1570 static int i915_pm_restore_early(struct device *kdev) 1571 { 1572 return i915_pm_resume_early(kdev); 1573 } 1574 1575 static int i915_pm_restore(struct device *kdev) 1576 { 1577 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1578 1579 i915_ggtt_mark_pte_lost(i915, true); 1580 return i915_pm_resume(kdev); 1581 } 1582 1583 static int intel_runtime_suspend(struct device *kdev) 1584 { 1585 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1586 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1587 int ret; 1588 1589 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1590 return -ENODEV; 1591 1592 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1593 1594 disable_rpm_wakeref_asserts(rpm); 1595 1596 /* 1597 * We are safe here against re-faults, since the fault handler takes 1598 * an RPM reference. 1599 */ 1600 i915_gem_runtime_suspend(dev_priv); 1601 1602 intel_gt_runtime_suspend(to_gt(dev_priv)); 1603 1604 intel_runtime_pm_disable_interrupts(dev_priv); 1605 1606 intel_uncore_suspend(&dev_priv->uncore); 1607 1608 intel_display_power_suspend(dev_priv); 1609 1610 ret = vlv_suspend_complete(dev_priv); 1611 if (ret) { 1612 drm_err(&dev_priv->drm, 1613 "Runtime suspend failed, disabling it (%d)\n", ret); 1614 intel_uncore_runtime_resume(&dev_priv->uncore); 1615 1616 intel_runtime_pm_enable_interrupts(dev_priv); 1617 1618 intel_gt_runtime_resume(to_gt(dev_priv)); 1619 1620 enable_rpm_wakeref_asserts(rpm); 1621 1622 return ret; 1623 } 1624 1625 enable_rpm_wakeref_asserts(rpm); 1626 intel_runtime_pm_driver_release(rpm); 1627 1628 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1629 drm_err(&dev_priv->drm, 1630 "Unclaimed access detected prior to suspending\n"); 1631 1632 rpm->suspended = true; 1633 1634 /* 1635 * FIXME: We really should find a document that references the arguments 1636 * used below! 1637 */ 1638 if (IS_BROADWELL(dev_priv)) { 1639 /* 1640 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1641 * being detected, and the call we do at intel_runtime_resume() 1642 * won't be able to restore them. Since PCI_D3hot matches the 1643 * actual specification and appears to be working, use it. 1644 */ 1645 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1646 } else { 1647 /* 1648 * current versions of firmware which depend on this opregion 1649 * notification have repurposed the D1 definition to mean 1650 * "runtime suspended" vs. what you would normally expect (D3) 1651 * to distinguish it from notifications that might be sent via 1652 * the suspend path. 1653 */ 1654 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1655 } 1656 1657 assert_forcewakes_inactive(&dev_priv->uncore); 1658 1659 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1660 intel_hpd_poll_enable(dev_priv); 1661 1662 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1663 return 0; 1664 } 1665 1666 static int intel_runtime_resume(struct device *kdev) 1667 { 1668 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1669 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1670 int ret; 1671 1672 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1673 return -ENODEV; 1674 1675 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1676 1677 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1678 disable_rpm_wakeref_asserts(rpm); 1679 1680 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1681 rpm->suspended = false; 1682 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1683 drm_dbg(&dev_priv->drm, 1684 "Unclaimed access during suspend, bios?\n"); 1685 1686 intel_display_power_resume(dev_priv); 1687 1688 ret = vlv_resume_prepare(dev_priv, true); 1689 1690 intel_uncore_runtime_resume(&dev_priv->uncore); 1691 1692 intel_runtime_pm_enable_interrupts(dev_priv); 1693 1694 /* 1695 * No point of rolling back things in case of an error, as the best 1696 * we can do is to hope that things will still work (and disable RPM). 1697 */ 1698 intel_gt_runtime_resume(to_gt(dev_priv)); 1699 1700 /* 1701 * On VLV/CHV display interrupts are part of the display 1702 * power well, so hpd is reinitialized from there. For 1703 * everyone else do it here. 1704 */ 1705 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1706 intel_hpd_init(dev_priv); 1707 intel_hpd_poll_disable(dev_priv); 1708 } 1709 1710 skl_watermark_ipc_update(dev_priv); 1711 1712 enable_rpm_wakeref_asserts(rpm); 1713 1714 if (ret) 1715 drm_err(&dev_priv->drm, 1716 "Runtime resume failed, disabling it (%d)\n", ret); 1717 else 1718 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1719 1720 return ret; 1721 } 1722 1723 const struct dev_pm_ops i915_pm_ops = { 1724 /* 1725 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1726 * PMSG_RESUME] 1727 */ 1728 .prepare = i915_pm_prepare, 1729 .suspend = i915_pm_suspend, 1730 .suspend_late = i915_pm_suspend_late, 1731 .resume_early = i915_pm_resume_early, 1732 .resume = i915_pm_resume, 1733 1734 /* 1735 * S4 event handlers 1736 * @freeze, @freeze_late : called (1) before creating the 1737 * hibernation image [PMSG_FREEZE] and 1738 * (2) after rebooting, before restoring 1739 * the image [PMSG_QUIESCE] 1740 * @thaw, @thaw_early : called (1) after creating the hibernation 1741 * image, before writing it [PMSG_THAW] 1742 * and (2) after failing to create or 1743 * restore the image [PMSG_RECOVER] 1744 * @poweroff, @poweroff_late: called after writing the hibernation 1745 * image, before rebooting [PMSG_HIBERNATE] 1746 * @restore, @restore_early : called after rebooting and restoring the 1747 * hibernation image [PMSG_RESTORE] 1748 */ 1749 .freeze = i915_pm_freeze, 1750 .freeze_late = i915_pm_freeze_late, 1751 .thaw_early = i915_pm_thaw_early, 1752 .thaw = i915_pm_thaw, 1753 .poweroff = i915_pm_suspend, 1754 .poweroff_late = i915_pm_poweroff_late, 1755 .restore_early = i915_pm_restore_early, 1756 .restore = i915_pm_restore, 1757 1758 /* S0ix (via runtime suspend) event handlers */ 1759 .runtime_suspend = intel_runtime_suspend, 1760 .runtime_resume = intel_runtime_resume, 1761 }; 1762 1763 static const struct file_operations i915_driver_fops = { 1764 .owner = THIS_MODULE, 1765 .open = drm_open, 1766 .release = drm_release_noglobal, 1767 .unlocked_ioctl = drm_ioctl, 1768 .mmap = i915_gem_mmap, 1769 .poll = drm_poll, 1770 .read = drm_read, 1771 .compat_ioctl = i915_ioc32_compat_ioctl, 1772 .llseek = noop_llseek, 1773 #ifdef CONFIG_PROC_FS 1774 .show_fdinfo = i915_drm_client_fdinfo, 1775 #endif 1776 }; 1777 1778 static int 1779 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1780 struct drm_file *file) 1781 { 1782 return -ENODEV; 1783 } 1784 1785 static const struct drm_ioctl_desc i915_ioctls[] = { 1786 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1787 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1788 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1789 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1790 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1791 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1792 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1794 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1795 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1796 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1797 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1798 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1799 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1800 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1801 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1802 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1804 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1805 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1806 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1807 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1809 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1810 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1821 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1822 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1823 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1824 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1825 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1826 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1827 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1828 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1829 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1830 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1831 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1832 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1833 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1834 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1835 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1836 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1837 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1838 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1839 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1840 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1841 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1842 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1843 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1844 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1845 }; 1846 1847 /* 1848 * Interface history: 1849 * 1850 * 1.1: Original. 1851 * 1.2: Add Power Management 1852 * 1.3: Add vblank support 1853 * 1.4: Fix cmdbuffer path, add heap destroy 1854 * 1.5: Add vblank pipe configuration 1855 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1856 * - Support vertical blank on secondary display pipe 1857 */ 1858 #define DRIVER_MAJOR 1 1859 #define DRIVER_MINOR 6 1860 #define DRIVER_PATCHLEVEL 0 1861 1862 static const struct drm_driver i915_drm_driver = { 1863 /* Don't use MTRRs here; the Xserver or userspace app should 1864 * deal with them for Intel hardware. 1865 */ 1866 .driver_features = 1867 DRIVER_GEM | 1868 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1869 DRIVER_SYNCOBJ_TIMELINE, 1870 .release = i915_driver_release, 1871 .open = i915_driver_open, 1872 .lastclose = i915_driver_lastclose, 1873 .postclose = i915_driver_postclose, 1874 1875 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1876 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1877 .gem_prime_import = i915_gem_prime_import, 1878 1879 .dumb_create = i915_gem_dumb_create, 1880 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1881 1882 .ioctls = i915_ioctls, 1883 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1884 .fops = &i915_driver_fops, 1885 .name = DRIVER_NAME, 1886 .desc = DRIVER_DESC, 1887 .date = DRIVER_DATE, 1888 .major = DRIVER_MAJOR, 1889 .minor = DRIVER_MINOR, 1890 .patchlevel = DRIVER_PATCHLEVEL, 1891 }; 1892