1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 65 #include "gem/i915_gem_context.h" 66 #include "gem/i915_gem_create.h" 67 #include "gem/i915_gem_dmabuf.h" 68 #include "gem/i915_gem_ioctls.h" 69 #include "gem/i915_gem_mman.h" 70 #include "gem/i915_gem_pm.h" 71 #include "gt/intel_gt.h" 72 #include "gt/intel_gt_pm.h" 73 #include "gt/intel_rc6.h" 74 75 #include "pxp/intel_pxp_pm.h" 76 77 #include "i915_file_private.h" 78 #include "i915_debugfs.h" 79 #include "i915_driver.h" 80 #include "i915_drm_client.h" 81 #include "i915_drv.h" 82 #include "i915_getparam.h" 83 #include "i915_ioc32.h" 84 #include "i915_ioctl.h" 85 #include "i915_irq.h" 86 #include "i915_memcpy.h" 87 #include "i915_perf.h" 88 #include "i915_query.h" 89 #include "i915_suspend.h" 90 #include "i915_switcheroo.h" 91 #include "i915_sysfs.h" 92 #include "i915_utils.h" 93 #include "i915_vgpu.h" 94 #include "intel_dram.h" 95 #include "intel_gvt.h" 96 #include "intel_memory_region.h" 97 #include "intel_pci_config.h" 98 #include "intel_pcode.h" 99 #include "intel_pm.h" 100 #include "intel_region_ttm.h" 101 #include "vlv_suspend.h" 102 103 /* Intel Rapid Start Technology ACPI device name */ 104 static const char irst_name[] = "INT3392"; 105 106 static const struct drm_driver i915_drm_driver; 107 108 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 109 { 110 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 111 112 dev_priv->bridge_dev = 113 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 114 if (!dev_priv->bridge_dev) { 115 drm_err(&dev_priv->drm, "bridge device not found\n"); 116 return -EIO; 117 } 118 return 0; 119 } 120 121 /* Allocate space for the MCH regs if needed, return nonzero on error */ 122 static int 123 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 124 { 125 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 126 u32 temp_lo, temp_hi = 0; 127 u64 mchbar_addr; 128 int ret; 129 130 if (GRAPHICS_VER(dev_priv) >= 4) 131 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 132 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 133 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 134 135 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 136 #ifdef CONFIG_PNP 137 if (mchbar_addr && 138 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 139 return 0; 140 #endif 141 142 /* Get some space for it */ 143 dev_priv->mch_res.name = "i915 MCHBAR"; 144 dev_priv->mch_res.flags = IORESOURCE_MEM; 145 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 146 &dev_priv->mch_res, 147 MCHBAR_SIZE, MCHBAR_SIZE, 148 PCIBIOS_MIN_MEM, 149 0, pcibios_align_resource, 150 dev_priv->bridge_dev); 151 if (ret) { 152 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 153 dev_priv->mch_res.start = 0; 154 return ret; 155 } 156 157 if (GRAPHICS_VER(dev_priv) >= 4) 158 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 159 upper_32_bits(dev_priv->mch_res.start)); 160 161 pci_write_config_dword(dev_priv->bridge_dev, reg, 162 lower_32_bits(dev_priv->mch_res.start)); 163 return 0; 164 } 165 166 /* Setup MCHBAR if possible, return true if we should disable it again */ 167 static void 168 intel_setup_mchbar(struct drm_i915_private *dev_priv) 169 { 170 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 171 u32 temp; 172 bool enabled; 173 174 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 175 return; 176 177 dev_priv->mchbar_need_disable = false; 178 179 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 180 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 181 enabled = !!(temp & DEVEN_MCHBAR_EN); 182 } else { 183 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 184 enabled = temp & 1; 185 } 186 187 /* If it's already enabled, don't have to do anything */ 188 if (enabled) 189 return; 190 191 if (intel_alloc_mchbar_resource(dev_priv)) 192 return; 193 194 dev_priv->mchbar_need_disable = true; 195 196 /* Space is allocated or reserved, so enable it. */ 197 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 198 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 199 temp | DEVEN_MCHBAR_EN); 200 } else { 201 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 202 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 203 } 204 } 205 206 static void 207 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 208 { 209 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 210 211 if (dev_priv->mchbar_need_disable) { 212 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 213 u32 deven_val; 214 215 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 216 &deven_val); 217 deven_val &= ~DEVEN_MCHBAR_EN; 218 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 219 deven_val); 220 } else { 221 u32 mchbar_val; 222 223 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 224 &mchbar_val); 225 mchbar_val &= ~1; 226 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 227 mchbar_val); 228 } 229 } 230 231 if (dev_priv->mch_res.start) 232 release_resource(&dev_priv->mch_res); 233 } 234 235 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 236 { 237 /* 238 * The i915 workqueue is primarily used for batched retirement of 239 * requests (and thus managing bo) once the task has been completed 240 * by the GPU. i915_retire_requests() is called directly when we 241 * need high-priority retirement, such as waiting for an explicit 242 * bo. 243 * 244 * It is also used for periodic low-priority events, such as 245 * idle-timers and recording error state. 246 * 247 * All tasks on the workqueue are expected to acquire the dev mutex 248 * so there is no point in running more than one instance of the 249 * workqueue at any time. Use an ordered one. 250 */ 251 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 252 if (dev_priv->wq == NULL) 253 goto out_err; 254 255 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 256 if (dev_priv->hotplug.dp_wq == NULL) 257 goto out_free_wq; 258 259 return 0; 260 261 out_free_wq: 262 destroy_workqueue(dev_priv->wq); 263 out_err: 264 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 265 266 return -ENOMEM; 267 } 268 269 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 270 { 271 destroy_workqueue(dev_priv->hotplug.dp_wq); 272 destroy_workqueue(dev_priv->wq); 273 } 274 275 /* 276 * We don't keep the workarounds for pre-production hardware, so we expect our 277 * driver to fail on these machines in one way or another. A little warning on 278 * dmesg may help both the user and the bug triagers. 279 * 280 * Our policy for removing pre-production workarounds is to keep the 281 * current gen workarounds as a guide to the bring-up of the next gen 282 * (workarounds have a habit of persisting!). Anything older than that 283 * should be removed along with the complications they introduce. 284 */ 285 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 286 { 287 bool pre = false; 288 289 pre |= IS_HSW_EARLY_SDV(dev_priv); 290 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 291 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 292 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 293 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 294 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 295 296 if (pre) { 297 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 298 "It may not be fully functional.\n"); 299 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 300 } 301 } 302 303 static void sanitize_gpu(struct drm_i915_private *i915) 304 { 305 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 306 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 307 } 308 309 /** 310 * i915_driver_early_probe - setup state not requiring device access 311 * @dev_priv: device private 312 * 313 * Initialize everything that is a "SW-only" state, that is state not 314 * requiring accessing the device or exposing the driver via kernel internal 315 * or userspace interfaces. Example steps belonging here: lock initialization, 316 * system memory allocation, setting up device specific attributes and 317 * function hooks not requiring accessing the device. 318 */ 319 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 320 { 321 int ret = 0; 322 323 if (i915_inject_probe_failure(dev_priv)) 324 return -ENODEV; 325 326 intel_device_info_subplatform_init(dev_priv); 327 intel_step_init(dev_priv); 328 329 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 330 331 spin_lock_init(&dev_priv->irq_lock); 332 spin_lock_init(&dev_priv->gpu_error.lock); 333 mutex_init(&dev_priv->backlight_lock); 334 335 mutex_init(&dev_priv->sb_lock); 336 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 337 338 mutex_init(&dev_priv->audio.mutex); 339 mutex_init(&dev_priv->wm.wm_mutex); 340 mutex_init(&dev_priv->pps_mutex); 341 mutex_init(&dev_priv->hdcp_comp_mutex); 342 343 i915_memcpy_init_early(dev_priv); 344 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 345 346 ret = i915_workqueues_init(dev_priv); 347 if (ret < 0) 348 return ret; 349 350 ret = vlv_suspend_init(dev_priv); 351 if (ret < 0) 352 goto err_workqueues; 353 354 ret = intel_region_ttm_device_init(dev_priv); 355 if (ret) 356 goto err_ttm; 357 358 intel_wopcm_init_early(&dev_priv->wopcm); 359 360 intel_root_gt_init_early(dev_priv); 361 362 i915_drm_clients_init(&dev_priv->clients, dev_priv); 363 364 i915_gem_init_early(dev_priv); 365 366 /* This must be called before any calls to HAS_PCH_* */ 367 intel_detect_pch(dev_priv); 368 369 intel_pm_setup(dev_priv); 370 ret = intel_power_domains_init(dev_priv); 371 if (ret < 0) 372 goto err_gem; 373 intel_irq_init(dev_priv); 374 intel_init_display_hooks(dev_priv); 375 intel_init_clock_gating_hooks(dev_priv); 376 377 intel_detect_preproduction_hw(dev_priv); 378 379 return 0; 380 381 err_gem: 382 i915_gem_cleanup_early(dev_priv); 383 intel_gt_driver_late_release_all(dev_priv); 384 i915_drm_clients_fini(&dev_priv->clients); 385 intel_region_ttm_device_fini(dev_priv); 386 err_ttm: 387 vlv_suspend_cleanup(dev_priv); 388 err_workqueues: 389 i915_workqueues_cleanup(dev_priv); 390 return ret; 391 } 392 393 /** 394 * i915_driver_late_release - cleanup the setup done in 395 * i915_driver_early_probe() 396 * @dev_priv: device private 397 */ 398 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 399 { 400 intel_irq_fini(dev_priv); 401 intel_power_domains_cleanup(dev_priv); 402 i915_gem_cleanup_early(dev_priv); 403 intel_gt_driver_late_release_all(dev_priv); 404 i915_drm_clients_fini(&dev_priv->clients); 405 intel_region_ttm_device_fini(dev_priv); 406 vlv_suspend_cleanup(dev_priv); 407 i915_workqueues_cleanup(dev_priv); 408 409 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 410 mutex_destroy(&dev_priv->sb_lock); 411 412 i915_params_free(&dev_priv->params); 413 } 414 415 /** 416 * i915_driver_mmio_probe - setup device MMIO 417 * @dev_priv: device private 418 * 419 * Setup minimal device state necessary for MMIO accesses later in the 420 * initialization sequence. The setup here should avoid any other device-wide 421 * side effects or exposing the driver via kernel internal or user space 422 * interfaces. 423 */ 424 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 425 { 426 int ret; 427 428 if (i915_inject_probe_failure(dev_priv)) 429 return -ENODEV; 430 431 ret = i915_get_bridge_dev(dev_priv); 432 if (ret < 0) 433 return ret; 434 435 ret = intel_uncore_init_mmio(&dev_priv->uncore); 436 if (ret) 437 return ret; 438 439 /* Try to make sure MCHBAR is enabled before poking at it */ 440 intel_setup_mchbar(dev_priv); 441 intel_device_info_runtime_init(dev_priv); 442 443 ret = intel_gt_init_mmio(to_gt(dev_priv)); 444 if (ret) 445 goto err_uncore; 446 447 /* As early as possible, scrub existing GPU state before clobbering */ 448 sanitize_gpu(dev_priv); 449 450 return 0; 451 452 err_uncore: 453 intel_teardown_mchbar(dev_priv); 454 intel_uncore_fini_mmio(&dev_priv->uncore); 455 pci_dev_put(dev_priv->bridge_dev); 456 457 return ret; 458 } 459 460 /** 461 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 462 * @dev_priv: device private 463 */ 464 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 465 { 466 intel_teardown_mchbar(dev_priv); 467 intel_uncore_fini_mmio(&dev_priv->uncore); 468 pci_dev_put(dev_priv->bridge_dev); 469 } 470 471 /** 472 * i915_set_dma_info - set all relevant PCI dma info as configured for the 473 * platform 474 * @i915: valid i915 instance 475 * 476 * Set the dma max segment size, device and coherent masks. The dma mask set 477 * needs to occur before i915_ggtt_probe_hw. 478 * 479 * A couple of platforms have special needs. Address them as well. 480 * 481 */ 482 static int i915_set_dma_info(struct drm_i915_private *i915) 483 { 484 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 485 int ret; 486 487 GEM_BUG_ON(!mask_size); 488 489 /* 490 * We don't have a max segment size, so set it to the max so sg's 491 * debugging layer doesn't complain 492 */ 493 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 494 495 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 496 if (ret) 497 goto mask_err; 498 499 /* overlay on gen2 is broken and can't address above 1G */ 500 if (GRAPHICS_VER(i915) == 2) 501 mask_size = 30; 502 503 /* 504 * 965GM sometimes incorrectly writes to hardware status page (HWS) 505 * using 32bit addressing, overwriting memory if HWS is located 506 * above 4GB. 507 * 508 * The documentation also mentions an issue with undefined 509 * behaviour if any general state is accessed within a page above 4GB, 510 * which also needs to be handled carefully. 511 */ 512 if (IS_I965G(i915) || IS_I965GM(i915)) 513 mask_size = 32; 514 515 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 516 if (ret) 517 goto mask_err; 518 519 return 0; 520 521 mask_err: 522 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 523 return ret; 524 } 525 526 static int i915_pcode_init(struct drm_i915_private *i915) 527 { 528 struct intel_gt *gt; 529 int id, ret; 530 531 for_each_gt(gt, i915, id) { 532 ret = intel_pcode_init(gt->uncore); 533 if (ret) { 534 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 535 return ret; 536 } 537 } 538 539 return 0; 540 } 541 542 /** 543 * i915_driver_hw_probe - setup state requiring device access 544 * @dev_priv: device private 545 * 546 * Setup state that requires accessing the device, but doesn't require 547 * exposing the driver via kernel internal or userspace interfaces. 548 */ 549 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 550 { 551 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 552 struct pci_dev *root_pdev; 553 int ret; 554 555 if (i915_inject_probe_failure(dev_priv)) 556 return -ENODEV; 557 558 if (HAS_PPGTT(dev_priv)) { 559 if (intel_vgpu_active(dev_priv) && 560 !intel_vgpu_has_full_ppgtt(dev_priv)) { 561 i915_report_error(dev_priv, 562 "incompatible vGPU found, support for isolated ppGTT required\n"); 563 return -ENXIO; 564 } 565 } 566 567 if (HAS_EXECLISTS(dev_priv)) { 568 /* 569 * Older GVT emulation depends upon intercepting CSB mmio, 570 * which we no longer use, preferring to use the HWSP cache 571 * instead. 572 */ 573 if (intel_vgpu_active(dev_priv) && 574 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 575 i915_report_error(dev_priv, 576 "old vGPU host found, support for HWSP emulation required\n"); 577 return -ENXIO; 578 } 579 } 580 581 /* needs to be done before ggtt probe */ 582 intel_dram_edram_detect(dev_priv); 583 584 ret = i915_set_dma_info(dev_priv); 585 if (ret) 586 return ret; 587 588 i915_perf_init(dev_priv); 589 590 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 591 if (ret) 592 goto err_perf; 593 594 ret = i915_ggtt_probe_hw(dev_priv); 595 if (ret) 596 goto err_perf; 597 598 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 599 if (ret) 600 goto err_ggtt; 601 602 ret = i915_ggtt_init_hw(dev_priv); 603 if (ret) 604 goto err_ggtt; 605 606 ret = intel_memory_regions_hw_probe(dev_priv); 607 if (ret) 608 goto err_ggtt; 609 610 ret = intel_gt_tiles_init(dev_priv); 611 if (ret) 612 goto err_mem_regions; 613 614 ret = i915_ggtt_enable_hw(dev_priv); 615 if (ret) { 616 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 617 goto err_mem_regions; 618 } 619 620 pci_set_master(pdev); 621 622 /* On the 945G/GM, the chipset reports the MSI capability on the 623 * integrated graphics even though the support isn't actually there 624 * according to the published specs. It doesn't appear to function 625 * correctly in testing on 945G. 626 * This may be a side effect of MSI having been made available for PEG 627 * and the registers being closely associated. 628 * 629 * According to chipset errata, on the 965GM, MSI interrupts may 630 * be lost or delayed, and was defeatured. MSI interrupts seem to 631 * get lost on g4x as well, and interrupt delivery seems to stay 632 * properly dead afterwards. So we'll just disable them for all 633 * pre-gen5 chipsets. 634 * 635 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 636 * interrupts even when in MSI mode. This results in spurious 637 * interrupt warnings if the legacy irq no. is shared with another 638 * device. The kernel then disables that interrupt source and so 639 * prevents the other device from working properly. 640 */ 641 if (GRAPHICS_VER(dev_priv) >= 5) { 642 if (pci_enable_msi(pdev) < 0) 643 drm_dbg(&dev_priv->drm, "can't enable MSI"); 644 } 645 646 ret = intel_gvt_init(dev_priv); 647 if (ret) 648 goto err_msi; 649 650 intel_opregion_setup(dev_priv); 651 652 ret = i915_pcode_init(dev_priv); 653 if (ret) 654 goto err_msi; 655 656 /* 657 * Fill the dram structure to get the system dram info. This will be 658 * used for memory latency calculation. 659 */ 660 intel_dram_detect(dev_priv); 661 662 intel_bw_init_hw(dev_priv); 663 664 /* 665 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 666 * This should be totally removed when we handle the pci states properly 667 * on runtime PM and on s2idle cases. 668 */ 669 root_pdev = pcie_find_root_port(pdev); 670 if (root_pdev) 671 pci_d3cold_disable(root_pdev); 672 673 return 0; 674 675 err_msi: 676 if (pdev->msi_enabled) 677 pci_disable_msi(pdev); 678 err_mem_regions: 679 intel_memory_regions_driver_release(dev_priv); 680 err_ggtt: 681 i915_ggtt_driver_release(dev_priv); 682 i915_gem_drain_freed_objects(dev_priv); 683 i915_ggtt_driver_late_release(dev_priv); 684 err_perf: 685 i915_perf_fini(dev_priv); 686 return ret; 687 } 688 689 /** 690 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 691 * @dev_priv: device private 692 */ 693 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 694 { 695 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 696 struct pci_dev *root_pdev; 697 698 i915_perf_fini(dev_priv); 699 700 if (pdev->msi_enabled) 701 pci_disable_msi(pdev); 702 703 root_pdev = pcie_find_root_port(pdev); 704 if (root_pdev) 705 pci_d3cold_enable(root_pdev); 706 } 707 708 /** 709 * i915_driver_register - register the driver with the rest of the system 710 * @dev_priv: device private 711 * 712 * Perform any steps necessary to make the driver available via kernel 713 * internal or userspace interfaces. 714 */ 715 static void i915_driver_register(struct drm_i915_private *dev_priv) 716 { 717 struct drm_device *dev = &dev_priv->drm; 718 719 i915_gem_driver_register(dev_priv); 720 i915_pmu_register(dev_priv); 721 722 intel_vgpu_register(dev_priv); 723 724 /* Reveal our presence to userspace */ 725 if (drm_dev_register(dev, 0)) { 726 drm_err(&dev_priv->drm, 727 "Failed to register driver for userspace access!\n"); 728 return; 729 } 730 731 i915_debugfs_register(dev_priv); 732 i915_setup_sysfs(dev_priv); 733 734 /* Depends on sysfs having been initialized */ 735 i915_perf_register(dev_priv); 736 737 intel_gt_driver_register(to_gt(dev_priv)); 738 739 intel_display_driver_register(dev_priv); 740 741 intel_power_domains_enable(dev_priv); 742 intel_runtime_pm_enable(&dev_priv->runtime_pm); 743 744 intel_register_dsm_handler(); 745 746 if (i915_switcheroo_register(dev_priv)) 747 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 748 } 749 750 /** 751 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 752 * @dev_priv: device private 753 */ 754 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 755 { 756 i915_switcheroo_unregister(dev_priv); 757 758 intel_unregister_dsm_handler(); 759 760 intel_runtime_pm_disable(&dev_priv->runtime_pm); 761 intel_power_domains_disable(dev_priv); 762 763 intel_display_driver_unregister(dev_priv); 764 765 intel_gt_driver_unregister(to_gt(dev_priv)); 766 767 i915_perf_unregister(dev_priv); 768 i915_pmu_unregister(dev_priv); 769 770 i915_teardown_sysfs(dev_priv); 771 drm_dev_unplug(&dev_priv->drm); 772 773 i915_gem_driver_unregister(dev_priv); 774 } 775 776 void 777 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 778 { 779 drm_printf(p, "iommu: %s\n", 780 str_enabled_disabled(i915_vtd_active(i915))); 781 } 782 783 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 784 { 785 if (drm_debug_enabled(DRM_UT_DRIVER)) { 786 struct drm_printer p = drm_debug_printer("i915 device info:"); 787 788 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 789 INTEL_DEVID(dev_priv), 790 INTEL_REVID(dev_priv), 791 intel_platform_name(INTEL_INFO(dev_priv)->platform), 792 intel_subplatform(RUNTIME_INFO(dev_priv), 793 INTEL_INFO(dev_priv)->platform), 794 GRAPHICS_VER(dev_priv)); 795 796 intel_device_info_print_static(INTEL_INFO(dev_priv), &p); 797 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); 798 i915_print_iommu_status(dev_priv, &p); 799 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 800 } 801 802 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 803 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 804 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 805 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 806 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 807 drm_info(&dev_priv->drm, 808 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 809 } 810 811 static struct drm_i915_private * 812 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 813 { 814 const struct intel_device_info *match_info = 815 (struct intel_device_info *)ent->driver_data; 816 struct intel_device_info *device_info; 817 struct drm_i915_private *i915; 818 819 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 820 struct drm_i915_private, drm); 821 if (IS_ERR(i915)) 822 return i915; 823 824 pci_set_drvdata(pdev, i915); 825 826 /* Device parameters start as a copy of module parameters. */ 827 i915_params_copy(&i915->params, &i915_modparams); 828 829 /* Setup the write-once "constant" device info */ 830 device_info = mkwrite_device_info(i915); 831 memcpy(device_info, match_info, sizeof(*device_info)); 832 RUNTIME_INFO(i915)->device_id = pdev->device; 833 834 return i915; 835 } 836 837 /** 838 * i915_driver_probe - setup chip and create an initial config 839 * @pdev: PCI device 840 * @ent: matching PCI ID entry 841 * 842 * The driver probe routine has to do several things: 843 * - drive output discovery via intel_modeset_init() 844 * - initialize the memory manager 845 * - allocate initial config memory 846 * - setup the DRM framebuffer with the allocated memory 847 */ 848 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 849 { 850 struct drm_i915_private *i915; 851 int ret; 852 853 i915 = i915_driver_create(pdev, ent); 854 if (IS_ERR(i915)) 855 return PTR_ERR(i915); 856 857 /* Disable nuclear pageflip by default on pre-ILK */ 858 if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5) 859 i915->drm.driver_features &= ~DRIVER_ATOMIC; 860 861 ret = pci_enable_device(pdev); 862 if (ret) 863 goto out_fini; 864 865 ret = i915_driver_early_probe(i915); 866 if (ret < 0) 867 goto out_pci_disable; 868 869 disable_rpm_wakeref_asserts(&i915->runtime_pm); 870 871 intel_vgpu_detect(i915); 872 873 ret = intel_gt_probe_all(i915); 874 if (ret < 0) 875 goto out_runtime_pm_put; 876 877 ret = i915_driver_mmio_probe(i915); 878 if (ret < 0) 879 goto out_tiles_cleanup; 880 881 ret = i915_driver_hw_probe(i915); 882 if (ret < 0) 883 goto out_cleanup_mmio; 884 885 ret = intel_modeset_init_noirq(i915); 886 if (ret < 0) 887 goto out_cleanup_hw; 888 889 ret = intel_irq_install(i915); 890 if (ret) 891 goto out_cleanup_modeset; 892 893 ret = intel_modeset_init_nogem(i915); 894 if (ret) 895 goto out_cleanup_irq; 896 897 ret = i915_gem_init(i915); 898 if (ret) 899 goto out_cleanup_modeset2; 900 901 ret = intel_modeset_init(i915); 902 if (ret) 903 goto out_cleanup_gem; 904 905 i915_driver_register(i915); 906 907 enable_rpm_wakeref_asserts(&i915->runtime_pm); 908 909 i915_welcome_messages(i915); 910 911 i915->do_release = true; 912 913 return 0; 914 915 out_cleanup_gem: 916 i915_gem_suspend(i915); 917 i915_gem_driver_remove(i915); 918 i915_gem_driver_release(i915); 919 out_cleanup_modeset2: 920 /* FIXME clean up the error path */ 921 intel_modeset_driver_remove(i915); 922 intel_irq_uninstall(i915); 923 intel_modeset_driver_remove_noirq(i915); 924 goto out_cleanup_modeset; 925 out_cleanup_irq: 926 intel_irq_uninstall(i915); 927 out_cleanup_modeset: 928 intel_modeset_driver_remove_nogem(i915); 929 out_cleanup_hw: 930 i915_driver_hw_remove(i915); 931 intel_memory_regions_driver_release(i915); 932 i915_ggtt_driver_release(i915); 933 i915_gem_drain_freed_objects(i915); 934 i915_ggtt_driver_late_release(i915); 935 out_cleanup_mmio: 936 i915_driver_mmio_release(i915); 937 out_tiles_cleanup: 938 intel_gt_release_all(i915); 939 out_runtime_pm_put: 940 enable_rpm_wakeref_asserts(&i915->runtime_pm); 941 i915_driver_late_release(i915); 942 out_pci_disable: 943 pci_disable_device(pdev); 944 out_fini: 945 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 946 return ret; 947 } 948 949 void i915_driver_remove(struct drm_i915_private *i915) 950 { 951 disable_rpm_wakeref_asserts(&i915->runtime_pm); 952 953 i915_driver_unregister(i915); 954 955 /* Flush any external code that still may be under the RCU lock */ 956 synchronize_rcu(); 957 958 i915_gem_suspend(i915); 959 960 intel_gvt_driver_remove(i915); 961 962 intel_modeset_driver_remove(i915); 963 964 intel_irq_uninstall(i915); 965 966 intel_modeset_driver_remove_noirq(i915); 967 968 i915_reset_error_state(i915); 969 i915_gem_driver_remove(i915); 970 971 intel_modeset_driver_remove_nogem(i915); 972 973 i915_driver_hw_remove(i915); 974 975 enable_rpm_wakeref_asserts(&i915->runtime_pm); 976 } 977 978 static void i915_driver_release(struct drm_device *dev) 979 { 980 struct drm_i915_private *dev_priv = to_i915(dev); 981 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 982 983 if (!dev_priv->do_release) 984 return; 985 986 disable_rpm_wakeref_asserts(rpm); 987 988 i915_gem_driver_release(dev_priv); 989 990 intel_memory_regions_driver_release(dev_priv); 991 i915_ggtt_driver_release(dev_priv); 992 i915_gem_drain_freed_objects(dev_priv); 993 i915_ggtt_driver_late_release(dev_priv); 994 995 i915_driver_mmio_release(dev_priv); 996 997 enable_rpm_wakeref_asserts(rpm); 998 intel_runtime_pm_driver_release(rpm); 999 1000 i915_driver_late_release(dev_priv); 1001 } 1002 1003 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 1004 { 1005 struct drm_i915_private *i915 = to_i915(dev); 1006 int ret; 1007 1008 ret = i915_gem_open(i915, file); 1009 if (ret) 1010 return ret; 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * i915_driver_lastclose - clean up after all DRM clients have exited 1017 * @dev: DRM device 1018 * 1019 * Take care of cleaning up after all DRM clients have exited. In the 1020 * mode setting case, we want to restore the kernel's initial mode (just 1021 * in case the last client left us in a bad state). 1022 * 1023 * Additionally, in the non-mode setting case, we'll tear down the GTT 1024 * and DMA structures, since the kernel won't be using them, and clea 1025 * up any GEM state. 1026 */ 1027 static void i915_driver_lastclose(struct drm_device *dev) 1028 { 1029 struct drm_i915_private *i915 = to_i915(dev); 1030 1031 intel_fbdev_restore_mode(dev); 1032 1033 if (HAS_DISPLAY(i915)) 1034 vga_switcheroo_process_delayed_switch(); 1035 } 1036 1037 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1038 { 1039 struct drm_i915_file_private *file_priv = file->driver_priv; 1040 1041 i915_gem_context_close(file); 1042 i915_drm_client_put(file_priv->client); 1043 1044 kfree_rcu(file_priv, rcu); 1045 1046 /* Catch up with all the deferred frees from "this" client */ 1047 i915_gem_flush_free_objects(to_i915(dev)); 1048 } 1049 1050 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1051 { 1052 struct drm_device *dev = &dev_priv->drm; 1053 struct intel_encoder *encoder; 1054 1055 if (!HAS_DISPLAY(dev_priv)) 1056 return; 1057 1058 drm_modeset_lock_all(dev); 1059 for_each_intel_encoder(dev, encoder) 1060 if (encoder->suspend) 1061 encoder->suspend(encoder); 1062 drm_modeset_unlock_all(dev); 1063 } 1064 1065 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1066 { 1067 struct drm_device *dev = &dev_priv->drm; 1068 struct intel_encoder *encoder; 1069 1070 if (!HAS_DISPLAY(dev_priv)) 1071 return; 1072 1073 drm_modeset_lock_all(dev); 1074 for_each_intel_encoder(dev, encoder) 1075 if (encoder->shutdown) 1076 encoder->shutdown(encoder); 1077 drm_modeset_unlock_all(dev); 1078 } 1079 1080 void i915_driver_shutdown(struct drm_i915_private *i915) 1081 { 1082 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1083 intel_runtime_pm_disable(&i915->runtime_pm); 1084 intel_power_domains_disable(i915); 1085 1086 if (HAS_DISPLAY(i915)) { 1087 drm_kms_helper_poll_disable(&i915->drm); 1088 1089 drm_atomic_helper_shutdown(&i915->drm); 1090 } 1091 1092 intel_dp_mst_suspend(i915); 1093 1094 intel_runtime_pm_disable_interrupts(i915); 1095 intel_hpd_cancel_work(i915); 1096 1097 intel_suspend_encoders(i915); 1098 intel_shutdown_encoders(i915); 1099 1100 intel_dmc_ucode_suspend(i915); 1101 1102 i915_gem_suspend(i915); 1103 1104 /* 1105 * The only requirement is to reboot with display DC states disabled, 1106 * for now leaving all display power wells in the INIT power domain 1107 * enabled. 1108 * 1109 * TODO: 1110 * - unify the pci_driver::shutdown sequence here with the 1111 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1112 * - unify the driver remove and system/runtime suspend sequences with 1113 * the above unified shutdown/poweroff sequence. 1114 */ 1115 intel_power_domains_driver_remove(i915); 1116 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1117 1118 intel_runtime_pm_driver_release(&i915->runtime_pm); 1119 } 1120 1121 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1122 { 1123 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1124 if (acpi_target_system_state() < ACPI_STATE_S3) 1125 return true; 1126 #endif 1127 return false; 1128 } 1129 1130 static int i915_drm_prepare(struct drm_device *dev) 1131 { 1132 struct drm_i915_private *i915 = to_i915(dev); 1133 1134 /* 1135 * NB intel_display_suspend() may issue new requests after we've 1136 * ostensibly marked the GPU as ready-to-sleep here. We need to 1137 * split out that work and pull it forward so that after point, 1138 * the GPU is not woken again. 1139 */ 1140 return i915_gem_backup_suspend(i915); 1141 } 1142 1143 static int i915_drm_suspend(struct drm_device *dev) 1144 { 1145 struct drm_i915_private *dev_priv = to_i915(dev); 1146 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1147 pci_power_t opregion_target_state; 1148 1149 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1150 1151 /* We do a lot of poking in a lot of registers, make sure they work 1152 * properly. */ 1153 intel_power_domains_disable(dev_priv); 1154 if (HAS_DISPLAY(dev_priv)) 1155 drm_kms_helper_poll_disable(dev); 1156 1157 pci_save_state(pdev); 1158 1159 intel_display_suspend(dev); 1160 1161 intel_dp_mst_suspend(dev_priv); 1162 1163 intel_runtime_pm_disable_interrupts(dev_priv); 1164 intel_hpd_cancel_work(dev_priv); 1165 1166 intel_suspend_encoders(dev_priv); 1167 1168 intel_suspend_hw(dev_priv); 1169 1170 /* Must be called before GGTT is suspended. */ 1171 intel_dpt_suspend(dev_priv); 1172 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1173 1174 i915_save_display(dev_priv); 1175 1176 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1177 intel_opregion_suspend(dev_priv, opregion_target_state); 1178 1179 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1180 1181 dev_priv->suspend_count++; 1182 1183 intel_dmc_ucode_suspend(dev_priv); 1184 1185 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1186 1187 i915_gem_drain_freed_objects(dev_priv); 1188 1189 return 0; 1190 } 1191 1192 static enum i915_drm_suspend_mode 1193 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1194 { 1195 if (hibernate) 1196 return I915_DRM_SUSPEND_HIBERNATE; 1197 1198 if (suspend_to_idle(dev_priv)) 1199 return I915_DRM_SUSPEND_IDLE; 1200 1201 return I915_DRM_SUSPEND_MEM; 1202 } 1203 1204 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1205 { 1206 struct drm_i915_private *dev_priv = to_i915(dev); 1207 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1208 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1209 int ret; 1210 1211 disable_rpm_wakeref_asserts(rpm); 1212 1213 i915_gem_suspend_late(dev_priv); 1214 1215 intel_uncore_suspend(&dev_priv->uncore); 1216 1217 intel_power_domains_suspend(dev_priv, 1218 get_suspend_mode(dev_priv, hibernation)); 1219 1220 intel_display_power_suspend_late(dev_priv); 1221 1222 ret = vlv_suspend_complete(dev_priv); 1223 if (ret) { 1224 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1225 intel_power_domains_resume(dev_priv); 1226 1227 goto out; 1228 } 1229 1230 pci_disable_device(pdev); 1231 /* 1232 * During hibernation on some platforms the BIOS may try to access 1233 * the device even though it's already in D3 and hang the machine. So 1234 * leave the device in D0 on those platforms and hope the BIOS will 1235 * power down the device properly. The issue was seen on multiple old 1236 * GENs with different BIOS vendors, so having an explicit blacklist 1237 * is inpractical; apply the workaround on everything pre GEN6. The 1238 * platforms where the issue was seen: 1239 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1240 * Fujitsu FSC S7110 1241 * Acer Aspire 1830T 1242 */ 1243 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1244 pci_set_power_state(pdev, PCI_D3hot); 1245 1246 out: 1247 enable_rpm_wakeref_asserts(rpm); 1248 if (!dev_priv->uncore.user_forcewake_count) 1249 intel_runtime_pm_driver_release(rpm); 1250 1251 return ret; 1252 } 1253 1254 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1255 pm_message_t state) 1256 { 1257 int error; 1258 1259 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1260 state.event != PM_EVENT_FREEZE)) 1261 return -EINVAL; 1262 1263 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1264 return 0; 1265 1266 error = i915_drm_suspend(&i915->drm); 1267 if (error) 1268 return error; 1269 1270 return i915_drm_suspend_late(&i915->drm, false); 1271 } 1272 1273 static int i915_drm_resume(struct drm_device *dev) 1274 { 1275 struct drm_i915_private *dev_priv = to_i915(dev); 1276 int ret; 1277 1278 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1279 1280 ret = i915_pcode_init(dev_priv); 1281 if (ret) 1282 return ret; 1283 1284 sanitize_gpu(dev_priv); 1285 1286 ret = i915_ggtt_enable_hw(dev_priv); 1287 if (ret) 1288 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1289 1290 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1291 /* Must be called after GGTT is resumed. */ 1292 intel_dpt_resume(dev_priv); 1293 1294 intel_dmc_ucode_resume(dev_priv); 1295 1296 i915_restore_display(dev_priv); 1297 intel_pps_unlock_regs_wa(dev_priv); 1298 1299 intel_init_pch_refclk(dev_priv); 1300 1301 /* 1302 * Interrupts have to be enabled before any batches are run. If not the 1303 * GPU will hang. i915_gem_init_hw() will initiate batches to 1304 * update/restore the context. 1305 * 1306 * drm_mode_config_reset() needs AUX interrupts. 1307 * 1308 * Modeset enabling in intel_modeset_init_hw() also needs working 1309 * interrupts. 1310 */ 1311 intel_runtime_pm_enable_interrupts(dev_priv); 1312 1313 if (HAS_DISPLAY(dev_priv)) 1314 drm_mode_config_reset(dev); 1315 1316 i915_gem_resume(dev_priv); 1317 1318 intel_modeset_init_hw(dev_priv); 1319 intel_init_clock_gating(dev_priv); 1320 intel_hpd_init(dev_priv); 1321 1322 /* MST sideband requires HPD interrupts enabled */ 1323 intel_dp_mst_resume(dev_priv); 1324 intel_display_resume(dev); 1325 1326 intel_hpd_poll_disable(dev_priv); 1327 if (HAS_DISPLAY(dev_priv)) 1328 drm_kms_helper_poll_enable(dev); 1329 1330 intel_opregion_resume(dev_priv); 1331 1332 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1333 1334 intel_power_domains_enable(dev_priv); 1335 1336 intel_gvt_resume(dev_priv); 1337 1338 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1339 1340 return 0; 1341 } 1342 1343 static int i915_drm_resume_early(struct drm_device *dev) 1344 { 1345 struct drm_i915_private *dev_priv = to_i915(dev); 1346 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1347 int ret; 1348 1349 /* 1350 * We have a resume ordering issue with the snd-hda driver also 1351 * requiring our device to be power up. Due to the lack of a 1352 * parent/child relationship we currently solve this with an early 1353 * resume hook. 1354 * 1355 * FIXME: This should be solved with a special hdmi sink device or 1356 * similar so that power domains can be employed. 1357 */ 1358 1359 /* 1360 * Note that we need to set the power state explicitly, since we 1361 * powered off the device during freeze and the PCI core won't power 1362 * it back up for us during thaw. Powering off the device during 1363 * freeze is not a hard requirement though, and during the 1364 * suspend/resume phases the PCI core makes sure we get here with the 1365 * device powered on. So in case we change our freeze logic and keep 1366 * the device powered we can also remove the following set power state 1367 * call. 1368 */ 1369 ret = pci_set_power_state(pdev, PCI_D0); 1370 if (ret) { 1371 drm_err(&dev_priv->drm, 1372 "failed to set PCI D0 power state (%d)\n", ret); 1373 return ret; 1374 } 1375 1376 /* 1377 * Note that pci_enable_device() first enables any parent bridge 1378 * device and only then sets the power state for this device. The 1379 * bridge enabling is a nop though, since bridge devices are resumed 1380 * first. The order of enabling power and enabling the device is 1381 * imposed by the PCI core as described above, so here we preserve the 1382 * same order for the freeze/thaw phases. 1383 * 1384 * TODO: eventually we should remove pci_disable_device() / 1385 * pci_enable_enable_device() from suspend/resume. Due to how they 1386 * depend on the device enable refcount we can't anyway depend on them 1387 * disabling/enabling the device. 1388 */ 1389 if (pci_enable_device(pdev)) 1390 return -EIO; 1391 1392 pci_set_master(pdev); 1393 1394 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1395 1396 ret = vlv_resume_prepare(dev_priv, false); 1397 if (ret) 1398 drm_err(&dev_priv->drm, 1399 "Resume prepare failed: %d, continuing anyway\n", ret); 1400 1401 intel_uncore_resume_early(&dev_priv->uncore); 1402 1403 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1404 1405 intel_display_power_resume_early(dev_priv); 1406 1407 intel_power_domains_resume(dev_priv); 1408 1409 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1410 1411 return ret; 1412 } 1413 1414 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1415 { 1416 int ret; 1417 1418 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1419 return 0; 1420 1421 ret = i915_drm_resume_early(&i915->drm); 1422 if (ret) 1423 return ret; 1424 1425 return i915_drm_resume(&i915->drm); 1426 } 1427 1428 static int i915_pm_prepare(struct device *kdev) 1429 { 1430 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1431 1432 if (!i915) { 1433 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1434 return -ENODEV; 1435 } 1436 1437 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1438 return 0; 1439 1440 return i915_drm_prepare(&i915->drm); 1441 } 1442 1443 static int i915_pm_suspend(struct device *kdev) 1444 { 1445 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1446 1447 if (!i915) { 1448 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1449 return -ENODEV; 1450 } 1451 1452 i915_ggtt_mark_pte_lost(i915, false); 1453 1454 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1455 return 0; 1456 1457 return i915_drm_suspend(&i915->drm); 1458 } 1459 1460 static int i915_pm_suspend_late(struct device *kdev) 1461 { 1462 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1463 1464 /* 1465 * We have a suspend ordering issue with the snd-hda driver also 1466 * requiring our device to be power up. Due to the lack of a 1467 * parent/child relationship we currently solve this with an late 1468 * suspend hook. 1469 * 1470 * FIXME: This should be solved with a special hdmi sink device or 1471 * similar so that power domains can be employed. 1472 */ 1473 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1474 return 0; 1475 1476 return i915_drm_suspend_late(&i915->drm, false); 1477 } 1478 1479 static int i915_pm_poweroff_late(struct device *kdev) 1480 { 1481 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1482 1483 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1484 return 0; 1485 1486 return i915_drm_suspend_late(&i915->drm, true); 1487 } 1488 1489 static int i915_pm_resume_early(struct device *kdev) 1490 { 1491 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1492 1493 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1494 return 0; 1495 1496 return i915_drm_resume_early(&i915->drm); 1497 } 1498 1499 static int i915_pm_resume(struct device *kdev) 1500 { 1501 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1502 1503 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1504 return 0; 1505 1506 /* 1507 * If IRST is enabled, or if we can't detect whether it's enabled, 1508 * then we must assume we lost the GGTT page table entries, since 1509 * they are not retained if IRST decided to enter S4. 1510 */ 1511 if (!IS_ENABLED(CONFIG_ACPI) || acpi_dev_present(irst_name, NULL, -1)) 1512 i915_ggtt_mark_pte_lost(i915, true); 1513 1514 return i915_drm_resume(&i915->drm); 1515 } 1516 1517 /* freeze: before creating the hibernation_image */ 1518 static int i915_pm_freeze(struct device *kdev) 1519 { 1520 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1521 int ret; 1522 1523 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1524 ret = i915_drm_suspend(&i915->drm); 1525 if (ret) 1526 return ret; 1527 } 1528 1529 ret = i915_gem_freeze(i915); 1530 if (ret) 1531 return ret; 1532 1533 return 0; 1534 } 1535 1536 static int i915_pm_freeze_late(struct device *kdev) 1537 { 1538 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1539 int ret; 1540 1541 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1542 ret = i915_drm_suspend_late(&i915->drm, true); 1543 if (ret) 1544 return ret; 1545 } 1546 1547 ret = i915_gem_freeze_late(i915); 1548 if (ret) 1549 return ret; 1550 1551 return 0; 1552 } 1553 1554 /* thaw: called after creating the hibernation image, but before turning off. */ 1555 static int i915_pm_thaw_early(struct device *kdev) 1556 { 1557 return i915_pm_resume_early(kdev); 1558 } 1559 1560 static int i915_pm_thaw(struct device *kdev) 1561 { 1562 return i915_pm_resume(kdev); 1563 } 1564 1565 /* restore: called after loading the hibernation image. */ 1566 static int i915_pm_restore_early(struct device *kdev) 1567 { 1568 return i915_pm_resume_early(kdev); 1569 } 1570 1571 static int i915_pm_restore(struct device *kdev) 1572 { 1573 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1574 1575 i915_ggtt_mark_pte_lost(i915, true); 1576 return i915_pm_resume(kdev); 1577 } 1578 1579 static int intel_runtime_suspend(struct device *kdev) 1580 { 1581 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1582 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1583 int ret; 1584 1585 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1586 return -ENODEV; 1587 1588 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1589 1590 disable_rpm_wakeref_asserts(rpm); 1591 1592 /* 1593 * We are safe here against re-faults, since the fault handler takes 1594 * an RPM reference. 1595 */ 1596 i915_gem_runtime_suspend(dev_priv); 1597 1598 intel_gt_runtime_suspend(to_gt(dev_priv)); 1599 1600 intel_runtime_pm_disable_interrupts(dev_priv); 1601 1602 intel_uncore_suspend(&dev_priv->uncore); 1603 1604 intel_display_power_suspend(dev_priv); 1605 1606 ret = vlv_suspend_complete(dev_priv); 1607 if (ret) { 1608 drm_err(&dev_priv->drm, 1609 "Runtime suspend failed, disabling it (%d)\n", ret); 1610 intel_uncore_runtime_resume(&dev_priv->uncore); 1611 1612 intel_runtime_pm_enable_interrupts(dev_priv); 1613 1614 intel_gt_runtime_resume(to_gt(dev_priv)); 1615 1616 enable_rpm_wakeref_asserts(rpm); 1617 1618 return ret; 1619 } 1620 1621 enable_rpm_wakeref_asserts(rpm); 1622 intel_runtime_pm_driver_release(rpm); 1623 1624 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1625 drm_err(&dev_priv->drm, 1626 "Unclaimed access detected prior to suspending\n"); 1627 1628 rpm->suspended = true; 1629 1630 /* 1631 * FIXME: We really should find a document that references the arguments 1632 * used below! 1633 */ 1634 if (IS_BROADWELL(dev_priv)) { 1635 /* 1636 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1637 * being detected, and the call we do at intel_runtime_resume() 1638 * won't be able to restore them. Since PCI_D3hot matches the 1639 * actual specification and appears to be working, use it. 1640 */ 1641 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1642 } else { 1643 /* 1644 * current versions of firmware which depend on this opregion 1645 * notification have repurposed the D1 definition to mean 1646 * "runtime suspended" vs. what you would normally expect (D3) 1647 * to distinguish it from notifications that might be sent via 1648 * the suspend path. 1649 */ 1650 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1651 } 1652 1653 assert_forcewakes_inactive(&dev_priv->uncore); 1654 1655 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1656 intel_hpd_poll_enable(dev_priv); 1657 1658 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1659 return 0; 1660 } 1661 1662 static int intel_runtime_resume(struct device *kdev) 1663 { 1664 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1665 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1666 int ret; 1667 1668 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1669 return -ENODEV; 1670 1671 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1672 1673 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1674 disable_rpm_wakeref_asserts(rpm); 1675 1676 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1677 rpm->suspended = false; 1678 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1679 drm_dbg(&dev_priv->drm, 1680 "Unclaimed access during suspend, bios?\n"); 1681 1682 intel_display_power_resume(dev_priv); 1683 1684 ret = vlv_resume_prepare(dev_priv, true); 1685 1686 intel_uncore_runtime_resume(&dev_priv->uncore); 1687 1688 intel_runtime_pm_enable_interrupts(dev_priv); 1689 1690 /* 1691 * No point of rolling back things in case of an error, as the best 1692 * we can do is to hope that things will still work (and disable RPM). 1693 */ 1694 intel_gt_runtime_resume(to_gt(dev_priv)); 1695 1696 /* 1697 * On VLV/CHV display interrupts are part of the display 1698 * power well, so hpd is reinitialized from there. For 1699 * everyone else do it here. 1700 */ 1701 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1702 intel_hpd_init(dev_priv); 1703 intel_hpd_poll_disable(dev_priv); 1704 } 1705 1706 intel_enable_ipc(dev_priv); 1707 1708 enable_rpm_wakeref_asserts(rpm); 1709 1710 if (ret) 1711 drm_err(&dev_priv->drm, 1712 "Runtime resume failed, disabling it (%d)\n", ret); 1713 else 1714 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1715 1716 return ret; 1717 } 1718 1719 const struct dev_pm_ops i915_pm_ops = { 1720 /* 1721 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1722 * PMSG_RESUME] 1723 */ 1724 .prepare = i915_pm_prepare, 1725 .suspend = i915_pm_suspend, 1726 .suspend_late = i915_pm_suspend_late, 1727 .resume_early = i915_pm_resume_early, 1728 .resume = i915_pm_resume, 1729 1730 /* 1731 * S4 event handlers 1732 * @freeze, @freeze_late : called (1) before creating the 1733 * hibernation image [PMSG_FREEZE] and 1734 * (2) after rebooting, before restoring 1735 * the image [PMSG_QUIESCE] 1736 * @thaw, @thaw_early : called (1) after creating the hibernation 1737 * image, before writing it [PMSG_THAW] 1738 * and (2) after failing to create or 1739 * restore the image [PMSG_RECOVER] 1740 * @poweroff, @poweroff_late: called after writing the hibernation 1741 * image, before rebooting [PMSG_HIBERNATE] 1742 * @restore, @restore_early : called after rebooting and restoring the 1743 * hibernation image [PMSG_RESTORE] 1744 */ 1745 .freeze = i915_pm_freeze, 1746 .freeze_late = i915_pm_freeze_late, 1747 .thaw_early = i915_pm_thaw_early, 1748 .thaw = i915_pm_thaw, 1749 .poweroff = i915_pm_suspend, 1750 .poweroff_late = i915_pm_poweroff_late, 1751 .restore_early = i915_pm_restore_early, 1752 .restore = i915_pm_restore, 1753 1754 /* S0ix (via runtime suspend) event handlers */ 1755 .runtime_suspend = intel_runtime_suspend, 1756 .runtime_resume = intel_runtime_resume, 1757 }; 1758 1759 static const struct file_operations i915_driver_fops = { 1760 .owner = THIS_MODULE, 1761 .open = drm_open, 1762 .release = drm_release_noglobal, 1763 .unlocked_ioctl = drm_ioctl, 1764 .mmap = i915_gem_mmap, 1765 .poll = drm_poll, 1766 .read = drm_read, 1767 .compat_ioctl = i915_ioc32_compat_ioctl, 1768 .llseek = noop_llseek, 1769 #ifdef CONFIG_PROC_FS 1770 .show_fdinfo = i915_drm_client_fdinfo, 1771 #endif 1772 }; 1773 1774 static int 1775 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1776 struct drm_file *file) 1777 { 1778 return -ENODEV; 1779 } 1780 1781 static const struct drm_ioctl_desc i915_ioctls[] = { 1782 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1783 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1784 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1785 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1786 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1787 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1788 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1789 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1790 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1791 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1792 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1793 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1794 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1795 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1796 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1797 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1798 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1799 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1800 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1801 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1802 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1804 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1805 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1806 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1807 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1809 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1810 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1815 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1820 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1821 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1822 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1823 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1824 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1825 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1826 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1827 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1828 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1829 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1830 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1831 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1832 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1833 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1834 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1835 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1836 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1837 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1838 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1839 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1840 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1841 }; 1842 1843 /* 1844 * Interface history: 1845 * 1846 * 1.1: Original. 1847 * 1.2: Add Power Management 1848 * 1.3: Add vblank support 1849 * 1.4: Fix cmdbuffer path, add heap destroy 1850 * 1.5: Add vblank pipe configuration 1851 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1852 * - Support vertical blank on secondary display pipe 1853 */ 1854 #define DRIVER_MAJOR 1 1855 #define DRIVER_MINOR 6 1856 #define DRIVER_PATCHLEVEL 0 1857 1858 static const struct drm_driver i915_drm_driver = { 1859 /* Don't use MTRRs here; the Xserver or userspace app should 1860 * deal with them for Intel hardware. 1861 */ 1862 .driver_features = 1863 DRIVER_GEM | 1864 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1865 DRIVER_SYNCOBJ_TIMELINE, 1866 .release = i915_driver_release, 1867 .open = i915_driver_open, 1868 .lastclose = i915_driver_lastclose, 1869 .postclose = i915_driver_postclose, 1870 1871 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1872 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1873 .gem_prime_import = i915_gem_prime_import, 1874 1875 .dumb_create = i915_gem_dumb_create, 1876 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1877 1878 .ioctls = i915_ioctls, 1879 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1880 .fops = &i915_driver_fops, 1881 .name = DRIVER_NAME, 1882 .desc = DRIVER_DESC, 1883 .date = DRIVER_DATE, 1884 .major = DRIVER_MAJOR, 1885 .minor = DRIVER_MINOR, 1886 .patchlevel = DRIVER_PATCHLEVEL, 1887 }; 1888