1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 65 #include "gem/i915_gem_context.h" 66 #include "gem/i915_gem_create.h" 67 #include "gem/i915_gem_dmabuf.h" 68 #include "gem/i915_gem_ioctls.h" 69 #include "gem/i915_gem_mman.h" 70 #include "gem/i915_gem_pm.h" 71 #include "gt/intel_gt.h" 72 #include "gt/intel_gt_pm.h" 73 #include "gt/intel_rc6.h" 74 75 #include "pxp/intel_pxp_pm.h" 76 77 #include "i915_file_private.h" 78 #include "i915_debugfs.h" 79 #include "i915_driver.h" 80 #include "i915_drv.h" 81 #include "i915_getparam.h" 82 #include "i915_ioc32.h" 83 #include "i915_ioctl.h" 84 #include "i915_irq.h" 85 #include "i915_memcpy.h" 86 #include "i915_perf.h" 87 #include "i915_query.h" 88 #include "i915_suspend.h" 89 #include "i915_switcheroo.h" 90 #include "i915_sysfs.h" 91 #include "i915_utils.h" 92 #include "i915_vgpu.h" 93 #include "intel_dram.h" 94 #include "intel_gvt.h" 95 #include "intel_memory_region.h" 96 #include "intel_pci_config.h" 97 #include "intel_pcode.h" 98 #include "intel_pm.h" 99 #include "intel_region_ttm.h" 100 #include "vlv_suspend.h" 101 102 static const struct drm_driver i915_drm_driver; 103 104 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 105 { 106 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 107 108 dev_priv->bridge_dev = 109 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 110 if (!dev_priv->bridge_dev) { 111 drm_err(&dev_priv->drm, "bridge device not found\n"); 112 return -EIO; 113 } 114 return 0; 115 } 116 117 /* Allocate space for the MCH regs if needed, return nonzero on error */ 118 static int 119 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 120 { 121 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 122 u32 temp_lo, temp_hi = 0; 123 u64 mchbar_addr; 124 int ret; 125 126 if (GRAPHICS_VER(dev_priv) >= 4) 127 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 128 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 129 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 130 131 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 132 #ifdef CONFIG_PNP 133 if (mchbar_addr && 134 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 135 return 0; 136 #endif 137 138 /* Get some space for it */ 139 dev_priv->mch_res.name = "i915 MCHBAR"; 140 dev_priv->mch_res.flags = IORESOURCE_MEM; 141 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 142 &dev_priv->mch_res, 143 MCHBAR_SIZE, MCHBAR_SIZE, 144 PCIBIOS_MIN_MEM, 145 0, pcibios_align_resource, 146 dev_priv->bridge_dev); 147 if (ret) { 148 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 149 dev_priv->mch_res.start = 0; 150 return ret; 151 } 152 153 if (GRAPHICS_VER(dev_priv) >= 4) 154 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 155 upper_32_bits(dev_priv->mch_res.start)); 156 157 pci_write_config_dword(dev_priv->bridge_dev, reg, 158 lower_32_bits(dev_priv->mch_res.start)); 159 return 0; 160 } 161 162 /* Setup MCHBAR if possible, return true if we should disable it again */ 163 static void 164 intel_setup_mchbar(struct drm_i915_private *dev_priv) 165 { 166 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 167 u32 temp; 168 bool enabled; 169 170 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 171 return; 172 173 dev_priv->mchbar_need_disable = false; 174 175 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 176 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 177 enabled = !!(temp & DEVEN_MCHBAR_EN); 178 } else { 179 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 180 enabled = temp & 1; 181 } 182 183 /* If it's already enabled, don't have to do anything */ 184 if (enabled) 185 return; 186 187 if (intel_alloc_mchbar_resource(dev_priv)) 188 return; 189 190 dev_priv->mchbar_need_disable = true; 191 192 /* Space is allocated or reserved, so enable it. */ 193 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 194 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 195 temp | DEVEN_MCHBAR_EN); 196 } else { 197 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 198 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 199 } 200 } 201 202 static void 203 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 204 { 205 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 206 207 if (dev_priv->mchbar_need_disable) { 208 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 209 u32 deven_val; 210 211 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 212 &deven_val); 213 deven_val &= ~DEVEN_MCHBAR_EN; 214 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 215 deven_val); 216 } else { 217 u32 mchbar_val; 218 219 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 220 &mchbar_val); 221 mchbar_val &= ~1; 222 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 223 mchbar_val); 224 } 225 } 226 227 if (dev_priv->mch_res.start) 228 release_resource(&dev_priv->mch_res); 229 } 230 231 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 232 { 233 /* 234 * The i915 workqueue is primarily used for batched retirement of 235 * requests (and thus managing bo) once the task has been completed 236 * by the GPU. i915_retire_requests() is called directly when we 237 * need high-priority retirement, such as waiting for an explicit 238 * bo. 239 * 240 * It is also used for periodic low-priority events, such as 241 * idle-timers and recording error state. 242 * 243 * All tasks on the workqueue are expected to acquire the dev mutex 244 * so there is no point in running more than one instance of the 245 * workqueue at any time. Use an ordered one. 246 */ 247 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 248 if (dev_priv->wq == NULL) 249 goto out_err; 250 251 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 252 if (dev_priv->hotplug.dp_wq == NULL) 253 goto out_free_wq; 254 255 return 0; 256 257 out_free_wq: 258 destroy_workqueue(dev_priv->wq); 259 out_err: 260 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 261 262 return -ENOMEM; 263 } 264 265 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 266 { 267 destroy_workqueue(dev_priv->hotplug.dp_wq); 268 destroy_workqueue(dev_priv->wq); 269 } 270 271 /* 272 * We don't keep the workarounds for pre-production hardware, so we expect our 273 * driver to fail on these machines in one way or another. A little warning on 274 * dmesg may help both the user and the bug triagers. 275 * 276 * Our policy for removing pre-production workarounds is to keep the 277 * current gen workarounds as a guide to the bring-up of the next gen 278 * (workarounds have a habit of persisting!). Anything older than that 279 * should be removed along with the complications they introduce. 280 */ 281 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 282 { 283 bool pre = false; 284 285 pre |= IS_HSW_EARLY_SDV(dev_priv); 286 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 287 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 288 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 289 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 290 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 291 292 if (pre) { 293 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 294 "It may not be fully functional.\n"); 295 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 296 } 297 } 298 299 static void sanitize_gpu(struct drm_i915_private *i915) 300 { 301 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 302 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 303 } 304 305 /** 306 * i915_driver_early_probe - setup state not requiring device access 307 * @dev_priv: device private 308 * 309 * Initialize everything that is a "SW-only" state, that is state not 310 * requiring accessing the device or exposing the driver via kernel internal 311 * or userspace interfaces. Example steps belonging here: lock initialization, 312 * system memory allocation, setting up device specific attributes and 313 * function hooks not requiring accessing the device. 314 */ 315 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 316 { 317 int ret = 0; 318 319 if (i915_inject_probe_failure(dev_priv)) 320 return -ENODEV; 321 322 intel_device_info_subplatform_init(dev_priv); 323 intel_step_init(dev_priv); 324 325 intel_gt_init_early(to_gt(dev_priv), dev_priv); 326 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 327 intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv)); 328 329 spin_lock_init(&dev_priv->irq_lock); 330 spin_lock_init(&dev_priv->gpu_error.lock); 331 mutex_init(&dev_priv->backlight_lock); 332 333 mutex_init(&dev_priv->sb_lock); 334 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 335 336 mutex_init(&dev_priv->audio.mutex); 337 mutex_init(&dev_priv->wm.wm_mutex); 338 mutex_init(&dev_priv->pps_mutex); 339 mutex_init(&dev_priv->hdcp_comp_mutex); 340 341 i915_memcpy_init_early(dev_priv); 342 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 343 344 ret = i915_workqueues_init(dev_priv); 345 if (ret < 0) 346 return ret; 347 348 ret = vlv_suspend_init(dev_priv); 349 if (ret < 0) 350 goto err_workqueues; 351 352 ret = intel_region_ttm_device_init(dev_priv); 353 if (ret) 354 goto err_ttm; 355 356 intel_wopcm_init_early(&dev_priv->wopcm); 357 358 __intel_gt_init_early(to_gt(dev_priv), dev_priv); 359 360 i915_gem_init_early(dev_priv); 361 362 /* This must be called before any calls to HAS_PCH_* */ 363 intel_detect_pch(dev_priv); 364 365 intel_pm_setup(dev_priv); 366 ret = intel_power_domains_init(dev_priv); 367 if (ret < 0) 368 goto err_gem; 369 intel_irq_init(dev_priv); 370 intel_init_display_hooks(dev_priv); 371 intel_init_clock_gating_hooks(dev_priv); 372 373 intel_detect_preproduction_hw(dev_priv); 374 375 return 0; 376 377 err_gem: 378 i915_gem_cleanup_early(dev_priv); 379 intel_gt_driver_late_release(to_gt(dev_priv)); 380 intel_region_ttm_device_fini(dev_priv); 381 err_ttm: 382 vlv_suspend_cleanup(dev_priv); 383 err_workqueues: 384 i915_workqueues_cleanup(dev_priv); 385 return ret; 386 } 387 388 /** 389 * i915_driver_late_release - cleanup the setup done in 390 * i915_driver_early_probe() 391 * @dev_priv: device private 392 */ 393 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 394 { 395 intel_irq_fini(dev_priv); 396 intel_power_domains_cleanup(dev_priv); 397 i915_gem_cleanup_early(dev_priv); 398 intel_gt_driver_late_release(to_gt(dev_priv)); 399 intel_region_ttm_device_fini(dev_priv); 400 vlv_suspend_cleanup(dev_priv); 401 i915_workqueues_cleanup(dev_priv); 402 403 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 404 mutex_destroy(&dev_priv->sb_lock); 405 406 i915_params_free(&dev_priv->params); 407 } 408 409 /** 410 * i915_driver_mmio_probe - setup device MMIO 411 * @dev_priv: device private 412 * 413 * Setup minimal device state necessary for MMIO accesses later in the 414 * initialization sequence. The setup here should avoid any other device-wide 415 * side effects or exposing the driver via kernel internal or user space 416 * interfaces. 417 */ 418 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 419 { 420 int ret; 421 422 if (i915_inject_probe_failure(dev_priv)) 423 return -ENODEV; 424 425 ret = i915_get_bridge_dev(dev_priv); 426 if (ret < 0) 427 return ret; 428 429 ret = intel_uncore_setup_mmio(&dev_priv->uncore); 430 if (ret < 0) 431 goto err_bridge; 432 433 ret = intel_uncore_init_mmio(&dev_priv->uncore); 434 if (ret) 435 goto err_mmio; 436 437 /* Try to make sure MCHBAR is enabled before poking at it */ 438 intel_setup_mchbar(dev_priv); 439 intel_device_info_runtime_init(dev_priv); 440 441 ret = intel_gt_init_mmio(to_gt(dev_priv)); 442 if (ret) 443 goto err_uncore; 444 445 /* As early as possible, scrub existing GPU state before clobbering */ 446 sanitize_gpu(dev_priv); 447 448 return 0; 449 450 err_uncore: 451 intel_teardown_mchbar(dev_priv); 452 intel_uncore_fini_mmio(&dev_priv->uncore); 453 err_mmio: 454 intel_uncore_cleanup_mmio(&dev_priv->uncore); 455 err_bridge: 456 pci_dev_put(dev_priv->bridge_dev); 457 458 return ret; 459 } 460 461 /** 462 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 463 * @dev_priv: device private 464 */ 465 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 466 { 467 intel_teardown_mchbar(dev_priv); 468 intel_uncore_fini_mmio(&dev_priv->uncore); 469 intel_uncore_cleanup_mmio(&dev_priv->uncore); 470 pci_dev_put(dev_priv->bridge_dev); 471 } 472 473 static void intel_sanitize_options(struct drm_i915_private *dev_priv) 474 { 475 intel_gvt_sanitize_options(dev_priv); 476 } 477 478 /** 479 * i915_set_dma_info - set all relevant PCI dma info as configured for the 480 * platform 481 * @i915: valid i915 instance 482 * 483 * Set the dma max segment size, device and coherent masks. The dma mask set 484 * needs to occur before i915_ggtt_probe_hw. 485 * 486 * A couple of platforms have special needs. Address them as well. 487 * 488 */ 489 static int i915_set_dma_info(struct drm_i915_private *i915) 490 { 491 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 492 int ret; 493 494 GEM_BUG_ON(!mask_size); 495 496 /* 497 * We don't have a max segment size, so set it to the max so sg's 498 * debugging layer doesn't complain 499 */ 500 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 501 502 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 503 if (ret) 504 goto mask_err; 505 506 /* overlay on gen2 is broken and can't address above 1G */ 507 if (GRAPHICS_VER(i915) == 2) 508 mask_size = 30; 509 510 /* 511 * 965GM sometimes incorrectly writes to hardware status page (HWS) 512 * using 32bit addressing, overwriting memory if HWS is located 513 * above 4GB. 514 * 515 * The documentation also mentions an issue with undefined 516 * behaviour if any general state is accessed within a page above 4GB, 517 * which also needs to be handled carefully. 518 */ 519 if (IS_I965G(i915) || IS_I965GM(i915)) 520 mask_size = 32; 521 522 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 523 if (ret) 524 goto mask_err; 525 526 return 0; 527 528 mask_err: 529 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 530 return ret; 531 } 532 533 /** 534 * i915_driver_hw_probe - setup state requiring device access 535 * @dev_priv: device private 536 * 537 * Setup state that requires accessing the device, but doesn't require 538 * exposing the driver via kernel internal or userspace interfaces. 539 */ 540 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 541 { 542 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 543 int ret; 544 545 if (i915_inject_probe_failure(dev_priv)) 546 return -ENODEV; 547 548 if (HAS_PPGTT(dev_priv)) { 549 if (intel_vgpu_active(dev_priv) && 550 !intel_vgpu_has_full_ppgtt(dev_priv)) { 551 i915_report_error(dev_priv, 552 "incompatible vGPU found, support for isolated ppGTT required\n"); 553 return -ENXIO; 554 } 555 } 556 557 if (HAS_EXECLISTS(dev_priv)) { 558 /* 559 * Older GVT emulation depends upon intercepting CSB mmio, 560 * which we no longer use, preferring to use the HWSP cache 561 * instead. 562 */ 563 if (intel_vgpu_active(dev_priv) && 564 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 565 i915_report_error(dev_priv, 566 "old vGPU host found, support for HWSP emulation required\n"); 567 return -ENXIO; 568 } 569 } 570 571 intel_sanitize_options(dev_priv); 572 573 /* needs to be done before ggtt probe */ 574 intel_dram_edram_detect(dev_priv); 575 576 ret = i915_set_dma_info(dev_priv); 577 if (ret) 578 return ret; 579 580 i915_perf_init(dev_priv); 581 582 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 583 if (ret) 584 goto err_perf; 585 586 ret = i915_ggtt_probe_hw(dev_priv); 587 if (ret) 588 goto err_perf; 589 590 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 591 if (ret) 592 goto err_ggtt; 593 594 ret = i915_ggtt_init_hw(dev_priv); 595 if (ret) 596 goto err_ggtt; 597 598 ret = intel_memory_regions_hw_probe(dev_priv); 599 if (ret) 600 goto err_ggtt; 601 602 ret = intel_gt_probe_lmem(to_gt(dev_priv)); 603 if (ret) 604 goto err_mem_regions; 605 606 ret = i915_ggtt_enable_hw(dev_priv); 607 if (ret) { 608 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 609 goto err_mem_regions; 610 } 611 612 pci_set_master(pdev); 613 614 /* On the 945G/GM, the chipset reports the MSI capability on the 615 * integrated graphics even though the support isn't actually there 616 * according to the published specs. It doesn't appear to function 617 * correctly in testing on 945G. 618 * This may be a side effect of MSI having been made available for PEG 619 * and the registers being closely associated. 620 * 621 * According to chipset errata, on the 965GM, MSI interrupts may 622 * be lost or delayed, and was defeatured. MSI interrupts seem to 623 * get lost on g4x as well, and interrupt delivery seems to stay 624 * properly dead afterwards. So we'll just disable them for all 625 * pre-gen5 chipsets. 626 * 627 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 628 * interrupts even when in MSI mode. This results in spurious 629 * interrupt warnings if the legacy irq no. is shared with another 630 * device. The kernel then disables that interrupt source and so 631 * prevents the other device from working properly. 632 */ 633 if (GRAPHICS_VER(dev_priv) >= 5) { 634 if (pci_enable_msi(pdev) < 0) 635 drm_dbg(&dev_priv->drm, "can't enable MSI"); 636 } 637 638 ret = intel_gvt_init(dev_priv); 639 if (ret) 640 goto err_msi; 641 642 intel_opregion_setup(dev_priv); 643 644 ret = intel_pcode_init(dev_priv); 645 if (ret) 646 goto err_msi; 647 648 /* 649 * Fill the dram structure to get the system dram info. This will be 650 * used for memory latency calculation. 651 */ 652 intel_dram_detect(dev_priv); 653 654 intel_bw_init_hw(dev_priv); 655 656 return 0; 657 658 err_msi: 659 if (pdev->msi_enabled) 660 pci_disable_msi(pdev); 661 err_mem_regions: 662 intel_memory_regions_driver_release(dev_priv); 663 err_ggtt: 664 i915_ggtt_driver_release(dev_priv); 665 i915_gem_drain_freed_objects(dev_priv); 666 i915_ggtt_driver_late_release(dev_priv); 667 err_perf: 668 i915_perf_fini(dev_priv); 669 return ret; 670 } 671 672 /** 673 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 674 * @dev_priv: device private 675 */ 676 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 677 { 678 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 679 680 i915_perf_fini(dev_priv); 681 682 if (pdev->msi_enabled) 683 pci_disable_msi(pdev); 684 } 685 686 /** 687 * i915_driver_register - register the driver with the rest of the system 688 * @dev_priv: device private 689 * 690 * Perform any steps necessary to make the driver available via kernel 691 * internal or userspace interfaces. 692 */ 693 static void i915_driver_register(struct drm_i915_private *dev_priv) 694 { 695 struct drm_device *dev = &dev_priv->drm; 696 697 i915_gem_driver_register(dev_priv); 698 i915_pmu_register(dev_priv); 699 700 intel_vgpu_register(dev_priv); 701 702 /* Reveal our presence to userspace */ 703 if (drm_dev_register(dev, 0)) { 704 drm_err(&dev_priv->drm, 705 "Failed to register driver for userspace access!\n"); 706 return; 707 } 708 709 i915_debugfs_register(dev_priv); 710 i915_setup_sysfs(dev_priv); 711 712 /* Depends on sysfs having been initialized */ 713 i915_perf_register(dev_priv); 714 715 intel_gt_driver_register(to_gt(dev_priv)); 716 717 intel_display_driver_register(dev_priv); 718 719 intel_power_domains_enable(dev_priv); 720 intel_runtime_pm_enable(&dev_priv->runtime_pm); 721 722 intel_register_dsm_handler(); 723 724 if (i915_switcheroo_register(dev_priv)) 725 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 726 } 727 728 /** 729 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 730 * @dev_priv: device private 731 */ 732 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 733 { 734 i915_switcheroo_unregister(dev_priv); 735 736 intel_unregister_dsm_handler(); 737 738 intel_runtime_pm_disable(&dev_priv->runtime_pm); 739 intel_power_domains_disable(dev_priv); 740 741 intel_display_driver_unregister(dev_priv); 742 743 intel_gt_driver_unregister(to_gt(dev_priv)); 744 745 i915_perf_unregister(dev_priv); 746 i915_pmu_unregister(dev_priv); 747 748 i915_teardown_sysfs(dev_priv); 749 drm_dev_unplug(&dev_priv->drm); 750 751 i915_gem_driver_unregister(dev_priv); 752 } 753 754 void 755 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 756 { 757 drm_printf(p, "iommu: %s\n", 758 str_enabled_disabled(i915_vtd_active(i915))); 759 } 760 761 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 762 { 763 if (drm_debug_enabled(DRM_UT_DRIVER)) { 764 struct drm_printer p = drm_debug_printer("i915 device info:"); 765 766 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 767 INTEL_DEVID(dev_priv), 768 INTEL_REVID(dev_priv), 769 intel_platform_name(INTEL_INFO(dev_priv)->platform), 770 intel_subplatform(RUNTIME_INFO(dev_priv), 771 INTEL_INFO(dev_priv)->platform), 772 GRAPHICS_VER(dev_priv)); 773 774 intel_device_info_print_static(INTEL_INFO(dev_priv), &p); 775 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); 776 i915_print_iommu_status(dev_priv, &p); 777 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 778 } 779 780 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 781 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 782 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 783 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 784 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 785 drm_info(&dev_priv->drm, 786 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 787 } 788 789 static struct drm_i915_private * 790 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 791 { 792 const struct intel_device_info *match_info = 793 (struct intel_device_info *)ent->driver_data; 794 struct intel_device_info *device_info; 795 struct drm_i915_private *i915; 796 797 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 798 struct drm_i915_private, drm); 799 if (IS_ERR(i915)) 800 return i915; 801 802 pci_set_drvdata(pdev, i915); 803 804 /* Device parameters start as a copy of module parameters. */ 805 i915_params_copy(&i915->params, &i915_modparams); 806 807 /* Setup the write-once "constant" device info */ 808 device_info = mkwrite_device_info(i915); 809 memcpy(device_info, match_info, sizeof(*device_info)); 810 RUNTIME_INFO(i915)->device_id = pdev->device; 811 812 return i915; 813 } 814 815 /** 816 * i915_driver_probe - setup chip and create an initial config 817 * @pdev: PCI device 818 * @ent: matching PCI ID entry 819 * 820 * The driver probe routine has to do several things: 821 * - drive output discovery via intel_modeset_init() 822 * - initialize the memory manager 823 * - allocate initial config memory 824 * - setup the DRM framebuffer with the allocated memory 825 */ 826 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 827 { 828 const struct intel_device_info *match_info = 829 (struct intel_device_info *)ent->driver_data; 830 struct drm_i915_private *i915; 831 int ret; 832 833 i915 = i915_driver_create(pdev, ent); 834 if (IS_ERR(i915)) 835 return PTR_ERR(i915); 836 837 /* Disable nuclear pageflip by default on pre-ILK */ 838 if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5) 839 i915->drm.driver_features &= ~DRIVER_ATOMIC; 840 841 ret = pci_enable_device(pdev); 842 if (ret) 843 goto out_fini; 844 845 ret = i915_driver_early_probe(i915); 846 if (ret < 0) 847 goto out_pci_disable; 848 849 disable_rpm_wakeref_asserts(&i915->runtime_pm); 850 851 intel_vgpu_detect(i915); 852 853 ret = i915_driver_mmio_probe(i915); 854 if (ret < 0) 855 goto out_runtime_pm_put; 856 857 ret = i915_driver_hw_probe(i915); 858 if (ret < 0) 859 goto out_cleanup_mmio; 860 861 ret = intel_modeset_init_noirq(i915); 862 if (ret < 0) 863 goto out_cleanup_hw; 864 865 ret = intel_irq_install(i915); 866 if (ret) 867 goto out_cleanup_modeset; 868 869 ret = intel_modeset_init_nogem(i915); 870 if (ret) 871 goto out_cleanup_irq; 872 873 ret = i915_gem_init(i915); 874 if (ret) 875 goto out_cleanup_modeset2; 876 877 ret = intel_modeset_init(i915); 878 if (ret) 879 goto out_cleanup_gem; 880 881 i915_driver_register(i915); 882 883 enable_rpm_wakeref_asserts(&i915->runtime_pm); 884 885 i915_welcome_messages(i915); 886 887 i915->do_release = true; 888 889 return 0; 890 891 out_cleanup_gem: 892 i915_gem_suspend(i915); 893 i915_gem_driver_remove(i915); 894 i915_gem_driver_release(i915); 895 out_cleanup_modeset2: 896 /* FIXME clean up the error path */ 897 intel_modeset_driver_remove(i915); 898 intel_irq_uninstall(i915); 899 intel_modeset_driver_remove_noirq(i915); 900 goto out_cleanup_modeset; 901 out_cleanup_irq: 902 intel_irq_uninstall(i915); 903 out_cleanup_modeset: 904 intel_modeset_driver_remove_nogem(i915); 905 out_cleanup_hw: 906 i915_driver_hw_remove(i915); 907 intel_memory_regions_driver_release(i915); 908 i915_ggtt_driver_release(i915); 909 i915_gem_drain_freed_objects(i915); 910 i915_ggtt_driver_late_release(i915); 911 out_cleanup_mmio: 912 i915_driver_mmio_release(i915); 913 out_runtime_pm_put: 914 enable_rpm_wakeref_asserts(&i915->runtime_pm); 915 i915_driver_late_release(i915); 916 out_pci_disable: 917 pci_disable_device(pdev); 918 out_fini: 919 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 920 return ret; 921 } 922 923 void i915_driver_remove(struct drm_i915_private *i915) 924 { 925 disable_rpm_wakeref_asserts(&i915->runtime_pm); 926 927 i915_driver_unregister(i915); 928 929 /* Flush any external code that still may be under the RCU lock */ 930 synchronize_rcu(); 931 932 i915_gem_suspend(i915); 933 934 intel_gvt_driver_remove(i915); 935 936 intel_modeset_driver_remove(i915); 937 938 intel_irq_uninstall(i915); 939 940 intel_modeset_driver_remove_noirq(i915); 941 942 i915_reset_error_state(i915); 943 i915_gem_driver_remove(i915); 944 945 intel_modeset_driver_remove_nogem(i915); 946 947 i915_driver_hw_remove(i915); 948 949 enable_rpm_wakeref_asserts(&i915->runtime_pm); 950 } 951 952 static void i915_driver_release(struct drm_device *dev) 953 { 954 struct drm_i915_private *dev_priv = to_i915(dev); 955 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 956 957 if (!dev_priv->do_release) 958 return; 959 960 disable_rpm_wakeref_asserts(rpm); 961 962 i915_gem_driver_release(dev_priv); 963 964 intel_memory_regions_driver_release(dev_priv); 965 i915_ggtt_driver_release(dev_priv); 966 i915_gem_drain_freed_objects(dev_priv); 967 i915_ggtt_driver_late_release(dev_priv); 968 969 i915_driver_mmio_release(dev_priv); 970 971 enable_rpm_wakeref_asserts(rpm); 972 intel_runtime_pm_driver_release(rpm); 973 974 i915_driver_late_release(dev_priv); 975 } 976 977 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 978 { 979 struct drm_i915_private *i915 = to_i915(dev); 980 int ret; 981 982 ret = i915_gem_open(i915, file); 983 if (ret) 984 return ret; 985 986 return 0; 987 } 988 989 /** 990 * i915_driver_lastclose - clean up after all DRM clients have exited 991 * @dev: DRM device 992 * 993 * Take care of cleaning up after all DRM clients have exited. In the 994 * mode setting case, we want to restore the kernel's initial mode (just 995 * in case the last client left us in a bad state). 996 * 997 * Additionally, in the non-mode setting case, we'll tear down the GTT 998 * and DMA structures, since the kernel won't be using them, and clea 999 * up any GEM state. 1000 */ 1001 static void i915_driver_lastclose(struct drm_device *dev) 1002 { 1003 struct drm_i915_private *i915 = to_i915(dev); 1004 1005 intel_fbdev_restore_mode(dev); 1006 1007 if (HAS_DISPLAY(i915)) 1008 vga_switcheroo_process_delayed_switch(); 1009 } 1010 1011 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1012 { 1013 struct drm_i915_file_private *file_priv = file->driver_priv; 1014 1015 i915_gem_context_close(file); 1016 1017 kfree_rcu(file_priv, rcu); 1018 1019 /* Catch up with all the deferred frees from "this" client */ 1020 i915_gem_flush_free_objects(to_i915(dev)); 1021 } 1022 1023 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1024 { 1025 struct drm_device *dev = &dev_priv->drm; 1026 struct intel_encoder *encoder; 1027 1028 if (!HAS_DISPLAY(dev_priv)) 1029 return; 1030 1031 drm_modeset_lock_all(dev); 1032 for_each_intel_encoder(dev, encoder) 1033 if (encoder->suspend) 1034 encoder->suspend(encoder); 1035 drm_modeset_unlock_all(dev); 1036 } 1037 1038 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1039 { 1040 struct drm_device *dev = &dev_priv->drm; 1041 struct intel_encoder *encoder; 1042 1043 if (!HAS_DISPLAY(dev_priv)) 1044 return; 1045 1046 drm_modeset_lock_all(dev); 1047 for_each_intel_encoder(dev, encoder) 1048 if (encoder->shutdown) 1049 encoder->shutdown(encoder); 1050 drm_modeset_unlock_all(dev); 1051 } 1052 1053 void i915_driver_shutdown(struct drm_i915_private *i915) 1054 { 1055 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1056 intel_runtime_pm_disable(&i915->runtime_pm); 1057 intel_power_domains_disable(i915); 1058 1059 i915_gem_suspend(i915); 1060 1061 if (HAS_DISPLAY(i915)) { 1062 drm_kms_helper_poll_disable(&i915->drm); 1063 1064 drm_atomic_helper_shutdown(&i915->drm); 1065 } 1066 1067 intel_dp_mst_suspend(i915); 1068 1069 intel_runtime_pm_disable_interrupts(i915); 1070 intel_hpd_cancel_work(i915); 1071 1072 intel_suspend_encoders(i915); 1073 intel_shutdown_encoders(i915); 1074 1075 intel_dmc_ucode_suspend(i915); 1076 1077 /* 1078 * The only requirement is to reboot with display DC states disabled, 1079 * for now leaving all display power wells in the INIT power domain 1080 * enabled. 1081 * 1082 * TODO: 1083 * - unify the pci_driver::shutdown sequence here with the 1084 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1085 * - unify the driver remove and system/runtime suspend sequences with 1086 * the above unified shutdown/poweroff sequence. 1087 */ 1088 intel_power_domains_driver_remove(i915); 1089 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1090 1091 intel_runtime_pm_driver_release(&i915->runtime_pm); 1092 } 1093 1094 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1095 { 1096 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1097 if (acpi_target_system_state() < ACPI_STATE_S3) 1098 return true; 1099 #endif 1100 return false; 1101 } 1102 1103 static int i915_drm_prepare(struct drm_device *dev) 1104 { 1105 struct drm_i915_private *i915 = to_i915(dev); 1106 1107 /* 1108 * NB intel_display_suspend() may issue new requests after we've 1109 * ostensibly marked the GPU as ready-to-sleep here. We need to 1110 * split out that work and pull it forward so that after point, 1111 * the GPU is not woken again. 1112 */ 1113 return i915_gem_backup_suspend(i915); 1114 } 1115 1116 static int i915_drm_suspend(struct drm_device *dev) 1117 { 1118 struct drm_i915_private *dev_priv = to_i915(dev); 1119 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1120 pci_power_t opregion_target_state; 1121 1122 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1123 1124 /* We do a lot of poking in a lot of registers, make sure they work 1125 * properly. */ 1126 intel_power_domains_disable(dev_priv); 1127 if (HAS_DISPLAY(dev_priv)) 1128 drm_kms_helper_poll_disable(dev); 1129 1130 pci_save_state(pdev); 1131 1132 intel_display_suspend(dev); 1133 1134 intel_dp_mst_suspend(dev_priv); 1135 1136 intel_runtime_pm_disable_interrupts(dev_priv); 1137 intel_hpd_cancel_work(dev_priv); 1138 1139 intel_suspend_encoders(dev_priv); 1140 1141 intel_suspend_hw(dev_priv); 1142 1143 /* Must be called before GGTT is suspended. */ 1144 intel_dpt_suspend(dev_priv); 1145 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1146 1147 i915_save_display(dev_priv); 1148 1149 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1150 intel_opregion_suspend(dev_priv, opregion_target_state); 1151 1152 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1153 1154 dev_priv->suspend_count++; 1155 1156 intel_dmc_ucode_suspend(dev_priv); 1157 1158 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1159 1160 return 0; 1161 } 1162 1163 static enum i915_drm_suspend_mode 1164 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1165 { 1166 if (hibernate) 1167 return I915_DRM_SUSPEND_HIBERNATE; 1168 1169 if (suspend_to_idle(dev_priv)) 1170 return I915_DRM_SUSPEND_IDLE; 1171 1172 return I915_DRM_SUSPEND_MEM; 1173 } 1174 1175 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1176 { 1177 struct drm_i915_private *dev_priv = to_i915(dev); 1178 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1179 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1180 int ret; 1181 1182 disable_rpm_wakeref_asserts(rpm); 1183 1184 i915_gem_suspend_late(dev_priv); 1185 1186 intel_uncore_suspend(&dev_priv->uncore); 1187 1188 intel_power_domains_suspend(dev_priv, 1189 get_suspend_mode(dev_priv, hibernation)); 1190 1191 intel_display_power_suspend_late(dev_priv); 1192 1193 ret = vlv_suspend_complete(dev_priv); 1194 if (ret) { 1195 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1196 intel_power_domains_resume(dev_priv); 1197 1198 goto out; 1199 } 1200 1201 /* 1202 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1203 * This should be totally removed when we handle the pci states properly 1204 * on runtime PM and on s2idle cases. 1205 */ 1206 if (suspend_to_idle(dev_priv)) 1207 pci_d3cold_disable(pdev); 1208 1209 pci_disable_device(pdev); 1210 /* 1211 * During hibernation on some platforms the BIOS may try to access 1212 * the device even though it's already in D3 and hang the machine. So 1213 * leave the device in D0 on those platforms and hope the BIOS will 1214 * power down the device properly. The issue was seen on multiple old 1215 * GENs with different BIOS vendors, so having an explicit blacklist 1216 * is inpractical; apply the workaround on everything pre GEN6. The 1217 * platforms where the issue was seen: 1218 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1219 * Fujitsu FSC S7110 1220 * Acer Aspire 1830T 1221 */ 1222 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1223 pci_set_power_state(pdev, PCI_D3hot); 1224 1225 out: 1226 enable_rpm_wakeref_asserts(rpm); 1227 if (!dev_priv->uncore.user_forcewake_count) 1228 intel_runtime_pm_driver_release(rpm); 1229 1230 return ret; 1231 } 1232 1233 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1234 pm_message_t state) 1235 { 1236 int error; 1237 1238 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1239 state.event != PM_EVENT_FREEZE)) 1240 return -EINVAL; 1241 1242 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1243 return 0; 1244 1245 error = i915_drm_suspend(&i915->drm); 1246 if (error) 1247 return error; 1248 1249 return i915_drm_suspend_late(&i915->drm, false); 1250 } 1251 1252 static int i915_drm_resume(struct drm_device *dev) 1253 { 1254 struct drm_i915_private *dev_priv = to_i915(dev); 1255 int ret; 1256 1257 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1258 1259 ret = intel_pcode_init(dev_priv); 1260 if (ret) 1261 return ret; 1262 1263 sanitize_gpu(dev_priv); 1264 1265 ret = i915_ggtt_enable_hw(dev_priv); 1266 if (ret) 1267 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1268 1269 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1270 /* Must be called after GGTT is resumed. */ 1271 intel_dpt_resume(dev_priv); 1272 1273 intel_dmc_ucode_resume(dev_priv); 1274 1275 i915_restore_display(dev_priv); 1276 intel_pps_unlock_regs_wa(dev_priv); 1277 1278 intel_init_pch_refclk(dev_priv); 1279 1280 /* 1281 * Interrupts have to be enabled before any batches are run. If not the 1282 * GPU will hang. i915_gem_init_hw() will initiate batches to 1283 * update/restore the context. 1284 * 1285 * drm_mode_config_reset() needs AUX interrupts. 1286 * 1287 * Modeset enabling in intel_modeset_init_hw() also needs working 1288 * interrupts. 1289 */ 1290 intel_runtime_pm_enable_interrupts(dev_priv); 1291 1292 if (HAS_DISPLAY(dev_priv)) 1293 drm_mode_config_reset(dev); 1294 1295 i915_gem_resume(dev_priv); 1296 1297 intel_modeset_init_hw(dev_priv); 1298 intel_init_clock_gating(dev_priv); 1299 intel_hpd_init(dev_priv); 1300 1301 /* MST sideband requires HPD interrupts enabled */ 1302 intel_dp_mst_resume(dev_priv); 1303 intel_display_resume(dev); 1304 1305 intel_hpd_poll_disable(dev_priv); 1306 if (HAS_DISPLAY(dev_priv)) 1307 drm_kms_helper_poll_enable(dev); 1308 1309 intel_opregion_resume(dev_priv); 1310 1311 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1312 1313 intel_power_domains_enable(dev_priv); 1314 1315 intel_gvt_resume(dev_priv); 1316 1317 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1318 1319 return 0; 1320 } 1321 1322 static int i915_drm_resume_early(struct drm_device *dev) 1323 { 1324 struct drm_i915_private *dev_priv = to_i915(dev); 1325 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1326 int ret; 1327 1328 /* 1329 * We have a resume ordering issue with the snd-hda driver also 1330 * requiring our device to be power up. Due to the lack of a 1331 * parent/child relationship we currently solve this with an early 1332 * resume hook. 1333 * 1334 * FIXME: This should be solved with a special hdmi sink device or 1335 * similar so that power domains can be employed. 1336 */ 1337 1338 /* 1339 * Note that we need to set the power state explicitly, since we 1340 * powered off the device during freeze and the PCI core won't power 1341 * it back up for us during thaw. Powering off the device during 1342 * freeze is not a hard requirement though, and during the 1343 * suspend/resume phases the PCI core makes sure we get here with the 1344 * device powered on. So in case we change our freeze logic and keep 1345 * the device powered we can also remove the following set power state 1346 * call. 1347 */ 1348 ret = pci_set_power_state(pdev, PCI_D0); 1349 if (ret) { 1350 drm_err(&dev_priv->drm, 1351 "failed to set PCI D0 power state (%d)\n", ret); 1352 return ret; 1353 } 1354 1355 /* 1356 * Note that pci_enable_device() first enables any parent bridge 1357 * device and only then sets the power state for this device. The 1358 * bridge enabling is a nop though, since bridge devices are resumed 1359 * first. The order of enabling power and enabling the device is 1360 * imposed by the PCI core as described above, so here we preserve the 1361 * same order for the freeze/thaw phases. 1362 * 1363 * TODO: eventually we should remove pci_disable_device() / 1364 * pci_enable_enable_device() from suspend/resume. Due to how they 1365 * depend on the device enable refcount we can't anyway depend on them 1366 * disabling/enabling the device. 1367 */ 1368 if (pci_enable_device(pdev)) 1369 return -EIO; 1370 1371 pci_set_master(pdev); 1372 1373 pci_d3cold_enable(pdev); 1374 1375 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1376 1377 ret = vlv_resume_prepare(dev_priv, false); 1378 if (ret) 1379 drm_err(&dev_priv->drm, 1380 "Resume prepare failed: %d, continuing anyway\n", ret); 1381 1382 intel_uncore_resume_early(&dev_priv->uncore); 1383 1384 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1385 1386 intel_display_power_resume_early(dev_priv); 1387 1388 intel_power_domains_resume(dev_priv); 1389 1390 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1391 1392 return ret; 1393 } 1394 1395 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1396 { 1397 int ret; 1398 1399 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1400 return 0; 1401 1402 ret = i915_drm_resume_early(&i915->drm); 1403 if (ret) 1404 return ret; 1405 1406 return i915_drm_resume(&i915->drm); 1407 } 1408 1409 static int i915_pm_prepare(struct device *kdev) 1410 { 1411 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1412 1413 if (!i915) { 1414 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1415 return -ENODEV; 1416 } 1417 1418 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1419 return 0; 1420 1421 return i915_drm_prepare(&i915->drm); 1422 } 1423 1424 static int i915_pm_suspend(struct device *kdev) 1425 { 1426 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1427 1428 if (!i915) { 1429 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1430 return -ENODEV; 1431 } 1432 1433 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1434 return 0; 1435 1436 return i915_drm_suspend(&i915->drm); 1437 } 1438 1439 static int i915_pm_suspend_late(struct device *kdev) 1440 { 1441 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1442 1443 /* 1444 * We have a suspend ordering issue with the snd-hda driver also 1445 * requiring our device to be power up. Due to the lack of a 1446 * parent/child relationship we currently solve this with an late 1447 * suspend hook. 1448 * 1449 * FIXME: This should be solved with a special hdmi sink device or 1450 * similar so that power domains can be employed. 1451 */ 1452 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1453 return 0; 1454 1455 return i915_drm_suspend_late(&i915->drm, false); 1456 } 1457 1458 static int i915_pm_poweroff_late(struct device *kdev) 1459 { 1460 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1461 1462 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1463 return 0; 1464 1465 return i915_drm_suspend_late(&i915->drm, true); 1466 } 1467 1468 static int i915_pm_resume_early(struct device *kdev) 1469 { 1470 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1471 1472 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1473 return 0; 1474 1475 return i915_drm_resume_early(&i915->drm); 1476 } 1477 1478 static int i915_pm_resume(struct device *kdev) 1479 { 1480 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1481 1482 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1483 return 0; 1484 1485 return i915_drm_resume(&i915->drm); 1486 } 1487 1488 /* freeze: before creating the hibernation_image */ 1489 static int i915_pm_freeze(struct device *kdev) 1490 { 1491 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1492 int ret; 1493 1494 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1495 ret = i915_drm_suspend(&i915->drm); 1496 if (ret) 1497 return ret; 1498 } 1499 1500 ret = i915_gem_freeze(i915); 1501 if (ret) 1502 return ret; 1503 1504 return 0; 1505 } 1506 1507 static int i915_pm_freeze_late(struct device *kdev) 1508 { 1509 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1510 int ret; 1511 1512 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1513 ret = i915_drm_suspend_late(&i915->drm, true); 1514 if (ret) 1515 return ret; 1516 } 1517 1518 ret = i915_gem_freeze_late(i915); 1519 if (ret) 1520 return ret; 1521 1522 return 0; 1523 } 1524 1525 /* thaw: called after creating the hibernation image, but before turning off. */ 1526 static int i915_pm_thaw_early(struct device *kdev) 1527 { 1528 return i915_pm_resume_early(kdev); 1529 } 1530 1531 static int i915_pm_thaw(struct device *kdev) 1532 { 1533 return i915_pm_resume(kdev); 1534 } 1535 1536 /* restore: called after loading the hibernation image. */ 1537 static int i915_pm_restore_early(struct device *kdev) 1538 { 1539 return i915_pm_resume_early(kdev); 1540 } 1541 1542 static int i915_pm_restore(struct device *kdev) 1543 { 1544 return i915_pm_resume(kdev); 1545 } 1546 1547 static int intel_runtime_suspend(struct device *kdev) 1548 { 1549 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1550 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1551 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1552 int ret; 1553 1554 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1555 return -ENODEV; 1556 1557 drm_dbg_kms(&dev_priv->drm, "Suspending device\n"); 1558 1559 disable_rpm_wakeref_asserts(rpm); 1560 1561 /* 1562 * We are safe here against re-faults, since the fault handler takes 1563 * an RPM reference. 1564 */ 1565 i915_gem_runtime_suspend(dev_priv); 1566 1567 intel_gt_runtime_suspend(to_gt(dev_priv)); 1568 1569 intel_runtime_pm_disable_interrupts(dev_priv); 1570 1571 intel_uncore_suspend(&dev_priv->uncore); 1572 1573 intel_display_power_suspend(dev_priv); 1574 1575 ret = vlv_suspend_complete(dev_priv); 1576 if (ret) { 1577 drm_err(&dev_priv->drm, 1578 "Runtime suspend failed, disabling it (%d)\n", ret); 1579 intel_uncore_runtime_resume(&dev_priv->uncore); 1580 1581 intel_runtime_pm_enable_interrupts(dev_priv); 1582 1583 intel_gt_runtime_resume(to_gt(dev_priv)); 1584 1585 enable_rpm_wakeref_asserts(rpm); 1586 1587 return ret; 1588 } 1589 1590 enable_rpm_wakeref_asserts(rpm); 1591 intel_runtime_pm_driver_release(rpm); 1592 1593 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1594 drm_err(&dev_priv->drm, 1595 "Unclaimed access detected prior to suspending\n"); 1596 1597 /* 1598 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1599 * This should be totally removed when we handle the pci states properly 1600 * on runtime PM and on s2idle cases. 1601 */ 1602 pci_d3cold_disable(pdev); 1603 rpm->suspended = true; 1604 1605 /* 1606 * FIXME: We really should find a document that references the arguments 1607 * used below! 1608 */ 1609 if (IS_BROADWELL(dev_priv)) { 1610 /* 1611 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1612 * being detected, and the call we do at intel_runtime_resume() 1613 * won't be able to restore them. Since PCI_D3hot matches the 1614 * actual specification and appears to be working, use it. 1615 */ 1616 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1617 } else { 1618 /* 1619 * current versions of firmware which depend on this opregion 1620 * notification have repurposed the D1 definition to mean 1621 * "runtime suspended" vs. what you would normally expect (D3) 1622 * to distinguish it from notifications that might be sent via 1623 * the suspend path. 1624 */ 1625 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1626 } 1627 1628 assert_forcewakes_inactive(&dev_priv->uncore); 1629 1630 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1631 intel_hpd_poll_enable(dev_priv); 1632 1633 drm_dbg_kms(&dev_priv->drm, "Device suspended\n"); 1634 return 0; 1635 } 1636 1637 static int intel_runtime_resume(struct device *kdev) 1638 { 1639 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1640 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1641 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1642 int ret; 1643 1644 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1645 return -ENODEV; 1646 1647 drm_dbg_kms(&dev_priv->drm, "Resuming device\n"); 1648 1649 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1650 disable_rpm_wakeref_asserts(rpm); 1651 1652 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1653 rpm->suspended = false; 1654 pci_d3cold_enable(pdev); 1655 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1656 drm_dbg(&dev_priv->drm, 1657 "Unclaimed access during suspend, bios?\n"); 1658 1659 intel_display_power_resume(dev_priv); 1660 1661 ret = vlv_resume_prepare(dev_priv, true); 1662 1663 intel_uncore_runtime_resume(&dev_priv->uncore); 1664 1665 intel_runtime_pm_enable_interrupts(dev_priv); 1666 1667 /* 1668 * No point of rolling back things in case of an error, as the best 1669 * we can do is to hope that things will still work (and disable RPM). 1670 */ 1671 intel_gt_runtime_resume(to_gt(dev_priv)); 1672 1673 /* 1674 * On VLV/CHV display interrupts are part of the display 1675 * power well, so hpd is reinitialized from there. For 1676 * everyone else do it here. 1677 */ 1678 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1679 intel_hpd_init(dev_priv); 1680 intel_hpd_poll_disable(dev_priv); 1681 } 1682 1683 intel_enable_ipc(dev_priv); 1684 1685 enable_rpm_wakeref_asserts(rpm); 1686 1687 if (ret) 1688 drm_err(&dev_priv->drm, 1689 "Runtime resume failed, disabling it (%d)\n", ret); 1690 else 1691 drm_dbg_kms(&dev_priv->drm, "Device resumed\n"); 1692 1693 return ret; 1694 } 1695 1696 const struct dev_pm_ops i915_pm_ops = { 1697 /* 1698 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1699 * PMSG_RESUME] 1700 */ 1701 .prepare = i915_pm_prepare, 1702 .suspend = i915_pm_suspend, 1703 .suspend_late = i915_pm_suspend_late, 1704 .resume_early = i915_pm_resume_early, 1705 .resume = i915_pm_resume, 1706 1707 /* 1708 * S4 event handlers 1709 * @freeze, @freeze_late : called (1) before creating the 1710 * hibernation image [PMSG_FREEZE] and 1711 * (2) after rebooting, before restoring 1712 * the image [PMSG_QUIESCE] 1713 * @thaw, @thaw_early : called (1) after creating the hibernation 1714 * image, before writing it [PMSG_THAW] 1715 * and (2) after failing to create or 1716 * restore the image [PMSG_RECOVER] 1717 * @poweroff, @poweroff_late: called after writing the hibernation 1718 * image, before rebooting [PMSG_HIBERNATE] 1719 * @restore, @restore_early : called after rebooting and restoring the 1720 * hibernation image [PMSG_RESTORE] 1721 */ 1722 .freeze = i915_pm_freeze, 1723 .freeze_late = i915_pm_freeze_late, 1724 .thaw_early = i915_pm_thaw_early, 1725 .thaw = i915_pm_thaw, 1726 .poweroff = i915_pm_suspend, 1727 .poweroff_late = i915_pm_poweroff_late, 1728 .restore_early = i915_pm_restore_early, 1729 .restore = i915_pm_restore, 1730 1731 /* S0ix (via runtime suspend) event handlers */ 1732 .runtime_suspend = intel_runtime_suspend, 1733 .runtime_resume = intel_runtime_resume, 1734 }; 1735 1736 static const struct file_operations i915_driver_fops = { 1737 .owner = THIS_MODULE, 1738 .open = drm_open, 1739 .release = drm_release_noglobal, 1740 .unlocked_ioctl = drm_ioctl, 1741 .mmap = i915_gem_mmap, 1742 .poll = drm_poll, 1743 .read = drm_read, 1744 .compat_ioctl = i915_ioc32_compat_ioctl, 1745 .llseek = noop_llseek, 1746 }; 1747 1748 static int 1749 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1750 struct drm_file *file) 1751 { 1752 return -ENODEV; 1753 } 1754 1755 static const struct drm_ioctl_desc i915_ioctls[] = { 1756 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1757 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1758 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1759 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1760 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1761 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1762 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1763 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1764 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1765 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1766 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1767 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1768 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1769 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1770 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1771 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1772 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1773 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1774 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1775 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1776 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1777 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1779 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1780 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1782 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1783 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1784 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1786 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1788 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1789 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1790 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1791 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1792 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1794 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1795 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1796 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1797 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1798 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1799 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1800 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1801 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1802 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1803 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1804 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1805 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1806 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1807 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1809 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1810 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1814 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1815 }; 1816 1817 /* 1818 * Interface history: 1819 * 1820 * 1.1: Original. 1821 * 1.2: Add Power Management 1822 * 1.3: Add vblank support 1823 * 1.4: Fix cmdbuffer path, add heap destroy 1824 * 1.5: Add vblank pipe configuration 1825 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1826 * - Support vertical blank on secondary display pipe 1827 */ 1828 #define DRIVER_MAJOR 1 1829 #define DRIVER_MINOR 6 1830 #define DRIVER_PATCHLEVEL 0 1831 1832 static const struct drm_driver i915_drm_driver = { 1833 /* Don't use MTRRs here; the Xserver or userspace app should 1834 * deal with them for Intel hardware. 1835 */ 1836 .driver_features = 1837 DRIVER_GEM | 1838 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1839 DRIVER_SYNCOBJ_TIMELINE, 1840 .release = i915_driver_release, 1841 .open = i915_driver_open, 1842 .lastclose = i915_driver_lastclose, 1843 .postclose = i915_driver_postclose, 1844 1845 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1846 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1847 .gem_prime_import = i915_gem_prime_import, 1848 1849 .dumb_create = i915_gem_dumb_create, 1850 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1851 1852 .ioctls = i915_ioctls, 1853 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1854 .fops = &i915_driver_fops, 1855 .name = DRIVER_NAME, 1856 .desc = DRIVER_DESC, 1857 .date = DRIVER_DATE, 1858 .major = DRIVER_MAJOR, 1859 .minor = DRIVER_MINOR, 1860 .patchlevel = DRIVER_PATCHLEVEL, 1861 }; 1862