1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/slab.h> 38 #include <linux/string_helpers.h> 39 #include <linux/vga_switcheroo.h> 40 #include <linux/vt.h> 41 42 #include <drm/drm_aperture.h> 43 #include <drm/drm_atomic_helper.h> 44 #include <drm/drm_ioctl.h> 45 #include <drm/drm_managed.h> 46 #include <drm/drm_probe_helper.h> 47 48 #include "display/intel_acpi.h" 49 #include "display/intel_bw.h" 50 #include "display/intel_cdclk.h" 51 #include "display/intel_display_driver.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 #include "display/skl_watermark.h" 65 66 #include "gem/i915_gem_context.h" 67 #include "gem/i915_gem_create.h" 68 #include "gem/i915_gem_dmabuf.h" 69 #include "gem/i915_gem_ioctls.h" 70 #include "gem/i915_gem_mman.h" 71 #include "gem/i915_gem_pm.h" 72 #include "gt/intel_gt.h" 73 #include "gt/intel_gt_pm.h" 74 #include "gt/intel_rc6.h" 75 76 #include "pxp/intel_pxp.h" 77 #include "pxp/intel_pxp_debugfs.h" 78 #include "pxp/intel_pxp_pm.h" 79 80 #include "soc/intel_dram.h" 81 #include "soc/intel_gmch.h" 82 83 #include "i915_debugfs.h" 84 #include "i915_driver.h" 85 #include "i915_drm_client.h" 86 #include "i915_drv.h" 87 #include "i915_file_private.h" 88 #include "i915_getparam.h" 89 #include "i915_hwmon.h" 90 #include "i915_ioc32.h" 91 #include "i915_ioctl.h" 92 #include "i915_irq.h" 93 #include "i915_memcpy.h" 94 #include "i915_perf.h" 95 #include "i915_query.h" 96 #include "i915_suspend.h" 97 #include "i915_switcheroo.h" 98 #include "i915_sysfs.h" 99 #include "i915_utils.h" 100 #include "i915_vgpu.h" 101 #include "intel_clock_gating.h" 102 #include "intel_gvt.h" 103 #include "intel_memory_region.h" 104 #include "intel_pci_config.h" 105 #include "intel_pcode.h" 106 #include "intel_region_ttm.h" 107 #include "vlv_suspend.h" 108 109 static const struct drm_driver i915_drm_driver; 110 111 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 112 { 113 /* 114 * The i915 workqueue is primarily used for batched retirement of 115 * requests (and thus managing bo) once the task has been completed 116 * by the GPU. i915_retire_requests() is called directly when we 117 * need high-priority retirement, such as waiting for an explicit 118 * bo. 119 * 120 * It is also used for periodic low-priority events, such as 121 * idle-timers and recording error state. 122 * 123 * All tasks on the workqueue are expected to acquire the dev mutex 124 * so there is no point in running more than one instance of the 125 * workqueue at any time. Use an ordered one. 126 */ 127 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 128 if (dev_priv->wq == NULL) 129 goto out_err; 130 131 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 132 if (dev_priv->display.hotplug.dp_wq == NULL) 133 goto out_free_wq; 134 135 /* 136 * The unordered i915 workqueue should be used for all work 137 * scheduling that do not require running in order, which used 138 * to be scheduled on the system_wq before moving to a driver 139 * instance due deprecation of flush_scheduled_work(). 140 */ 141 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); 142 if (dev_priv->unordered_wq == NULL) 143 goto out_free_dp_wq; 144 145 return 0; 146 147 out_free_dp_wq: 148 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 149 out_free_wq: 150 destroy_workqueue(dev_priv->wq); 151 out_err: 152 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 153 154 return -ENOMEM; 155 } 156 157 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 158 { 159 destroy_workqueue(dev_priv->unordered_wq); 160 destroy_workqueue(dev_priv->display.hotplug.dp_wq); 161 destroy_workqueue(dev_priv->wq); 162 } 163 164 /* 165 * We don't keep the workarounds for pre-production hardware, so we expect our 166 * driver to fail on these machines in one way or another. A little warning on 167 * dmesg may help both the user and the bug triagers. 168 * 169 * Our policy for removing pre-production workarounds is to keep the 170 * current gen workarounds as a guide to the bring-up of the next gen 171 * (workarounds have a habit of persisting!). Anything older than that 172 * should be removed along with the complications they introduce. 173 */ 174 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 175 { 176 bool pre = false; 177 178 pre |= IS_HSW_EARLY_SDV(dev_priv); 179 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 180 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 181 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 182 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 183 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 184 pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 185 pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 186 187 if (pre) { 188 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 189 "It may not be fully functional.\n"); 190 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 191 } 192 } 193 194 static void sanitize_gpu(struct drm_i915_private *i915) 195 { 196 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { 197 struct intel_gt *gt; 198 unsigned int i; 199 200 for_each_gt(gt, i915, i) 201 __intel_gt_reset(gt, ALL_ENGINES); 202 } 203 } 204 205 /** 206 * i915_driver_early_probe - setup state not requiring device access 207 * @dev_priv: device private 208 * 209 * Initialize everything that is a "SW-only" state, that is state not 210 * requiring accessing the device or exposing the driver via kernel internal 211 * or userspace interfaces. Example steps belonging here: lock initialization, 212 * system memory allocation, setting up device specific attributes and 213 * function hooks not requiring accessing the device. 214 */ 215 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 216 { 217 int ret = 0; 218 219 if (i915_inject_probe_failure(dev_priv)) 220 return -ENODEV; 221 222 intel_device_info_runtime_init_early(dev_priv); 223 224 intel_step_init(dev_priv); 225 226 intel_uncore_mmio_debug_init_early(dev_priv); 227 228 spin_lock_init(&dev_priv->irq_lock); 229 spin_lock_init(&dev_priv->gpu_error.lock); 230 mutex_init(&dev_priv->display.backlight.lock); 231 232 mutex_init(&dev_priv->sb_lock); 233 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 234 235 mutex_init(&dev_priv->display.audio.mutex); 236 mutex_init(&dev_priv->display.wm.wm_mutex); 237 mutex_init(&dev_priv->display.pps.mutex); 238 mutex_init(&dev_priv->display.hdcp.hdcp_mutex); 239 240 i915_memcpy_init_early(dev_priv); 241 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 242 243 ret = i915_workqueues_init(dev_priv); 244 if (ret < 0) 245 return ret; 246 247 ret = vlv_suspend_init(dev_priv); 248 if (ret < 0) 249 goto err_workqueues; 250 251 ret = intel_region_ttm_device_init(dev_priv); 252 if (ret) 253 goto err_ttm; 254 255 ret = intel_root_gt_init_early(dev_priv); 256 if (ret < 0) 257 goto err_rootgt; 258 259 i915_gem_init_early(dev_priv); 260 261 /* This must be called before any calls to HAS_PCH_* */ 262 intel_detect_pch(dev_priv); 263 264 intel_irq_init(dev_priv); 265 intel_display_driver_early_probe(dev_priv); 266 intel_clock_gating_hooks_init(dev_priv); 267 268 intel_detect_preproduction_hw(dev_priv); 269 270 return 0; 271 272 err_rootgt: 273 intel_region_ttm_device_fini(dev_priv); 274 err_ttm: 275 vlv_suspend_cleanup(dev_priv); 276 err_workqueues: 277 i915_workqueues_cleanup(dev_priv); 278 return ret; 279 } 280 281 /** 282 * i915_driver_late_release - cleanup the setup done in 283 * i915_driver_early_probe() 284 * @dev_priv: device private 285 */ 286 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 287 { 288 intel_irq_fini(dev_priv); 289 intel_power_domains_cleanup(dev_priv); 290 i915_gem_cleanup_early(dev_priv); 291 intel_gt_driver_late_release_all(dev_priv); 292 intel_region_ttm_device_fini(dev_priv); 293 vlv_suspend_cleanup(dev_priv); 294 i915_workqueues_cleanup(dev_priv); 295 296 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 297 mutex_destroy(&dev_priv->sb_lock); 298 299 i915_params_free(&dev_priv->params); 300 } 301 302 /** 303 * i915_driver_mmio_probe - setup device MMIO 304 * @dev_priv: device private 305 * 306 * Setup minimal device state necessary for MMIO accesses later in the 307 * initialization sequence. The setup here should avoid any other device-wide 308 * side effects or exposing the driver via kernel internal or user space 309 * interfaces. 310 */ 311 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 312 { 313 struct intel_gt *gt; 314 int ret, i; 315 316 if (i915_inject_probe_failure(dev_priv)) 317 return -ENODEV; 318 319 ret = intel_gmch_bridge_setup(dev_priv); 320 if (ret < 0) 321 return ret; 322 323 for_each_gt(gt, dev_priv, i) { 324 ret = intel_uncore_init_mmio(gt->uncore); 325 if (ret) 326 return ret; 327 328 ret = drmm_add_action_or_reset(&dev_priv->drm, 329 intel_uncore_fini_mmio, 330 gt->uncore); 331 if (ret) 332 return ret; 333 } 334 335 /* Try to make sure MCHBAR is enabled before poking at it */ 336 intel_gmch_bar_setup(dev_priv); 337 intel_device_info_runtime_init(dev_priv); 338 339 for_each_gt(gt, dev_priv, i) { 340 ret = intel_gt_init_mmio(gt); 341 if (ret) 342 goto err_uncore; 343 } 344 345 /* As early as possible, scrub existing GPU state before clobbering */ 346 sanitize_gpu(dev_priv); 347 348 return 0; 349 350 err_uncore: 351 intel_gmch_bar_teardown(dev_priv); 352 353 return ret; 354 } 355 356 /** 357 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 358 * @dev_priv: device private 359 */ 360 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 361 { 362 intel_gmch_bar_teardown(dev_priv); 363 } 364 365 /** 366 * i915_set_dma_info - set all relevant PCI dma info as configured for the 367 * platform 368 * @i915: valid i915 instance 369 * 370 * Set the dma max segment size, device and coherent masks. The dma mask set 371 * needs to occur before i915_ggtt_probe_hw. 372 * 373 * A couple of platforms have special needs. Address them as well. 374 * 375 */ 376 static int i915_set_dma_info(struct drm_i915_private *i915) 377 { 378 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 379 int ret; 380 381 GEM_BUG_ON(!mask_size); 382 383 /* 384 * We don't have a max segment size, so set it to the max so sg's 385 * debugging layer doesn't complain 386 */ 387 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 388 389 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 390 if (ret) 391 goto mask_err; 392 393 /* overlay on gen2 is broken and can't address above 1G */ 394 if (GRAPHICS_VER(i915) == 2) 395 mask_size = 30; 396 397 /* 398 * 965GM sometimes incorrectly writes to hardware status page (HWS) 399 * using 32bit addressing, overwriting memory if HWS is located 400 * above 4GB. 401 * 402 * The documentation also mentions an issue with undefined 403 * behaviour if any general state is accessed within a page above 4GB, 404 * which also needs to be handled carefully. 405 */ 406 if (IS_I965G(i915) || IS_I965GM(i915)) 407 mask_size = 32; 408 409 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 410 if (ret) 411 goto mask_err; 412 413 return 0; 414 415 mask_err: 416 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 417 return ret; 418 } 419 420 static int i915_pcode_init(struct drm_i915_private *i915) 421 { 422 struct intel_gt *gt; 423 int id, ret; 424 425 for_each_gt(gt, i915, id) { 426 ret = intel_pcode_init(gt->uncore); 427 if (ret) { 428 drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret); 429 return ret; 430 } 431 } 432 433 return 0; 434 } 435 436 /** 437 * i915_driver_hw_probe - setup state requiring device access 438 * @dev_priv: device private 439 * 440 * Setup state that requires accessing the device, but doesn't require 441 * exposing the driver via kernel internal or userspace interfaces. 442 */ 443 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 444 { 445 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 446 struct pci_dev *root_pdev; 447 int ret; 448 449 if (i915_inject_probe_failure(dev_priv)) 450 return -ENODEV; 451 452 if (HAS_PPGTT(dev_priv)) { 453 if (intel_vgpu_active(dev_priv) && 454 !intel_vgpu_has_full_ppgtt(dev_priv)) { 455 i915_report_error(dev_priv, 456 "incompatible vGPU found, support for isolated ppGTT required\n"); 457 return -ENXIO; 458 } 459 } 460 461 if (HAS_EXECLISTS(dev_priv)) { 462 /* 463 * Older GVT emulation depends upon intercepting CSB mmio, 464 * which we no longer use, preferring to use the HWSP cache 465 * instead. 466 */ 467 if (intel_vgpu_active(dev_priv) && 468 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 469 i915_report_error(dev_priv, 470 "old vGPU host found, support for HWSP emulation required\n"); 471 return -ENXIO; 472 } 473 } 474 475 /* needs to be done before ggtt probe */ 476 intel_dram_edram_detect(dev_priv); 477 478 ret = i915_set_dma_info(dev_priv); 479 if (ret) 480 return ret; 481 482 ret = i915_perf_init(dev_priv); 483 if (ret) 484 return ret; 485 486 ret = i915_ggtt_probe_hw(dev_priv); 487 if (ret) 488 goto err_perf; 489 490 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 491 if (ret) 492 goto err_ggtt; 493 494 ret = i915_ggtt_init_hw(dev_priv); 495 if (ret) 496 goto err_ggtt; 497 498 /* 499 * Make sure we probe lmem before we probe stolen-lmem. The BAR size 500 * might be different due to bar resizing. 501 */ 502 ret = intel_gt_tiles_init(dev_priv); 503 if (ret) 504 goto err_ggtt; 505 506 ret = intel_memory_regions_hw_probe(dev_priv); 507 if (ret) 508 goto err_ggtt; 509 510 ret = i915_ggtt_enable_hw(dev_priv); 511 if (ret) { 512 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 513 goto err_mem_regions; 514 } 515 516 pci_set_master(pdev); 517 518 /* On the 945G/GM, the chipset reports the MSI capability on the 519 * integrated graphics even though the support isn't actually there 520 * according to the published specs. It doesn't appear to function 521 * correctly in testing on 945G. 522 * This may be a side effect of MSI having been made available for PEG 523 * and the registers being closely associated. 524 * 525 * According to chipset errata, on the 965GM, MSI interrupts may 526 * be lost or delayed, and was defeatured. MSI interrupts seem to 527 * get lost on g4x as well, and interrupt delivery seems to stay 528 * properly dead afterwards. So we'll just disable them for all 529 * pre-gen5 chipsets. 530 * 531 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 532 * interrupts even when in MSI mode. This results in spurious 533 * interrupt warnings if the legacy irq no. is shared with another 534 * device. The kernel then disables that interrupt source and so 535 * prevents the other device from working properly. 536 */ 537 if (GRAPHICS_VER(dev_priv) >= 5) { 538 if (pci_enable_msi(pdev) < 0) 539 drm_dbg(&dev_priv->drm, "can't enable MSI"); 540 } 541 542 ret = intel_gvt_init(dev_priv); 543 if (ret) 544 goto err_msi; 545 546 intel_opregion_setup(dev_priv); 547 548 ret = i915_pcode_init(dev_priv); 549 if (ret) 550 goto err_opregion; 551 552 /* 553 * Fill the dram structure to get the system dram info. This will be 554 * used for memory latency calculation. 555 */ 556 intel_dram_detect(dev_priv); 557 558 intel_bw_init_hw(dev_priv); 559 560 /* 561 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 562 * This should be totally removed when we handle the pci states properly 563 * on runtime PM and on s2idle cases. 564 */ 565 root_pdev = pcie_find_root_port(pdev); 566 if (root_pdev) 567 pci_d3cold_disable(root_pdev); 568 569 return 0; 570 571 err_opregion: 572 intel_opregion_cleanup(dev_priv); 573 err_msi: 574 if (pdev->msi_enabled) 575 pci_disable_msi(pdev); 576 err_mem_regions: 577 intel_memory_regions_driver_release(dev_priv); 578 err_ggtt: 579 i915_ggtt_driver_release(dev_priv); 580 i915_gem_drain_freed_objects(dev_priv); 581 i915_ggtt_driver_late_release(dev_priv); 582 err_perf: 583 i915_perf_fini(dev_priv); 584 return ret; 585 } 586 587 /** 588 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 589 * @dev_priv: device private 590 */ 591 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 592 { 593 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 594 struct pci_dev *root_pdev; 595 596 i915_perf_fini(dev_priv); 597 598 intel_opregion_cleanup(dev_priv); 599 600 if (pdev->msi_enabled) 601 pci_disable_msi(pdev); 602 603 root_pdev = pcie_find_root_port(pdev); 604 if (root_pdev) 605 pci_d3cold_enable(root_pdev); 606 } 607 608 /** 609 * i915_driver_register - register the driver with the rest of the system 610 * @dev_priv: device private 611 * 612 * Perform any steps necessary to make the driver available via kernel 613 * internal or userspace interfaces. 614 */ 615 static void i915_driver_register(struct drm_i915_private *dev_priv) 616 { 617 struct intel_gt *gt; 618 unsigned int i; 619 620 i915_gem_driver_register(dev_priv); 621 i915_pmu_register(dev_priv); 622 623 intel_vgpu_register(dev_priv); 624 625 /* Reveal our presence to userspace */ 626 if (drm_dev_register(&dev_priv->drm, 0)) { 627 drm_err(&dev_priv->drm, 628 "Failed to register driver for userspace access!\n"); 629 return; 630 } 631 632 i915_debugfs_register(dev_priv); 633 i915_setup_sysfs(dev_priv); 634 635 /* Depends on sysfs having been initialized */ 636 i915_perf_register(dev_priv); 637 638 for_each_gt(gt, dev_priv, i) 639 intel_gt_driver_register(gt); 640 641 intel_pxp_debugfs_register(dev_priv->pxp); 642 643 i915_hwmon_register(dev_priv); 644 645 intel_display_driver_register(dev_priv); 646 647 intel_power_domains_enable(dev_priv); 648 intel_runtime_pm_enable(&dev_priv->runtime_pm); 649 650 intel_register_dsm_handler(); 651 652 if (i915_switcheroo_register(dev_priv)) 653 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 654 } 655 656 /** 657 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 658 * @dev_priv: device private 659 */ 660 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 661 { 662 struct intel_gt *gt; 663 unsigned int i; 664 665 i915_switcheroo_unregister(dev_priv); 666 667 intel_unregister_dsm_handler(); 668 669 intel_runtime_pm_disable(&dev_priv->runtime_pm); 670 intel_power_domains_disable(dev_priv); 671 672 intel_display_driver_unregister(dev_priv); 673 674 intel_pxp_fini(dev_priv); 675 676 for_each_gt(gt, dev_priv, i) 677 intel_gt_driver_unregister(gt); 678 679 i915_hwmon_unregister(dev_priv); 680 681 i915_perf_unregister(dev_priv); 682 i915_pmu_unregister(dev_priv); 683 684 i915_teardown_sysfs(dev_priv); 685 drm_dev_unplug(&dev_priv->drm); 686 687 i915_gem_driver_unregister(dev_priv); 688 } 689 690 void 691 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 692 { 693 drm_printf(p, "iommu: %s\n", 694 str_enabled_disabled(i915_vtd_active(i915))); 695 } 696 697 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 698 { 699 if (drm_debug_enabled(DRM_UT_DRIVER)) { 700 struct drm_printer p = drm_debug_printer("i915 device info:"); 701 struct intel_gt *gt; 702 unsigned int i; 703 704 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 705 INTEL_DEVID(dev_priv), 706 INTEL_REVID(dev_priv), 707 intel_platform_name(INTEL_INFO(dev_priv)->platform), 708 intel_subplatform(RUNTIME_INFO(dev_priv), 709 INTEL_INFO(dev_priv)->platform), 710 GRAPHICS_VER(dev_priv)); 711 712 intel_device_info_print(INTEL_INFO(dev_priv), 713 RUNTIME_INFO(dev_priv), &p); 714 i915_print_iommu_status(dev_priv, &p); 715 for_each_gt(gt, dev_priv, i) 716 intel_gt_info_print(>->info, &p); 717 } 718 719 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 720 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 721 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 722 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 723 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 724 drm_info(&dev_priv->drm, 725 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 726 } 727 728 static struct drm_i915_private * 729 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 730 { 731 const struct intel_device_info *match_info = 732 (struct intel_device_info *)ent->driver_data; 733 struct drm_i915_private *i915; 734 735 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 736 struct drm_i915_private, drm); 737 if (IS_ERR(i915)) 738 return i915; 739 740 pci_set_drvdata(pdev, i915); 741 742 /* Device parameters start as a copy of module parameters. */ 743 i915_params_copy(&i915->params, &i915_modparams); 744 745 /* Set up device info and initial runtime info. */ 746 intel_device_info_driver_create(i915, pdev->device, match_info); 747 748 return i915; 749 } 750 751 /** 752 * i915_driver_probe - setup chip and create an initial config 753 * @pdev: PCI device 754 * @ent: matching PCI ID entry 755 * 756 * The driver probe routine has to do several things: 757 * - drive output discovery via intel_display_driver_probe() 758 * - initialize the memory manager 759 * - allocate initial config memory 760 * - setup the DRM framebuffer with the allocated memory 761 */ 762 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 763 { 764 struct drm_i915_private *i915; 765 int ret; 766 767 ret = pci_enable_device(pdev); 768 if (ret) { 769 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret)); 770 return ret; 771 } 772 773 i915 = i915_driver_create(pdev, ent); 774 if (IS_ERR(i915)) { 775 pci_disable_device(pdev); 776 return PTR_ERR(i915); 777 } 778 779 ret = i915_driver_early_probe(i915); 780 if (ret < 0) 781 goto out_pci_disable; 782 783 disable_rpm_wakeref_asserts(&i915->runtime_pm); 784 785 intel_vgpu_detect(i915); 786 787 ret = intel_gt_probe_all(i915); 788 if (ret < 0) 789 goto out_runtime_pm_put; 790 791 ret = i915_driver_mmio_probe(i915); 792 if (ret < 0) 793 goto out_tiles_cleanup; 794 795 ret = i915_driver_hw_probe(i915); 796 if (ret < 0) 797 goto out_cleanup_mmio; 798 799 ret = intel_display_driver_probe_noirq(i915); 800 if (ret < 0) 801 goto out_cleanup_hw; 802 803 ret = intel_irq_install(i915); 804 if (ret) 805 goto out_cleanup_modeset; 806 807 ret = intel_display_driver_probe_nogem(i915); 808 if (ret) 809 goto out_cleanup_irq; 810 811 ret = i915_gem_init(i915); 812 if (ret) 813 goto out_cleanup_modeset2; 814 815 intel_pxp_init(i915); 816 817 ret = intel_display_driver_probe(i915); 818 if (ret) 819 goto out_cleanup_gem; 820 821 i915_driver_register(i915); 822 823 enable_rpm_wakeref_asserts(&i915->runtime_pm); 824 825 i915_welcome_messages(i915); 826 827 i915->do_release = true; 828 829 return 0; 830 831 out_cleanup_gem: 832 i915_gem_suspend(i915); 833 i915_gem_driver_remove(i915); 834 i915_gem_driver_release(i915); 835 out_cleanup_modeset2: 836 /* FIXME clean up the error path */ 837 intel_display_driver_remove(i915); 838 intel_irq_uninstall(i915); 839 intel_display_driver_remove_noirq(i915); 840 goto out_cleanup_modeset; 841 out_cleanup_irq: 842 intel_irq_uninstall(i915); 843 out_cleanup_modeset: 844 intel_display_driver_remove_nogem(i915); 845 out_cleanup_hw: 846 i915_driver_hw_remove(i915); 847 intel_memory_regions_driver_release(i915); 848 i915_ggtt_driver_release(i915); 849 i915_gem_drain_freed_objects(i915); 850 i915_ggtt_driver_late_release(i915); 851 out_cleanup_mmio: 852 i915_driver_mmio_release(i915); 853 out_tiles_cleanup: 854 intel_gt_release_all(i915); 855 out_runtime_pm_put: 856 enable_rpm_wakeref_asserts(&i915->runtime_pm); 857 i915_driver_late_release(i915); 858 out_pci_disable: 859 pci_disable_device(pdev); 860 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 861 return ret; 862 } 863 864 void i915_driver_remove(struct drm_i915_private *i915) 865 { 866 intel_wakeref_t wakeref; 867 868 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 869 870 i915_driver_unregister(i915); 871 872 /* Flush any external code that still may be under the RCU lock */ 873 synchronize_rcu(); 874 875 i915_gem_suspend(i915); 876 877 intel_gvt_driver_remove(i915); 878 879 intel_display_driver_remove(i915); 880 881 intel_irq_uninstall(i915); 882 883 intel_display_driver_remove_noirq(i915); 884 885 i915_reset_error_state(i915); 886 i915_gem_driver_remove(i915); 887 888 intel_display_driver_remove_nogem(i915); 889 890 i915_driver_hw_remove(i915); 891 892 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 893 } 894 895 static void i915_driver_release(struct drm_device *dev) 896 { 897 struct drm_i915_private *dev_priv = to_i915(dev); 898 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 899 intel_wakeref_t wakeref; 900 901 if (!dev_priv->do_release) 902 return; 903 904 wakeref = intel_runtime_pm_get(rpm); 905 906 i915_gem_driver_release(dev_priv); 907 908 intel_memory_regions_driver_release(dev_priv); 909 i915_ggtt_driver_release(dev_priv); 910 i915_gem_drain_freed_objects(dev_priv); 911 i915_ggtt_driver_late_release(dev_priv); 912 913 i915_driver_mmio_release(dev_priv); 914 915 intel_runtime_pm_put(rpm, wakeref); 916 917 intel_runtime_pm_driver_release(rpm); 918 919 i915_driver_late_release(dev_priv); 920 } 921 922 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 923 { 924 struct drm_i915_private *i915 = to_i915(dev); 925 int ret; 926 927 ret = i915_gem_open(i915, file); 928 if (ret) 929 return ret; 930 931 return 0; 932 } 933 934 /** 935 * i915_driver_lastclose - clean up after all DRM clients have exited 936 * @dev: DRM device 937 * 938 * Take care of cleaning up after all DRM clients have exited. In the 939 * mode setting case, we want to restore the kernel's initial mode (just 940 * in case the last client left us in a bad state). 941 * 942 * Additionally, in the non-mode setting case, we'll tear down the GTT 943 * and DMA structures, since the kernel won't be using them, and clea 944 * up any GEM state. 945 */ 946 static void i915_driver_lastclose(struct drm_device *dev) 947 { 948 struct drm_i915_private *i915 = to_i915(dev); 949 950 intel_fbdev_restore_mode(i915); 951 952 vga_switcheroo_process_delayed_switch(); 953 } 954 955 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 956 { 957 struct drm_i915_file_private *file_priv = file->driver_priv; 958 959 i915_gem_context_close(file); 960 i915_drm_client_put(file_priv->client); 961 962 kfree_rcu(file_priv, rcu); 963 964 /* Catch up with all the deferred frees from "this" client */ 965 i915_gem_flush_free_objects(to_i915(dev)); 966 } 967 968 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 969 { 970 struct intel_encoder *encoder; 971 972 if (!HAS_DISPLAY(dev_priv)) 973 return; 974 975 /* 976 * TODO: check and remove holding the modeset locks if none of 977 * the encoders depends on this. 978 */ 979 drm_modeset_lock_all(&dev_priv->drm); 980 for_each_intel_encoder(&dev_priv->drm, encoder) 981 if (encoder->suspend) 982 encoder->suspend(encoder); 983 drm_modeset_unlock_all(&dev_priv->drm); 984 985 for_each_intel_encoder(&dev_priv->drm, encoder) 986 if (encoder->suspend_complete) 987 encoder->suspend_complete(encoder); 988 } 989 990 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 991 { 992 struct intel_encoder *encoder; 993 994 if (!HAS_DISPLAY(dev_priv)) 995 return; 996 997 /* 998 * TODO: check and remove holding the modeset locks if none of 999 * the encoders depends on this. 1000 */ 1001 drm_modeset_lock_all(&dev_priv->drm); 1002 for_each_intel_encoder(&dev_priv->drm, encoder) 1003 if (encoder->shutdown) 1004 encoder->shutdown(encoder); 1005 drm_modeset_unlock_all(&dev_priv->drm); 1006 1007 for_each_intel_encoder(&dev_priv->drm, encoder) 1008 if (encoder->shutdown_complete) 1009 encoder->shutdown_complete(encoder); 1010 } 1011 1012 void i915_driver_shutdown(struct drm_i915_private *i915) 1013 { 1014 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1015 intel_runtime_pm_disable(&i915->runtime_pm); 1016 intel_power_domains_disable(i915); 1017 1018 if (HAS_DISPLAY(i915)) { 1019 drm_kms_helper_poll_disable(&i915->drm); 1020 1021 drm_atomic_helper_shutdown(&i915->drm); 1022 } 1023 1024 intel_dp_mst_suspend(i915); 1025 1026 intel_runtime_pm_disable_interrupts(i915); 1027 intel_hpd_cancel_work(i915); 1028 1029 intel_suspend_encoders(i915); 1030 intel_shutdown_encoders(i915); 1031 1032 intel_dmc_suspend(i915); 1033 1034 i915_gem_suspend(i915); 1035 1036 /* 1037 * The only requirement is to reboot with display DC states disabled, 1038 * for now leaving all display power wells in the INIT power domain 1039 * enabled. 1040 * 1041 * TODO: 1042 * - unify the pci_driver::shutdown sequence here with the 1043 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1044 * - unify the driver remove and system/runtime suspend sequences with 1045 * the above unified shutdown/poweroff sequence. 1046 */ 1047 intel_power_domains_driver_remove(i915); 1048 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1049 1050 intel_runtime_pm_driver_release(&i915->runtime_pm); 1051 } 1052 1053 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1054 { 1055 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1056 if (acpi_target_system_state() < ACPI_STATE_S3) 1057 return true; 1058 #endif 1059 return false; 1060 } 1061 1062 static void i915_drm_complete(struct drm_device *dev) 1063 { 1064 struct drm_i915_private *i915 = to_i915(dev); 1065 1066 intel_pxp_resume_complete(i915->pxp); 1067 } 1068 1069 static int i915_drm_prepare(struct drm_device *dev) 1070 { 1071 struct drm_i915_private *i915 = to_i915(dev); 1072 1073 intel_pxp_suspend_prepare(i915->pxp); 1074 1075 /* 1076 * NB intel_display_driver_suspend() may issue new requests after we've 1077 * ostensibly marked the GPU as ready-to-sleep here. We need to 1078 * split out that work and pull it forward so that after point, 1079 * the GPU is not woken again. 1080 */ 1081 return i915_gem_backup_suspend(i915); 1082 } 1083 1084 static int i915_drm_suspend(struct drm_device *dev) 1085 { 1086 struct drm_i915_private *dev_priv = to_i915(dev); 1087 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1088 pci_power_t opregion_target_state; 1089 1090 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1091 1092 /* We do a lot of poking in a lot of registers, make sure they work 1093 * properly. */ 1094 intel_power_domains_disable(dev_priv); 1095 if (HAS_DISPLAY(dev_priv)) 1096 drm_kms_helper_poll_disable(dev); 1097 1098 pci_save_state(pdev); 1099 1100 intel_display_driver_suspend(dev_priv); 1101 1102 intel_dp_mst_suspend(dev_priv); 1103 1104 intel_runtime_pm_disable_interrupts(dev_priv); 1105 intel_hpd_cancel_work(dev_priv); 1106 1107 intel_suspend_encoders(dev_priv); 1108 1109 /* Must be called before GGTT is suspended. */ 1110 intel_dpt_suspend(dev_priv); 1111 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1112 1113 i915_save_display(dev_priv); 1114 1115 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1116 intel_opregion_suspend(dev_priv, opregion_target_state); 1117 1118 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1119 1120 dev_priv->suspend_count++; 1121 1122 intel_dmc_suspend(dev_priv); 1123 1124 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1125 1126 i915_gem_drain_freed_objects(dev_priv); 1127 1128 return 0; 1129 } 1130 1131 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1132 { 1133 struct drm_i915_private *dev_priv = to_i915(dev); 1134 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1135 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1136 struct intel_gt *gt; 1137 int ret, i; 1138 bool s2idle = !hibernation && suspend_to_idle(dev_priv); 1139 1140 disable_rpm_wakeref_asserts(rpm); 1141 1142 intel_pxp_suspend(dev_priv->pxp); 1143 1144 i915_gem_suspend_late(dev_priv); 1145 1146 for_each_gt(gt, dev_priv, i) 1147 intel_uncore_suspend(gt->uncore); 1148 1149 intel_power_domains_suspend(dev_priv, s2idle); 1150 1151 intel_display_power_suspend_late(dev_priv); 1152 1153 ret = vlv_suspend_complete(dev_priv); 1154 if (ret) { 1155 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1156 intel_power_domains_resume(dev_priv); 1157 1158 goto out; 1159 } 1160 1161 pci_disable_device(pdev); 1162 /* 1163 * During hibernation on some platforms the BIOS may try to access 1164 * the device even though it's already in D3 and hang the machine. So 1165 * leave the device in D0 on those platforms and hope the BIOS will 1166 * power down the device properly. The issue was seen on multiple old 1167 * GENs with different BIOS vendors, so having an explicit blacklist 1168 * is inpractical; apply the workaround on everything pre GEN6. The 1169 * platforms where the issue was seen: 1170 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1171 * Fujitsu FSC S7110 1172 * Acer Aspire 1830T 1173 */ 1174 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1175 pci_set_power_state(pdev, PCI_D3hot); 1176 1177 out: 1178 enable_rpm_wakeref_asserts(rpm); 1179 if (!dev_priv->uncore.user_forcewake_count) 1180 intel_runtime_pm_driver_release(rpm); 1181 1182 return ret; 1183 } 1184 1185 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1186 pm_message_t state) 1187 { 1188 int error; 1189 1190 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1191 state.event != PM_EVENT_FREEZE)) 1192 return -EINVAL; 1193 1194 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1195 return 0; 1196 1197 error = i915_drm_suspend(&i915->drm); 1198 if (error) 1199 return error; 1200 1201 return i915_drm_suspend_late(&i915->drm, false); 1202 } 1203 1204 static int i915_drm_resume(struct drm_device *dev) 1205 { 1206 struct drm_i915_private *dev_priv = to_i915(dev); 1207 struct intel_gt *gt; 1208 int ret, i; 1209 1210 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1211 1212 ret = i915_pcode_init(dev_priv); 1213 if (ret) 1214 return ret; 1215 1216 sanitize_gpu(dev_priv); 1217 1218 ret = i915_ggtt_enable_hw(dev_priv); 1219 if (ret) 1220 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1221 1222 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1223 1224 for_each_gt(gt, dev_priv, i) 1225 if (GRAPHICS_VER(gt->i915) >= 8) 1226 setup_private_pat(gt); 1227 1228 /* Must be called after GGTT is resumed. */ 1229 intel_dpt_resume(dev_priv); 1230 1231 intel_dmc_resume(dev_priv); 1232 1233 i915_restore_display(dev_priv); 1234 intel_pps_unlock_regs_wa(dev_priv); 1235 1236 intel_init_pch_refclk(dev_priv); 1237 1238 /* 1239 * Interrupts have to be enabled before any batches are run. If not the 1240 * GPU will hang. i915_gem_init_hw() will initiate batches to 1241 * update/restore the context. 1242 * 1243 * drm_mode_config_reset() needs AUX interrupts. 1244 * 1245 * Modeset enabling in intel_display_driver_init_hw() also needs working 1246 * interrupts. 1247 */ 1248 intel_runtime_pm_enable_interrupts(dev_priv); 1249 1250 if (HAS_DISPLAY(dev_priv)) 1251 drm_mode_config_reset(dev); 1252 1253 i915_gem_resume(dev_priv); 1254 1255 intel_display_driver_init_hw(dev_priv); 1256 1257 intel_clock_gating_init(dev_priv); 1258 intel_hpd_init(dev_priv); 1259 1260 /* MST sideband requires HPD interrupts enabled */ 1261 intel_dp_mst_resume(dev_priv); 1262 intel_display_driver_resume(dev_priv); 1263 1264 intel_hpd_poll_disable(dev_priv); 1265 if (HAS_DISPLAY(dev_priv)) 1266 drm_kms_helper_poll_enable(dev); 1267 1268 intel_opregion_resume(dev_priv); 1269 1270 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1271 1272 intel_power_domains_enable(dev_priv); 1273 1274 intel_gvt_resume(dev_priv); 1275 1276 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1277 1278 return 0; 1279 } 1280 1281 static int i915_drm_resume_early(struct drm_device *dev) 1282 { 1283 struct drm_i915_private *dev_priv = to_i915(dev); 1284 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1285 struct intel_gt *gt; 1286 int ret, i; 1287 1288 /* 1289 * We have a resume ordering issue with the snd-hda driver also 1290 * requiring our device to be power up. Due to the lack of a 1291 * parent/child relationship we currently solve this with an early 1292 * resume hook. 1293 * 1294 * FIXME: This should be solved with a special hdmi sink device or 1295 * similar so that power domains can be employed. 1296 */ 1297 1298 /* 1299 * Note that we need to set the power state explicitly, since we 1300 * powered off the device during freeze and the PCI core won't power 1301 * it back up for us during thaw. Powering off the device during 1302 * freeze is not a hard requirement though, and during the 1303 * suspend/resume phases the PCI core makes sure we get here with the 1304 * device powered on. So in case we change our freeze logic and keep 1305 * the device powered we can also remove the following set power state 1306 * call. 1307 */ 1308 ret = pci_set_power_state(pdev, PCI_D0); 1309 if (ret) { 1310 drm_err(&dev_priv->drm, 1311 "failed to set PCI D0 power state (%d)\n", ret); 1312 return ret; 1313 } 1314 1315 /* 1316 * Note that pci_enable_device() first enables any parent bridge 1317 * device and only then sets the power state for this device. The 1318 * bridge enabling is a nop though, since bridge devices are resumed 1319 * first. The order of enabling power and enabling the device is 1320 * imposed by the PCI core as described above, so here we preserve the 1321 * same order for the freeze/thaw phases. 1322 * 1323 * TODO: eventually we should remove pci_disable_device() / 1324 * pci_enable_enable_device() from suspend/resume. Due to how they 1325 * depend on the device enable refcount we can't anyway depend on them 1326 * disabling/enabling the device. 1327 */ 1328 if (pci_enable_device(pdev)) 1329 return -EIO; 1330 1331 pci_set_master(pdev); 1332 1333 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1334 1335 ret = vlv_resume_prepare(dev_priv, false); 1336 if (ret) 1337 drm_err(&dev_priv->drm, 1338 "Resume prepare failed: %d, continuing anyway\n", ret); 1339 1340 for_each_gt(gt, dev_priv, i) { 1341 intel_uncore_resume_early(gt->uncore); 1342 intel_gt_check_and_clear_faults(gt); 1343 } 1344 1345 intel_display_power_resume_early(dev_priv); 1346 1347 intel_power_domains_resume(dev_priv); 1348 1349 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1350 1351 return ret; 1352 } 1353 1354 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1355 { 1356 int ret; 1357 1358 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1359 return 0; 1360 1361 ret = i915_drm_resume_early(&i915->drm); 1362 if (ret) 1363 return ret; 1364 1365 return i915_drm_resume(&i915->drm); 1366 } 1367 1368 static int i915_pm_prepare(struct device *kdev) 1369 { 1370 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1371 1372 if (!i915) { 1373 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1374 return -ENODEV; 1375 } 1376 1377 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1378 return 0; 1379 1380 return i915_drm_prepare(&i915->drm); 1381 } 1382 1383 static int i915_pm_suspend(struct device *kdev) 1384 { 1385 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1386 1387 if (!i915) { 1388 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1389 return -ENODEV; 1390 } 1391 1392 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1393 return 0; 1394 1395 return i915_drm_suspend(&i915->drm); 1396 } 1397 1398 static int i915_pm_suspend_late(struct device *kdev) 1399 { 1400 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1401 1402 /* 1403 * We have a suspend ordering issue with the snd-hda driver also 1404 * requiring our device to be power up. Due to the lack of a 1405 * parent/child relationship we currently solve this with an late 1406 * suspend hook. 1407 * 1408 * FIXME: This should be solved with a special hdmi sink device or 1409 * similar so that power domains can be employed. 1410 */ 1411 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1412 return 0; 1413 1414 return i915_drm_suspend_late(&i915->drm, false); 1415 } 1416 1417 static int i915_pm_poweroff_late(struct device *kdev) 1418 { 1419 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1420 1421 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1422 return 0; 1423 1424 return i915_drm_suspend_late(&i915->drm, true); 1425 } 1426 1427 static int i915_pm_resume_early(struct device *kdev) 1428 { 1429 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1430 1431 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1432 return 0; 1433 1434 return i915_drm_resume_early(&i915->drm); 1435 } 1436 1437 static int i915_pm_resume(struct device *kdev) 1438 { 1439 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1440 1441 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1442 return 0; 1443 1444 return i915_drm_resume(&i915->drm); 1445 } 1446 1447 static void i915_pm_complete(struct device *kdev) 1448 { 1449 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1450 1451 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1452 return; 1453 1454 i915_drm_complete(&i915->drm); 1455 } 1456 1457 /* freeze: before creating the hibernation_image */ 1458 static int i915_pm_freeze(struct device *kdev) 1459 { 1460 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1461 int ret; 1462 1463 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1464 ret = i915_drm_suspend(&i915->drm); 1465 if (ret) 1466 return ret; 1467 } 1468 1469 ret = i915_gem_freeze(i915); 1470 if (ret) 1471 return ret; 1472 1473 return 0; 1474 } 1475 1476 static int i915_pm_freeze_late(struct device *kdev) 1477 { 1478 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1479 int ret; 1480 1481 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1482 ret = i915_drm_suspend_late(&i915->drm, true); 1483 if (ret) 1484 return ret; 1485 } 1486 1487 ret = i915_gem_freeze_late(i915); 1488 if (ret) 1489 return ret; 1490 1491 return 0; 1492 } 1493 1494 /* thaw: called after creating the hibernation image, but before turning off. */ 1495 static int i915_pm_thaw_early(struct device *kdev) 1496 { 1497 return i915_pm_resume_early(kdev); 1498 } 1499 1500 static int i915_pm_thaw(struct device *kdev) 1501 { 1502 return i915_pm_resume(kdev); 1503 } 1504 1505 /* restore: called after loading the hibernation image. */ 1506 static int i915_pm_restore_early(struct device *kdev) 1507 { 1508 return i915_pm_resume_early(kdev); 1509 } 1510 1511 static int i915_pm_restore(struct device *kdev) 1512 { 1513 return i915_pm_resume(kdev); 1514 } 1515 1516 static int intel_runtime_suspend(struct device *kdev) 1517 { 1518 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1519 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1520 struct intel_gt *gt; 1521 int ret, i; 1522 1523 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1524 return -ENODEV; 1525 1526 drm_dbg(&dev_priv->drm, "Suspending device\n"); 1527 1528 disable_rpm_wakeref_asserts(rpm); 1529 1530 /* 1531 * We are safe here against re-faults, since the fault handler takes 1532 * an RPM reference. 1533 */ 1534 i915_gem_runtime_suspend(dev_priv); 1535 1536 intel_pxp_runtime_suspend(dev_priv->pxp); 1537 1538 for_each_gt(gt, dev_priv, i) 1539 intel_gt_runtime_suspend(gt); 1540 1541 intel_runtime_pm_disable_interrupts(dev_priv); 1542 1543 for_each_gt(gt, dev_priv, i) 1544 intel_uncore_suspend(gt->uncore); 1545 1546 intel_display_power_suspend(dev_priv); 1547 1548 ret = vlv_suspend_complete(dev_priv); 1549 if (ret) { 1550 drm_err(&dev_priv->drm, 1551 "Runtime suspend failed, disabling it (%d)\n", ret); 1552 intel_uncore_runtime_resume(&dev_priv->uncore); 1553 1554 intel_runtime_pm_enable_interrupts(dev_priv); 1555 1556 for_each_gt(gt, dev_priv, i) 1557 intel_gt_runtime_resume(gt); 1558 1559 enable_rpm_wakeref_asserts(rpm); 1560 1561 return ret; 1562 } 1563 1564 enable_rpm_wakeref_asserts(rpm); 1565 intel_runtime_pm_driver_release(rpm); 1566 1567 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1568 drm_err(&dev_priv->drm, 1569 "Unclaimed access detected prior to suspending\n"); 1570 1571 rpm->suspended = true; 1572 1573 /* 1574 * FIXME: We really should find a document that references the arguments 1575 * used below! 1576 */ 1577 if (IS_BROADWELL(dev_priv)) { 1578 /* 1579 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1580 * being detected, and the call we do at intel_runtime_resume() 1581 * won't be able to restore them. Since PCI_D3hot matches the 1582 * actual specification and appears to be working, use it. 1583 */ 1584 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1585 } else { 1586 /* 1587 * current versions of firmware which depend on this opregion 1588 * notification have repurposed the D1 definition to mean 1589 * "runtime suspended" vs. what you would normally expect (D3) 1590 * to distinguish it from notifications that might be sent via 1591 * the suspend path. 1592 */ 1593 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1594 } 1595 1596 assert_forcewakes_inactive(&dev_priv->uncore); 1597 1598 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1599 intel_hpd_poll_enable(dev_priv); 1600 1601 drm_dbg(&dev_priv->drm, "Device suspended\n"); 1602 return 0; 1603 } 1604 1605 static int intel_runtime_resume(struct device *kdev) 1606 { 1607 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1608 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1609 struct intel_gt *gt; 1610 int ret, i; 1611 1612 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1613 return -ENODEV; 1614 1615 drm_dbg(&dev_priv->drm, "Resuming device\n"); 1616 1617 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1618 disable_rpm_wakeref_asserts(rpm); 1619 1620 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1621 rpm->suspended = false; 1622 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1623 drm_dbg(&dev_priv->drm, 1624 "Unclaimed access during suspend, bios?\n"); 1625 1626 intel_display_power_resume(dev_priv); 1627 1628 ret = vlv_resume_prepare(dev_priv, true); 1629 1630 for_each_gt(gt, dev_priv, i) 1631 intel_uncore_runtime_resume(gt->uncore); 1632 1633 intel_runtime_pm_enable_interrupts(dev_priv); 1634 1635 /* 1636 * No point of rolling back things in case of an error, as the best 1637 * we can do is to hope that things will still work (and disable RPM). 1638 */ 1639 for_each_gt(gt, dev_priv, i) 1640 intel_gt_runtime_resume(gt); 1641 1642 intel_pxp_runtime_resume(dev_priv->pxp); 1643 1644 /* 1645 * On VLV/CHV display interrupts are part of the display 1646 * power well, so hpd is reinitialized from there. For 1647 * everyone else do it here. 1648 */ 1649 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1650 intel_hpd_init(dev_priv); 1651 intel_hpd_poll_disable(dev_priv); 1652 } 1653 1654 skl_watermark_ipc_update(dev_priv); 1655 1656 enable_rpm_wakeref_asserts(rpm); 1657 1658 if (ret) 1659 drm_err(&dev_priv->drm, 1660 "Runtime resume failed, disabling it (%d)\n", ret); 1661 else 1662 drm_dbg(&dev_priv->drm, "Device resumed\n"); 1663 1664 return ret; 1665 } 1666 1667 const struct dev_pm_ops i915_pm_ops = { 1668 /* 1669 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1670 * PMSG_RESUME] 1671 */ 1672 .prepare = i915_pm_prepare, 1673 .suspend = i915_pm_suspend, 1674 .suspend_late = i915_pm_suspend_late, 1675 .resume_early = i915_pm_resume_early, 1676 .resume = i915_pm_resume, 1677 .complete = i915_pm_complete, 1678 1679 /* 1680 * S4 event handlers 1681 * @freeze, @freeze_late : called (1) before creating the 1682 * hibernation image [PMSG_FREEZE] and 1683 * (2) after rebooting, before restoring 1684 * the image [PMSG_QUIESCE] 1685 * @thaw, @thaw_early : called (1) after creating the hibernation 1686 * image, before writing it [PMSG_THAW] 1687 * and (2) after failing to create or 1688 * restore the image [PMSG_RECOVER] 1689 * @poweroff, @poweroff_late: called after writing the hibernation 1690 * image, before rebooting [PMSG_HIBERNATE] 1691 * @restore, @restore_early : called after rebooting and restoring the 1692 * hibernation image [PMSG_RESTORE] 1693 */ 1694 .freeze = i915_pm_freeze, 1695 .freeze_late = i915_pm_freeze_late, 1696 .thaw_early = i915_pm_thaw_early, 1697 .thaw = i915_pm_thaw, 1698 .poweroff = i915_pm_suspend, 1699 .poweroff_late = i915_pm_poweroff_late, 1700 .restore_early = i915_pm_restore_early, 1701 .restore = i915_pm_restore, 1702 1703 /* S0ix (via runtime suspend) event handlers */ 1704 .runtime_suspend = intel_runtime_suspend, 1705 .runtime_resume = intel_runtime_resume, 1706 }; 1707 1708 static const struct file_operations i915_driver_fops = { 1709 .owner = THIS_MODULE, 1710 .open = drm_open, 1711 .release = drm_release_noglobal, 1712 .unlocked_ioctl = drm_ioctl, 1713 .mmap = i915_gem_mmap, 1714 .poll = drm_poll, 1715 .read = drm_read, 1716 .compat_ioctl = i915_ioc32_compat_ioctl, 1717 .llseek = noop_llseek, 1718 #ifdef CONFIG_PROC_FS 1719 .show_fdinfo = drm_show_fdinfo, 1720 #endif 1721 }; 1722 1723 static int 1724 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1725 struct drm_file *file) 1726 { 1727 return -ENODEV; 1728 } 1729 1730 static const struct drm_ioctl_desc i915_ioctls[] = { 1731 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1732 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1733 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1734 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1735 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1736 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1737 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1738 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1739 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1740 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1741 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1742 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1743 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1744 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1745 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1746 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1747 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1748 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1749 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1750 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1751 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1752 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1753 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1754 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1755 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1756 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1757 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1758 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1759 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1760 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1761 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1762 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1763 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1764 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1765 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1766 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1767 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1768 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1769 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1770 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1771 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1772 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1773 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1774 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1775 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1776 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1777 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1779 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1780 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1782 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1783 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1784 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1786 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1788 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1789 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1790 }; 1791 1792 /* 1793 * Interface history: 1794 * 1795 * 1.1: Original. 1796 * 1.2: Add Power Management 1797 * 1.3: Add vblank support 1798 * 1.4: Fix cmdbuffer path, add heap destroy 1799 * 1.5: Add vblank pipe configuration 1800 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1801 * - Support vertical blank on secondary display pipe 1802 */ 1803 #define DRIVER_MAJOR 1 1804 #define DRIVER_MINOR 6 1805 #define DRIVER_PATCHLEVEL 0 1806 1807 static const struct drm_driver i915_drm_driver = { 1808 /* Don't use MTRRs here; the Xserver or userspace app should 1809 * deal with them for Intel hardware. 1810 */ 1811 .driver_features = 1812 DRIVER_GEM | 1813 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1814 DRIVER_SYNCOBJ_TIMELINE, 1815 .release = i915_driver_release, 1816 .open = i915_driver_open, 1817 .lastclose = i915_driver_lastclose, 1818 .postclose = i915_driver_postclose, 1819 .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), 1820 1821 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1822 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1823 .gem_prime_import = i915_gem_prime_import, 1824 1825 .dumb_create = i915_gem_dumb_create, 1826 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1827 1828 .ioctls = i915_ioctls, 1829 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1830 .fops = &i915_driver_fops, 1831 .name = DRIVER_NAME, 1832 .desc = DRIVER_DESC, 1833 .date = DRIVER_DATE, 1834 .major = DRIVER_MAJOR, 1835 .minor = DRIVER_MINOR, 1836 .patchlevel = DRIVER_PATCHLEVEL, 1837 }; 1838