1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/acpi.h> 31 #include <linux/device.h> 32 #include <linux/module.h> 33 #include <linux/oom.h> 34 #include <linux/pci.h> 35 #include <linux/pm.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/pnp.h> 38 #include <linux/slab.h> 39 #include <linux/string_helpers.h> 40 #include <linux/vga_switcheroo.h> 41 #include <linux/vt.h> 42 43 #include <drm/drm_aperture.h> 44 #include <drm/drm_atomic_helper.h> 45 #include <drm/drm_ioctl.h> 46 #include <drm/drm_managed.h> 47 #include <drm/drm_probe_helper.h> 48 49 #include "display/intel_acpi.h" 50 #include "display/intel_bw.h" 51 #include "display/intel_cdclk.h" 52 #include "display/intel_display_types.h" 53 #include "display/intel_dmc.h" 54 #include "display/intel_dp.h" 55 #include "display/intel_dpt.h" 56 #include "display/intel_fbdev.h" 57 #include "display/intel_hotplug.h" 58 #include "display/intel_overlay.h" 59 #include "display/intel_pch_refclk.h" 60 #include "display/intel_pipe_crc.h" 61 #include "display/intel_pps.h" 62 #include "display/intel_sprite.h" 63 #include "display/intel_vga.h" 64 65 #include "gem/i915_gem_context.h" 66 #include "gem/i915_gem_create.h" 67 #include "gem/i915_gem_dmabuf.h" 68 #include "gem/i915_gem_ioctls.h" 69 #include "gem/i915_gem_mman.h" 70 #include "gem/i915_gem_pm.h" 71 #include "gt/intel_gt.h" 72 #include "gt/intel_gt_pm.h" 73 #include "gt/intel_rc6.h" 74 75 #include "pxp/intel_pxp_pm.h" 76 77 #include "i915_file_private.h" 78 #include "i915_debugfs.h" 79 #include "i915_driver.h" 80 #include "i915_drm_client.h" 81 #include "i915_drv.h" 82 #include "i915_getparam.h" 83 #include "i915_ioc32.h" 84 #include "i915_ioctl.h" 85 #include "i915_irq.h" 86 #include "i915_memcpy.h" 87 #include "i915_perf.h" 88 #include "i915_query.h" 89 #include "i915_suspend.h" 90 #include "i915_switcheroo.h" 91 #include "i915_sysfs.h" 92 #include "i915_utils.h" 93 #include "i915_vgpu.h" 94 #include "intel_dram.h" 95 #include "intel_gvt.h" 96 #include "intel_memory_region.h" 97 #include "intel_pci_config.h" 98 #include "intel_pcode.h" 99 #include "intel_pm.h" 100 #include "intel_region_ttm.h" 101 #include "vlv_suspend.h" 102 103 static const struct drm_driver i915_drm_driver; 104 105 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) 106 { 107 int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); 108 109 dev_priv->bridge_dev = 110 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); 111 if (!dev_priv->bridge_dev) { 112 drm_err(&dev_priv->drm, "bridge device not found\n"); 113 return -EIO; 114 } 115 return 0; 116 } 117 118 /* Allocate space for the MCH regs if needed, return nonzero on error */ 119 static int 120 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) 121 { 122 int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 123 u32 temp_lo, temp_hi = 0; 124 u64 mchbar_addr; 125 int ret; 126 127 if (GRAPHICS_VER(dev_priv) >= 4) 128 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 129 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); 130 mchbar_addr = ((u64)temp_hi << 32) | temp_lo; 131 132 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 133 #ifdef CONFIG_PNP 134 if (mchbar_addr && 135 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) 136 return 0; 137 #endif 138 139 /* Get some space for it */ 140 dev_priv->mch_res.name = "i915 MCHBAR"; 141 dev_priv->mch_res.flags = IORESOURCE_MEM; 142 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, 143 &dev_priv->mch_res, 144 MCHBAR_SIZE, MCHBAR_SIZE, 145 PCIBIOS_MIN_MEM, 146 0, pcibios_align_resource, 147 dev_priv->bridge_dev); 148 if (ret) { 149 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret); 150 dev_priv->mch_res.start = 0; 151 return ret; 152 } 153 154 if (GRAPHICS_VER(dev_priv) >= 4) 155 pci_write_config_dword(dev_priv->bridge_dev, reg + 4, 156 upper_32_bits(dev_priv->mch_res.start)); 157 158 pci_write_config_dword(dev_priv->bridge_dev, reg, 159 lower_32_bits(dev_priv->mch_res.start)); 160 return 0; 161 } 162 163 /* Setup MCHBAR if possible, return true if we should disable it again */ 164 static void 165 intel_setup_mchbar(struct drm_i915_private *dev_priv) 166 { 167 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 168 u32 temp; 169 bool enabled; 170 171 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 172 return; 173 174 dev_priv->mchbar_need_disable = false; 175 176 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 177 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp); 178 enabled = !!(temp & DEVEN_MCHBAR_EN); 179 } else { 180 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 181 enabled = temp & 1; 182 } 183 184 /* If it's already enabled, don't have to do anything */ 185 if (enabled) 186 return; 187 188 if (intel_alloc_mchbar_resource(dev_priv)) 189 return; 190 191 dev_priv->mchbar_need_disable = true; 192 193 /* Space is allocated or reserved, so enable it. */ 194 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 195 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 196 temp | DEVEN_MCHBAR_EN); 197 } else { 198 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); 199 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); 200 } 201 } 202 203 static void 204 intel_teardown_mchbar(struct drm_i915_private *dev_priv) 205 { 206 int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; 207 208 if (dev_priv->mchbar_need_disable) { 209 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 210 u32 deven_val; 211 212 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, 213 &deven_val); 214 deven_val &= ~DEVEN_MCHBAR_EN; 215 pci_write_config_dword(dev_priv->bridge_dev, DEVEN, 216 deven_val); 217 } else { 218 u32 mchbar_val; 219 220 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, 221 &mchbar_val); 222 mchbar_val &= ~1; 223 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, 224 mchbar_val); 225 } 226 } 227 228 if (dev_priv->mch_res.start) 229 release_resource(&dev_priv->mch_res); 230 } 231 232 static int i915_workqueues_init(struct drm_i915_private *dev_priv) 233 { 234 /* 235 * The i915 workqueue is primarily used for batched retirement of 236 * requests (and thus managing bo) once the task has been completed 237 * by the GPU. i915_retire_requests() is called directly when we 238 * need high-priority retirement, such as waiting for an explicit 239 * bo. 240 * 241 * It is also used for periodic low-priority events, such as 242 * idle-timers and recording error state. 243 * 244 * All tasks on the workqueue are expected to acquire the dev mutex 245 * so there is no point in running more than one instance of the 246 * workqueue at any time. Use an ordered one. 247 */ 248 dev_priv->wq = alloc_ordered_workqueue("i915", 0); 249 if (dev_priv->wq == NULL) 250 goto out_err; 251 252 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); 253 if (dev_priv->hotplug.dp_wq == NULL) 254 goto out_free_wq; 255 256 return 0; 257 258 out_free_wq: 259 destroy_workqueue(dev_priv->wq); 260 out_err: 261 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n"); 262 263 return -ENOMEM; 264 } 265 266 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv) 267 { 268 destroy_workqueue(dev_priv->hotplug.dp_wq); 269 destroy_workqueue(dev_priv->wq); 270 } 271 272 /* 273 * We don't keep the workarounds for pre-production hardware, so we expect our 274 * driver to fail on these machines in one way or another. A little warning on 275 * dmesg may help both the user and the bug triagers. 276 * 277 * Our policy for removing pre-production workarounds is to keep the 278 * current gen workarounds as a guide to the bring-up of the next gen 279 * (workarounds have a habit of persisting!). Anything older than that 280 * should be removed along with the complications they introduce. 281 */ 282 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) 283 { 284 bool pre = false; 285 286 pre |= IS_HSW_EARLY_SDV(dev_priv); 287 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; 288 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; 289 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; 290 pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3; 291 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; 292 293 if (pre) { 294 drm_err(&dev_priv->drm, "This is a pre-production stepping. " 295 "It may not be fully functional.\n"); 296 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 297 } 298 } 299 300 static void sanitize_gpu(struct drm_i915_private *i915) 301 { 302 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) 303 __intel_gt_reset(to_gt(i915), ALL_ENGINES); 304 } 305 306 /** 307 * i915_driver_early_probe - setup state not requiring device access 308 * @dev_priv: device private 309 * 310 * Initialize everything that is a "SW-only" state, that is state not 311 * requiring accessing the device or exposing the driver via kernel internal 312 * or userspace interfaces. Example steps belonging here: lock initialization, 313 * system memory allocation, setting up device specific attributes and 314 * function hooks not requiring accessing the device. 315 */ 316 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 317 { 318 int ret = 0; 319 320 if (i915_inject_probe_failure(dev_priv)) 321 return -ENODEV; 322 323 intel_device_info_subplatform_init(dev_priv); 324 intel_step_init(dev_priv); 325 326 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); 327 328 spin_lock_init(&dev_priv->irq_lock); 329 spin_lock_init(&dev_priv->gpu_error.lock); 330 mutex_init(&dev_priv->backlight_lock); 331 332 mutex_init(&dev_priv->sb_lock); 333 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 334 335 mutex_init(&dev_priv->audio.mutex); 336 mutex_init(&dev_priv->wm.wm_mutex); 337 mutex_init(&dev_priv->pps_mutex); 338 mutex_init(&dev_priv->hdcp_comp_mutex); 339 340 i915_memcpy_init_early(dev_priv); 341 intel_runtime_pm_init_early(&dev_priv->runtime_pm); 342 343 ret = i915_workqueues_init(dev_priv); 344 if (ret < 0) 345 return ret; 346 347 ret = vlv_suspend_init(dev_priv); 348 if (ret < 0) 349 goto err_workqueues; 350 351 ret = intel_region_ttm_device_init(dev_priv); 352 if (ret) 353 goto err_ttm; 354 355 intel_wopcm_init_early(&dev_priv->wopcm); 356 357 intel_root_gt_init_early(dev_priv); 358 359 i915_drm_clients_init(&dev_priv->clients, dev_priv); 360 361 i915_gem_init_early(dev_priv); 362 363 /* This must be called before any calls to HAS_PCH_* */ 364 intel_detect_pch(dev_priv); 365 366 intel_pm_setup(dev_priv); 367 ret = intel_power_domains_init(dev_priv); 368 if (ret < 0) 369 goto err_gem; 370 intel_irq_init(dev_priv); 371 intel_init_display_hooks(dev_priv); 372 intel_init_clock_gating_hooks(dev_priv); 373 374 intel_detect_preproduction_hw(dev_priv); 375 376 return 0; 377 378 err_gem: 379 i915_gem_cleanup_early(dev_priv); 380 intel_gt_driver_late_release_all(dev_priv); 381 i915_drm_clients_fini(&dev_priv->clients); 382 intel_region_ttm_device_fini(dev_priv); 383 err_ttm: 384 vlv_suspend_cleanup(dev_priv); 385 err_workqueues: 386 i915_workqueues_cleanup(dev_priv); 387 return ret; 388 } 389 390 /** 391 * i915_driver_late_release - cleanup the setup done in 392 * i915_driver_early_probe() 393 * @dev_priv: device private 394 */ 395 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 396 { 397 intel_irq_fini(dev_priv); 398 intel_power_domains_cleanup(dev_priv); 399 i915_gem_cleanup_early(dev_priv); 400 intel_gt_driver_late_release_all(dev_priv); 401 i915_drm_clients_fini(&dev_priv->clients); 402 intel_region_ttm_device_fini(dev_priv); 403 vlv_suspend_cleanup(dev_priv); 404 i915_workqueues_cleanup(dev_priv); 405 406 cpu_latency_qos_remove_request(&dev_priv->sb_qos); 407 mutex_destroy(&dev_priv->sb_lock); 408 409 i915_params_free(&dev_priv->params); 410 } 411 412 /** 413 * i915_driver_mmio_probe - setup device MMIO 414 * @dev_priv: device private 415 * 416 * Setup minimal device state necessary for MMIO accesses later in the 417 * initialization sequence. The setup here should avoid any other device-wide 418 * side effects or exposing the driver via kernel internal or user space 419 * interfaces. 420 */ 421 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 422 { 423 int ret; 424 425 if (i915_inject_probe_failure(dev_priv)) 426 return -ENODEV; 427 428 ret = i915_get_bridge_dev(dev_priv); 429 if (ret < 0) 430 return ret; 431 432 ret = intel_uncore_init_mmio(&dev_priv->uncore); 433 if (ret) 434 return ret; 435 436 /* Try to make sure MCHBAR is enabled before poking at it */ 437 intel_setup_mchbar(dev_priv); 438 intel_device_info_runtime_init(dev_priv); 439 440 ret = intel_gt_init_mmio(to_gt(dev_priv)); 441 if (ret) 442 goto err_uncore; 443 444 /* As early as possible, scrub existing GPU state before clobbering */ 445 sanitize_gpu(dev_priv); 446 447 return 0; 448 449 err_uncore: 450 intel_teardown_mchbar(dev_priv); 451 intel_uncore_fini_mmio(&dev_priv->uncore); 452 pci_dev_put(dev_priv->bridge_dev); 453 454 return ret; 455 } 456 457 /** 458 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() 459 * @dev_priv: device private 460 */ 461 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv) 462 { 463 intel_teardown_mchbar(dev_priv); 464 intel_uncore_fini_mmio(&dev_priv->uncore); 465 pci_dev_put(dev_priv->bridge_dev); 466 } 467 468 static void intel_sanitize_options(struct drm_i915_private *dev_priv) 469 { 470 intel_gvt_sanitize_options(dev_priv); 471 } 472 473 /** 474 * i915_set_dma_info - set all relevant PCI dma info as configured for the 475 * platform 476 * @i915: valid i915 instance 477 * 478 * Set the dma max segment size, device and coherent masks. The dma mask set 479 * needs to occur before i915_ggtt_probe_hw. 480 * 481 * A couple of platforms have special needs. Address them as well. 482 * 483 */ 484 static int i915_set_dma_info(struct drm_i915_private *i915) 485 { 486 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size; 487 int ret; 488 489 GEM_BUG_ON(!mask_size); 490 491 /* 492 * We don't have a max segment size, so set it to the max so sg's 493 * debugging layer doesn't complain 494 */ 495 dma_set_max_seg_size(i915->drm.dev, UINT_MAX); 496 497 ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 498 if (ret) 499 goto mask_err; 500 501 /* overlay on gen2 is broken and can't address above 1G */ 502 if (GRAPHICS_VER(i915) == 2) 503 mask_size = 30; 504 505 /* 506 * 965GM sometimes incorrectly writes to hardware status page (HWS) 507 * using 32bit addressing, overwriting memory if HWS is located 508 * above 4GB. 509 * 510 * The documentation also mentions an issue with undefined 511 * behaviour if any general state is accessed within a page above 4GB, 512 * which also needs to be handled carefully. 513 */ 514 if (IS_I965G(i915) || IS_I965GM(i915)) 515 mask_size = 32; 516 517 ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)); 518 if (ret) 519 goto mask_err; 520 521 return 0; 522 523 mask_err: 524 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret); 525 return ret; 526 } 527 528 /** 529 * i915_driver_hw_probe - setup state requiring device access 530 * @dev_priv: device private 531 * 532 * Setup state that requires accessing the device, but doesn't require 533 * exposing the driver via kernel internal or userspace interfaces. 534 */ 535 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv) 536 { 537 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 538 int ret; 539 540 if (i915_inject_probe_failure(dev_priv)) 541 return -ENODEV; 542 543 if (HAS_PPGTT(dev_priv)) { 544 if (intel_vgpu_active(dev_priv) && 545 !intel_vgpu_has_full_ppgtt(dev_priv)) { 546 i915_report_error(dev_priv, 547 "incompatible vGPU found, support for isolated ppGTT required\n"); 548 return -ENXIO; 549 } 550 } 551 552 if (HAS_EXECLISTS(dev_priv)) { 553 /* 554 * Older GVT emulation depends upon intercepting CSB mmio, 555 * which we no longer use, preferring to use the HWSP cache 556 * instead. 557 */ 558 if (intel_vgpu_active(dev_priv) && 559 !intel_vgpu_has_hwsp_emulation(dev_priv)) { 560 i915_report_error(dev_priv, 561 "old vGPU host found, support for HWSP emulation required\n"); 562 return -ENXIO; 563 } 564 } 565 566 intel_sanitize_options(dev_priv); 567 568 /* needs to be done before ggtt probe */ 569 intel_dram_edram_detect(dev_priv); 570 571 ret = i915_set_dma_info(dev_priv); 572 if (ret) 573 return ret; 574 575 i915_perf_init(dev_priv); 576 577 ret = intel_gt_assign_ggtt(to_gt(dev_priv)); 578 if (ret) 579 goto err_perf; 580 581 ret = i915_ggtt_probe_hw(dev_priv); 582 if (ret) 583 goto err_perf; 584 585 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); 586 if (ret) 587 goto err_ggtt; 588 589 ret = i915_ggtt_init_hw(dev_priv); 590 if (ret) 591 goto err_ggtt; 592 593 ret = intel_memory_regions_hw_probe(dev_priv); 594 if (ret) 595 goto err_ggtt; 596 597 ret = intel_gt_tiles_init(dev_priv); 598 if (ret) 599 goto err_mem_regions; 600 601 ret = i915_ggtt_enable_hw(dev_priv); 602 if (ret) { 603 drm_err(&dev_priv->drm, "failed to enable GGTT\n"); 604 goto err_mem_regions; 605 } 606 607 pci_set_master(pdev); 608 609 /* On the 945G/GM, the chipset reports the MSI capability on the 610 * integrated graphics even though the support isn't actually there 611 * according to the published specs. It doesn't appear to function 612 * correctly in testing on 945G. 613 * This may be a side effect of MSI having been made available for PEG 614 * and the registers being closely associated. 615 * 616 * According to chipset errata, on the 965GM, MSI interrupts may 617 * be lost or delayed, and was defeatured. MSI interrupts seem to 618 * get lost on g4x as well, and interrupt delivery seems to stay 619 * properly dead afterwards. So we'll just disable them for all 620 * pre-gen5 chipsets. 621 * 622 * dp aux and gmbus irq on gen4 seems to be able to generate legacy 623 * interrupts even when in MSI mode. This results in spurious 624 * interrupt warnings if the legacy irq no. is shared with another 625 * device. The kernel then disables that interrupt source and so 626 * prevents the other device from working properly. 627 */ 628 if (GRAPHICS_VER(dev_priv) >= 5) { 629 if (pci_enable_msi(pdev) < 0) 630 drm_dbg(&dev_priv->drm, "can't enable MSI"); 631 } 632 633 ret = intel_gvt_init(dev_priv); 634 if (ret) 635 goto err_msi; 636 637 intel_opregion_setup(dev_priv); 638 639 ret = intel_pcode_init(dev_priv); 640 if (ret) 641 goto err_msi; 642 643 /* 644 * Fill the dram structure to get the system dram info. This will be 645 * used for memory latency calculation. 646 */ 647 intel_dram_detect(dev_priv); 648 649 intel_bw_init_hw(dev_priv); 650 651 return 0; 652 653 err_msi: 654 if (pdev->msi_enabled) 655 pci_disable_msi(pdev); 656 err_mem_regions: 657 intel_memory_regions_driver_release(dev_priv); 658 err_ggtt: 659 i915_ggtt_driver_release(dev_priv); 660 i915_gem_drain_freed_objects(dev_priv); 661 i915_ggtt_driver_late_release(dev_priv); 662 err_perf: 663 i915_perf_fini(dev_priv); 664 return ret; 665 } 666 667 /** 668 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() 669 * @dev_priv: device private 670 */ 671 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv) 672 { 673 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 674 675 i915_perf_fini(dev_priv); 676 677 if (pdev->msi_enabled) 678 pci_disable_msi(pdev); 679 } 680 681 /** 682 * i915_driver_register - register the driver with the rest of the system 683 * @dev_priv: device private 684 * 685 * Perform any steps necessary to make the driver available via kernel 686 * internal or userspace interfaces. 687 */ 688 static void i915_driver_register(struct drm_i915_private *dev_priv) 689 { 690 struct drm_device *dev = &dev_priv->drm; 691 692 i915_gem_driver_register(dev_priv); 693 i915_pmu_register(dev_priv); 694 695 intel_vgpu_register(dev_priv); 696 697 /* Reveal our presence to userspace */ 698 if (drm_dev_register(dev, 0)) { 699 drm_err(&dev_priv->drm, 700 "Failed to register driver for userspace access!\n"); 701 return; 702 } 703 704 i915_debugfs_register(dev_priv); 705 i915_setup_sysfs(dev_priv); 706 707 /* Depends on sysfs having been initialized */ 708 i915_perf_register(dev_priv); 709 710 intel_gt_driver_register(to_gt(dev_priv)); 711 712 intel_display_driver_register(dev_priv); 713 714 intel_power_domains_enable(dev_priv); 715 intel_runtime_pm_enable(&dev_priv->runtime_pm); 716 717 intel_register_dsm_handler(); 718 719 if (i915_switcheroo_register(dev_priv)) 720 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n"); 721 } 722 723 /** 724 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() 725 * @dev_priv: device private 726 */ 727 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 728 { 729 i915_switcheroo_unregister(dev_priv); 730 731 intel_unregister_dsm_handler(); 732 733 intel_runtime_pm_disable(&dev_priv->runtime_pm); 734 intel_power_domains_disable(dev_priv); 735 736 intel_display_driver_unregister(dev_priv); 737 738 intel_gt_driver_unregister(to_gt(dev_priv)); 739 740 i915_perf_unregister(dev_priv); 741 i915_pmu_unregister(dev_priv); 742 743 i915_teardown_sysfs(dev_priv); 744 drm_dev_unplug(&dev_priv->drm); 745 746 i915_gem_driver_unregister(dev_priv); 747 } 748 749 void 750 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p) 751 { 752 drm_printf(p, "iommu: %s\n", 753 str_enabled_disabled(i915_vtd_active(i915))); 754 } 755 756 static void i915_welcome_messages(struct drm_i915_private *dev_priv) 757 { 758 if (drm_debug_enabled(DRM_UT_DRIVER)) { 759 struct drm_printer p = drm_debug_printer("i915 device info:"); 760 761 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", 762 INTEL_DEVID(dev_priv), 763 INTEL_REVID(dev_priv), 764 intel_platform_name(INTEL_INFO(dev_priv)->platform), 765 intel_subplatform(RUNTIME_INFO(dev_priv), 766 INTEL_INFO(dev_priv)->platform), 767 GRAPHICS_VER(dev_priv)); 768 769 intel_device_info_print_static(INTEL_INFO(dev_priv), &p); 770 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p); 771 i915_print_iommu_status(dev_priv, &p); 772 intel_gt_info_print(&to_gt(dev_priv)->info, &p); 773 } 774 775 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)) 776 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n"); 777 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 778 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n"); 779 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 780 drm_info(&dev_priv->drm, 781 "DRM_I915_DEBUG_RUNTIME_PM enabled\n"); 782 } 783 784 static struct drm_i915_private * 785 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) 786 { 787 const struct intel_device_info *match_info = 788 (struct intel_device_info *)ent->driver_data; 789 struct intel_device_info *device_info; 790 struct drm_i915_private *i915; 791 792 i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver, 793 struct drm_i915_private, drm); 794 if (IS_ERR(i915)) 795 return i915; 796 797 pci_set_drvdata(pdev, i915); 798 799 /* Device parameters start as a copy of module parameters. */ 800 i915_params_copy(&i915->params, &i915_modparams); 801 802 /* Setup the write-once "constant" device info */ 803 device_info = mkwrite_device_info(i915); 804 memcpy(device_info, match_info, sizeof(*device_info)); 805 RUNTIME_INFO(i915)->device_id = pdev->device; 806 807 return i915; 808 } 809 810 /** 811 * i915_driver_probe - setup chip and create an initial config 812 * @pdev: PCI device 813 * @ent: matching PCI ID entry 814 * 815 * The driver probe routine has to do several things: 816 * - drive output discovery via intel_modeset_init() 817 * - initialize the memory manager 818 * - allocate initial config memory 819 * - setup the DRM framebuffer with the allocated memory 820 */ 821 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 822 { 823 const struct intel_device_info *match_info = 824 (struct intel_device_info *)ent->driver_data; 825 struct drm_i915_private *i915; 826 int ret; 827 828 i915 = i915_driver_create(pdev, ent); 829 if (IS_ERR(i915)) 830 return PTR_ERR(i915); 831 832 /* Disable nuclear pageflip by default on pre-ILK */ 833 if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5) 834 i915->drm.driver_features &= ~DRIVER_ATOMIC; 835 836 ret = pci_enable_device(pdev); 837 if (ret) 838 goto out_fini; 839 840 ret = i915_driver_early_probe(i915); 841 if (ret < 0) 842 goto out_pci_disable; 843 844 disable_rpm_wakeref_asserts(&i915->runtime_pm); 845 846 intel_vgpu_detect(i915); 847 848 ret = intel_gt_probe_all(i915); 849 if (ret < 0) 850 goto out_runtime_pm_put; 851 852 ret = i915_driver_mmio_probe(i915); 853 if (ret < 0) 854 goto out_tiles_cleanup; 855 856 ret = i915_driver_hw_probe(i915); 857 if (ret < 0) 858 goto out_cleanup_mmio; 859 860 ret = intel_modeset_init_noirq(i915); 861 if (ret < 0) 862 goto out_cleanup_hw; 863 864 ret = intel_irq_install(i915); 865 if (ret) 866 goto out_cleanup_modeset; 867 868 ret = intel_modeset_init_nogem(i915); 869 if (ret) 870 goto out_cleanup_irq; 871 872 ret = i915_gem_init(i915); 873 if (ret) 874 goto out_cleanup_modeset2; 875 876 ret = intel_modeset_init(i915); 877 if (ret) 878 goto out_cleanup_gem; 879 880 i915_driver_register(i915); 881 882 enable_rpm_wakeref_asserts(&i915->runtime_pm); 883 884 i915_welcome_messages(i915); 885 886 i915->do_release = true; 887 888 return 0; 889 890 out_cleanup_gem: 891 i915_gem_suspend(i915); 892 i915_gem_driver_remove(i915); 893 i915_gem_driver_release(i915); 894 out_cleanup_modeset2: 895 /* FIXME clean up the error path */ 896 intel_modeset_driver_remove(i915); 897 intel_irq_uninstall(i915); 898 intel_modeset_driver_remove_noirq(i915); 899 goto out_cleanup_modeset; 900 out_cleanup_irq: 901 intel_irq_uninstall(i915); 902 out_cleanup_modeset: 903 intel_modeset_driver_remove_nogem(i915); 904 out_cleanup_hw: 905 i915_driver_hw_remove(i915); 906 intel_memory_regions_driver_release(i915); 907 i915_ggtt_driver_release(i915); 908 i915_gem_drain_freed_objects(i915); 909 i915_ggtt_driver_late_release(i915); 910 out_cleanup_mmio: 911 i915_driver_mmio_release(i915); 912 out_tiles_cleanup: 913 intel_gt_release_all(i915); 914 out_runtime_pm_put: 915 enable_rpm_wakeref_asserts(&i915->runtime_pm); 916 i915_driver_late_release(i915); 917 out_pci_disable: 918 pci_disable_device(pdev); 919 out_fini: 920 i915_probe_error(i915, "Device initialization failed (%d)\n", ret); 921 return ret; 922 } 923 924 void i915_driver_remove(struct drm_i915_private *i915) 925 { 926 disable_rpm_wakeref_asserts(&i915->runtime_pm); 927 928 i915_driver_unregister(i915); 929 930 /* Flush any external code that still may be under the RCU lock */ 931 synchronize_rcu(); 932 933 i915_gem_suspend(i915); 934 935 intel_gvt_driver_remove(i915); 936 937 intel_modeset_driver_remove(i915); 938 939 intel_irq_uninstall(i915); 940 941 intel_modeset_driver_remove_noirq(i915); 942 943 i915_reset_error_state(i915); 944 i915_gem_driver_remove(i915); 945 946 intel_modeset_driver_remove_nogem(i915); 947 948 i915_driver_hw_remove(i915); 949 950 enable_rpm_wakeref_asserts(&i915->runtime_pm); 951 } 952 953 static void i915_driver_release(struct drm_device *dev) 954 { 955 struct drm_i915_private *dev_priv = to_i915(dev); 956 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 957 958 if (!dev_priv->do_release) 959 return; 960 961 disable_rpm_wakeref_asserts(rpm); 962 963 i915_gem_driver_release(dev_priv); 964 965 intel_memory_regions_driver_release(dev_priv); 966 i915_ggtt_driver_release(dev_priv); 967 i915_gem_drain_freed_objects(dev_priv); 968 i915_ggtt_driver_late_release(dev_priv); 969 970 i915_driver_mmio_release(dev_priv); 971 972 enable_rpm_wakeref_asserts(rpm); 973 intel_runtime_pm_driver_release(rpm); 974 975 i915_driver_late_release(dev_priv); 976 } 977 978 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) 979 { 980 struct drm_i915_private *i915 = to_i915(dev); 981 int ret; 982 983 ret = i915_gem_open(i915, file); 984 if (ret) 985 return ret; 986 987 return 0; 988 } 989 990 /** 991 * i915_driver_lastclose - clean up after all DRM clients have exited 992 * @dev: DRM device 993 * 994 * Take care of cleaning up after all DRM clients have exited. In the 995 * mode setting case, we want to restore the kernel's initial mode (just 996 * in case the last client left us in a bad state). 997 * 998 * Additionally, in the non-mode setting case, we'll tear down the GTT 999 * and DMA structures, since the kernel won't be using them, and clea 1000 * up any GEM state. 1001 */ 1002 static void i915_driver_lastclose(struct drm_device *dev) 1003 { 1004 struct drm_i915_private *i915 = to_i915(dev); 1005 1006 intel_fbdev_restore_mode(dev); 1007 1008 if (HAS_DISPLAY(i915)) 1009 vga_switcheroo_process_delayed_switch(); 1010 } 1011 1012 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 1013 { 1014 struct drm_i915_file_private *file_priv = file->driver_priv; 1015 1016 i915_gem_context_close(file); 1017 i915_drm_client_put(file_priv->client); 1018 1019 kfree_rcu(file_priv, rcu); 1020 1021 /* Catch up with all the deferred frees from "this" client */ 1022 i915_gem_flush_free_objects(to_i915(dev)); 1023 } 1024 1025 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 1026 { 1027 struct drm_device *dev = &dev_priv->drm; 1028 struct intel_encoder *encoder; 1029 1030 if (!HAS_DISPLAY(dev_priv)) 1031 return; 1032 1033 drm_modeset_lock_all(dev); 1034 for_each_intel_encoder(dev, encoder) 1035 if (encoder->suspend) 1036 encoder->suspend(encoder); 1037 drm_modeset_unlock_all(dev); 1038 } 1039 1040 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv) 1041 { 1042 struct drm_device *dev = &dev_priv->drm; 1043 struct intel_encoder *encoder; 1044 1045 if (!HAS_DISPLAY(dev_priv)) 1046 return; 1047 1048 drm_modeset_lock_all(dev); 1049 for_each_intel_encoder(dev, encoder) 1050 if (encoder->shutdown) 1051 encoder->shutdown(encoder); 1052 drm_modeset_unlock_all(dev); 1053 } 1054 1055 void i915_driver_shutdown(struct drm_i915_private *i915) 1056 { 1057 disable_rpm_wakeref_asserts(&i915->runtime_pm); 1058 intel_runtime_pm_disable(&i915->runtime_pm); 1059 intel_power_domains_disable(i915); 1060 1061 i915_gem_suspend(i915); 1062 1063 if (HAS_DISPLAY(i915)) { 1064 drm_kms_helper_poll_disable(&i915->drm); 1065 1066 drm_atomic_helper_shutdown(&i915->drm); 1067 } 1068 1069 intel_dp_mst_suspend(i915); 1070 1071 intel_runtime_pm_disable_interrupts(i915); 1072 intel_hpd_cancel_work(i915); 1073 1074 intel_suspend_encoders(i915); 1075 intel_shutdown_encoders(i915); 1076 1077 intel_dmc_ucode_suspend(i915); 1078 1079 /* 1080 * The only requirement is to reboot with display DC states disabled, 1081 * for now leaving all display power wells in the INIT power domain 1082 * enabled. 1083 * 1084 * TODO: 1085 * - unify the pci_driver::shutdown sequence here with the 1086 * pci_driver.driver.pm.poweroff,poweroff_late sequence. 1087 * - unify the driver remove and system/runtime suspend sequences with 1088 * the above unified shutdown/poweroff sequence. 1089 */ 1090 intel_power_domains_driver_remove(i915); 1091 enable_rpm_wakeref_asserts(&i915->runtime_pm); 1092 1093 intel_runtime_pm_driver_release(&i915->runtime_pm); 1094 } 1095 1096 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 1097 { 1098 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 1099 if (acpi_target_system_state() < ACPI_STATE_S3) 1100 return true; 1101 #endif 1102 return false; 1103 } 1104 1105 static int i915_drm_prepare(struct drm_device *dev) 1106 { 1107 struct drm_i915_private *i915 = to_i915(dev); 1108 1109 /* 1110 * NB intel_display_suspend() may issue new requests after we've 1111 * ostensibly marked the GPU as ready-to-sleep here. We need to 1112 * split out that work and pull it forward so that after point, 1113 * the GPU is not woken again. 1114 */ 1115 return i915_gem_backup_suspend(i915); 1116 } 1117 1118 static int i915_drm_suspend(struct drm_device *dev) 1119 { 1120 struct drm_i915_private *dev_priv = to_i915(dev); 1121 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1122 pci_power_t opregion_target_state; 1123 1124 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1125 1126 /* We do a lot of poking in a lot of registers, make sure they work 1127 * properly. */ 1128 intel_power_domains_disable(dev_priv); 1129 if (HAS_DISPLAY(dev_priv)) 1130 drm_kms_helper_poll_disable(dev); 1131 1132 pci_save_state(pdev); 1133 1134 intel_display_suspend(dev); 1135 1136 intel_dp_mst_suspend(dev_priv); 1137 1138 intel_runtime_pm_disable_interrupts(dev_priv); 1139 intel_hpd_cancel_work(dev_priv); 1140 1141 intel_suspend_encoders(dev_priv); 1142 1143 intel_suspend_hw(dev_priv); 1144 1145 /* Must be called before GGTT is suspended. */ 1146 intel_dpt_suspend(dev_priv); 1147 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1148 1149 i915_save_display(dev_priv); 1150 1151 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1152 intel_opregion_suspend(dev_priv, opregion_target_state); 1153 1154 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1155 1156 dev_priv->suspend_count++; 1157 1158 intel_dmc_ucode_suspend(dev_priv); 1159 1160 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1161 1162 return 0; 1163 } 1164 1165 static enum i915_drm_suspend_mode 1166 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate) 1167 { 1168 if (hibernate) 1169 return I915_DRM_SUSPEND_HIBERNATE; 1170 1171 if (suspend_to_idle(dev_priv)) 1172 return I915_DRM_SUSPEND_IDLE; 1173 1174 return I915_DRM_SUSPEND_MEM; 1175 } 1176 1177 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1178 { 1179 struct drm_i915_private *dev_priv = to_i915(dev); 1180 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1181 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1182 int ret; 1183 1184 disable_rpm_wakeref_asserts(rpm); 1185 1186 i915_gem_suspend_late(dev_priv); 1187 1188 intel_uncore_suspend(&dev_priv->uncore); 1189 1190 intel_power_domains_suspend(dev_priv, 1191 get_suspend_mode(dev_priv, hibernation)); 1192 1193 intel_display_power_suspend_late(dev_priv); 1194 1195 ret = vlv_suspend_complete(dev_priv); 1196 if (ret) { 1197 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1198 intel_power_domains_resume(dev_priv); 1199 1200 goto out; 1201 } 1202 1203 /* 1204 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1205 * This should be totally removed when we handle the pci states properly 1206 * on runtime PM and on s2idle cases. 1207 */ 1208 if (suspend_to_idle(dev_priv)) 1209 pci_d3cold_disable(pdev); 1210 1211 pci_disable_device(pdev); 1212 /* 1213 * During hibernation on some platforms the BIOS may try to access 1214 * the device even though it's already in D3 and hang the machine. So 1215 * leave the device in D0 on those platforms and hope the BIOS will 1216 * power down the device properly. The issue was seen on multiple old 1217 * GENs with different BIOS vendors, so having an explicit blacklist 1218 * is inpractical; apply the workaround on everything pre GEN6. The 1219 * platforms where the issue was seen: 1220 * Lenovo Thinkpad X301, X61s, X60, T60, X41 1221 * Fujitsu FSC S7110 1222 * Acer Aspire 1830T 1223 */ 1224 if (!(hibernation && GRAPHICS_VER(dev_priv) < 6)) 1225 pci_set_power_state(pdev, PCI_D3hot); 1226 1227 out: 1228 enable_rpm_wakeref_asserts(rpm); 1229 if (!dev_priv->uncore.user_forcewake_count) 1230 intel_runtime_pm_driver_release(rpm); 1231 1232 return ret; 1233 } 1234 1235 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915, 1236 pm_message_t state) 1237 { 1238 int error; 1239 1240 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND && 1241 state.event != PM_EVENT_FREEZE)) 1242 return -EINVAL; 1243 1244 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1245 return 0; 1246 1247 error = i915_drm_suspend(&i915->drm); 1248 if (error) 1249 return error; 1250 1251 return i915_drm_suspend_late(&i915->drm, false); 1252 } 1253 1254 static int i915_drm_resume(struct drm_device *dev) 1255 { 1256 struct drm_i915_private *dev_priv = to_i915(dev); 1257 int ret; 1258 1259 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1260 1261 ret = intel_pcode_init(dev_priv); 1262 if (ret) 1263 return ret; 1264 1265 sanitize_gpu(dev_priv); 1266 1267 ret = i915_ggtt_enable_hw(dev_priv); 1268 if (ret) 1269 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n"); 1270 1271 i915_ggtt_resume(to_gt(dev_priv)->ggtt); 1272 /* Must be called after GGTT is resumed. */ 1273 intel_dpt_resume(dev_priv); 1274 1275 intel_dmc_ucode_resume(dev_priv); 1276 1277 i915_restore_display(dev_priv); 1278 intel_pps_unlock_regs_wa(dev_priv); 1279 1280 intel_init_pch_refclk(dev_priv); 1281 1282 /* 1283 * Interrupts have to be enabled before any batches are run. If not the 1284 * GPU will hang. i915_gem_init_hw() will initiate batches to 1285 * update/restore the context. 1286 * 1287 * drm_mode_config_reset() needs AUX interrupts. 1288 * 1289 * Modeset enabling in intel_modeset_init_hw() also needs working 1290 * interrupts. 1291 */ 1292 intel_runtime_pm_enable_interrupts(dev_priv); 1293 1294 if (HAS_DISPLAY(dev_priv)) 1295 drm_mode_config_reset(dev); 1296 1297 i915_gem_resume(dev_priv); 1298 1299 intel_modeset_init_hw(dev_priv); 1300 intel_init_clock_gating(dev_priv); 1301 intel_hpd_init(dev_priv); 1302 1303 /* MST sideband requires HPD interrupts enabled */ 1304 intel_dp_mst_resume(dev_priv); 1305 intel_display_resume(dev); 1306 1307 intel_hpd_poll_disable(dev_priv); 1308 if (HAS_DISPLAY(dev_priv)) 1309 drm_kms_helper_poll_enable(dev); 1310 1311 intel_opregion_resume(dev_priv); 1312 1313 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1314 1315 intel_power_domains_enable(dev_priv); 1316 1317 intel_gvt_resume(dev_priv); 1318 1319 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1320 1321 return 0; 1322 } 1323 1324 static int i915_drm_resume_early(struct drm_device *dev) 1325 { 1326 struct drm_i915_private *dev_priv = to_i915(dev); 1327 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1328 int ret; 1329 1330 /* 1331 * We have a resume ordering issue with the snd-hda driver also 1332 * requiring our device to be power up. Due to the lack of a 1333 * parent/child relationship we currently solve this with an early 1334 * resume hook. 1335 * 1336 * FIXME: This should be solved with a special hdmi sink device or 1337 * similar so that power domains can be employed. 1338 */ 1339 1340 /* 1341 * Note that we need to set the power state explicitly, since we 1342 * powered off the device during freeze and the PCI core won't power 1343 * it back up for us during thaw. Powering off the device during 1344 * freeze is not a hard requirement though, and during the 1345 * suspend/resume phases the PCI core makes sure we get here with the 1346 * device powered on. So in case we change our freeze logic and keep 1347 * the device powered we can also remove the following set power state 1348 * call. 1349 */ 1350 ret = pci_set_power_state(pdev, PCI_D0); 1351 if (ret) { 1352 drm_err(&dev_priv->drm, 1353 "failed to set PCI D0 power state (%d)\n", ret); 1354 return ret; 1355 } 1356 1357 /* 1358 * Note that pci_enable_device() first enables any parent bridge 1359 * device and only then sets the power state for this device. The 1360 * bridge enabling is a nop though, since bridge devices are resumed 1361 * first. The order of enabling power and enabling the device is 1362 * imposed by the PCI core as described above, so here we preserve the 1363 * same order for the freeze/thaw phases. 1364 * 1365 * TODO: eventually we should remove pci_disable_device() / 1366 * pci_enable_enable_device() from suspend/resume. Due to how they 1367 * depend on the device enable refcount we can't anyway depend on them 1368 * disabling/enabling the device. 1369 */ 1370 if (pci_enable_device(pdev)) 1371 return -EIO; 1372 1373 pci_set_master(pdev); 1374 1375 pci_d3cold_enable(pdev); 1376 1377 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1378 1379 ret = vlv_resume_prepare(dev_priv, false); 1380 if (ret) 1381 drm_err(&dev_priv->drm, 1382 "Resume prepare failed: %d, continuing anyway\n", ret); 1383 1384 intel_uncore_resume_early(&dev_priv->uncore); 1385 1386 intel_gt_check_and_clear_faults(to_gt(dev_priv)); 1387 1388 intel_display_power_resume_early(dev_priv); 1389 1390 intel_power_domains_resume(dev_priv); 1391 1392 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1393 1394 return ret; 1395 } 1396 1397 int i915_driver_resume_switcheroo(struct drm_i915_private *i915) 1398 { 1399 int ret; 1400 1401 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1402 return 0; 1403 1404 ret = i915_drm_resume_early(&i915->drm); 1405 if (ret) 1406 return ret; 1407 1408 return i915_drm_resume(&i915->drm); 1409 } 1410 1411 static int i915_pm_prepare(struct device *kdev) 1412 { 1413 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1414 1415 if (!i915) { 1416 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1417 return -ENODEV; 1418 } 1419 1420 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1421 return 0; 1422 1423 return i915_drm_prepare(&i915->drm); 1424 } 1425 1426 static int i915_pm_suspend(struct device *kdev) 1427 { 1428 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1429 1430 if (!i915) { 1431 dev_err(kdev, "DRM not initialized, aborting suspend.\n"); 1432 return -ENODEV; 1433 } 1434 1435 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1436 return 0; 1437 1438 return i915_drm_suspend(&i915->drm); 1439 } 1440 1441 static int i915_pm_suspend_late(struct device *kdev) 1442 { 1443 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1444 1445 /* 1446 * We have a suspend ordering issue with the snd-hda driver also 1447 * requiring our device to be power up. Due to the lack of a 1448 * parent/child relationship we currently solve this with an late 1449 * suspend hook. 1450 * 1451 * FIXME: This should be solved with a special hdmi sink device or 1452 * similar so that power domains can be employed. 1453 */ 1454 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1455 return 0; 1456 1457 return i915_drm_suspend_late(&i915->drm, false); 1458 } 1459 1460 static int i915_pm_poweroff_late(struct device *kdev) 1461 { 1462 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1463 1464 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1465 return 0; 1466 1467 return i915_drm_suspend_late(&i915->drm, true); 1468 } 1469 1470 static int i915_pm_resume_early(struct device *kdev) 1471 { 1472 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1473 1474 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1475 return 0; 1476 1477 return i915_drm_resume_early(&i915->drm); 1478 } 1479 1480 static int i915_pm_resume(struct device *kdev) 1481 { 1482 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1483 1484 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) 1485 return 0; 1486 1487 return i915_drm_resume(&i915->drm); 1488 } 1489 1490 /* freeze: before creating the hibernation_image */ 1491 static int i915_pm_freeze(struct device *kdev) 1492 { 1493 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1494 int ret; 1495 1496 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1497 ret = i915_drm_suspend(&i915->drm); 1498 if (ret) 1499 return ret; 1500 } 1501 1502 ret = i915_gem_freeze(i915); 1503 if (ret) 1504 return ret; 1505 1506 return 0; 1507 } 1508 1509 static int i915_pm_freeze_late(struct device *kdev) 1510 { 1511 struct drm_i915_private *i915 = kdev_to_i915(kdev); 1512 int ret; 1513 1514 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { 1515 ret = i915_drm_suspend_late(&i915->drm, true); 1516 if (ret) 1517 return ret; 1518 } 1519 1520 ret = i915_gem_freeze_late(i915); 1521 if (ret) 1522 return ret; 1523 1524 return 0; 1525 } 1526 1527 /* thaw: called after creating the hibernation image, but before turning off. */ 1528 static int i915_pm_thaw_early(struct device *kdev) 1529 { 1530 return i915_pm_resume_early(kdev); 1531 } 1532 1533 static int i915_pm_thaw(struct device *kdev) 1534 { 1535 return i915_pm_resume(kdev); 1536 } 1537 1538 /* restore: called after loading the hibernation image. */ 1539 static int i915_pm_restore_early(struct device *kdev) 1540 { 1541 return i915_pm_resume_early(kdev); 1542 } 1543 1544 static int i915_pm_restore(struct device *kdev) 1545 { 1546 return i915_pm_resume(kdev); 1547 } 1548 1549 static int intel_runtime_suspend(struct device *kdev) 1550 { 1551 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1552 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1553 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1554 int ret; 1555 1556 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1557 return -ENODEV; 1558 1559 drm_dbg_kms(&dev_priv->drm, "Suspending device\n"); 1560 1561 disable_rpm_wakeref_asserts(rpm); 1562 1563 /* 1564 * We are safe here against re-faults, since the fault handler takes 1565 * an RPM reference. 1566 */ 1567 i915_gem_runtime_suspend(dev_priv); 1568 1569 intel_gt_runtime_suspend(to_gt(dev_priv)); 1570 1571 intel_runtime_pm_disable_interrupts(dev_priv); 1572 1573 intel_uncore_suspend(&dev_priv->uncore); 1574 1575 intel_display_power_suspend(dev_priv); 1576 1577 ret = vlv_suspend_complete(dev_priv); 1578 if (ret) { 1579 drm_err(&dev_priv->drm, 1580 "Runtime suspend failed, disabling it (%d)\n", ret); 1581 intel_uncore_runtime_resume(&dev_priv->uncore); 1582 1583 intel_runtime_pm_enable_interrupts(dev_priv); 1584 1585 intel_gt_runtime_resume(to_gt(dev_priv)); 1586 1587 enable_rpm_wakeref_asserts(rpm); 1588 1589 return ret; 1590 } 1591 1592 enable_rpm_wakeref_asserts(rpm); 1593 intel_runtime_pm_driver_release(rpm); 1594 1595 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) 1596 drm_err(&dev_priv->drm, 1597 "Unclaimed access detected prior to suspending\n"); 1598 1599 /* 1600 * FIXME: Temporary hammer to avoid freezing the machine on our DGFX 1601 * This should be totally removed when we handle the pci states properly 1602 * on runtime PM and on s2idle cases. 1603 */ 1604 pci_d3cold_disable(pdev); 1605 rpm->suspended = true; 1606 1607 /* 1608 * FIXME: We really should find a document that references the arguments 1609 * used below! 1610 */ 1611 if (IS_BROADWELL(dev_priv)) { 1612 /* 1613 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1614 * being detected, and the call we do at intel_runtime_resume() 1615 * won't be able to restore them. Since PCI_D3hot matches the 1616 * actual specification and appears to be working, use it. 1617 */ 1618 intel_opregion_notify_adapter(dev_priv, PCI_D3hot); 1619 } else { 1620 /* 1621 * current versions of firmware which depend on this opregion 1622 * notification have repurposed the D1 definition to mean 1623 * "runtime suspended" vs. what you would normally expect (D3) 1624 * to distinguish it from notifications that might be sent via 1625 * the suspend path. 1626 */ 1627 intel_opregion_notify_adapter(dev_priv, PCI_D1); 1628 } 1629 1630 assert_forcewakes_inactive(&dev_priv->uncore); 1631 1632 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1633 intel_hpd_poll_enable(dev_priv); 1634 1635 drm_dbg_kms(&dev_priv->drm, "Device suspended\n"); 1636 return 0; 1637 } 1638 1639 static int intel_runtime_resume(struct device *kdev) 1640 { 1641 struct drm_i915_private *dev_priv = kdev_to_i915(kdev); 1642 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1643 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1644 int ret; 1645 1646 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))) 1647 return -ENODEV; 1648 1649 drm_dbg_kms(&dev_priv->drm, "Resuming device\n"); 1650 1651 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count)); 1652 disable_rpm_wakeref_asserts(rpm); 1653 1654 intel_opregion_notify_adapter(dev_priv, PCI_D0); 1655 rpm->suspended = false; 1656 pci_d3cold_enable(pdev); 1657 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) 1658 drm_dbg(&dev_priv->drm, 1659 "Unclaimed access during suspend, bios?\n"); 1660 1661 intel_display_power_resume(dev_priv); 1662 1663 ret = vlv_resume_prepare(dev_priv, true); 1664 1665 intel_uncore_runtime_resume(&dev_priv->uncore); 1666 1667 intel_runtime_pm_enable_interrupts(dev_priv); 1668 1669 /* 1670 * No point of rolling back things in case of an error, as the best 1671 * we can do is to hope that things will still work (and disable RPM). 1672 */ 1673 intel_gt_runtime_resume(to_gt(dev_priv)); 1674 1675 /* 1676 * On VLV/CHV display interrupts are part of the display 1677 * power well, so hpd is reinitialized from there. For 1678 * everyone else do it here. 1679 */ 1680 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { 1681 intel_hpd_init(dev_priv); 1682 intel_hpd_poll_disable(dev_priv); 1683 } 1684 1685 intel_enable_ipc(dev_priv); 1686 1687 enable_rpm_wakeref_asserts(rpm); 1688 1689 if (ret) 1690 drm_err(&dev_priv->drm, 1691 "Runtime resume failed, disabling it (%d)\n", ret); 1692 else 1693 drm_dbg_kms(&dev_priv->drm, "Device resumed\n"); 1694 1695 return ret; 1696 } 1697 1698 const struct dev_pm_ops i915_pm_ops = { 1699 /* 1700 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1701 * PMSG_RESUME] 1702 */ 1703 .prepare = i915_pm_prepare, 1704 .suspend = i915_pm_suspend, 1705 .suspend_late = i915_pm_suspend_late, 1706 .resume_early = i915_pm_resume_early, 1707 .resume = i915_pm_resume, 1708 1709 /* 1710 * S4 event handlers 1711 * @freeze, @freeze_late : called (1) before creating the 1712 * hibernation image [PMSG_FREEZE] and 1713 * (2) after rebooting, before restoring 1714 * the image [PMSG_QUIESCE] 1715 * @thaw, @thaw_early : called (1) after creating the hibernation 1716 * image, before writing it [PMSG_THAW] 1717 * and (2) after failing to create or 1718 * restore the image [PMSG_RECOVER] 1719 * @poweroff, @poweroff_late: called after writing the hibernation 1720 * image, before rebooting [PMSG_HIBERNATE] 1721 * @restore, @restore_early : called after rebooting and restoring the 1722 * hibernation image [PMSG_RESTORE] 1723 */ 1724 .freeze = i915_pm_freeze, 1725 .freeze_late = i915_pm_freeze_late, 1726 .thaw_early = i915_pm_thaw_early, 1727 .thaw = i915_pm_thaw, 1728 .poweroff = i915_pm_suspend, 1729 .poweroff_late = i915_pm_poweroff_late, 1730 .restore_early = i915_pm_restore_early, 1731 .restore = i915_pm_restore, 1732 1733 /* S0ix (via runtime suspend) event handlers */ 1734 .runtime_suspend = intel_runtime_suspend, 1735 .runtime_resume = intel_runtime_resume, 1736 }; 1737 1738 static const struct file_operations i915_driver_fops = { 1739 .owner = THIS_MODULE, 1740 .open = drm_open, 1741 .release = drm_release_noglobal, 1742 .unlocked_ioctl = drm_ioctl, 1743 .mmap = i915_gem_mmap, 1744 .poll = drm_poll, 1745 .read = drm_read, 1746 .compat_ioctl = i915_ioc32_compat_ioctl, 1747 .llseek = noop_llseek, 1748 #ifdef CONFIG_PROC_FS 1749 .show_fdinfo = i915_drm_client_fdinfo, 1750 #endif 1751 }; 1752 1753 static int 1754 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, 1755 struct drm_file *file) 1756 { 1757 return -ENODEV; 1758 } 1759 1760 static const struct drm_ioctl_desc i915_ioctls[] = { 1761 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1762 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH), 1763 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH), 1764 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH), 1765 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), 1766 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), 1767 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW), 1768 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1769 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), 1770 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), 1771 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1772 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH), 1773 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1774 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1775 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), 1776 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), 1777 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1778 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1779 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH), 1780 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW), 1781 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1782 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), 1783 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW), 1784 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), 1785 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), 1786 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW), 1787 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1788 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1789 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), 1790 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW), 1791 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), 1792 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), 1793 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), 1794 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW), 1795 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), 1796 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), 1797 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW), 1798 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW), 1799 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), 1800 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0), 1801 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), 1802 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER), 1803 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER), 1804 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER), 1805 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER), 1806 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW), 1807 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), 1808 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), 1809 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), 1810 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW), 1811 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), 1812 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), 1813 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), 1814 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), 1815 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW), 1816 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW), 1817 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW), 1818 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW), 1819 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW), 1820 }; 1821 1822 /* 1823 * Interface history: 1824 * 1825 * 1.1: Original. 1826 * 1.2: Add Power Management 1827 * 1.3: Add vblank support 1828 * 1.4: Fix cmdbuffer path, add heap destroy 1829 * 1.5: Add vblank pipe configuration 1830 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 1831 * - Support vertical blank on secondary display pipe 1832 */ 1833 #define DRIVER_MAJOR 1 1834 #define DRIVER_MINOR 6 1835 #define DRIVER_PATCHLEVEL 0 1836 1837 static const struct drm_driver i915_drm_driver = { 1838 /* Don't use MTRRs here; the Xserver or userspace app should 1839 * deal with them for Intel hardware. 1840 */ 1841 .driver_features = 1842 DRIVER_GEM | 1843 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | 1844 DRIVER_SYNCOBJ_TIMELINE, 1845 .release = i915_driver_release, 1846 .open = i915_driver_open, 1847 .lastclose = i915_driver_lastclose, 1848 .postclose = i915_driver_postclose, 1849 1850 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1851 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1852 .gem_prime_import = i915_gem_prime_import, 1853 1854 .dumb_create = i915_gem_dumb_create, 1855 .dumb_map_offset = i915_gem_dumb_mmap_offset, 1856 1857 .ioctls = i915_ioctls, 1858 .num_ioctls = ARRAY_SIZE(i915_ioctls), 1859 .fops = &i915_driver_fops, 1860 .name = DRIVER_NAME, 1861 .desc = DRIVER_DESC, 1862 .date = DRIVER_DATE, 1863 .major = DRIVER_MAJOR, 1864 .minor = DRIVER_MINOR, 1865 .patchlevel = DRIVER_PATCHLEVEL, 1866 }; 1867