1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/drm_debugfs.h> 34 35 #include "gem/i915_gem_context.h" 36 #include "gt/intel_gt.h" 37 #include "gt/intel_gt_buffer_pool.h" 38 #include "gt/intel_gt_clock_utils.h" 39 #include "gt/intel_gt_debugfs.h" 40 #include "gt/intel_gt_pm.h" 41 #include "gt/intel_gt_pm_debugfs.h" 42 #include "gt/intel_gt_regs.h" 43 #include "gt/intel_gt_requests.h" 44 #include "gt/intel_rc6.h" 45 #include "gt/intel_reset.h" 46 #include "gt/intel_rps.h" 47 #include "gt/intel_sseu_debugfs.h" 48 49 #include "i915_debugfs.h" 50 #include "i915_debugfs_params.h" 51 #include "i915_driver.h" 52 #include "i915_irq.h" 53 #include "i915_scheduler.h" 54 #include "intel_mchbar_regs.h" 55 56 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 57 { 58 return to_i915(node->minor->dev); 59 } 60 61 static int i915_capabilities(struct seq_file *m, void *data) 62 { 63 struct drm_i915_private *i915 = node_to_i915(m->private); 64 struct drm_printer p = drm_seq_file_printer(m); 65 66 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 67 68 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 69 i915_print_iommu_status(i915, &p); 70 intel_gt_info_print(&to_gt(i915)->info, &p); 71 intel_driver_caps_print(&i915->caps, &p); 72 73 kernel_param_lock(THIS_MODULE); 74 i915_params_dump(&i915->params, &p); 75 kernel_param_unlock(THIS_MODULE); 76 77 return 0; 78 } 79 80 static char get_tiling_flag(struct drm_i915_gem_object *obj) 81 { 82 switch (i915_gem_object_get_tiling(obj)) { 83 default: 84 case I915_TILING_NONE: return ' '; 85 case I915_TILING_X: return 'X'; 86 case I915_TILING_Y: return 'Y'; 87 } 88 } 89 90 static char get_global_flag(struct drm_i915_gem_object *obj) 91 { 92 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 93 } 94 95 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 96 { 97 return obj->mm.mapping ? 'M' : ' '; 98 } 99 100 static const char * 101 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 102 { 103 size_t x = 0; 104 105 switch (page_sizes) { 106 case 0: 107 return ""; 108 case I915_GTT_PAGE_SIZE_4K: 109 return "4K"; 110 case I915_GTT_PAGE_SIZE_64K: 111 return "64K"; 112 case I915_GTT_PAGE_SIZE_2M: 113 return "2M"; 114 default: 115 if (!buf) 116 return "M"; 117 118 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 119 x += snprintf(buf + x, len - x, "2M, "); 120 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 121 x += snprintf(buf + x, len - x, "64K, "); 122 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 123 x += snprintf(buf + x, len - x, "4K, "); 124 buf[x-2] = '\0'; 125 126 return buf; 127 } 128 } 129 130 static const char *stringify_vma_type(const struct i915_vma *vma) 131 { 132 if (i915_vma_is_ggtt(vma)) 133 return "ggtt"; 134 135 if (i915_vma_is_dpt(vma)) 136 return "dpt"; 137 138 return "ppgtt"; 139 } 140 141 static const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 142 { 143 switch (type) { 144 case I915_CACHE_NONE: return " uncached"; 145 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 146 case I915_CACHE_L3_LLC: return " L3+LLC"; 147 case I915_CACHE_WT: return " WT"; 148 default: return ""; 149 } 150 } 151 152 void 153 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 154 { 155 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 156 struct i915_vma *vma; 157 int pin_count = 0; 158 159 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 160 &obj->base, 161 get_tiling_flag(obj), 162 get_global_flag(obj), 163 get_pin_mapped_flag(obj), 164 obj->base.size / 1024, 165 obj->read_domains, 166 obj->write_domain, 167 i915_cache_level_str(dev_priv, obj->cache_level), 168 obj->mm.dirty ? " dirty" : "", 169 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 170 if (obj->base.name) 171 seq_printf(m, " (name: %d)", obj->base.name); 172 173 spin_lock(&obj->vma.lock); 174 list_for_each_entry(vma, &obj->vma.list, obj_link) { 175 if (!drm_mm_node_allocated(&vma->node)) 176 continue; 177 178 spin_unlock(&obj->vma.lock); 179 180 if (i915_vma_is_pinned(vma)) 181 pin_count++; 182 183 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 184 stringify_vma_type(vma), 185 i915_vma_offset(vma), i915_vma_size(vma), 186 stringify_page_sizes(vma->resource->page_sizes_gtt, 187 NULL, 0)); 188 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 189 switch (vma->gtt_view.type) { 190 case I915_GTT_VIEW_NORMAL: 191 seq_puts(m, ", normal"); 192 break; 193 194 case I915_GTT_VIEW_PARTIAL: 195 seq_printf(m, ", partial [%08llx+%x]", 196 vma->gtt_view.partial.offset << PAGE_SHIFT, 197 vma->gtt_view.partial.size << PAGE_SHIFT); 198 break; 199 200 case I915_GTT_VIEW_ROTATED: 201 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 202 vma->gtt_view.rotated.plane[0].width, 203 vma->gtt_view.rotated.plane[0].height, 204 vma->gtt_view.rotated.plane[0].src_stride, 205 vma->gtt_view.rotated.plane[0].dst_stride, 206 vma->gtt_view.rotated.plane[0].offset, 207 vma->gtt_view.rotated.plane[1].width, 208 vma->gtt_view.rotated.plane[1].height, 209 vma->gtt_view.rotated.plane[1].src_stride, 210 vma->gtt_view.rotated.plane[1].dst_stride, 211 vma->gtt_view.rotated.plane[1].offset); 212 break; 213 214 case I915_GTT_VIEW_REMAPPED: 215 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 216 vma->gtt_view.remapped.plane[0].width, 217 vma->gtt_view.remapped.plane[0].height, 218 vma->gtt_view.remapped.plane[0].src_stride, 219 vma->gtt_view.remapped.plane[0].dst_stride, 220 vma->gtt_view.remapped.plane[0].offset, 221 vma->gtt_view.remapped.plane[1].width, 222 vma->gtt_view.remapped.plane[1].height, 223 vma->gtt_view.remapped.plane[1].src_stride, 224 vma->gtt_view.remapped.plane[1].dst_stride, 225 vma->gtt_view.remapped.plane[1].offset); 226 break; 227 228 default: 229 MISSING_CASE(vma->gtt_view.type); 230 break; 231 } 232 } 233 if (vma->fence) 234 seq_printf(m, " , fence: %d", vma->fence->id); 235 seq_puts(m, ")"); 236 237 spin_lock(&obj->vma.lock); 238 } 239 spin_unlock(&obj->vma.lock); 240 241 seq_printf(m, " (pinned x %d)", pin_count); 242 if (i915_gem_object_is_stolen(obj)) 243 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 244 if (i915_gem_object_is_framebuffer(obj)) 245 seq_printf(m, " (fb)"); 246 } 247 248 static int i915_gem_object_info(struct seq_file *m, void *data) 249 { 250 struct drm_i915_private *i915 = node_to_i915(m->private); 251 struct drm_printer p = drm_seq_file_printer(m); 252 struct intel_memory_region *mr; 253 enum intel_region_id id; 254 255 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 256 i915->mm.shrink_count, 257 atomic_read(&i915->mm.free_count), 258 i915->mm.shrink_memory); 259 for_each_memory_region(mr, i915, id) 260 intel_memory_region_debug(mr, &p); 261 262 return 0; 263 } 264 265 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 266 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 267 size_t count, loff_t *pos) 268 { 269 struct i915_gpu_coredump *error; 270 ssize_t ret; 271 void *buf; 272 273 error = file->private_data; 274 if (!error) 275 return 0; 276 277 /* Bounce buffer required because of kernfs __user API convenience. */ 278 buf = kmalloc(count, GFP_KERNEL); 279 if (!buf) 280 return -ENOMEM; 281 282 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 283 if (ret <= 0) 284 goto out; 285 286 if (!copy_to_user(ubuf, buf, ret)) 287 *pos += ret; 288 else 289 ret = -EFAULT; 290 291 out: 292 kfree(buf); 293 return ret; 294 } 295 296 static int gpu_state_release(struct inode *inode, struct file *file) 297 { 298 i915_gpu_coredump_put(file->private_data); 299 return 0; 300 } 301 302 static int i915_gpu_info_open(struct inode *inode, struct file *file) 303 { 304 struct drm_i915_private *i915 = inode->i_private; 305 struct i915_gpu_coredump *gpu; 306 intel_wakeref_t wakeref; 307 308 gpu = NULL; 309 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 310 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 311 312 if (IS_ERR(gpu)) 313 return PTR_ERR(gpu); 314 315 file->private_data = gpu; 316 return 0; 317 } 318 319 static const struct file_operations i915_gpu_info_fops = { 320 .owner = THIS_MODULE, 321 .open = i915_gpu_info_open, 322 .read = gpu_state_read, 323 .llseek = default_llseek, 324 .release = gpu_state_release, 325 }; 326 327 static ssize_t 328 i915_error_state_write(struct file *filp, 329 const char __user *ubuf, 330 size_t cnt, 331 loff_t *ppos) 332 { 333 struct i915_gpu_coredump *error = filp->private_data; 334 335 if (!error) 336 return 0; 337 338 drm_dbg(&error->i915->drm, "Resetting error state\n"); 339 i915_reset_error_state(error->i915); 340 341 return cnt; 342 } 343 344 static int i915_error_state_open(struct inode *inode, struct file *file) 345 { 346 struct i915_gpu_coredump *error; 347 348 error = i915_first_error_state(inode->i_private); 349 if (IS_ERR(error)) 350 return PTR_ERR(error); 351 352 file->private_data = error; 353 return 0; 354 } 355 356 static const struct file_operations i915_error_state_fops = { 357 .owner = THIS_MODULE, 358 .open = i915_error_state_open, 359 .read = gpu_state_read, 360 .write = i915_error_state_write, 361 .llseek = default_llseek, 362 .release = gpu_state_release, 363 }; 364 #endif 365 366 static int i915_frequency_info(struct seq_file *m, void *unused) 367 { 368 struct drm_i915_private *i915 = node_to_i915(m->private); 369 struct intel_gt *gt = to_gt(i915); 370 struct drm_printer p = drm_seq_file_printer(m); 371 372 intel_gt_pm_frequency_dump(gt, &p); 373 374 return 0; 375 } 376 377 static const char *swizzle_string(unsigned swizzle) 378 { 379 switch (swizzle) { 380 case I915_BIT_6_SWIZZLE_NONE: 381 return "none"; 382 case I915_BIT_6_SWIZZLE_9: 383 return "bit9"; 384 case I915_BIT_6_SWIZZLE_9_10: 385 return "bit9/bit10"; 386 case I915_BIT_6_SWIZZLE_9_11: 387 return "bit9/bit11"; 388 case I915_BIT_6_SWIZZLE_9_10_11: 389 return "bit9/bit10/bit11"; 390 case I915_BIT_6_SWIZZLE_9_17: 391 return "bit9/bit17"; 392 case I915_BIT_6_SWIZZLE_9_10_17: 393 return "bit9/bit10/bit17"; 394 case I915_BIT_6_SWIZZLE_UNKNOWN: 395 return "unknown"; 396 } 397 398 return "bug"; 399 } 400 401 static int i915_swizzle_info(struct seq_file *m, void *data) 402 { 403 struct drm_i915_private *dev_priv = node_to_i915(m->private); 404 struct intel_uncore *uncore = &dev_priv->uncore; 405 intel_wakeref_t wakeref; 406 407 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 408 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 409 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 410 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 411 412 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 413 seq_puts(m, "L-shaped memory detected\n"); 414 415 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 416 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 417 return 0; 418 419 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 420 421 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 422 seq_printf(m, "DDC = 0x%08x\n", 423 intel_uncore_read(uncore, DCC)); 424 seq_printf(m, "DDC2 = 0x%08x\n", 425 intel_uncore_read(uncore, DCC2)); 426 seq_printf(m, "C0DRB3 = 0x%04x\n", 427 intel_uncore_read16(uncore, C0DRB3_BW)); 428 seq_printf(m, "C1DRB3 = 0x%04x\n", 429 intel_uncore_read16(uncore, C1DRB3_BW)); 430 } else if (GRAPHICS_VER(dev_priv) >= 6) { 431 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 432 intel_uncore_read(uncore, MAD_DIMM_C0)); 433 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 434 intel_uncore_read(uncore, MAD_DIMM_C1)); 435 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 436 intel_uncore_read(uncore, MAD_DIMM_C2)); 437 seq_printf(m, "TILECTL = 0x%08x\n", 438 intel_uncore_read(uncore, TILECTL)); 439 if (GRAPHICS_VER(dev_priv) >= 8) 440 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 441 intel_uncore_read(uncore, GAMTARBMODE)); 442 else 443 seq_printf(m, "ARB_MODE = 0x%08x\n", 444 intel_uncore_read(uncore, ARB_MODE)); 445 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 446 intel_uncore_read(uncore, DISP_ARB_CTL)); 447 } 448 449 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 450 451 return 0; 452 } 453 454 static int i915_rps_boost_info(struct seq_file *m, void *data) 455 { 456 struct drm_i915_private *dev_priv = node_to_i915(m->private); 457 struct intel_rps *rps = &to_gt(dev_priv)->rps; 458 459 seq_printf(m, "RPS enabled? %s\n", 460 str_yes_no(intel_rps_is_enabled(rps))); 461 seq_printf(m, "RPS active? %s\n", 462 str_yes_no(intel_rps_is_active(rps))); 463 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 464 seq_printf(m, "Boosts outstanding? %d\n", 465 atomic_read(&rps->num_waiters)); 466 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 467 seq_printf(m, "Frequency requested %d, actual %d\n", 468 intel_gpu_freq(rps, rps->cur_freq), 469 intel_rps_read_actual_frequency(rps)); 470 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 471 intel_gpu_freq(rps, rps->min_freq), 472 intel_gpu_freq(rps, rps->min_freq_softlimit), 473 intel_gpu_freq(rps, rps->max_freq_softlimit), 474 intel_gpu_freq(rps, rps->max_freq)); 475 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 476 intel_gpu_freq(rps, rps->idle_freq), 477 intel_gpu_freq(rps, rps->efficient_freq), 478 intel_gpu_freq(rps, rps->boost_freq)); 479 480 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 481 482 return 0; 483 } 484 485 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 486 { 487 struct drm_i915_private *dev_priv = node_to_i915(m->private); 488 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 489 490 if (!HAS_RUNTIME_PM(dev_priv)) 491 seq_puts(m, "Runtime power management not supported\n"); 492 493 seq_printf(m, "Runtime power status: %s\n", 494 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 495 496 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 497 seq_printf(m, "IRQs disabled: %s\n", 498 str_yes_no(!intel_irqs_enabled(dev_priv))); 499 #ifdef CONFIG_PM 500 seq_printf(m, "Usage count: %d\n", 501 atomic_read(&dev_priv->drm.dev->power.usage_count)); 502 #else 503 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 504 #endif 505 seq_printf(m, "PCI device power state: %s [%d]\n", 506 pci_power_name(pdev->current_state), 507 pdev->current_state); 508 509 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 510 struct drm_printer p = drm_seq_file_printer(m); 511 512 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 513 } 514 515 return 0; 516 } 517 518 static int i915_engine_info(struct seq_file *m, void *unused) 519 { 520 struct drm_i915_private *i915 = node_to_i915(m->private); 521 struct intel_engine_cs *engine; 522 intel_wakeref_t wakeref; 523 struct drm_printer p; 524 525 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 526 527 seq_printf(m, "GT awake? %s [%d], %llums\n", 528 str_yes_no(to_gt(i915)->awake), 529 atomic_read(&to_gt(i915)->wakeref.count), 530 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 531 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 532 to_gt(i915)->clock_frequency, 533 to_gt(i915)->clock_period_ns); 534 535 p = drm_seq_file_printer(m); 536 for_each_uabi_engine(engine, i915) 537 intel_engine_dump(engine, &p, "%s\n", engine->name); 538 539 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 540 541 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 542 543 return 0; 544 } 545 546 static int i915_wa_registers(struct seq_file *m, void *unused) 547 { 548 struct drm_i915_private *i915 = node_to_i915(m->private); 549 struct intel_engine_cs *engine; 550 551 for_each_uabi_engine(engine, i915) { 552 const struct i915_wa_list *wal = &engine->ctx_wa_list; 553 const struct i915_wa *wa; 554 unsigned int count; 555 556 count = wal->count; 557 if (!count) 558 continue; 559 560 seq_printf(m, "%s: Workarounds applied: %u\n", 561 engine->name, count); 562 563 for (wa = wal->list; count--; wa++) 564 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 565 i915_mmio_reg_offset(wa->reg), 566 wa->set, wa->clr); 567 568 seq_printf(m, "\n"); 569 } 570 571 return 0; 572 } 573 574 static int i915_wedged_get(void *data, u64 *val) 575 { 576 struct drm_i915_private *i915 = data; 577 struct intel_gt *gt; 578 unsigned int i; 579 580 *val = 0; 581 582 for_each_gt(gt, i915, i) { 583 int ret; 584 585 ret = intel_gt_debugfs_reset_show(gt, val); 586 if (ret) 587 return ret; 588 589 /* at least one tile should be wedged */ 590 if (*val) 591 break; 592 } 593 594 return 0; 595 } 596 597 static int i915_wedged_set(void *data, u64 val) 598 { 599 struct drm_i915_private *i915 = data; 600 struct intel_gt *gt; 601 unsigned int i; 602 603 for_each_gt(gt, i915, i) 604 intel_gt_debugfs_reset_store(gt, val); 605 606 return 0; 607 } 608 609 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 610 i915_wedged_get, i915_wedged_set, 611 "%llu\n"); 612 613 static int 614 i915_perf_noa_delay_set(void *data, u64 val) 615 { 616 struct drm_i915_private *i915 = data; 617 618 /* 619 * This would lead to infinite waits as we're doing timestamp 620 * difference on the CS with only 32bits. 621 */ 622 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 623 return -EINVAL; 624 625 atomic64_set(&i915->perf.noa_programming_delay, val); 626 return 0; 627 } 628 629 static int 630 i915_perf_noa_delay_get(void *data, u64 *val) 631 { 632 struct drm_i915_private *i915 = data; 633 634 *val = atomic64_read(&i915->perf.noa_programming_delay); 635 return 0; 636 } 637 638 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 639 i915_perf_noa_delay_get, 640 i915_perf_noa_delay_set, 641 "%llu\n"); 642 643 #define DROP_UNBOUND BIT(0) 644 #define DROP_BOUND BIT(1) 645 #define DROP_RETIRE BIT(2) 646 #define DROP_ACTIVE BIT(3) 647 #define DROP_FREED BIT(4) 648 #define DROP_SHRINK_ALL BIT(5) 649 #define DROP_IDLE BIT(6) 650 #define DROP_RESET_ACTIVE BIT(7) 651 #define DROP_RESET_SEQNO BIT(8) 652 #define DROP_RCU BIT(9) 653 #define DROP_ALL (DROP_UNBOUND | \ 654 DROP_BOUND | \ 655 DROP_RETIRE | \ 656 DROP_ACTIVE | \ 657 DROP_FREED | \ 658 DROP_SHRINK_ALL |\ 659 DROP_IDLE | \ 660 DROP_RESET_ACTIVE | \ 661 DROP_RESET_SEQNO | \ 662 DROP_RCU) 663 static int 664 i915_drop_caches_get(void *data, u64 *val) 665 { 666 *val = DROP_ALL; 667 668 return 0; 669 } 670 671 static int 672 gt_drop_caches(struct intel_gt *gt, u64 val) 673 { 674 int ret; 675 676 if (val & DROP_RESET_ACTIVE && 677 wait_for(intel_engines_are_idle(gt), 200)) 678 intel_gt_set_wedged(gt); 679 680 if (val & DROP_RETIRE) 681 intel_gt_retire_requests(gt); 682 683 if (val & (DROP_IDLE | DROP_ACTIVE)) { 684 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 685 if (ret) 686 return ret; 687 } 688 689 if (val & DROP_IDLE) { 690 ret = intel_gt_pm_wait_for_idle(gt); 691 if (ret) 692 return ret; 693 } 694 695 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 696 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 697 698 if (val & DROP_FREED) 699 intel_gt_flush_buffer_pool(gt); 700 701 return 0; 702 } 703 704 static int 705 i915_drop_caches_set(void *data, u64 val) 706 { 707 struct drm_i915_private *i915 = data; 708 unsigned int flags; 709 int ret; 710 711 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 712 val, val & DROP_ALL); 713 714 ret = gt_drop_caches(to_gt(i915), val); 715 if (ret) 716 return ret; 717 718 fs_reclaim_acquire(GFP_KERNEL); 719 flags = memalloc_noreclaim_save(); 720 if (val & DROP_BOUND) 721 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 722 723 if (val & DROP_UNBOUND) 724 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 725 726 if (val & DROP_SHRINK_ALL) 727 i915_gem_shrink_all(i915); 728 memalloc_noreclaim_restore(flags); 729 fs_reclaim_release(GFP_KERNEL); 730 731 if (val & DROP_RCU) 732 rcu_barrier(); 733 734 if (val & DROP_FREED) 735 i915_gem_drain_freed_objects(i915); 736 737 return 0; 738 } 739 740 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 741 i915_drop_caches_get, i915_drop_caches_set, 742 "0x%08llx\n"); 743 744 static int i915_sseu_status(struct seq_file *m, void *unused) 745 { 746 struct drm_i915_private *i915 = node_to_i915(m->private); 747 struct intel_gt *gt = to_gt(i915); 748 749 return intel_sseu_status(m, gt); 750 } 751 752 static int i915_forcewake_open(struct inode *inode, struct file *file) 753 { 754 struct drm_i915_private *i915 = inode->i_private; 755 struct intel_gt *gt; 756 unsigned int i; 757 758 for_each_gt(gt, i915, i) 759 intel_gt_pm_debugfs_forcewake_user_open(gt); 760 761 return 0; 762 } 763 764 static int i915_forcewake_release(struct inode *inode, struct file *file) 765 { 766 struct drm_i915_private *i915 = inode->i_private; 767 struct intel_gt *gt; 768 unsigned int i; 769 770 for_each_gt(gt, i915, i) 771 intel_gt_pm_debugfs_forcewake_user_release(gt); 772 773 return 0; 774 } 775 776 static const struct file_operations i915_forcewake_fops = { 777 .owner = THIS_MODULE, 778 .open = i915_forcewake_open, 779 .release = i915_forcewake_release, 780 }; 781 782 static const struct drm_info_list i915_debugfs_list[] = { 783 {"i915_capabilities", i915_capabilities, 0}, 784 {"i915_gem_objects", i915_gem_object_info, 0}, 785 {"i915_frequency_info", i915_frequency_info, 0}, 786 {"i915_swizzle_info", i915_swizzle_info, 0}, 787 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 788 {"i915_engine_info", i915_engine_info, 0}, 789 {"i915_wa_registers", i915_wa_registers, 0}, 790 {"i915_sseu_status", i915_sseu_status, 0}, 791 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 792 }; 793 794 static const struct i915_debugfs_files { 795 const char *name; 796 const struct file_operations *fops; 797 } i915_debugfs_files[] = { 798 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 799 {"i915_wedged", &i915_wedged_fops}, 800 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 801 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 802 {"i915_error_state", &i915_error_state_fops}, 803 {"i915_gpu_info", &i915_gpu_info_fops}, 804 #endif 805 }; 806 807 void i915_debugfs_register(struct drm_i915_private *dev_priv) 808 { 809 struct drm_minor *minor = dev_priv->drm.primary; 810 int i; 811 812 i915_debugfs_params(dev_priv); 813 814 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 815 to_i915(minor->dev), &i915_forcewake_fops); 816 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 817 debugfs_create_file(i915_debugfs_files[i].name, 818 S_IRUGO | S_IWUSR, 819 minor->debugfs_root, 820 to_i915(minor->dev), 821 i915_debugfs_files[i].fops); 822 } 823 824 drm_debugfs_create_files(i915_debugfs_list, 825 ARRAY_SIZE(i915_debugfs_list), 826 minor->debugfs_root, minor); 827 } 828