1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/circ_buf.h> 31 #include <linux/ctype.h> 32 #include <linux/debugfs.h> 33 #include <linux/slab.h> 34 #include <linux/export.h> 35 #include <linux/list_sort.h> 36 #include <asm/msr-index.h> 37 #include <drm/drmP.h> 38 #include "intel_drv.h" 39 #include "intel_ringbuffer.h" 40 #include <drm/i915_drm.h> 41 #include "i915_drv.h" 42 43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 44 { 45 return to_i915(node->minor->dev); 46 } 47 48 /* As the drm_debugfs_init() routines are called before dev->dev_private is 49 * allocated we need to hook into the minor for release. */ 50 static int 51 drm_add_fake_info_node(struct drm_minor *minor, 52 struct dentry *ent, 53 const void *key) 54 { 55 struct drm_info_node *node; 56 57 node = kmalloc(sizeof(*node), GFP_KERNEL); 58 if (node == NULL) { 59 debugfs_remove(ent); 60 return -ENOMEM; 61 } 62 63 node->minor = minor; 64 node->dent = ent; 65 node->info_ent = (void *)key; 66 67 mutex_lock(&minor->debugfs_lock); 68 list_add(&node->list, &minor->debugfs_list); 69 mutex_unlock(&minor->debugfs_lock); 70 71 return 0; 72 } 73 74 static int i915_capabilities(struct seq_file *m, void *data) 75 { 76 struct drm_i915_private *dev_priv = node_to_i915(m->private); 77 const struct intel_device_info *info = INTEL_INFO(dev_priv); 78 79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); 80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); 81 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 82 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 83 #undef PRINT_FLAG 84 85 return 0; 86 } 87 88 static char get_active_flag(struct drm_i915_gem_object *obj) 89 { 90 return i915_gem_object_is_active(obj) ? '*' : ' '; 91 } 92 93 static char get_pin_flag(struct drm_i915_gem_object *obj) 94 { 95 return obj->pin_display ? 'p' : ' '; 96 } 97 98 static char get_tiling_flag(struct drm_i915_gem_object *obj) 99 { 100 switch (i915_gem_object_get_tiling(obj)) { 101 default: 102 case I915_TILING_NONE: return ' '; 103 case I915_TILING_X: return 'X'; 104 case I915_TILING_Y: return 'Y'; 105 } 106 } 107 108 static char get_global_flag(struct drm_i915_gem_object *obj) 109 { 110 return !list_empty(&obj->userfault_link) ? 'g' : ' '; 111 } 112 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 114 { 115 return obj->mm.mapping ? 'M' : ' '; 116 } 117 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) 119 { 120 u64 size = 0; 121 struct i915_vma *vma; 122 123 list_for_each_entry(vma, &obj->vma_list, obj_link) { 124 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node)) 125 size += vma->node.size; 126 } 127 128 return size; 129 } 130 131 static void 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 133 { 134 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 135 struct intel_engine_cs *engine; 136 struct i915_vma *vma; 137 unsigned int frontbuffer_bits; 138 int pin_count = 0; 139 140 lockdep_assert_held(&obj->base.dev->struct_mutex); 141 142 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", 143 &obj->base, 144 get_active_flag(obj), 145 get_pin_flag(obj), 146 get_tiling_flag(obj), 147 get_global_flag(obj), 148 get_pin_mapped_flag(obj), 149 obj->base.size / 1024, 150 obj->base.read_domains, 151 obj->base.write_domain, 152 i915_cache_level_str(dev_priv, obj->cache_level), 153 obj->mm.dirty ? " dirty" : "", 154 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 155 if (obj->base.name) 156 seq_printf(m, " (name: %d)", obj->base.name); 157 list_for_each_entry(vma, &obj->vma_list, obj_link) { 158 if (i915_vma_is_pinned(vma)) 159 pin_count++; 160 } 161 seq_printf(m, " (pinned x %d)", pin_count); 162 if (obj->pin_display) 163 seq_printf(m, " (display)"); 164 list_for_each_entry(vma, &obj->vma_list, obj_link) { 165 if (!drm_mm_node_allocated(&vma->node)) 166 continue; 167 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", 169 i915_vma_is_ggtt(vma) ? "g" : "pp", 170 vma->node.start, vma->node.size); 171 if (i915_vma_is_ggtt(vma)) 172 seq_printf(m, ", type: %u", vma->ggtt_view.type); 173 if (vma->fence) 174 seq_printf(m, " , fence: %d%s", 175 vma->fence->id, 176 i915_gem_active_isset(&vma->last_fence) ? "*" : ""); 177 seq_puts(m, ")"); 178 } 179 if (obj->stolen) 180 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 181 182 engine = i915_gem_object_last_write_engine(obj); 183 if (engine) 184 seq_printf(m, " (%s)", engine->name); 185 186 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits); 187 if (frontbuffer_bits) 188 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits); 189 } 190 191 static int obj_rank_by_stolen(void *priv, 192 struct list_head *A, struct list_head *B) 193 { 194 struct drm_i915_gem_object *a = 195 container_of(A, struct drm_i915_gem_object, obj_exec_link); 196 struct drm_i915_gem_object *b = 197 container_of(B, struct drm_i915_gem_object, obj_exec_link); 198 199 if (a->stolen->start < b->stolen->start) 200 return -1; 201 if (a->stolen->start > b->stolen->start) 202 return 1; 203 return 0; 204 } 205 206 static int i915_gem_stolen_list_info(struct seq_file *m, void *data) 207 { 208 struct drm_i915_private *dev_priv = node_to_i915(m->private); 209 struct drm_device *dev = &dev_priv->drm; 210 struct drm_i915_gem_object *obj; 211 u64 total_obj_size, total_gtt_size; 212 LIST_HEAD(stolen); 213 int count, ret; 214 215 ret = mutex_lock_interruptible(&dev->struct_mutex); 216 if (ret) 217 return ret; 218 219 total_obj_size = total_gtt_size = count = 0; 220 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { 221 if (obj->stolen == NULL) 222 continue; 223 224 list_add(&obj->obj_exec_link, &stolen); 225 226 total_obj_size += obj->base.size; 227 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 228 count++; 229 } 230 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { 231 if (obj->stolen == NULL) 232 continue; 233 234 list_add(&obj->obj_exec_link, &stolen); 235 236 total_obj_size += obj->base.size; 237 count++; 238 } 239 list_sort(NULL, &stolen, obj_rank_by_stolen); 240 seq_puts(m, "Stolen:\n"); 241 while (!list_empty(&stolen)) { 242 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); 243 seq_puts(m, " "); 244 describe_obj(m, obj); 245 seq_putc(m, '\n'); 246 list_del_init(&obj->obj_exec_link); 247 } 248 mutex_unlock(&dev->struct_mutex); 249 250 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 251 count, total_obj_size, total_gtt_size); 252 return 0; 253 } 254 255 struct file_stats { 256 struct drm_i915_file_private *file_priv; 257 unsigned long count; 258 u64 total, unbound; 259 u64 global, shared; 260 u64 active, inactive; 261 }; 262 263 static int per_file_stats(int id, void *ptr, void *data) 264 { 265 struct drm_i915_gem_object *obj = ptr; 266 struct file_stats *stats = data; 267 struct i915_vma *vma; 268 269 stats->count++; 270 stats->total += obj->base.size; 271 if (!obj->bind_count) 272 stats->unbound += obj->base.size; 273 if (obj->base.name || obj->base.dma_buf) 274 stats->shared += obj->base.size; 275 276 list_for_each_entry(vma, &obj->vma_list, obj_link) { 277 if (!drm_mm_node_allocated(&vma->node)) 278 continue; 279 280 if (i915_vma_is_ggtt(vma)) { 281 stats->global += vma->node.size; 282 } else { 283 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm); 284 285 if (ppgtt->base.file != stats->file_priv) 286 continue; 287 } 288 289 if (i915_vma_is_active(vma)) 290 stats->active += vma->node.size; 291 else 292 stats->inactive += vma->node.size; 293 } 294 295 return 0; 296 } 297 298 #define print_file_stats(m, name, stats) do { \ 299 if (stats.count) \ 300 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ 301 name, \ 302 stats.count, \ 303 stats.total, \ 304 stats.active, \ 305 stats.inactive, \ 306 stats.global, \ 307 stats.shared, \ 308 stats.unbound); \ 309 } while (0) 310 311 static void print_batch_pool_stats(struct seq_file *m, 312 struct drm_i915_private *dev_priv) 313 { 314 struct drm_i915_gem_object *obj; 315 struct file_stats stats; 316 struct intel_engine_cs *engine; 317 enum intel_engine_id id; 318 int j; 319 320 memset(&stats, 0, sizeof(stats)); 321 322 for_each_engine(engine, dev_priv, id) { 323 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { 324 list_for_each_entry(obj, 325 &engine->batch_pool.cache_list[j], 326 batch_pool_link) 327 per_file_stats(0, obj, &stats); 328 } 329 } 330 331 print_file_stats(m, "[k]batch pool", stats); 332 } 333 334 static int per_file_ctx_stats(int id, void *ptr, void *data) 335 { 336 struct i915_gem_context *ctx = ptr; 337 int n; 338 339 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) { 340 if (ctx->engine[n].state) 341 per_file_stats(0, ctx->engine[n].state->obj, data); 342 if (ctx->engine[n].ring) 343 per_file_stats(0, ctx->engine[n].ring->vma->obj, data); 344 } 345 346 return 0; 347 } 348 349 static void print_context_stats(struct seq_file *m, 350 struct drm_i915_private *dev_priv) 351 { 352 struct drm_device *dev = &dev_priv->drm; 353 struct file_stats stats; 354 struct drm_file *file; 355 356 memset(&stats, 0, sizeof(stats)); 357 358 mutex_lock(&dev->struct_mutex); 359 if (dev_priv->kernel_context) 360 per_file_ctx_stats(0, dev_priv->kernel_context, &stats); 361 362 list_for_each_entry(file, &dev->filelist, lhead) { 363 struct drm_i915_file_private *fpriv = file->driver_priv; 364 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats); 365 } 366 mutex_unlock(&dev->struct_mutex); 367 368 print_file_stats(m, "[k]contexts", stats); 369 } 370 371 static int i915_gem_object_info(struct seq_file *m, void *data) 372 { 373 struct drm_i915_private *dev_priv = node_to_i915(m->private); 374 struct drm_device *dev = &dev_priv->drm; 375 struct i915_ggtt *ggtt = &dev_priv->ggtt; 376 u32 count, mapped_count, purgeable_count, dpy_count; 377 u64 size, mapped_size, purgeable_size, dpy_size; 378 struct drm_i915_gem_object *obj; 379 struct drm_file *file; 380 int ret; 381 382 ret = mutex_lock_interruptible(&dev->struct_mutex); 383 if (ret) 384 return ret; 385 386 seq_printf(m, "%u objects, %llu bytes\n", 387 dev_priv->mm.object_count, 388 dev_priv->mm.object_memory); 389 390 size = count = 0; 391 mapped_size = mapped_count = 0; 392 purgeable_size = purgeable_count = 0; 393 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) { 394 size += obj->base.size; 395 ++count; 396 397 if (obj->mm.madv == I915_MADV_DONTNEED) { 398 purgeable_size += obj->base.size; 399 ++purgeable_count; 400 } 401 402 if (obj->mm.mapping) { 403 mapped_count++; 404 mapped_size += obj->base.size; 405 } 406 } 407 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); 408 409 size = count = dpy_size = dpy_count = 0; 410 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { 411 size += obj->base.size; 412 ++count; 413 414 if (obj->pin_display) { 415 dpy_size += obj->base.size; 416 ++dpy_count; 417 } 418 419 if (obj->mm.madv == I915_MADV_DONTNEED) { 420 purgeable_size += obj->base.size; 421 ++purgeable_count; 422 } 423 424 if (obj->mm.mapping) { 425 mapped_count++; 426 mapped_size += obj->base.size; 427 } 428 } 429 seq_printf(m, "%u bound objects, %llu bytes\n", 430 count, size); 431 seq_printf(m, "%u purgeable objects, %llu bytes\n", 432 purgeable_count, purgeable_size); 433 seq_printf(m, "%u mapped objects, %llu bytes\n", 434 mapped_count, mapped_size); 435 seq_printf(m, "%u display objects (pinned), %llu bytes\n", 436 dpy_count, dpy_size); 437 438 seq_printf(m, "%llu [%llu] gtt total\n", 439 ggtt->base.total, ggtt->mappable_end - ggtt->base.start); 440 441 seq_putc(m, '\n'); 442 print_batch_pool_stats(m, dev_priv); 443 mutex_unlock(&dev->struct_mutex); 444 445 mutex_lock(&dev->filelist_mutex); 446 print_context_stats(m, dev_priv); 447 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 448 struct file_stats stats; 449 struct drm_i915_file_private *file_priv = file->driver_priv; 450 struct drm_i915_gem_request *request; 451 struct task_struct *task; 452 453 memset(&stats, 0, sizeof(stats)); 454 stats.file_priv = file->driver_priv; 455 spin_lock(&file->table_lock); 456 idr_for_each(&file->object_idr, per_file_stats, &stats); 457 spin_unlock(&file->table_lock); 458 /* 459 * Although we have a valid reference on file->pid, that does 460 * not guarantee that the task_struct who called get_pid() is 461 * still alive (e.g. get_pid(current) => fork() => exit()). 462 * Therefore, we need to protect this ->comm access using RCU. 463 */ 464 mutex_lock(&dev->struct_mutex); 465 request = list_first_entry_or_null(&file_priv->mm.request_list, 466 struct drm_i915_gem_request, 467 client_list); 468 rcu_read_lock(); 469 task = pid_task(request && request->ctx->pid ? 470 request->ctx->pid : file->pid, 471 PIDTYPE_PID); 472 print_file_stats(m, task ? task->comm : "<unknown>", stats); 473 rcu_read_unlock(); 474 mutex_unlock(&dev->struct_mutex); 475 } 476 mutex_unlock(&dev->filelist_mutex); 477 478 return 0; 479 } 480 481 static int i915_gem_gtt_info(struct seq_file *m, void *data) 482 { 483 struct drm_info_node *node = m->private; 484 struct drm_i915_private *dev_priv = node_to_i915(node); 485 struct drm_device *dev = &dev_priv->drm; 486 bool show_pin_display_only = !!node->info_ent->data; 487 struct drm_i915_gem_object *obj; 488 u64 total_obj_size, total_gtt_size; 489 int count, ret; 490 491 ret = mutex_lock_interruptible(&dev->struct_mutex); 492 if (ret) 493 return ret; 494 495 total_obj_size = total_gtt_size = count = 0; 496 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) { 497 if (show_pin_display_only && !obj->pin_display) 498 continue; 499 500 seq_puts(m, " "); 501 describe_obj(m, obj); 502 seq_putc(m, '\n'); 503 total_obj_size += obj->base.size; 504 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 505 count++; 506 } 507 508 mutex_unlock(&dev->struct_mutex); 509 510 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 511 count, total_obj_size, total_gtt_size); 512 513 return 0; 514 } 515 516 static int i915_gem_pageflip_info(struct seq_file *m, void *data) 517 { 518 struct drm_i915_private *dev_priv = node_to_i915(m->private); 519 struct drm_device *dev = &dev_priv->drm; 520 struct intel_crtc *crtc; 521 int ret; 522 523 ret = mutex_lock_interruptible(&dev->struct_mutex); 524 if (ret) 525 return ret; 526 527 for_each_intel_crtc(dev, crtc) { 528 const char pipe = pipe_name(crtc->pipe); 529 const char plane = plane_name(crtc->plane); 530 struct intel_flip_work *work; 531 532 spin_lock_irq(&dev->event_lock); 533 work = crtc->flip_work; 534 if (work == NULL) { 535 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 536 pipe, plane); 537 } else { 538 u32 pending; 539 u32 addr; 540 541 pending = atomic_read(&work->pending); 542 if (pending) { 543 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n", 544 pipe, plane); 545 } else { 546 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 547 pipe, plane); 548 } 549 if (work->flip_queued_req) { 550 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req); 551 552 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", 553 engine->name, 554 i915_gem_request_get_seqno(work->flip_queued_req), 555 atomic_read(&dev_priv->gt.global_timeline.next_seqno), 556 intel_engine_get_seqno(engine), 557 i915_gem_request_completed(work->flip_queued_req)); 558 } else 559 seq_printf(m, "Flip not associated with any ring\n"); 560 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", 561 work->flip_queued_vblank, 562 work->flip_ready_vblank, 563 intel_crtc_get_vblank_counter(crtc)); 564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 565 566 if (INTEL_GEN(dev_priv) >= 4) 567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); 568 else 569 addr = I915_READ(DSPADDR(crtc->plane)); 570 seq_printf(m, "Current scanout address 0x%08x\n", addr); 571 572 if (work->pending_flip_obj) { 573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); 574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); 575 } 576 } 577 spin_unlock_irq(&dev->event_lock); 578 } 579 580 mutex_unlock(&dev->struct_mutex); 581 582 return 0; 583 } 584 585 static int i915_gem_batch_pool_info(struct seq_file *m, void *data) 586 { 587 struct drm_i915_private *dev_priv = node_to_i915(m->private); 588 struct drm_device *dev = &dev_priv->drm; 589 struct drm_i915_gem_object *obj; 590 struct intel_engine_cs *engine; 591 enum intel_engine_id id; 592 int total = 0; 593 int ret, j; 594 595 ret = mutex_lock_interruptible(&dev->struct_mutex); 596 if (ret) 597 return ret; 598 599 for_each_engine(engine, dev_priv, id) { 600 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) { 601 int count; 602 603 count = 0; 604 list_for_each_entry(obj, 605 &engine->batch_pool.cache_list[j], 606 batch_pool_link) 607 count++; 608 seq_printf(m, "%s cache[%d]: %d objects\n", 609 engine->name, j, count); 610 611 list_for_each_entry(obj, 612 &engine->batch_pool.cache_list[j], 613 batch_pool_link) { 614 seq_puts(m, " "); 615 describe_obj(m, obj); 616 seq_putc(m, '\n'); 617 } 618 619 total += count; 620 } 621 } 622 623 seq_printf(m, "total: %d\n", total); 624 625 mutex_unlock(&dev->struct_mutex); 626 627 return 0; 628 } 629 630 static void print_request(struct seq_file *m, 631 struct drm_i915_gem_request *rq, 632 const char *prefix) 633 { 634 seq_printf(m, "%s%x [%x:%x] @ %d: %s\n", prefix, 635 rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno, 636 jiffies_to_msecs(jiffies - rq->emitted_jiffies), 637 rq->timeline->common->name); 638 } 639 640 static int i915_gem_request_info(struct seq_file *m, void *data) 641 { 642 struct drm_i915_private *dev_priv = node_to_i915(m->private); 643 struct drm_device *dev = &dev_priv->drm; 644 struct drm_i915_gem_request *req; 645 struct intel_engine_cs *engine; 646 enum intel_engine_id id; 647 int ret, any; 648 649 ret = mutex_lock_interruptible(&dev->struct_mutex); 650 if (ret) 651 return ret; 652 653 any = 0; 654 for_each_engine(engine, dev_priv, id) { 655 int count; 656 657 count = 0; 658 list_for_each_entry(req, &engine->timeline->requests, link) 659 count++; 660 if (count == 0) 661 continue; 662 663 seq_printf(m, "%s requests: %d\n", engine->name, count); 664 list_for_each_entry(req, &engine->timeline->requests, link) 665 print_request(m, req, " "); 666 667 any++; 668 } 669 mutex_unlock(&dev->struct_mutex); 670 671 if (any == 0) 672 seq_puts(m, "No requests\n"); 673 674 return 0; 675 } 676 677 static void i915_ring_seqno_info(struct seq_file *m, 678 struct intel_engine_cs *engine) 679 { 680 struct intel_breadcrumbs *b = &engine->breadcrumbs; 681 struct rb_node *rb; 682 683 seq_printf(m, "Current sequence (%s): %x\n", 684 engine->name, intel_engine_get_seqno(engine)); 685 686 spin_lock_irq(&b->lock); 687 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 688 struct intel_wait *w = container_of(rb, typeof(*w), node); 689 690 seq_printf(m, "Waiting (%s): %s [%d] on %x\n", 691 engine->name, w->tsk->comm, w->tsk->pid, w->seqno); 692 } 693 spin_unlock_irq(&b->lock); 694 } 695 696 static int i915_gem_seqno_info(struct seq_file *m, void *data) 697 { 698 struct drm_i915_private *dev_priv = node_to_i915(m->private); 699 struct intel_engine_cs *engine; 700 enum intel_engine_id id; 701 702 for_each_engine(engine, dev_priv, id) 703 i915_ring_seqno_info(m, engine); 704 705 return 0; 706 } 707 708 709 static int i915_interrupt_info(struct seq_file *m, void *data) 710 { 711 struct drm_i915_private *dev_priv = node_to_i915(m->private); 712 struct intel_engine_cs *engine; 713 enum intel_engine_id id; 714 int i, pipe; 715 716 intel_runtime_pm_get(dev_priv); 717 718 if (IS_CHERRYVIEW(dev_priv)) { 719 seq_printf(m, "Master Interrupt Control:\t%08x\n", 720 I915_READ(GEN8_MASTER_IRQ)); 721 722 seq_printf(m, "Display IER:\t%08x\n", 723 I915_READ(VLV_IER)); 724 seq_printf(m, "Display IIR:\t%08x\n", 725 I915_READ(VLV_IIR)); 726 seq_printf(m, "Display IIR_RW:\t%08x\n", 727 I915_READ(VLV_IIR_RW)); 728 seq_printf(m, "Display IMR:\t%08x\n", 729 I915_READ(VLV_IMR)); 730 for_each_pipe(dev_priv, pipe) { 731 enum intel_display_power_domain power_domain; 732 733 power_domain = POWER_DOMAIN_PIPE(pipe); 734 if (!intel_display_power_get_if_enabled(dev_priv, 735 power_domain)) { 736 seq_printf(m, "Pipe %c power disabled\n", 737 pipe_name(pipe)); 738 continue; 739 } 740 741 seq_printf(m, "Pipe %c stat:\t%08x\n", 742 pipe_name(pipe), 743 I915_READ(PIPESTAT(pipe))); 744 745 intel_display_power_put(dev_priv, power_domain); 746 } 747 748 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 749 seq_printf(m, "Port hotplug:\t%08x\n", 750 I915_READ(PORT_HOTPLUG_EN)); 751 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 752 I915_READ(VLV_DPFLIPSTAT)); 753 seq_printf(m, "DPINVGTT:\t%08x\n", 754 I915_READ(DPINVGTT)); 755 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 756 757 for (i = 0; i < 4; i++) { 758 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 759 i, I915_READ(GEN8_GT_IMR(i))); 760 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 761 i, I915_READ(GEN8_GT_IIR(i))); 762 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 763 i, I915_READ(GEN8_GT_IER(i))); 764 } 765 766 seq_printf(m, "PCU interrupt mask:\t%08x\n", 767 I915_READ(GEN8_PCU_IMR)); 768 seq_printf(m, "PCU interrupt identity:\t%08x\n", 769 I915_READ(GEN8_PCU_IIR)); 770 seq_printf(m, "PCU interrupt enable:\t%08x\n", 771 I915_READ(GEN8_PCU_IER)); 772 } else if (INTEL_GEN(dev_priv) >= 8) { 773 seq_printf(m, "Master Interrupt Control:\t%08x\n", 774 I915_READ(GEN8_MASTER_IRQ)); 775 776 for (i = 0; i < 4; i++) { 777 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 778 i, I915_READ(GEN8_GT_IMR(i))); 779 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 780 i, I915_READ(GEN8_GT_IIR(i))); 781 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 782 i, I915_READ(GEN8_GT_IER(i))); 783 } 784 785 for_each_pipe(dev_priv, pipe) { 786 enum intel_display_power_domain power_domain; 787 788 power_domain = POWER_DOMAIN_PIPE(pipe); 789 if (!intel_display_power_get_if_enabled(dev_priv, 790 power_domain)) { 791 seq_printf(m, "Pipe %c power disabled\n", 792 pipe_name(pipe)); 793 continue; 794 } 795 seq_printf(m, "Pipe %c IMR:\t%08x\n", 796 pipe_name(pipe), 797 I915_READ(GEN8_DE_PIPE_IMR(pipe))); 798 seq_printf(m, "Pipe %c IIR:\t%08x\n", 799 pipe_name(pipe), 800 I915_READ(GEN8_DE_PIPE_IIR(pipe))); 801 seq_printf(m, "Pipe %c IER:\t%08x\n", 802 pipe_name(pipe), 803 I915_READ(GEN8_DE_PIPE_IER(pipe))); 804 805 intel_display_power_put(dev_priv, power_domain); 806 } 807 808 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", 809 I915_READ(GEN8_DE_PORT_IMR)); 810 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", 811 I915_READ(GEN8_DE_PORT_IIR)); 812 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", 813 I915_READ(GEN8_DE_PORT_IER)); 814 815 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", 816 I915_READ(GEN8_DE_MISC_IMR)); 817 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", 818 I915_READ(GEN8_DE_MISC_IIR)); 819 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", 820 I915_READ(GEN8_DE_MISC_IER)); 821 822 seq_printf(m, "PCU interrupt mask:\t%08x\n", 823 I915_READ(GEN8_PCU_IMR)); 824 seq_printf(m, "PCU interrupt identity:\t%08x\n", 825 I915_READ(GEN8_PCU_IIR)); 826 seq_printf(m, "PCU interrupt enable:\t%08x\n", 827 I915_READ(GEN8_PCU_IER)); 828 } else if (IS_VALLEYVIEW(dev_priv)) { 829 seq_printf(m, "Display IER:\t%08x\n", 830 I915_READ(VLV_IER)); 831 seq_printf(m, "Display IIR:\t%08x\n", 832 I915_READ(VLV_IIR)); 833 seq_printf(m, "Display IIR_RW:\t%08x\n", 834 I915_READ(VLV_IIR_RW)); 835 seq_printf(m, "Display IMR:\t%08x\n", 836 I915_READ(VLV_IMR)); 837 for_each_pipe(dev_priv, pipe) 838 seq_printf(m, "Pipe %c stat:\t%08x\n", 839 pipe_name(pipe), 840 I915_READ(PIPESTAT(pipe))); 841 842 seq_printf(m, "Master IER:\t%08x\n", 843 I915_READ(VLV_MASTER_IER)); 844 845 seq_printf(m, "Render IER:\t%08x\n", 846 I915_READ(GTIER)); 847 seq_printf(m, "Render IIR:\t%08x\n", 848 I915_READ(GTIIR)); 849 seq_printf(m, "Render IMR:\t%08x\n", 850 I915_READ(GTIMR)); 851 852 seq_printf(m, "PM IER:\t\t%08x\n", 853 I915_READ(GEN6_PMIER)); 854 seq_printf(m, "PM IIR:\t\t%08x\n", 855 I915_READ(GEN6_PMIIR)); 856 seq_printf(m, "PM IMR:\t\t%08x\n", 857 I915_READ(GEN6_PMIMR)); 858 859 seq_printf(m, "Port hotplug:\t%08x\n", 860 I915_READ(PORT_HOTPLUG_EN)); 861 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 862 I915_READ(VLV_DPFLIPSTAT)); 863 seq_printf(m, "DPINVGTT:\t%08x\n", 864 I915_READ(DPINVGTT)); 865 866 } else if (!HAS_PCH_SPLIT(dev_priv)) { 867 seq_printf(m, "Interrupt enable: %08x\n", 868 I915_READ(IER)); 869 seq_printf(m, "Interrupt identity: %08x\n", 870 I915_READ(IIR)); 871 seq_printf(m, "Interrupt mask: %08x\n", 872 I915_READ(IMR)); 873 for_each_pipe(dev_priv, pipe) 874 seq_printf(m, "Pipe %c stat: %08x\n", 875 pipe_name(pipe), 876 I915_READ(PIPESTAT(pipe))); 877 } else { 878 seq_printf(m, "North Display Interrupt enable: %08x\n", 879 I915_READ(DEIER)); 880 seq_printf(m, "North Display Interrupt identity: %08x\n", 881 I915_READ(DEIIR)); 882 seq_printf(m, "North Display Interrupt mask: %08x\n", 883 I915_READ(DEIMR)); 884 seq_printf(m, "South Display Interrupt enable: %08x\n", 885 I915_READ(SDEIER)); 886 seq_printf(m, "South Display Interrupt identity: %08x\n", 887 I915_READ(SDEIIR)); 888 seq_printf(m, "South Display Interrupt mask: %08x\n", 889 I915_READ(SDEIMR)); 890 seq_printf(m, "Graphics Interrupt enable: %08x\n", 891 I915_READ(GTIER)); 892 seq_printf(m, "Graphics Interrupt identity: %08x\n", 893 I915_READ(GTIIR)); 894 seq_printf(m, "Graphics Interrupt mask: %08x\n", 895 I915_READ(GTIMR)); 896 } 897 for_each_engine(engine, dev_priv, id) { 898 if (INTEL_GEN(dev_priv) >= 6) { 899 seq_printf(m, 900 "Graphics Interrupt mask (%s): %08x\n", 901 engine->name, I915_READ_IMR(engine)); 902 } 903 i915_ring_seqno_info(m, engine); 904 } 905 intel_runtime_pm_put(dev_priv); 906 907 return 0; 908 } 909 910 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 911 { 912 struct drm_i915_private *dev_priv = node_to_i915(m->private); 913 struct drm_device *dev = &dev_priv->drm; 914 int i, ret; 915 916 ret = mutex_lock_interruptible(&dev->struct_mutex); 917 if (ret) 918 return ret; 919 920 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 921 for (i = 0; i < dev_priv->num_fence_regs; i++) { 922 struct i915_vma *vma = dev_priv->fence_regs[i].vma; 923 924 seq_printf(m, "Fence %d, pin count = %d, object = ", 925 i, dev_priv->fence_regs[i].pin_count); 926 if (!vma) 927 seq_puts(m, "unused"); 928 else 929 describe_obj(m, vma->obj); 930 seq_putc(m, '\n'); 931 } 932 933 mutex_unlock(&dev->struct_mutex); 934 return 0; 935 } 936 937 static int i915_hws_info(struct seq_file *m, void *data) 938 { 939 struct drm_info_node *node = m->private; 940 struct drm_i915_private *dev_priv = node_to_i915(node); 941 struct intel_engine_cs *engine; 942 const u32 *hws; 943 int i; 944 945 engine = dev_priv->engine[(uintptr_t)node->info_ent->data]; 946 hws = engine->status_page.page_addr; 947 if (hws == NULL) 948 return 0; 949 950 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 951 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 952 i * 4, 953 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 954 } 955 return 0; 956 } 957 958 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 959 960 static ssize_t 961 i915_error_state_write(struct file *filp, 962 const char __user *ubuf, 963 size_t cnt, 964 loff_t *ppos) 965 { 966 struct i915_error_state_file_priv *error_priv = filp->private_data; 967 968 DRM_DEBUG_DRIVER("Resetting error state\n"); 969 i915_destroy_error_state(error_priv->dev); 970 971 return cnt; 972 } 973 974 static int i915_error_state_open(struct inode *inode, struct file *file) 975 { 976 struct drm_i915_private *dev_priv = inode->i_private; 977 struct i915_error_state_file_priv *error_priv; 978 979 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); 980 if (!error_priv) 981 return -ENOMEM; 982 983 error_priv->dev = &dev_priv->drm; 984 985 i915_error_state_get(&dev_priv->drm, error_priv); 986 987 file->private_data = error_priv; 988 989 return 0; 990 } 991 992 static int i915_error_state_release(struct inode *inode, struct file *file) 993 { 994 struct i915_error_state_file_priv *error_priv = file->private_data; 995 996 i915_error_state_put(error_priv); 997 kfree(error_priv); 998 999 return 0; 1000 } 1001 1002 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, 1003 size_t count, loff_t *pos) 1004 { 1005 struct i915_error_state_file_priv *error_priv = file->private_data; 1006 struct drm_i915_error_state_buf error_str; 1007 loff_t tmp_pos = 0; 1008 ssize_t ret_count = 0; 1009 int ret; 1010 1011 ret = i915_error_state_buf_init(&error_str, 1012 to_i915(error_priv->dev), count, *pos); 1013 if (ret) 1014 return ret; 1015 1016 ret = i915_error_state_to_str(&error_str, error_priv); 1017 if (ret) 1018 goto out; 1019 1020 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, 1021 error_str.buf, 1022 error_str.bytes); 1023 1024 if (ret_count < 0) 1025 ret = ret_count; 1026 else 1027 *pos = error_str.start + ret_count; 1028 out: 1029 i915_error_state_buf_release(&error_str); 1030 return ret ?: ret_count; 1031 } 1032 1033 static const struct file_operations i915_error_state_fops = { 1034 .owner = THIS_MODULE, 1035 .open = i915_error_state_open, 1036 .read = i915_error_state_read, 1037 .write = i915_error_state_write, 1038 .llseek = default_llseek, 1039 .release = i915_error_state_release, 1040 }; 1041 1042 #endif 1043 1044 static int 1045 i915_next_seqno_get(void *data, u64 *val) 1046 { 1047 struct drm_i915_private *dev_priv = data; 1048 1049 *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno); 1050 return 0; 1051 } 1052 1053 static int 1054 i915_next_seqno_set(void *data, u64 val) 1055 { 1056 struct drm_i915_private *dev_priv = data; 1057 struct drm_device *dev = &dev_priv->drm; 1058 int ret; 1059 1060 ret = mutex_lock_interruptible(&dev->struct_mutex); 1061 if (ret) 1062 return ret; 1063 1064 ret = i915_gem_set_global_seqno(dev, val); 1065 mutex_unlock(&dev->struct_mutex); 1066 1067 return ret; 1068 } 1069 1070 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 1071 i915_next_seqno_get, i915_next_seqno_set, 1072 "0x%llx\n"); 1073 1074 static int i915_frequency_info(struct seq_file *m, void *unused) 1075 { 1076 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1077 struct drm_device *dev = &dev_priv->drm; 1078 int ret = 0; 1079 1080 intel_runtime_pm_get(dev_priv); 1081 1082 if (IS_GEN5(dev_priv)) { 1083 u16 rgvswctl = I915_READ16(MEMSWCTL); 1084 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 1085 1086 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 1087 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 1088 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 1089 MEMSTAT_VID_SHIFT); 1090 seq_printf(m, "Current P-state: %d\n", 1091 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 1092 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1093 u32 freq_sts; 1094 1095 mutex_lock(&dev_priv->rps.hw_lock); 1096 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 1097 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 1098 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1099 1100 seq_printf(m, "actual GPU freq: %d MHz\n", 1101 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); 1102 1103 seq_printf(m, "current GPU freq: %d MHz\n", 1104 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1105 1106 seq_printf(m, "max GPU freq: %d MHz\n", 1107 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1108 1109 seq_printf(m, "min GPU freq: %d MHz\n", 1110 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1111 1112 seq_printf(m, "idle GPU freq: %d MHz\n", 1113 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1114 1115 seq_printf(m, 1116 "efficient (RPe) frequency: %d MHz\n", 1117 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1118 mutex_unlock(&dev_priv->rps.hw_lock); 1119 } else if (INTEL_GEN(dev_priv) >= 6) { 1120 u32 rp_state_limits; 1121 u32 gt_perf_status; 1122 u32 rp_state_cap; 1123 u32 rpmodectl, rpinclimit, rpdeclimit; 1124 u32 rpstat, cagf, reqf; 1125 u32 rpupei, rpcurup, rpprevup; 1126 u32 rpdownei, rpcurdown, rpprevdown; 1127 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 1128 int max_freq; 1129 1130 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 1131 if (IS_BROXTON(dev_priv)) { 1132 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 1133 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); 1134 } else { 1135 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 1136 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 1137 } 1138 1139 /* RPSTAT1 is in the GT power well */ 1140 ret = mutex_lock_interruptible(&dev->struct_mutex); 1141 if (ret) 1142 goto out; 1143 1144 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1145 1146 reqf = I915_READ(GEN6_RPNSWREQ); 1147 if (IS_GEN9(dev_priv)) 1148 reqf >>= 23; 1149 else { 1150 reqf &= ~GEN6_TURBO_DISABLE; 1151 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1152 reqf >>= 24; 1153 else 1154 reqf >>= 25; 1155 } 1156 reqf = intel_gpu_freq(dev_priv, reqf); 1157 1158 rpmodectl = I915_READ(GEN6_RP_CONTROL); 1159 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); 1160 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); 1161 1162 rpstat = I915_READ(GEN6_RPSTAT1); 1163 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 1164 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 1165 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 1166 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 1167 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 1168 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 1169 if (IS_GEN9(dev_priv)) 1170 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 1171 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1172 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 1173 else 1174 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 1175 cagf = intel_gpu_freq(dev_priv, cagf); 1176 1177 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1178 mutex_unlock(&dev->struct_mutex); 1179 1180 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 1181 pm_ier = I915_READ(GEN6_PMIER); 1182 pm_imr = I915_READ(GEN6_PMIMR); 1183 pm_isr = I915_READ(GEN6_PMISR); 1184 pm_iir = I915_READ(GEN6_PMIIR); 1185 pm_mask = I915_READ(GEN6_PMINTRMSK); 1186 } else { 1187 pm_ier = I915_READ(GEN8_GT_IER(2)); 1188 pm_imr = I915_READ(GEN8_GT_IMR(2)); 1189 pm_isr = I915_READ(GEN8_GT_ISR(2)); 1190 pm_iir = I915_READ(GEN8_GT_IIR(2)); 1191 pm_mask = I915_READ(GEN6_PMINTRMSK); 1192 } 1193 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", 1194 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); 1195 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep); 1196 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 1197 seq_printf(m, "Render p-state ratio: %d\n", 1198 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8); 1199 seq_printf(m, "Render p-state VID: %d\n", 1200 gt_perf_status & 0xff); 1201 seq_printf(m, "Render p-state limit: %d\n", 1202 rp_state_limits & 0xff); 1203 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 1204 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 1205 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 1206 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 1207 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 1208 seq_printf(m, "CAGF: %dMHz\n", cagf); 1209 seq_printf(m, "RP CUR UP EI: %d (%dus)\n", 1210 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei)); 1211 seq_printf(m, "RP CUR UP: %d (%dus)\n", 1212 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup)); 1213 seq_printf(m, "RP PREV UP: %d (%dus)\n", 1214 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup)); 1215 seq_printf(m, "Up threshold: %d%%\n", 1216 dev_priv->rps.up_threshold); 1217 1218 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", 1219 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei)); 1220 seq_printf(m, "RP CUR DOWN: %d (%dus)\n", 1221 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown)); 1222 seq_printf(m, "RP PREV DOWN: %d (%dus)\n", 1223 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown)); 1224 seq_printf(m, "Down threshold: %d%%\n", 1225 dev_priv->rps.down_threshold); 1226 1227 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 : 1228 rp_state_cap >> 16) & 0xff; 1229 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1230 GEN9_FREQ_SCALER : 1); 1231 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 1232 intel_gpu_freq(dev_priv, max_freq)); 1233 1234 max_freq = (rp_state_cap & 0xff00) >> 8; 1235 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1236 GEN9_FREQ_SCALER : 1); 1237 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 1238 intel_gpu_freq(dev_priv, max_freq)); 1239 1240 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 : 1241 rp_state_cap >> 0) & 0xff; 1242 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1243 GEN9_FREQ_SCALER : 1); 1244 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1245 intel_gpu_freq(dev_priv, max_freq)); 1246 seq_printf(m, "Max overclocked frequency: %dMHz\n", 1247 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1248 1249 seq_printf(m, "Current freq: %d MHz\n", 1250 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1251 seq_printf(m, "Actual freq: %d MHz\n", cagf); 1252 seq_printf(m, "Idle freq: %d MHz\n", 1253 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1254 seq_printf(m, "Min freq: %d MHz\n", 1255 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1256 seq_printf(m, "Boost freq: %d MHz\n", 1257 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); 1258 seq_printf(m, "Max freq: %d MHz\n", 1259 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1260 seq_printf(m, 1261 "efficient (RPe) frequency: %d MHz\n", 1262 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1263 } else { 1264 seq_puts(m, "no P-state info available\n"); 1265 } 1266 1267 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); 1268 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); 1269 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); 1270 1271 out: 1272 intel_runtime_pm_put(dev_priv); 1273 return ret; 1274 } 1275 1276 static void i915_instdone_info(struct drm_i915_private *dev_priv, 1277 struct seq_file *m, 1278 struct intel_instdone *instdone) 1279 { 1280 int slice; 1281 int subslice; 1282 1283 seq_printf(m, "\t\tINSTDONE: 0x%08x\n", 1284 instdone->instdone); 1285 1286 if (INTEL_GEN(dev_priv) <= 3) 1287 return; 1288 1289 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", 1290 instdone->slice_common); 1291 1292 if (INTEL_GEN(dev_priv) <= 6) 1293 return; 1294 1295 for_each_instdone_slice_subslice(dev_priv, slice, subslice) 1296 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 1297 slice, subslice, instdone->sampler[slice][subslice]); 1298 1299 for_each_instdone_slice_subslice(dev_priv, slice, subslice) 1300 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", 1301 slice, subslice, instdone->row[slice][subslice]); 1302 } 1303 1304 static int i915_hangcheck_info(struct seq_file *m, void *unused) 1305 { 1306 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1307 struct intel_engine_cs *engine; 1308 u64 acthd[I915_NUM_ENGINES]; 1309 u32 seqno[I915_NUM_ENGINES]; 1310 struct intel_instdone instdone; 1311 enum intel_engine_id id; 1312 1313 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) 1314 seq_printf(m, "Wedged\n"); 1315 if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags)) 1316 seq_printf(m, "Reset in progress\n"); 1317 if (waitqueue_active(&dev_priv->gpu_error.wait_queue)) 1318 seq_printf(m, "Waiter holding struct mutex\n"); 1319 if (waitqueue_active(&dev_priv->gpu_error.reset_queue)) 1320 seq_printf(m, "struct_mutex blocked for reset\n"); 1321 1322 if (!i915.enable_hangcheck) { 1323 seq_printf(m, "Hangcheck disabled\n"); 1324 return 0; 1325 } 1326 1327 intel_runtime_pm_get(dev_priv); 1328 1329 for_each_engine(engine, dev_priv, id) { 1330 acthd[id] = intel_engine_get_active_head(engine); 1331 seqno[id] = intel_engine_get_seqno(engine); 1332 } 1333 1334 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone); 1335 1336 intel_runtime_pm_put(dev_priv); 1337 1338 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { 1339 seq_printf(m, "Hangcheck active, fires in %dms\n", 1340 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - 1341 jiffies)); 1342 } else 1343 seq_printf(m, "Hangcheck inactive\n"); 1344 1345 for_each_engine(engine, dev_priv, id) { 1346 struct intel_breadcrumbs *b = &engine->breadcrumbs; 1347 struct rb_node *rb; 1348 1349 seq_printf(m, "%s:\n", engine->name); 1350 seq_printf(m, "\tseqno = %x [current %x, last %x]\n", 1351 engine->hangcheck.seqno, seqno[id], 1352 intel_engine_last_submit(engine)); 1353 seq_printf(m, "\twaiters? %s, fake irq active? %s\n", 1354 yesno(intel_engine_has_waiter(engine)), 1355 yesno(test_bit(engine->id, 1356 &dev_priv->gpu_error.missed_irq_rings))); 1357 spin_lock_irq(&b->lock); 1358 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 1359 struct intel_wait *w = container_of(rb, typeof(*w), node); 1360 1361 seq_printf(m, "\t%s [%d] waiting for %x\n", 1362 w->tsk->comm, w->tsk->pid, w->seqno); 1363 } 1364 spin_unlock_irq(&b->lock); 1365 1366 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", 1367 (long long)engine->hangcheck.acthd, 1368 (long long)acthd[id]); 1369 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score); 1370 seq_printf(m, "\taction = %d\n", engine->hangcheck.action); 1371 1372 if (engine->id == RCS) { 1373 seq_puts(m, "\tinstdone read =\n"); 1374 1375 i915_instdone_info(dev_priv, m, &instdone); 1376 1377 seq_puts(m, "\tinstdone accu =\n"); 1378 1379 i915_instdone_info(dev_priv, m, 1380 &engine->hangcheck.instdone); 1381 } 1382 } 1383 1384 return 0; 1385 } 1386 1387 static int ironlake_drpc_info(struct seq_file *m) 1388 { 1389 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1390 u32 rgvmodectl, rstdbyctl; 1391 u16 crstandvid; 1392 1393 intel_runtime_pm_get(dev_priv); 1394 1395 rgvmodectl = I915_READ(MEMMODECTL); 1396 rstdbyctl = I915_READ(RSTDBYCTL); 1397 crstandvid = I915_READ16(CRSTANDVID); 1398 1399 intel_runtime_pm_put(dev_priv); 1400 1401 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 1402 seq_printf(m, "Boost freq: %d\n", 1403 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 1404 MEMMODE_BOOST_FREQ_SHIFT); 1405 seq_printf(m, "HW control enabled: %s\n", 1406 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 1407 seq_printf(m, "SW control enabled: %s\n", 1408 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 1409 seq_printf(m, "Gated voltage change: %s\n", 1410 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 1411 seq_printf(m, "Starting frequency: P%d\n", 1412 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 1413 seq_printf(m, "Max P-state: P%d\n", 1414 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 1415 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 1416 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 1417 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 1418 seq_printf(m, "Render standby enabled: %s\n", 1419 yesno(!(rstdbyctl & RCX_SW_EXIT))); 1420 seq_puts(m, "Current RS state: "); 1421 switch (rstdbyctl & RSX_STATUS_MASK) { 1422 case RSX_STATUS_ON: 1423 seq_puts(m, "on\n"); 1424 break; 1425 case RSX_STATUS_RC1: 1426 seq_puts(m, "RC1\n"); 1427 break; 1428 case RSX_STATUS_RC1E: 1429 seq_puts(m, "RC1E\n"); 1430 break; 1431 case RSX_STATUS_RS1: 1432 seq_puts(m, "RS1\n"); 1433 break; 1434 case RSX_STATUS_RS2: 1435 seq_puts(m, "RS2 (RC6)\n"); 1436 break; 1437 case RSX_STATUS_RS3: 1438 seq_puts(m, "RC3 (RC6+)\n"); 1439 break; 1440 default: 1441 seq_puts(m, "unknown\n"); 1442 break; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int i915_forcewake_domains(struct seq_file *m, void *data) 1449 { 1450 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1451 struct intel_uncore_forcewake_domain *fw_domain; 1452 1453 spin_lock_irq(&dev_priv->uncore.lock); 1454 for_each_fw_domain(fw_domain, dev_priv) { 1455 seq_printf(m, "%s.wake_count = %u\n", 1456 intel_uncore_forcewake_domain_to_str(fw_domain->id), 1457 fw_domain->wake_count); 1458 } 1459 spin_unlock_irq(&dev_priv->uncore.lock); 1460 1461 return 0; 1462 } 1463 1464 static int vlv_drpc_info(struct seq_file *m) 1465 { 1466 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1467 u32 rpmodectl1, rcctl1, pw_status; 1468 1469 intel_runtime_pm_get(dev_priv); 1470 1471 pw_status = I915_READ(VLV_GTLC_PW_STATUS); 1472 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1473 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1474 1475 intel_runtime_pm_put(dev_priv); 1476 1477 seq_printf(m, "Video Turbo Mode: %s\n", 1478 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1479 seq_printf(m, "Turbo enabled: %s\n", 1480 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1481 seq_printf(m, "HW control enabled: %s\n", 1482 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1483 seq_printf(m, "SW control enabled: %s\n", 1484 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1485 GEN6_RP_MEDIA_SW_MODE)); 1486 seq_printf(m, "RC6 Enabled: %s\n", 1487 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 1488 GEN6_RC_CTL_EI_MODE(1)))); 1489 seq_printf(m, "Render Power Well: %s\n", 1490 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 1491 seq_printf(m, "Media Power Well: %s\n", 1492 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1493 1494 seq_printf(m, "Render RC6 residency since boot: %u\n", 1495 I915_READ(VLV_GT_RENDER_RC6)); 1496 seq_printf(m, "Media RC6 residency since boot: %u\n", 1497 I915_READ(VLV_GT_MEDIA_RC6)); 1498 1499 return i915_forcewake_domains(m, NULL); 1500 } 1501 1502 static int gen6_drpc_info(struct seq_file *m) 1503 { 1504 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1505 struct drm_device *dev = &dev_priv->drm; 1506 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; 1507 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0; 1508 unsigned forcewake_count; 1509 int count = 0, ret; 1510 1511 ret = mutex_lock_interruptible(&dev->struct_mutex); 1512 if (ret) 1513 return ret; 1514 intel_runtime_pm_get(dev_priv); 1515 1516 spin_lock_irq(&dev_priv->uncore.lock); 1517 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; 1518 spin_unlock_irq(&dev_priv->uncore.lock); 1519 1520 if (forcewake_count) { 1521 seq_puts(m, "RC information inaccurate because somebody " 1522 "holds a forcewake reference \n"); 1523 } else { 1524 /* NB: we cannot use forcewake, else we read the wrong values */ 1525 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1526 udelay(10); 1527 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1528 } 1529 1530 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); 1531 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); 1532 1533 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1534 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1535 if (INTEL_GEN(dev_priv) >= 9) { 1536 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); 1537 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); 1538 } 1539 mutex_unlock(&dev->struct_mutex); 1540 mutex_lock(&dev_priv->rps.hw_lock); 1541 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 1542 mutex_unlock(&dev_priv->rps.hw_lock); 1543 1544 intel_runtime_pm_put(dev_priv); 1545 1546 seq_printf(m, "Video Turbo Mode: %s\n", 1547 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1548 seq_printf(m, "HW control enabled: %s\n", 1549 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1550 seq_printf(m, "SW control enabled: %s\n", 1551 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1552 GEN6_RP_MEDIA_SW_MODE)); 1553 seq_printf(m, "RC1e Enabled: %s\n", 1554 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1555 seq_printf(m, "RC6 Enabled: %s\n", 1556 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1557 if (INTEL_GEN(dev_priv) >= 9) { 1558 seq_printf(m, "Render Well Gating Enabled: %s\n", 1559 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); 1560 seq_printf(m, "Media Well Gating Enabled: %s\n", 1561 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE)); 1562 } 1563 seq_printf(m, "Deep RC6 Enabled: %s\n", 1564 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1565 seq_printf(m, "Deepest RC6 Enabled: %s\n", 1566 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1567 seq_puts(m, "Current RC state: "); 1568 switch (gt_core_status & GEN6_RCn_MASK) { 1569 case GEN6_RC0: 1570 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1571 seq_puts(m, "Core Power Down\n"); 1572 else 1573 seq_puts(m, "on\n"); 1574 break; 1575 case GEN6_RC3: 1576 seq_puts(m, "RC3\n"); 1577 break; 1578 case GEN6_RC6: 1579 seq_puts(m, "RC6\n"); 1580 break; 1581 case GEN6_RC7: 1582 seq_puts(m, "RC7\n"); 1583 break; 1584 default: 1585 seq_puts(m, "Unknown\n"); 1586 break; 1587 } 1588 1589 seq_printf(m, "Core Power Down: %s\n", 1590 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1591 if (INTEL_GEN(dev_priv) >= 9) { 1592 seq_printf(m, "Render Power Well: %s\n", 1593 (gen9_powergate_status & 1594 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); 1595 seq_printf(m, "Media Power Well: %s\n", 1596 (gen9_powergate_status & 1597 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1598 } 1599 1600 /* Not exactly sure what this is */ 1601 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1602 I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1603 seq_printf(m, "RC6 residency since boot: %u\n", 1604 I915_READ(GEN6_GT_GFX_RC6)); 1605 seq_printf(m, "RC6+ residency since boot: %u\n", 1606 I915_READ(GEN6_GT_GFX_RC6p)); 1607 seq_printf(m, "RC6++ residency since boot: %u\n", 1608 I915_READ(GEN6_GT_GFX_RC6pp)); 1609 1610 seq_printf(m, "RC6 voltage: %dmV\n", 1611 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 1612 seq_printf(m, "RC6+ voltage: %dmV\n", 1613 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 1614 seq_printf(m, "RC6++ voltage: %dmV\n", 1615 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 1616 return i915_forcewake_domains(m, NULL); 1617 } 1618 1619 static int i915_drpc_info(struct seq_file *m, void *unused) 1620 { 1621 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1622 1623 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1624 return vlv_drpc_info(m); 1625 else if (INTEL_GEN(dev_priv) >= 6) 1626 return gen6_drpc_info(m); 1627 else 1628 return ironlake_drpc_info(m); 1629 } 1630 1631 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 1632 { 1633 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1634 1635 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 1636 dev_priv->fb_tracking.busy_bits); 1637 1638 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 1639 dev_priv->fb_tracking.flip_bits); 1640 1641 return 0; 1642 } 1643 1644 static int i915_fbc_status(struct seq_file *m, void *unused) 1645 { 1646 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1647 1648 if (!HAS_FBC(dev_priv)) { 1649 seq_puts(m, "FBC unsupported on this chipset\n"); 1650 return 0; 1651 } 1652 1653 intel_runtime_pm_get(dev_priv); 1654 mutex_lock(&dev_priv->fbc.lock); 1655 1656 if (intel_fbc_is_active(dev_priv)) 1657 seq_puts(m, "FBC enabled\n"); 1658 else 1659 seq_printf(m, "FBC disabled: %s\n", 1660 dev_priv->fbc.no_fbc_reason); 1661 1662 if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) { 1663 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ? 1664 BDW_FBC_COMPRESSION_MASK : 1665 IVB_FBC_COMPRESSION_MASK; 1666 seq_printf(m, "Compressing: %s\n", 1667 yesno(I915_READ(FBC_STATUS2) & mask)); 1668 } 1669 1670 mutex_unlock(&dev_priv->fbc.lock); 1671 intel_runtime_pm_put(dev_priv); 1672 1673 return 0; 1674 } 1675 1676 static int i915_fbc_fc_get(void *data, u64 *val) 1677 { 1678 struct drm_i915_private *dev_priv = data; 1679 1680 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) 1681 return -ENODEV; 1682 1683 *val = dev_priv->fbc.false_color; 1684 1685 return 0; 1686 } 1687 1688 static int i915_fbc_fc_set(void *data, u64 val) 1689 { 1690 struct drm_i915_private *dev_priv = data; 1691 u32 reg; 1692 1693 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) 1694 return -ENODEV; 1695 1696 mutex_lock(&dev_priv->fbc.lock); 1697 1698 reg = I915_READ(ILK_DPFC_CONTROL); 1699 dev_priv->fbc.false_color = val; 1700 1701 I915_WRITE(ILK_DPFC_CONTROL, val ? 1702 (reg | FBC_CTL_FALSE_COLOR) : 1703 (reg & ~FBC_CTL_FALSE_COLOR)); 1704 1705 mutex_unlock(&dev_priv->fbc.lock); 1706 return 0; 1707 } 1708 1709 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, 1710 i915_fbc_fc_get, i915_fbc_fc_set, 1711 "%llu\n"); 1712 1713 static int i915_ips_status(struct seq_file *m, void *unused) 1714 { 1715 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1716 1717 if (!HAS_IPS(dev_priv)) { 1718 seq_puts(m, "not supported\n"); 1719 return 0; 1720 } 1721 1722 intel_runtime_pm_get(dev_priv); 1723 1724 seq_printf(m, "Enabled by kernel parameter: %s\n", 1725 yesno(i915.enable_ips)); 1726 1727 if (INTEL_GEN(dev_priv) >= 8) { 1728 seq_puts(m, "Currently: unknown\n"); 1729 } else { 1730 if (I915_READ(IPS_CTL) & IPS_ENABLE) 1731 seq_puts(m, "Currently: enabled\n"); 1732 else 1733 seq_puts(m, "Currently: disabled\n"); 1734 } 1735 1736 intel_runtime_pm_put(dev_priv); 1737 1738 return 0; 1739 } 1740 1741 static int i915_sr_status(struct seq_file *m, void *unused) 1742 { 1743 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1744 bool sr_enabled = false; 1745 1746 intel_runtime_pm_get(dev_priv); 1747 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 1748 1749 if (HAS_PCH_SPLIT(dev_priv)) 1750 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1751 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) || 1752 IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1753 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1754 else if (IS_I915GM(dev_priv)) 1755 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1756 else if (IS_PINEVIEW(dev_priv)) 1757 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1758 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1759 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 1760 1761 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 1762 intel_runtime_pm_put(dev_priv); 1763 1764 seq_printf(m, "self-refresh: %s\n", 1765 sr_enabled ? "enabled" : "disabled"); 1766 1767 return 0; 1768 } 1769 1770 static int i915_emon_status(struct seq_file *m, void *unused) 1771 { 1772 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1773 struct drm_device *dev = &dev_priv->drm; 1774 unsigned long temp, chipset, gfx; 1775 int ret; 1776 1777 if (!IS_GEN5(dev_priv)) 1778 return -ENODEV; 1779 1780 ret = mutex_lock_interruptible(&dev->struct_mutex); 1781 if (ret) 1782 return ret; 1783 1784 temp = i915_mch_val(dev_priv); 1785 chipset = i915_chipset_val(dev_priv); 1786 gfx = i915_gfx_val(dev_priv); 1787 mutex_unlock(&dev->struct_mutex); 1788 1789 seq_printf(m, "GMCH temp: %ld\n", temp); 1790 seq_printf(m, "Chipset power: %ld\n", chipset); 1791 seq_printf(m, "GFX power: %ld\n", gfx); 1792 seq_printf(m, "Total power: %ld\n", chipset + gfx); 1793 1794 return 0; 1795 } 1796 1797 static int i915_ring_freq_table(struct seq_file *m, void *unused) 1798 { 1799 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1800 int ret = 0; 1801 int gpu_freq, ia_freq; 1802 unsigned int max_gpu_freq, min_gpu_freq; 1803 1804 if (!HAS_LLC(dev_priv)) { 1805 seq_puts(m, "unsupported on this chipset\n"); 1806 return 0; 1807 } 1808 1809 intel_runtime_pm_get(dev_priv); 1810 1811 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 1812 if (ret) 1813 goto out; 1814 1815 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 1816 /* Convert GT frequency to 50 HZ units */ 1817 min_gpu_freq = 1818 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; 1819 max_gpu_freq = 1820 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; 1821 } else { 1822 min_gpu_freq = dev_priv->rps.min_freq_softlimit; 1823 max_gpu_freq = dev_priv->rps.max_freq_softlimit; 1824 } 1825 1826 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 1827 1828 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 1829 ia_freq = gpu_freq; 1830 sandybridge_pcode_read(dev_priv, 1831 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1832 &ia_freq); 1833 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 1834 intel_gpu_freq(dev_priv, (gpu_freq * 1835 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? 1836 GEN9_FREQ_SCALER : 1))), 1837 ((ia_freq >> 0) & 0xff) * 100, 1838 ((ia_freq >> 8) & 0xff) * 100); 1839 } 1840 1841 mutex_unlock(&dev_priv->rps.hw_lock); 1842 1843 out: 1844 intel_runtime_pm_put(dev_priv); 1845 return ret; 1846 } 1847 1848 static int i915_opregion(struct seq_file *m, void *unused) 1849 { 1850 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1851 struct drm_device *dev = &dev_priv->drm; 1852 struct intel_opregion *opregion = &dev_priv->opregion; 1853 int ret; 1854 1855 ret = mutex_lock_interruptible(&dev->struct_mutex); 1856 if (ret) 1857 goto out; 1858 1859 if (opregion->header) 1860 seq_write(m, opregion->header, OPREGION_SIZE); 1861 1862 mutex_unlock(&dev->struct_mutex); 1863 1864 out: 1865 return 0; 1866 } 1867 1868 static int i915_vbt(struct seq_file *m, void *unused) 1869 { 1870 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; 1871 1872 if (opregion->vbt) 1873 seq_write(m, opregion->vbt, opregion->vbt_size); 1874 1875 return 0; 1876 } 1877 1878 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 1879 { 1880 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1881 struct drm_device *dev = &dev_priv->drm; 1882 struct intel_framebuffer *fbdev_fb = NULL; 1883 struct drm_framebuffer *drm_fb; 1884 int ret; 1885 1886 ret = mutex_lock_interruptible(&dev->struct_mutex); 1887 if (ret) 1888 return ret; 1889 1890 #ifdef CONFIG_DRM_FBDEV_EMULATION 1891 if (dev_priv->fbdev) { 1892 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); 1893 1894 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1895 fbdev_fb->base.width, 1896 fbdev_fb->base.height, 1897 fbdev_fb->base.depth, 1898 fbdev_fb->base.bits_per_pixel, 1899 fbdev_fb->base.modifier[0], 1900 drm_framebuffer_read_refcount(&fbdev_fb->base)); 1901 describe_obj(m, fbdev_fb->obj); 1902 seq_putc(m, '\n'); 1903 } 1904 #endif 1905 1906 mutex_lock(&dev->mode_config.fb_lock); 1907 drm_for_each_fb(drm_fb, dev) { 1908 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 1909 if (fb == fbdev_fb) 1910 continue; 1911 1912 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1913 fb->base.width, 1914 fb->base.height, 1915 fb->base.depth, 1916 fb->base.bits_per_pixel, 1917 fb->base.modifier[0], 1918 drm_framebuffer_read_refcount(&fb->base)); 1919 describe_obj(m, fb->obj); 1920 seq_putc(m, '\n'); 1921 } 1922 mutex_unlock(&dev->mode_config.fb_lock); 1923 mutex_unlock(&dev->struct_mutex); 1924 1925 return 0; 1926 } 1927 1928 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring) 1929 { 1930 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", 1931 ring->space, ring->head, ring->tail, 1932 ring->last_retired_head); 1933 } 1934 1935 static int i915_context_status(struct seq_file *m, void *unused) 1936 { 1937 struct drm_i915_private *dev_priv = node_to_i915(m->private); 1938 struct drm_device *dev = &dev_priv->drm; 1939 struct intel_engine_cs *engine; 1940 struct i915_gem_context *ctx; 1941 enum intel_engine_id id; 1942 int ret; 1943 1944 ret = mutex_lock_interruptible(&dev->struct_mutex); 1945 if (ret) 1946 return ret; 1947 1948 list_for_each_entry(ctx, &dev_priv->context_list, link) { 1949 seq_printf(m, "HW context %u ", ctx->hw_id); 1950 if (ctx->pid) { 1951 struct task_struct *task; 1952 1953 task = get_pid_task(ctx->pid, PIDTYPE_PID); 1954 if (task) { 1955 seq_printf(m, "(%s [%d]) ", 1956 task->comm, task->pid); 1957 put_task_struct(task); 1958 } 1959 } else if (IS_ERR(ctx->file_priv)) { 1960 seq_puts(m, "(deleted) "); 1961 } else { 1962 seq_puts(m, "(kernel) "); 1963 } 1964 1965 seq_putc(m, ctx->remap_slice ? 'R' : 'r'); 1966 seq_putc(m, '\n'); 1967 1968 for_each_engine(engine, dev_priv, id) { 1969 struct intel_context *ce = &ctx->engine[engine->id]; 1970 1971 seq_printf(m, "%s: ", engine->name); 1972 seq_putc(m, ce->initialised ? 'I' : 'i'); 1973 if (ce->state) 1974 describe_obj(m, ce->state->obj); 1975 if (ce->ring) 1976 describe_ctx_ring(m, ce->ring); 1977 seq_putc(m, '\n'); 1978 } 1979 1980 seq_putc(m, '\n'); 1981 } 1982 1983 mutex_unlock(&dev->struct_mutex); 1984 1985 return 0; 1986 } 1987 1988 static void i915_dump_lrc_obj(struct seq_file *m, 1989 struct i915_gem_context *ctx, 1990 struct intel_engine_cs *engine) 1991 { 1992 struct i915_vma *vma = ctx->engine[engine->id].state; 1993 struct page *page; 1994 int j; 1995 1996 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id); 1997 1998 if (!vma) { 1999 seq_puts(m, "\tFake context\n"); 2000 return; 2001 } 2002 2003 if (vma->flags & I915_VMA_GLOBAL_BIND) 2004 seq_printf(m, "\tBound in GGTT at 0x%08x\n", 2005 i915_ggtt_offset(vma)); 2006 2007 if (i915_gem_object_pin_pages(vma->obj)) { 2008 seq_puts(m, "\tFailed to get pages for context object\n\n"); 2009 return; 2010 } 2011 2012 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN); 2013 if (page) { 2014 u32 *reg_state = kmap_atomic(page); 2015 2016 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { 2017 seq_printf(m, 2018 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n", 2019 j * 4, 2020 reg_state[j], reg_state[j + 1], 2021 reg_state[j + 2], reg_state[j + 3]); 2022 } 2023 kunmap_atomic(reg_state); 2024 } 2025 2026 i915_gem_object_unpin_pages(vma->obj); 2027 seq_putc(m, '\n'); 2028 } 2029 2030 static int i915_dump_lrc(struct seq_file *m, void *unused) 2031 { 2032 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2033 struct drm_device *dev = &dev_priv->drm; 2034 struct intel_engine_cs *engine; 2035 struct i915_gem_context *ctx; 2036 enum intel_engine_id id; 2037 int ret; 2038 2039 if (!i915.enable_execlists) { 2040 seq_printf(m, "Logical Ring Contexts are disabled\n"); 2041 return 0; 2042 } 2043 2044 ret = mutex_lock_interruptible(&dev->struct_mutex); 2045 if (ret) 2046 return ret; 2047 2048 list_for_each_entry(ctx, &dev_priv->context_list, link) 2049 for_each_engine(engine, dev_priv, id) 2050 i915_dump_lrc_obj(m, ctx, engine); 2051 2052 mutex_unlock(&dev->struct_mutex); 2053 2054 return 0; 2055 } 2056 2057 static const char *swizzle_string(unsigned swizzle) 2058 { 2059 switch (swizzle) { 2060 case I915_BIT_6_SWIZZLE_NONE: 2061 return "none"; 2062 case I915_BIT_6_SWIZZLE_9: 2063 return "bit9"; 2064 case I915_BIT_6_SWIZZLE_9_10: 2065 return "bit9/bit10"; 2066 case I915_BIT_6_SWIZZLE_9_11: 2067 return "bit9/bit11"; 2068 case I915_BIT_6_SWIZZLE_9_10_11: 2069 return "bit9/bit10/bit11"; 2070 case I915_BIT_6_SWIZZLE_9_17: 2071 return "bit9/bit17"; 2072 case I915_BIT_6_SWIZZLE_9_10_17: 2073 return "bit9/bit10/bit17"; 2074 case I915_BIT_6_SWIZZLE_UNKNOWN: 2075 return "unknown"; 2076 } 2077 2078 return "bug"; 2079 } 2080 2081 static int i915_swizzle_info(struct seq_file *m, void *data) 2082 { 2083 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2084 2085 intel_runtime_pm_get(dev_priv); 2086 2087 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 2088 swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 2089 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 2090 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 2091 2092 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { 2093 seq_printf(m, "DDC = 0x%08x\n", 2094 I915_READ(DCC)); 2095 seq_printf(m, "DDC2 = 0x%08x\n", 2096 I915_READ(DCC2)); 2097 seq_printf(m, "C0DRB3 = 0x%04x\n", 2098 I915_READ16(C0DRB3)); 2099 seq_printf(m, "C1DRB3 = 0x%04x\n", 2100 I915_READ16(C1DRB3)); 2101 } else if (INTEL_GEN(dev_priv) >= 6) { 2102 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 2103 I915_READ(MAD_DIMM_C0)); 2104 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 2105 I915_READ(MAD_DIMM_C1)); 2106 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 2107 I915_READ(MAD_DIMM_C2)); 2108 seq_printf(m, "TILECTL = 0x%08x\n", 2109 I915_READ(TILECTL)); 2110 if (INTEL_GEN(dev_priv) >= 8) 2111 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 2112 I915_READ(GAMTARBMODE)); 2113 else 2114 seq_printf(m, "ARB_MODE = 0x%08x\n", 2115 I915_READ(ARB_MODE)); 2116 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 2117 I915_READ(DISP_ARB_CTL)); 2118 } 2119 2120 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 2121 seq_puts(m, "L-shaped memory detected\n"); 2122 2123 intel_runtime_pm_put(dev_priv); 2124 2125 return 0; 2126 } 2127 2128 static int per_file_ctx(int id, void *ptr, void *data) 2129 { 2130 struct i915_gem_context *ctx = ptr; 2131 struct seq_file *m = data; 2132 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 2133 2134 if (!ppgtt) { 2135 seq_printf(m, " no ppgtt for context %d\n", 2136 ctx->user_handle); 2137 return 0; 2138 } 2139 2140 if (i915_gem_context_is_default(ctx)) 2141 seq_puts(m, " default context:\n"); 2142 else 2143 seq_printf(m, " context %d:\n", ctx->user_handle); 2144 ppgtt->debug_dump(ppgtt, m); 2145 2146 return 0; 2147 } 2148 2149 static void gen8_ppgtt_info(struct seq_file *m, 2150 struct drm_i915_private *dev_priv) 2151 { 2152 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2153 struct intel_engine_cs *engine; 2154 enum intel_engine_id id; 2155 int i; 2156 2157 if (!ppgtt) 2158 return; 2159 2160 for_each_engine(engine, dev_priv, id) { 2161 seq_printf(m, "%s\n", engine->name); 2162 for (i = 0; i < 4; i++) { 2163 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i)); 2164 pdp <<= 32; 2165 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i)); 2166 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); 2167 } 2168 } 2169 } 2170 2171 static void gen6_ppgtt_info(struct seq_file *m, 2172 struct drm_i915_private *dev_priv) 2173 { 2174 struct intel_engine_cs *engine; 2175 enum intel_engine_id id; 2176 2177 if (IS_GEN6(dev_priv)) 2178 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 2179 2180 for_each_engine(engine, dev_priv, id) { 2181 seq_printf(m, "%s\n", engine->name); 2182 if (IS_GEN7(dev_priv)) 2183 seq_printf(m, "GFX_MODE: 0x%08x\n", 2184 I915_READ(RING_MODE_GEN7(engine))); 2185 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", 2186 I915_READ(RING_PP_DIR_BASE(engine))); 2187 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", 2188 I915_READ(RING_PP_DIR_BASE_READ(engine))); 2189 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", 2190 I915_READ(RING_PP_DIR_DCLV(engine))); 2191 } 2192 if (dev_priv->mm.aliasing_ppgtt) { 2193 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2194 2195 seq_puts(m, "aliasing PPGTT:\n"); 2196 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); 2197 2198 ppgtt->debug_dump(ppgtt, m); 2199 } 2200 2201 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 2202 } 2203 2204 static int i915_ppgtt_info(struct seq_file *m, void *data) 2205 { 2206 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2207 struct drm_device *dev = &dev_priv->drm; 2208 struct drm_file *file; 2209 int ret; 2210 2211 mutex_lock(&dev->filelist_mutex); 2212 ret = mutex_lock_interruptible(&dev->struct_mutex); 2213 if (ret) 2214 goto out_unlock; 2215 2216 intel_runtime_pm_get(dev_priv); 2217 2218 if (INTEL_GEN(dev_priv) >= 8) 2219 gen8_ppgtt_info(m, dev_priv); 2220 else if (INTEL_GEN(dev_priv) >= 6) 2221 gen6_ppgtt_info(m, dev_priv); 2222 2223 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2224 struct drm_i915_file_private *file_priv = file->driver_priv; 2225 struct task_struct *task; 2226 2227 task = get_pid_task(file->pid, PIDTYPE_PID); 2228 if (!task) { 2229 ret = -ESRCH; 2230 goto out_rpm; 2231 } 2232 seq_printf(m, "\nproc: %s\n", task->comm); 2233 put_task_struct(task); 2234 idr_for_each(&file_priv->context_idr, per_file_ctx, 2235 (void *)(unsigned long)m); 2236 } 2237 2238 out_rpm: 2239 intel_runtime_pm_put(dev_priv); 2240 mutex_unlock(&dev->struct_mutex); 2241 out_unlock: 2242 mutex_unlock(&dev->filelist_mutex); 2243 return ret; 2244 } 2245 2246 static int count_irq_waiters(struct drm_i915_private *i915) 2247 { 2248 struct intel_engine_cs *engine; 2249 enum intel_engine_id id; 2250 int count = 0; 2251 2252 for_each_engine(engine, i915, id) 2253 count += intel_engine_has_waiter(engine); 2254 2255 return count; 2256 } 2257 2258 static const char *rps_power_to_str(unsigned int power) 2259 { 2260 static const char * const strings[] = { 2261 [LOW_POWER] = "low power", 2262 [BETWEEN] = "mixed", 2263 [HIGH_POWER] = "high power", 2264 }; 2265 2266 if (power >= ARRAY_SIZE(strings) || !strings[power]) 2267 return "unknown"; 2268 2269 return strings[power]; 2270 } 2271 2272 static int i915_rps_boost_info(struct seq_file *m, void *data) 2273 { 2274 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2275 struct drm_device *dev = &dev_priv->drm; 2276 struct drm_file *file; 2277 2278 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); 2279 seq_printf(m, "GPU busy? %s [%d requests]\n", 2280 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests); 2281 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); 2282 seq_printf(m, "Frequency requested %d\n", 2283 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 2284 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 2285 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 2286 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), 2287 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), 2288 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 2289 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 2290 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq), 2291 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 2292 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq)); 2293 2294 mutex_lock(&dev->filelist_mutex); 2295 spin_lock(&dev_priv->rps.client_lock); 2296 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2297 struct drm_i915_file_private *file_priv = file->driver_priv; 2298 struct task_struct *task; 2299 2300 rcu_read_lock(); 2301 task = pid_task(file->pid, PIDTYPE_PID); 2302 seq_printf(m, "%s [%d]: %d boosts%s\n", 2303 task ? task->comm : "<unknown>", 2304 task ? task->pid : -1, 2305 file_priv->rps.boosts, 2306 list_empty(&file_priv->rps.link) ? "" : ", active"); 2307 rcu_read_unlock(); 2308 } 2309 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts); 2310 spin_unlock(&dev_priv->rps.client_lock); 2311 mutex_unlock(&dev->filelist_mutex); 2312 2313 if (INTEL_GEN(dev_priv) >= 6 && 2314 dev_priv->rps.enabled && 2315 dev_priv->gt.active_requests) { 2316 u32 rpup, rpupei; 2317 u32 rpdown, rpdownei; 2318 2319 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 2320 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; 2321 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; 2322 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; 2323 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; 2324 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 2325 2326 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", 2327 rps_power_to_str(dev_priv->rps.power)); 2328 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", 2329 100 * rpup / rpupei, 2330 dev_priv->rps.up_threshold); 2331 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", 2332 100 * rpdown / rpdownei, 2333 dev_priv->rps.down_threshold); 2334 } else { 2335 seq_puts(m, "\nRPS Autotuning inactive\n"); 2336 } 2337 2338 return 0; 2339 } 2340 2341 static int i915_llc(struct seq_file *m, void *data) 2342 { 2343 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2344 const bool edram = INTEL_GEN(dev_priv) > 8; 2345 2346 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); 2347 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", 2348 intel_uncore_edram_size(dev_priv)/1024/1024); 2349 2350 return 0; 2351 } 2352 2353 static int i915_guc_load_status_info(struct seq_file *m, void *data) 2354 { 2355 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2356 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; 2357 u32 tmp, i; 2358 2359 if (!HAS_GUC_UCODE(dev_priv)) 2360 return 0; 2361 2362 seq_printf(m, "GuC firmware status:\n"); 2363 seq_printf(m, "\tpath: %s\n", 2364 guc_fw->guc_fw_path); 2365 seq_printf(m, "\tfetch: %s\n", 2366 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); 2367 seq_printf(m, "\tload: %s\n", 2368 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); 2369 seq_printf(m, "\tversion wanted: %d.%d\n", 2370 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); 2371 seq_printf(m, "\tversion found: %d.%d\n", 2372 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); 2373 seq_printf(m, "\theader: offset is %d; size = %d\n", 2374 guc_fw->header_offset, guc_fw->header_size); 2375 seq_printf(m, "\tuCode: offset is %d; size = %d\n", 2376 guc_fw->ucode_offset, guc_fw->ucode_size); 2377 seq_printf(m, "\tRSA: offset is %d; size = %d\n", 2378 guc_fw->rsa_offset, guc_fw->rsa_size); 2379 2380 tmp = I915_READ(GUC_STATUS); 2381 2382 seq_printf(m, "\nGuC status 0x%08x:\n", tmp); 2383 seq_printf(m, "\tBootrom status = 0x%x\n", 2384 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); 2385 seq_printf(m, "\tuKernel status = 0x%x\n", 2386 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); 2387 seq_printf(m, "\tMIA Core status = 0x%x\n", 2388 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); 2389 seq_puts(m, "\nScratch registers:\n"); 2390 for (i = 0; i < 16; i++) 2391 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); 2392 2393 return 0; 2394 } 2395 2396 static void i915_guc_log_info(struct seq_file *m, 2397 struct drm_i915_private *dev_priv) 2398 { 2399 struct intel_guc *guc = &dev_priv->guc; 2400 2401 seq_puts(m, "\nGuC logging stats:\n"); 2402 2403 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n", 2404 guc->log.flush_count[GUC_ISR_LOG_BUFFER], 2405 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]); 2406 2407 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n", 2408 guc->log.flush_count[GUC_DPC_LOG_BUFFER], 2409 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]); 2410 2411 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n", 2412 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER], 2413 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]); 2414 2415 seq_printf(m, "\tTotal flush interrupt count: %u\n", 2416 guc->log.flush_interrupt_count); 2417 2418 seq_printf(m, "\tCapture miss count: %u\n", 2419 guc->log.capture_miss_count); 2420 } 2421 2422 static void i915_guc_client_info(struct seq_file *m, 2423 struct drm_i915_private *dev_priv, 2424 struct i915_guc_client *client) 2425 { 2426 struct intel_engine_cs *engine; 2427 enum intel_engine_id id; 2428 uint64_t tot = 0; 2429 2430 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", 2431 client->priority, client->ctx_index, client->proc_desc_offset); 2432 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", 2433 client->doorbell_id, client->doorbell_offset, client->cookie); 2434 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", 2435 client->wq_size, client->wq_offset, client->wq_tail); 2436 2437 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space); 2438 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); 2439 seq_printf(m, "\tLast submission result: %d\n", client->retcode); 2440 2441 for_each_engine(engine, dev_priv, id) { 2442 u64 submissions = client->submissions[id]; 2443 tot += submissions; 2444 seq_printf(m, "\tSubmissions: %llu %s\n", 2445 submissions, engine->name); 2446 } 2447 seq_printf(m, "\tTotal: %llu\n", tot); 2448 } 2449 2450 static int i915_guc_info(struct seq_file *m, void *data) 2451 { 2452 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2453 struct drm_device *dev = &dev_priv->drm; 2454 struct intel_guc guc; 2455 struct i915_guc_client client = {}; 2456 struct intel_engine_cs *engine; 2457 enum intel_engine_id id; 2458 u64 total = 0; 2459 2460 if (!HAS_GUC_SCHED(dev_priv)) 2461 return 0; 2462 2463 if (mutex_lock_interruptible(&dev->struct_mutex)) 2464 return 0; 2465 2466 /* Take a local copy of the GuC data, so we can dump it at leisure */ 2467 guc = dev_priv->guc; 2468 if (guc.execbuf_client) 2469 client = *guc.execbuf_client; 2470 2471 mutex_unlock(&dev->struct_mutex); 2472 2473 seq_printf(m, "Doorbell map:\n"); 2474 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap); 2475 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline); 2476 2477 seq_printf(m, "GuC total action count: %llu\n", guc.action_count); 2478 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); 2479 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); 2480 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); 2481 seq_printf(m, "GuC last action error code: %d\n", guc.action_err); 2482 2483 seq_printf(m, "\nGuC submissions:\n"); 2484 for_each_engine(engine, dev_priv, id) { 2485 u64 submissions = guc.submissions[id]; 2486 total += submissions; 2487 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n", 2488 engine->name, submissions, guc.last_seqno[id]); 2489 } 2490 seq_printf(m, "\t%s: %llu\n", "Total", total); 2491 2492 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); 2493 i915_guc_client_info(m, dev_priv, &client); 2494 2495 i915_guc_log_info(m, dev_priv); 2496 2497 /* Add more as required ... */ 2498 2499 return 0; 2500 } 2501 2502 static int i915_guc_log_dump(struct seq_file *m, void *data) 2503 { 2504 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2505 struct drm_i915_gem_object *obj; 2506 int i = 0, pg; 2507 2508 if (!dev_priv->guc.log.vma) 2509 return 0; 2510 2511 obj = dev_priv->guc.log.vma->obj; 2512 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) { 2513 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg)); 2514 2515 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) 2516 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", 2517 *(log + i), *(log + i + 1), 2518 *(log + i + 2), *(log + i + 3)); 2519 2520 kunmap_atomic(log); 2521 } 2522 2523 seq_putc(m, '\n'); 2524 2525 return 0; 2526 } 2527 2528 static int i915_guc_log_control_get(void *data, u64 *val) 2529 { 2530 struct drm_device *dev = data; 2531 struct drm_i915_private *dev_priv = to_i915(dev); 2532 2533 if (!dev_priv->guc.log.vma) 2534 return -EINVAL; 2535 2536 *val = i915.guc_log_level; 2537 2538 return 0; 2539 } 2540 2541 static int i915_guc_log_control_set(void *data, u64 val) 2542 { 2543 struct drm_device *dev = data; 2544 struct drm_i915_private *dev_priv = to_i915(dev); 2545 int ret; 2546 2547 if (!dev_priv->guc.log.vma) 2548 return -EINVAL; 2549 2550 ret = mutex_lock_interruptible(&dev->struct_mutex); 2551 if (ret) 2552 return ret; 2553 2554 intel_runtime_pm_get(dev_priv); 2555 ret = i915_guc_log_control(dev_priv, val); 2556 intel_runtime_pm_put(dev_priv); 2557 2558 mutex_unlock(&dev->struct_mutex); 2559 return ret; 2560 } 2561 2562 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops, 2563 i915_guc_log_control_get, i915_guc_log_control_set, 2564 "%lld\n"); 2565 2566 static int i915_edp_psr_status(struct seq_file *m, void *data) 2567 { 2568 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2569 u32 psrperf = 0; 2570 u32 stat[3]; 2571 enum pipe pipe; 2572 bool enabled = false; 2573 2574 if (!HAS_PSR(dev_priv)) { 2575 seq_puts(m, "PSR not supported\n"); 2576 return 0; 2577 } 2578 2579 intel_runtime_pm_get(dev_priv); 2580 2581 mutex_lock(&dev_priv->psr.lock); 2582 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); 2583 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); 2584 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); 2585 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); 2586 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", 2587 dev_priv->psr.busy_frontbuffer_bits); 2588 seq_printf(m, "Re-enable work scheduled: %s\n", 2589 yesno(work_busy(&dev_priv->psr.work.work))); 2590 2591 if (HAS_DDI(dev_priv)) 2592 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; 2593 else { 2594 for_each_pipe(dev_priv, pipe) { 2595 enum transcoder cpu_transcoder = 2596 intel_pipe_to_cpu_transcoder(dev_priv, pipe); 2597 enum intel_display_power_domain power_domain; 2598 2599 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); 2600 if (!intel_display_power_get_if_enabled(dev_priv, 2601 power_domain)) 2602 continue; 2603 2604 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & 2605 VLV_EDP_PSR_CURR_STATE_MASK; 2606 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2607 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2608 enabled = true; 2609 2610 intel_display_power_put(dev_priv, power_domain); 2611 } 2612 } 2613 2614 seq_printf(m, "Main link in standby mode: %s\n", 2615 yesno(dev_priv->psr.link_standby)); 2616 2617 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); 2618 2619 if (!HAS_DDI(dev_priv)) 2620 for_each_pipe(dev_priv, pipe) { 2621 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2622 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2623 seq_printf(m, " pipe %c", pipe_name(pipe)); 2624 } 2625 seq_puts(m, "\n"); 2626 2627 /* 2628 * VLV/CHV PSR has no kind of performance counter 2629 * SKL+ Perf counter is reset to 0 everytime DC state is entered 2630 */ 2631 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 2632 psrperf = I915_READ(EDP_PSR_PERF_CNT) & 2633 EDP_PSR_PERF_CNT_MASK; 2634 2635 seq_printf(m, "Performance_Counter: %u\n", psrperf); 2636 } 2637 mutex_unlock(&dev_priv->psr.lock); 2638 2639 intel_runtime_pm_put(dev_priv); 2640 return 0; 2641 } 2642 2643 static int i915_sink_crc(struct seq_file *m, void *data) 2644 { 2645 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2646 struct drm_device *dev = &dev_priv->drm; 2647 struct intel_connector *connector; 2648 struct intel_dp *intel_dp = NULL; 2649 int ret; 2650 u8 crc[6]; 2651 2652 drm_modeset_lock_all(dev); 2653 for_each_intel_connector(dev, connector) { 2654 struct drm_crtc *crtc; 2655 2656 if (!connector->base.state->best_encoder) 2657 continue; 2658 2659 crtc = connector->base.state->crtc; 2660 if (!crtc->state->active) 2661 continue; 2662 2663 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 2664 continue; 2665 2666 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder); 2667 2668 ret = intel_dp_sink_crc(intel_dp, crc); 2669 if (ret) 2670 goto out; 2671 2672 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", 2673 crc[0], crc[1], crc[2], 2674 crc[3], crc[4], crc[5]); 2675 goto out; 2676 } 2677 ret = -ENODEV; 2678 out: 2679 drm_modeset_unlock_all(dev); 2680 return ret; 2681 } 2682 2683 static int i915_energy_uJ(struct seq_file *m, void *data) 2684 { 2685 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2686 u64 power; 2687 u32 units; 2688 2689 if (INTEL_GEN(dev_priv) < 6) 2690 return -ENODEV; 2691 2692 intel_runtime_pm_get(dev_priv); 2693 2694 rdmsrl(MSR_RAPL_POWER_UNIT, power); 2695 power = (power & 0x1f00) >> 8; 2696 units = 1000000 / (1 << power); /* convert to uJ */ 2697 power = I915_READ(MCH_SECP_NRG_STTS); 2698 power *= units; 2699 2700 intel_runtime_pm_put(dev_priv); 2701 2702 seq_printf(m, "%llu", (long long unsigned)power); 2703 2704 return 0; 2705 } 2706 2707 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 2708 { 2709 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2710 struct pci_dev *pdev = dev_priv->drm.pdev; 2711 2712 if (!HAS_RUNTIME_PM(dev_priv)) 2713 seq_puts(m, "Runtime power management not supported\n"); 2714 2715 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); 2716 seq_printf(m, "IRQs disabled: %s\n", 2717 yesno(!intel_irqs_enabled(dev_priv))); 2718 #ifdef CONFIG_PM 2719 seq_printf(m, "Usage count: %d\n", 2720 atomic_read(&dev_priv->drm.dev->power.usage_count)); 2721 #else 2722 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 2723 #endif 2724 seq_printf(m, "PCI device power state: %s [%d]\n", 2725 pci_power_name(pdev->current_state), 2726 pdev->current_state); 2727 2728 return 0; 2729 } 2730 2731 static int i915_power_domain_info(struct seq_file *m, void *unused) 2732 { 2733 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2734 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2735 int i; 2736 2737 mutex_lock(&power_domains->lock); 2738 2739 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2740 for (i = 0; i < power_domains->power_well_count; i++) { 2741 struct i915_power_well *power_well; 2742 enum intel_display_power_domain power_domain; 2743 2744 power_well = &power_domains->power_wells[i]; 2745 seq_printf(m, "%-25s %d\n", power_well->name, 2746 power_well->count); 2747 2748 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; 2749 power_domain++) { 2750 if (!(BIT(power_domain) & power_well->domains)) 2751 continue; 2752 2753 seq_printf(m, " %-23s %d\n", 2754 intel_display_power_domain_str(power_domain), 2755 power_domains->domain_use_count[power_domain]); 2756 } 2757 } 2758 2759 mutex_unlock(&power_domains->lock); 2760 2761 return 0; 2762 } 2763 2764 static int i915_dmc_info(struct seq_file *m, void *unused) 2765 { 2766 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2767 struct intel_csr *csr; 2768 2769 if (!HAS_CSR(dev_priv)) { 2770 seq_puts(m, "not supported\n"); 2771 return 0; 2772 } 2773 2774 csr = &dev_priv->csr; 2775 2776 intel_runtime_pm_get(dev_priv); 2777 2778 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); 2779 seq_printf(m, "path: %s\n", csr->fw_path); 2780 2781 if (!csr->dmc_payload) 2782 goto out; 2783 2784 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), 2785 CSR_VERSION_MINOR(csr->version)); 2786 2787 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) { 2788 seq_printf(m, "DC3 -> DC5 count: %d\n", 2789 I915_READ(SKL_CSR_DC3_DC5_COUNT)); 2790 seq_printf(m, "DC5 -> DC6 count: %d\n", 2791 I915_READ(SKL_CSR_DC5_DC6_COUNT)); 2792 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) { 2793 seq_printf(m, "DC3 -> DC5 count: %d\n", 2794 I915_READ(BXT_CSR_DC3_DC5_COUNT)); 2795 } 2796 2797 out: 2798 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); 2799 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); 2800 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); 2801 2802 intel_runtime_pm_put(dev_priv); 2803 2804 return 0; 2805 } 2806 2807 static void intel_seq_print_mode(struct seq_file *m, int tabs, 2808 struct drm_display_mode *mode) 2809 { 2810 int i; 2811 2812 for (i = 0; i < tabs; i++) 2813 seq_putc(m, '\t'); 2814 2815 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", 2816 mode->base.id, mode->name, 2817 mode->vrefresh, mode->clock, 2818 mode->hdisplay, mode->hsync_start, 2819 mode->hsync_end, mode->htotal, 2820 mode->vdisplay, mode->vsync_start, 2821 mode->vsync_end, mode->vtotal, 2822 mode->type, mode->flags); 2823 } 2824 2825 static void intel_encoder_info(struct seq_file *m, 2826 struct intel_crtc *intel_crtc, 2827 struct intel_encoder *intel_encoder) 2828 { 2829 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2830 struct drm_device *dev = &dev_priv->drm; 2831 struct drm_crtc *crtc = &intel_crtc->base; 2832 struct intel_connector *intel_connector; 2833 struct drm_encoder *encoder; 2834 2835 encoder = &intel_encoder->base; 2836 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", 2837 encoder->base.id, encoder->name); 2838 for_each_connector_on_encoder(dev, encoder, intel_connector) { 2839 struct drm_connector *connector = &intel_connector->base; 2840 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", 2841 connector->base.id, 2842 connector->name, 2843 drm_get_connector_status_name(connector->status)); 2844 if (connector->status == connector_status_connected) { 2845 struct drm_display_mode *mode = &crtc->mode; 2846 seq_printf(m, ", mode:\n"); 2847 intel_seq_print_mode(m, 2, mode); 2848 } else { 2849 seq_putc(m, '\n'); 2850 } 2851 } 2852 } 2853 2854 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2855 { 2856 struct drm_i915_private *dev_priv = node_to_i915(m->private); 2857 struct drm_device *dev = &dev_priv->drm; 2858 struct drm_crtc *crtc = &intel_crtc->base; 2859 struct intel_encoder *intel_encoder; 2860 struct drm_plane_state *plane_state = crtc->primary->state; 2861 struct drm_framebuffer *fb = plane_state->fb; 2862 2863 if (fb) 2864 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", 2865 fb->base.id, plane_state->src_x >> 16, 2866 plane_state->src_y >> 16, fb->width, fb->height); 2867 else 2868 seq_puts(m, "\tprimary plane disabled\n"); 2869 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 2870 intel_encoder_info(m, intel_crtc, intel_encoder); 2871 } 2872 2873 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) 2874 { 2875 struct drm_display_mode *mode = panel->fixed_mode; 2876 2877 seq_printf(m, "\tfixed mode:\n"); 2878 intel_seq_print_mode(m, 2, mode); 2879 } 2880 2881 static void intel_dp_info(struct seq_file *m, 2882 struct intel_connector *intel_connector) 2883 { 2884 struct intel_encoder *intel_encoder = intel_connector->encoder; 2885 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2886 2887 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 2888 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); 2889 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) 2890 intel_panel_info(m, &intel_connector->panel); 2891 2892 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, 2893 &intel_dp->aux); 2894 } 2895 2896 static void intel_hdmi_info(struct seq_file *m, 2897 struct intel_connector *intel_connector) 2898 { 2899 struct intel_encoder *intel_encoder = intel_connector->encoder; 2900 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 2901 2902 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); 2903 } 2904 2905 static void intel_lvds_info(struct seq_file *m, 2906 struct intel_connector *intel_connector) 2907 { 2908 intel_panel_info(m, &intel_connector->panel); 2909 } 2910 2911 static void intel_connector_info(struct seq_file *m, 2912 struct drm_connector *connector) 2913 { 2914 struct intel_connector *intel_connector = to_intel_connector(connector); 2915 struct intel_encoder *intel_encoder = intel_connector->encoder; 2916 struct drm_display_mode *mode; 2917 2918 seq_printf(m, "connector %d: type %s, status: %s\n", 2919 connector->base.id, connector->name, 2920 drm_get_connector_status_name(connector->status)); 2921 if (connector->status == connector_status_connected) { 2922 seq_printf(m, "\tname: %s\n", connector->display_info.name); 2923 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 2924 connector->display_info.width_mm, 2925 connector->display_info.height_mm); 2926 seq_printf(m, "\tsubpixel order: %s\n", 2927 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 2928 seq_printf(m, "\tCEA rev: %d\n", 2929 connector->display_info.cea_rev); 2930 } 2931 2932 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 2933 return; 2934 2935 switch (connector->connector_type) { 2936 case DRM_MODE_CONNECTOR_DisplayPort: 2937 case DRM_MODE_CONNECTOR_eDP: 2938 intel_dp_info(m, intel_connector); 2939 break; 2940 case DRM_MODE_CONNECTOR_LVDS: 2941 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 2942 intel_lvds_info(m, intel_connector); 2943 break; 2944 case DRM_MODE_CONNECTOR_HDMIA: 2945 if (intel_encoder->type == INTEL_OUTPUT_HDMI || 2946 intel_encoder->type == INTEL_OUTPUT_UNKNOWN) 2947 intel_hdmi_info(m, intel_connector); 2948 break; 2949 default: 2950 break; 2951 } 2952 2953 seq_printf(m, "\tmodes:\n"); 2954 list_for_each_entry(mode, &connector->modes, head) 2955 intel_seq_print_mode(m, 2, mode); 2956 } 2957 2958 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe) 2959 { 2960 u32 state; 2961 2962 if (IS_845G(dev_priv) || IS_I865G(dev_priv)) 2963 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; 2964 else 2965 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 2966 2967 return state; 2968 } 2969 2970 static bool cursor_position(struct drm_i915_private *dev_priv, 2971 int pipe, int *x, int *y) 2972 { 2973 u32 pos; 2974 2975 pos = I915_READ(CURPOS(pipe)); 2976 2977 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; 2978 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) 2979 *x = -*x; 2980 2981 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; 2982 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) 2983 *y = -*y; 2984 2985 return cursor_active(dev_priv, pipe); 2986 } 2987 2988 static const char *plane_type(enum drm_plane_type type) 2989 { 2990 switch (type) { 2991 case DRM_PLANE_TYPE_OVERLAY: 2992 return "OVL"; 2993 case DRM_PLANE_TYPE_PRIMARY: 2994 return "PRI"; 2995 case DRM_PLANE_TYPE_CURSOR: 2996 return "CUR"; 2997 /* 2998 * Deliberately omitting default: to generate compiler warnings 2999 * when a new drm_plane_type gets added. 3000 */ 3001 } 3002 3003 return "unknown"; 3004 } 3005 3006 static const char *plane_rotation(unsigned int rotation) 3007 { 3008 static char buf[48]; 3009 /* 3010 * According to doc only one DRM_ROTATE_ is allowed but this 3011 * will print them all to visualize if the values are misused 3012 */ 3013 snprintf(buf, sizeof(buf), 3014 "%s%s%s%s%s%s(0x%08x)", 3015 (rotation & DRM_ROTATE_0) ? "0 " : "", 3016 (rotation & DRM_ROTATE_90) ? "90 " : "", 3017 (rotation & DRM_ROTATE_180) ? "180 " : "", 3018 (rotation & DRM_ROTATE_270) ? "270 " : "", 3019 (rotation & DRM_REFLECT_X) ? "FLIPX " : "", 3020 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "", 3021 rotation); 3022 3023 return buf; 3024 } 3025 3026 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) 3027 { 3028 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3029 struct drm_device *dev = &dev_priv->drm; 3030 struct intel_plane *intel_plane; 3031 3032 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 3033 struct drm_plane_state *state; 3034 struct drm_plane *plane = &intel_plane->base; 3035 char *format_name; 3036 3037 if (!plane->state) { 3038 seq_puts(m, "plane->state is NULL!\n"); 3039 continue; 3040 } 3041 3042 state = plane->state; 3043 3044 if (state->fb) { 3045 format_name = drm_get_format_name(state->fb->pixel_format); 3046 } else { 3047 format_name = kstrdup("N/A", GFP_KERNEL); 3048 } 3049 3050 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", 3051 plane->base.id, 3052 plane_type(intel_plane->base.type), 3053 state->crtc_x, state->crtc_y, 3054 state->crtc_w, state->crtc_h, 3055 (state->src_x >> 16), 3056 ((state->src_x & 0xffff) * 15625) >> 10, 3057 (state->src_y >> 16), 3058 ((state->src_y & 0xffff) * 15625) >> 10, 3059 (state->src_w >> 16), 3060 ((state->src_w & 0xffff) * 15625) >> 10, 3061 (state->src_h >> 16), 3062 ((state->src_h & 0xffff) * 15625) >> 10, 3063 format_name, 3064 plane_rotation(state->rotation)); 3065 3066 kfree(format_name); 3067 } 3068 } 3069 3070 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) 3071 { 3072 struct intel_crtc_state *pipe_config; 3073 int num_scalers = intel_crtc->num_scalers; 3074 int i; 3075 3076 pipe_config = to_intel_crtc_state(intel_crtc->base.state); 3077 3078 /* Not all platformas have a scaler */ 3079 if (num_scalers) { 3080 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", 3081 num_scalers, 3082 pipe_config->scaler_state.scaler_users, 3083 pipe_config->scaler_state.scaler_id); 3084 3085 for (i = 0; i < SKL_NUM_SCALERS; i++) { 3086 struct intel_scaler *sc = 3087 &pipe_config->scaler_state.scalers[i]; 3088 3089 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 3090 i, yesno(sc->in_use), sc->mode); 3091 } 3092 seq_puts(m, "\n"); 3093 } else { 3094 seq_puts(m, "\tNo scalers available on this platform\n"); 3095 } 3096 } 3097 3098 static int i915_display_info(struct seq_file *m, void *unused) 3099 { 3100 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3101 struct drm_device *dev = &dev_priv->drm; 3102 struct intel_crtc *crtc; 3103 struct drm_connector *connector; 3104 3105 intel_runtime_pm_get(dev_priv); 3106 drm_modeset_lock_all(dev); 3107 seq_printf(m, "CRTC info\n"); 3108 seq_printf(m, "---------\n"); 3109 for_each_intel_crtc(dev, crtc) { 3110 bool active; 3111 struct intel_crtc_state *pipe_config; 3112 int x, y; 3113 3114 pipe_config = to_intel_crtc_state(crtc->base.state); 3115 3116 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", 3117 crtc->base.base.id, pipe_name(crtc->pipe), 3118 yesno(pipe_config->base.active), 3119 pipe_config->pipe_src_w, pipe_config->pipe_src_h, 3120 yesno(pipe_config->dither), pipe_config->pipe_bpp); 3121 3122 if (pipe_config->base.active) { 3123 intel_crtc_info(m, crtc); 3124 3125 active = cursor_position(dev_priv, crtc->pipe, &x, &y); 3126 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", 3127 yesno(crtc->cursor_base), 3128 x, y, crtc->base.cursor->state->crtc_w, 3129 crtc->base.cursor->state->crtc_h, 3130 crtc->cursor_addr, yesno(active)); 3131 intel_scaler_info(m, crtc); 3132 intel_plane_info(m, crtc); 3133 } 3134 3135 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", 3136 yesno(!crtc->cpu_fifo_underrun_disabled), 3137 yesno(!crtc->pch_fifo_underrun_disabled)); 3138 } 3139 3140 seq_printf(m, "\n"); 3141 seq_printf(m, "Connector info\n"); 3142 seq_printf(m, "--------------\n"); 3143 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3144 intel_connector_info(m, connector); 3145 } 3146 drm_modeset_unlock_all(dev); 3147 intel_runtime_pm_put(dev_priv); 3148 3149 return 0; 3150 } 3151 3152 static int i915_engine_info(struct seq_file *m, void *unused) 3153 { 3154 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3155 struct intel_engine_cs *engine; 3156 enum intel_engine_id id; 3157 3158 intel_runtime_pm_get(dev_priv); 3159 3160 for_each_engine(engine, dev_priv, id) { 3161 struct intel_breadcrumbs *b = &engine->breadcrumbs; 3162 struct drm_i915_gem_request *rq; 3163 struct rb_node *rb; 3164 u64 addr; 3165 3166 seq_printf(m, "%s\n", engine->name); 3167 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n", 3168 intel_engine_get_seqno(engine), 3169 intel_engine_last_submit(engine), 3170 engine->hangcheck.seqno, 3171 engine->hangcheck.score); 3172 3173 rcu_read_lock(); 3174 3175 seq_printf(m, "\tRequests:\n"); 3176 3177 rq = list_first_entry(&engine->timeline->requests, 3178 struct drm_i915_gem_request, link); 3179 if (&rq->link != &engine->timeline->requests) 3180 print_request(m, rq, "\t\tfirst "); 3181 3182 rq = list_last_entry(&engine->timeline->requests, 3183 struct drm_i915_gem_request, link); 3184 if (&rq->link != &engine->timeline->requests) 3185 print_request(m, rq, "\t\tlast "); 3186 3187 rq = i915_gem_find_active_request(engine); 3188 if (rq) { 3189 print_request(m, rq, "\t\tactive "); 3190 seq_printf(m, 3191 "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n", 3192 rq->head, rq->postfix, rq->tail, 3193 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u, 3194 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u); 3195 } 3196 3197 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n", 3198 I915_READ(RING_START(engine->mmio_base)), 3199 rq ? i915_ggtt_offset(rq->ring->vma) : 0); 3200 seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n", 3201 I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR, 3202 rq ? rq->ring->head : 0); 3203 seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n", 3204 I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR, 3205 rq ? rq->ring->tail : 0); 3206 seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n", 3207 I915_READ(RING_CTL(engine->mmio_base)), 3208 I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : ""); 3209 3210 rcu_read_unlock(); 3211 3212 addr = intel_engine_get_active_head(engine); 3213 seq_printf(m, "\tACTHD: 0x%08x_%08x\n", 3214 upper_32_bits(addr), lower_32_bits(addr)); 3215 addr = intel_engine_get_last_batch_head(engine); 3216 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n", 3217 upper_32_bits(addr), lower_32_bits(addr)); 3218 3219 if (i915.enable_execlists) { 3220 u32 ptr, read, write; 3221 3222 seq_printf(m, "\tExeclist status: 0x%08x %08x\n", 3223 I915_READ(RING_EXECLIST_STATUS_LO(engine)), 3224 I915_READ(RING_EXECLIST_STATUS_HI(engine))); 3225 3226 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine)); 3227 read = GEN8_CSB_READ_PTR(ptr); 3228 write = GEN8_CSB_WRITE_PTR(ptr); 3229 seq_printf(m, "\tExeclist CSB read %d, write %d\n", 3230 read, write); 3231 if (read >= GEN8_CSB_ENTRIES) 3232 read = 0; 3233 if (write >= GEN8_CSB_ENTRIES) 3234 write = 0; 3235 if (read > write) 3236 write += GEN8_CSB_ENTRIES; 3237 while (read < write) { 3238 unsigned int idx = ++read % GEN8_CSB_ENTRIES; 3239 3240 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n", 3241 idx, 3242 I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)), 3243 I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx))); 3244 } 3245 3246 rcu_read_lock(); 3247 rq = READ_ONCE(engine->execlist_port[0].request); 3248 if (rq) 3249 print_request(m, rq, "\t\tELSP[0] "); 3250 else 3251 seq_printf(m, "\t\tELSP[0] idle\n"); 3252 rq = READ_ONCE(engine->execlist_port[1].request); 3253 if (rq) 3254 print_request(m, rq, "\t\tELSP[1] "); 3255 else 3256 seq_printf(m, "\t\tELSP[1] idle\n"); 3257 rcu_read_unlock(); 3258 3259 spin_lock_irq(&engine->execlist_lock); 3260 list_for_each_entry(rq, &engine->execlist_queue, execlist_link) { 3261 print_request(m, rq, "\t\tQ "); 3262 } 3263 spin_unlock_irq(&engine->execlist_lock); 3264 } else if (INTEL_GEN(dev_priv) > 6) { 3265 seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n", 3266 I915_READ(RING_PP_DIR_BASE(engine))); 3267 seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", 3268 I915_READ(RING_PP_DIR_BASE_READ(engine))); 3269 seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n", 3270 I915_READ(RING_PP_DIR_DCLV(engine))); 3271 } 3272 3273 spin_lock_irq(&b->lock); 3274 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) { 3275 struct intel_wait *w = container_of(rb, typeof(*w), node); 3276 3277 seq_printf(m, "\t%s [%d] waiting for %x\n", 3278 w->tsk->comm, w->tsk->pid, w->seqno); 3279 } 3280 spin_unlock_irq(&b->lock); 3281 3282 seq_puts(m, "\n"); 3283 } 3284 3285 intel_runtime_pm_put(dev_priv); 3286 3287 return 0; 3288 } 3289 3290 static int i915_semaphore_status(struct seq_file *m, void *unused) 3291 { 3292 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3293 struct drm_device *dev = &dev_priv->drm; 3294 struct intel_engine_cs *engine; 3295 int num_rings = INTEL_INFO(dev_priv)->num_rings; 3296 enum intel_engine_id id; 3297 int j, ret; 3298 3299 if (!i915.semaphores) { 3300 seq_puts(m, "Semaphores are disabled\n"); 3301 return 0; 3302 } 3303 3304 ret = mutex_lock_interruptible(&dev->struct_mutex); 3305 if (ret) 3306 return ret; 3307 intel_runtime_pm_get(dev_priv); 3308 3309 if (IS_BROADWELL(dev_priv)) { 3310 struct page *page; 3311 uint64_t *seqno; 3312 3313 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0); 3314 3315 seqno = (uint64_t *)kmap_atomic(page); 3316 for_each_engine(engine, dev_priv, id) { 3317 uint64_t offset; 3318 3319 seq_printf(m, "%s\n", engine->name); 3320 3321 seq_puts(m, " Last signal:"); 3322 for (j = 0; j < num_rings; j++) { 3323 offset = id * I915_NUM_ENGINES + j; 3324 seq_printf(m, "0x%08llx (0x%02llx) ", 3325 seqno[offset], offset * 8); 3326 } 3327 seq_putc(m, '\n'); 3328 3329 seq_puts(m, " Last wait: "); 3330 for (j = 0; j < num_rings; j++) { 3331 offset = id + (j * I915_NUM_ENGINES); 3332 seq_printf(m, "0x%08llx (0x%02llx) ", 3333 seqno[offset], offset * 8); 3334 } 3335 seq_putc(m, '\n'); 3336 3337 } 3338 kunmap_atomic(seqno); 3339 } else { 3340 seq_puts(m, " Last signal:"); 3341 for_each_engine(engine, dev_priv, id) 3342 for (j = 0; j < num_rings; j++) 3343 seq_printf(m, "0x%08x\n", 3344 I915_READ(engine->semaphore.mbox.signal[j])); 3345 seq_putc(m, '\n'); 3346 } 3347 3348 intel_runtime_pm_put(dev_priv); 3349 mutex_unlock(&dev->struct_mutex); 3350 return 0; 3351 } 3352 3353 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 3354 { 3355 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3356 struct drm_device *dev = &dev_priv->drm; 3357 int i; 3358 3359 drm_modeset_lock_all(dev); 3360 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 3361 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 3362 3363 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); 3364 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", 3365 pll->config.crtc_mask, pll->active_mask, yesno(pll->on)); 3366 seq_printf(m, " tracked hardware state:\n"); 3367 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); 3368 seq_printf(m, " dpll_md: 0x%08x\n", 3369 pll->config.hw_state.dpll_md); 3370 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); 3371 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); 3372 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); 3373 } 3374 drm_modeset_unlock_all(dev); 3375 3376 return 0; 3377 } 3378 3379 static int i915_wa_registers(struct seq_file *m, void *unused) 3380 { 3381 int i; 3382 int ret; 3383 struct intel_engine_cs *engine; 3384 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3385 struct drm_device *dev = &dev_priv->drm; 3386 struct i915_workarounds *workarounds = &dev_priv->workarounds; 3387 enum intel_engine_id id; 3388 3389 ret = mutex_lock_interruptible(&dev->struct_mutex); 3390 if (ret) 3391 return ret; 3392 3393 intel_runtime_pm_get(dev_priv); 3394 3395 seq_printf(m, "Workarounds applied: %d\n", workarounds->count); 3396 for_each_engine(engine, dev_priv, id) 3397 seq_printf(m, "HW whitelist count for %s: %d\n", 3398 engine->name, workarounds->hw_whitelist_count[id]); 3399 for (i = 0; i < workarounds->count; ++i) { 3400 i915_reg_t addr; 3401 u32 mask, value, read; 3402 bool ok; 3403 3404 addr = workarounds->reg[i].addr; 3405 mask = workarounds->reg[i].mask; 3406 value = workarounds->reg[i].value; 3407 read = I915_READ(addr); 3408 ok = (value & mask) == (read & mask); 3409 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", 3410 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); 3411 } 3412 3413 intel_runtime_pm_put(dev_priv); 3414 mutex_unlock(&dev->struct_mutex); 3415 3416 return 0; 3417 } 3418 3419 static int i915_ddb_info(struct seq_file *m, void *unused) 3420 { 3421 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3422 struct drm_device *dev = &dev_priv->drm; 3423 struct skl_ddb_allocation *ddb; 3424 struct skl_ddb_entry *entry; 3425 enum pipe pipe; 3426 int plane; 3427 3428 if (INTEL_GEN(dev_priv) < 9) 3429 return 0; 3430 3431 drm_modeset_lock_all(dev); 3432 3433 ddb = &dev_priv->wm.skl_hw.ddb; 3434 3435 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 3436 3437 for_each_pipe(dev_priv, pipe) { 3438 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 3439 3440 for_each_universal_plane(dev_priv, pipe, plane) { 3441 entry = &ddb->plane[pipe][plane]; 3442 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, 3443 entry->start, entry->end, 3444 skl_ddb_entry_size(entry)); 3445 } 3446 3447 entry = &ddb->plane[pipe][PLANE_CURSOR]; 3448 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 3449 entry->end, skl_ddb_entry_size(entry)); 3450 } 3451 3452 drm_modeset_unlock_all(dev); 3453 3454 return 0; 3455 } 3456 3457 static void drrs_status_per_crtc(struct seq_file *m, 3458 struct drm_device *dev, 3459 struct intel_crtc *intel_crtc) 3460 { 3461 struct drm_i915_private *dev_priv = to_i915(dev); 3462 struct i915_drrs *drrs = &dev_priv->drrs; 3463 int vrefresh = 0; 3464 struct drm_connector *connector; 3465 3466 drm_for_each_connector(connector, dev) { 3467 if (connector->state->crtc != &intel_crtc->base) 3468 continue; 3469 3470 seq_printf(m, "%s:\n", connector->name); 3471 } 3472 3473 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) 3474 seq_puts(m, "\tVBT: DRRS_type: Static"); 3475 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) 3476 seq_puts(m, "\tVBT: DRRS_type: Seamless"); 3477 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) 3478 seq_puts(m, "\tVBT: DRRS_type: None"); 3479 else 3480 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); 3481 3482 seq_puts(m, "\n\n"); 3483 3484 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { 3485 struct intel_panel *panel; 3486 3487 mutex_lock(&drrs->mutex); 3488 /* DRRS Supported */ 3489 seq_puts(m, "\tDRRS Supported: Yes\n"); 3490 3491 /* disable_drrs() will make drrs->dp NULL */ 3492 if (!drrs->dp) { 3493 seq_puts(m, "Idleness DRRS: Disabled"); 3494 mutex_unlock(&drrs->mutex); 3495 return; 3496 } 3497 3498 panel = &drrs->dp->attached_connector->panel; 3499 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", 3500 drrs->busy_frontbuffer_bits); 3501 3502 seq_puts(m, "\n\t\t"); 3503 if (drrs->refresh_rate_type == DRRS_HIGH_RR) { 3504 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); 3505 vrefresh = panel->fixed_mode->vrefresh; 3506 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { 3507 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); 3508 vrefresh = panel->downclock_mode->vrefresh; 3509 } else { 3510 seq_printf(m, "DRRS_State: Unknown(%d)\n", 3511 drrs->refresh_rate_type); 3512 mutex_unlock(&drrs->mutex); 3513 return; 3514 } 3515 seq_printf(m, "\t\tVrefresh: %d", vrefresh); 3516 3517 seq_puts(m, "\n\t\t"); 3518 mutex_unlock(&drrs->mutex); 3519 } else { 3520 /* DRRS not supported. Print the VBT parameter*/ 3521 seq_puts(m, "\tDRRS Supported : No"); 3522 } 3523 seq_puts(m, "\n"); 3524 } 3525 3526 static int i915_drrs_status(struct seq_file *m, void *unused) 3527 { 3528 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3529 struct drm_device *dev = &dev_priv->drm; 3530 struct intel_crtc *intel_crtc; 3531 int active_crtc_cnt = 0; 3532 3533 drm_modeset_lock_all(dev); 3534 for_each_intel_crtc(dev, intel_crtc) { 3535 if (intel_crtc->base.state->active) { 3536 active_crtc_cnt++; 3537 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); 3538 3539 drrs_status_per_crtc(m, dev, intel_crtc); 3540 } 3541 } 3542 drm_modeset_unlock_all(dev); 3543 3544 if (!active_crtc_cnt) 3545 seq_puts(m, "No active crtc found\n"); 3546 3547 return 0; 3548 } 3549 3550 struct pipe_crc_info { 3551 const char *name; 3552 struct drm_i915_private *dev_priv; 3553 enum pipe pipe; 3554 }; 3555 3556 static int i915_dp_mst_info(struct seq_file *m, void *unused) 3557 { 3558 struct drm_i915_private *dev_priv = node_to_i915(m->private); 3559 struct drm_device *dev = &dev_priv->drm; 3560 struct intel_encoder *intel_encoder; 3561 struct intel_digital_port *intel_dig_port; 3562 struct drm_connector *connector; 3563 3564 drm_modeset_lock_all(dev); 3565 drm_for_each_connector(connector, dev) { 3566 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 3567 continue; 3568 3569 intel_encoder = intel_attached_encoder(connector); 3570 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) 3571 continue; 3572 3573 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 3574 if (!intel_dig_port->dp.can_mst) 3575 continue; 3576 3577 seq_printf(m, "MST Source Port %c\n", 3578 port_name(intel_dig_port->port)); 3579 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); 3580 } 3581 drm_modeset_unlock_all(dev); 3582 return 0; 3583 } 3584 3585 static int i915_pipe_crc_open(struct inode *inode, struct file *filep) 3586 { 3587 struct pipe_crc_info *info = inode->i_private; 3588 struct drm_i915_private *dev_priv = info->dev_priv; 3589 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3590 3591 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) 3592 return -ENODEV; 3593 3594 spin_lock_irq(&pipe_crc->lock); 3595 3596 if (pipe_crc->opened) { 3597 spin_unlock_irq(&pipe_crc->lock); 3598 return -EBUSY; /* already open */ 3599 } 3600 3601 pipe_crc->opened = true; 3602 filep->private_data = inode->i_private; 3603 3604 spin_unlock_irq(&pipe_crc->lock); 3605 3606 return 0; 3607 } 3608 3609 static int i915_pipe_crc_release(struct inode *inode, struct file *filep) 3610 { 3611 struct pipe_crc_info *info = inode->i_private; 3612 struct drm_i915_private *dev_priv = info->dev_priv; 3613 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3614 3615 spin_lock_irq(&pipe_crc->lock); 3616 pipe_crc->opened = false; 3617 spin_unlock_irq(&pipe_crc->lock); 3618 3619 return 0; 3620 } 3621 3622 /* (6 fields, 8 chars each, space separated (5) + '\n') */ 3623 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) 3624 /* account for \'0' */ 3625 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) 3626 3627 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) 3628 { 3629 assert_spin_locked(&pipe_crc->lock); 3630 return CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3631 INTEL_PIPE_CRC_ENTRIES_NR); 3632 } 3633 3634 static ssize_t 3635 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, 3636 loff_t *pos) 3637 { 3638 struct pipe_crc_info *info = filep->private_data; 3639 struct drm_i915_private *dev_priv = info->dev_priv; 3640 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3641 char buf[PIPE_CRC_BUFFER_LEN]; 3642 int n_entries; 3643 ssize_t bytes_read; 3644 3645 /* 3646 * Don't allow user space to provide buffers not big enough to hold 3647 * a line of data. 3648 */ 3649 if (count < PIPE_CRC_LINE_LEN) 3650 return -EINVAL; 3651 3652 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) 3653 return 0; 3654 3655 /* nothing to read */ 3656 spin_lock_irq(&pipe_crc->lock); 3657 while (pipe_crc_data_count(pipe_crc) == 0) { 3658 int ret; 3659 3660 if (filep->f_flags & O_NONBLOCK) { 3661 spin_unlock_irq(&pipe_crc->lock); 3662 return -EAGAIN; 3663 } 3664 3665 ret = wait_event_interruptible_lock_irq(pipe_crc->wq, 3666 pipe_crc_data_count(pipe_crc), pipe_crc->lock); 3667 if (ret) { 3668 spin_unlock_irq(&pipe_crc->lock); 3669 return ret; 3670 } 3671 } 3672 3673 /* We now have one or more entries to read */ 3674 n_entries = count / PIPE_CRC_LINE_LEN; 3675 3676 bytes_read = 0; 3677 while (n_entries > 0) { 3678 struct intel_pipe_crc_entry *entry = 3679 &pipe_crc->entries[pipe_crc->tail]; 3680 3681 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3682 INTEL_PIPE_CRC_ENTRIES_NR) < 1) 3683 break; 3684 3685 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); 3686 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 3687 3688 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, 3689 "%8u %8x %8x %8x %8x %8x\n", 3690 entry->frame, entry->crc[0], 3691 entry->crc[1], entry->crc[2], 3692 entry->crc[3], entry->crc[4]); 3693 3694 spin_unlock_irq(&pipe_crc->lock); 3695 3696 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) 3697 return -EFAULT; 3698 3699 user_buf += PIPE_CRC_LINE_LEN; 3700 n_entries--; 3701 3702 spin_lock_irq(&pipe_crc->lock); 3703 } 3704 3705 spin_unlock_irq(&pipe_crc->lock); 3706 3707 return bytes_read; 3708 } 3709 3710 static const struct file_operations i915_pipe_crc_fops = { 3711 .owner = THIS_MODULE, 3712 .open = i915_pipe_crc_open, 3713 .read = i915_pipe_crc_read, 3714 .release = i915_pipe_crc_release, 3715 }; 3716 3717 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { 3718 { 3719 .name = "i915_pipe_A_crc", 3720 .pipe = PIPE_A, 3721 }, 3722 { 3723 .name = "i915_pipe_B_crc", 3724 .pipe = PIPE_B, 3725 }, 3726 { 3727 .name = "i915_pipe_C_crc", 3728 .pipe = PIPE_C, 3729 }, 3730 }; 3731 3732 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, 3733 enum pipe pipe) 3734 { 3735 struct drm_i915_private *dev_priv = to_i915(minor->dev); 3736 struct dentry *ent; 3737 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; 3738 3739 info->dev_priv = dev_priv; 3740 ent = debugfs_create_file(info->name, S_IRUGO, root, info, 3741 &i915_pipe_crc_fops); 3742 if (!ent) 3743 return -ENOMEM; 3744 3745 return drm_add_fake_info_node(minor, ent, info); 3746 } 3747 3748 static const char * const pipe_crc_sources[] = { 3749 "none", 3750 "plane1", 3751 "plane2", 3752 "pf", 3753 "pipe", 3754 "TV", 3755 "DP-B", 3756 "DP-C", 3757 "DP-D", 3758 "auto", 3759 }; 3760 3761 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) 3762 { 3763 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); 3764 return pipe_crc_sources[source]; 3765 } 3766 3767 static int display_crc_ctl_show(struct seq_file *m, void *data) 3768 { 3769 struct drm_i915_private *dev_priv = m->private; 3770 int i; 3771 3772 for (i = 0; i < I915_MAX_PIPES; i++) 3773 seq_printf(m, "%c %s\n", pipe_name(i), 3774 pipe_crc_source_name(dev_priv->pipe_crc[i].source)); 3775 3776 return 0; 3777 } 3778 3779 static int display_crc_ctl_open(struct inode *inode, struct file *file) 3780 { 3781 return single_open(file, display_crc_ctl_show, inode->i_private); 3782 } 3783 3784 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3785 uint32_t *val) 3786 { 3787 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3788 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3789 3790 switch (*source) { 3791 case INTEL_PIPE_CRC_SOURCE_PIPE: 3792 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 3793 break; 3794 case INTEL_PIPE_CRC_SOURCE_NONE: 3795 *val = 0; 3796 break; 3797 default: 3798 return -EINVAL; 3799 } 3800 3801 return 0; 3802 } 3803 3804 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, 3805 enum pipe pipe, 3806 enum intel_pipe_crc_source *source) 3807 { 3808 struct drm_device *dev = &dev_priv->drm; 3809 struct intel_encoder *encoder; 3810 struct intel_crtc *crtc; 3811 struct intel_digital_port *dig_port; 3812 int ret = 0; 3813 3814 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3815 3816 drm_modeset_lock_all(dev); 3817 for_each_intel_encoder(dev, encoder) { 3818 if (!encoder->base.crtc) 3819 continue; 3820 3821 crtc = to_intel_crtc(encoder->base.crtc); 3822 3823 if (crtc->pipe != pipe) 3824 continue; 3825 3826 switch (encoder->type) { 3827 case INTEL_OUTPUT_TVOUT: 3828 *source = INTEL_PIPE_CRC_SOURCE_TV; 3829 break; 3830 case INTEL_OUTPUT_DP: 3831 case INTEL_OUTPUT_EDP: 3832 dig_port = enc_to_dig_port(&encoder->base); 3833 switch (dig_port->port) { 3834 case PORT_B: 3835 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 3836 break; 3837 case PORT_C: 3838 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 3839 break; 3840 case PORT_D: 3841 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 3842 break; 3843 default: 3844 WARN(1, "nonexisting DP port %c\n", 3845 port_name(dig_port->port)); 3846 break; 3847 } 3848 break; 3849 default: 3850 break; 3851 } 3852 } 3853 drm_modeset_unlock_all(dev); 3854 3855 return ret; 3856 } 3857 3858 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 3859 enum pipe pipe, 3860 enum intel_pipe_crc_source *source, 3861 uint32_t *val) 3862 { 3863 bool need_stable_symbols = false; 3864 3865 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3866 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 3867 if (ret) 3868 return ret; 3869 } 3870 3871 switch (*source) { 3872 case INTEL_PIPE_CRC_SOURCE_PIPE: 3873 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 3874 break; 3875 case INTEL_PIPE_CRC_SOURCE_DP_B: 3876 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 3877 need_stable_symbols = true; 3878 break; 3879 case INTEL_PIPE_CRC_SOURCE_DP_C: 3880 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 3881 need_stable_symbols = true; 3882 break; 3883 case INTEL_PIPE_CRC_SOURCE_DP_D: 3884 if (!IS_CHERRYVIEW(dev_priv)) 3885 return -EINVAL; 3886 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 3887 need_stable_symbols = true; 3888 break; 3889 case INTEL_PIPE_CRC_SOURCE_NONE: 3890 *val = 0; 3891 break; 3892 default: 3893 return -EINVAL; 3894 } 3895 3896 /* 3897 * When the pipe CRC tap point is after the transcoders we need 3898 * to tweak symbol-level features to produce a deterministic series of 3899 * symbols for a given frame. We need to reset those features only once 3900 * a frame (instead of every nth symbol): 3901 * - DC-balance: used to ensure a better clock recovery from the data 3902 * link (SDVO) 3903 * - DisplayPort scrambling: used for EMI reduction 3904 */ 3905 if (need_stable_symbols) { 3906 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3907 3908 tmp |= DC_BALANCE_RESET_VLV; 3909 switch (pipe) { 3910 case PIPE_A: 3911 tmp |= PIPE_A_SCRAMBLE_RESET; 3912 break; 3913 case PIPE_B: 3914 tmp |= PIPE_B_SCRAMBLE_RESET; 3915 break; 3916 case PIPE_C: 3917 tmp |= PIPE_C_SCRAMBLE_RESET; 3918 break; 3919 default: 3920 return -EINVAL; 3921 } 3922 I915_WRITE(PORT_DFT2_G4X, tmp); 3923 } 3924 3925 return 0; 3926 } 3927 3928 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 3929 enum pipe pipe, 3930 enum intel_pipe_crc_source *source, 3931 uint32_t *val) 3932 { 3933 bool need_stable_symbols = false; 3934 3935 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3936 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); 3937 if (ret) 3938 return ret; 3939 } 3940 3941 switch (*source) { 3942 case INTEL_PIPE_CRC_SOURCE_PIPE: 3943 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 3944 break; 3945 case INTEL_PIPE_CRC_SOURCE_TV: 3946 if (!SUPPORTS_TV(dev_priv)) 3947 return -EINVAL; 3948 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 3949 break; 3950 case INTEL_PIPE_CRC_SOURCE_DP_B: 3951 if (!IS_G4X(dev_priv)) 3952 return -EINVAL; 3953 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; 3954 need_stable_symbols = true; 3955 break; 3956 case INTEL_PIPE_CRC_SOURCE_DP_C: 3957 if (!IS_G4X(dev_priv)) 3958 return -EINVAL; 3959 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; 3960 need_stable_symbols = true; 3961 break; 3962 case INTEL_PIPE_CRC_SOURCE_DP_D: 3963 if (!IS_G4X(dev_priv)) 3964 return -EINVAL; 3965 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; 3966 need_stable_symbols = true; 3967 break; 3968 case INTEL_PIPE_CRC_SOURCE_NONE: 3969 *val = 0; 3970 break; 3971 default: 3972 return -EINVAL; 3973 } 3974 3975 /* 3976 * When the pipe CRC tap point is after the transcoders we need 3977 * to tweak symbol-level features to produce a deterministic series of 3978 * symbols for a given frame. We need to reset those features only once 3979 * a frame (instead of every nth symbol): 3980 * - DC-balance: used to ensure a better clock recovery from the data 3981 * link (SDVO) 3982 * - DisplayPort scrambling: used for EMI reduction 3983 */ 3984 if (need_stable_symbols) { 3985 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3986 3987 WARN_ON(!IS_G4X(dev_priv)); 3988 3989 I915_WRITE(PORT_DFT_I9XX, 3990 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); 3991 3992 if (pipe == PIPE_A) 3993 tmp |= PIPE_A_SCRAMBLE_RESET; 3994 else 3995 tmp |= PIPE_B_SCRAMBLE_RESET; 3996 3997 I915_WRITE(PORT_DFT2_G4X, tmp); 3998 } 3999 4000 return 0; 4001 } 4002 4003 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, 4004 enum pipe pipe) 4005 { 4006 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 4007 4008 switch (pipe) { 4009 case PIPE_A: 4010 tmp &= ~PIPE_A_SCRAMBLE_RESET; 4011 break; 4012 case PIPE_B: 4013 tmp &= ~PIPE_B_SCRAMBLE_RESET; 4014 break; 4015 case PIPE_C: 4016 tmp &= ~PIPE_C_SCRAMBLE_RESET; 4017 break; 4018 default: 4019 return; 4020 } 4021 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 4022 tmp &= ~DC_BALANCE_RESET_VLV; 4023 I915_WRITE(PORT_DFT2_G4X, tmp); 4024 4025 } 4026 4027 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, 4028 enum pipe pipe) 4029 { 4030 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 4031 4032 if (pipe == PIPE_A) 4033 tmp &= ~PIPE_A_SCRAMBLE_RESET; 4034 else 4035 tmp &= ~PIPE_B_SCRAMBLE_RESET; 4036 I915_WRITE(PORT_DFT2_G4X, tmp); 4037 4038 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { 4039 I915_WRITE(PORT_DFT_I9XX, 4040 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); 4041 } 4042 } 4043 4044 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 4045 uint32_t *val) 4046 { 4047 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 4048 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 4049 4050 switch (*source) { 4051 case INTEL_PIPE_CRC_SOURCE_PLANE1: 4052 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 4053 break; 4054 case INTEL_PIPE_CRC_SOURCE_PLANE2: 4055 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 4056 break; 4057 case INTEL_PIPE_CRC_SOURCE_PIPE: 4058 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 4059 break; 4060 case INTEL_PIPE_CRC_SOURCE_NONE: 4061 *val = 0; 4062 break; 4063 default: 4064 return -EINVAL; 4065 } 4066 4067 return 0; 4068 } 4069 4070 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, 4071 bool enable) 4072 { 4073 struct drm_device *dev = &dev_priv->drm; 4074 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); 4075 struct intel_crtc_state *pipe_config; 4076 struct drm_atomic_state *state; 4077 int ret = 0; 4078 4079 drm_modeset_lock_all(dev); 4080 state = drm_atomic_state_alloc(dev); 4081 if (!state) { 4082 ret = -ENOMEM; 4083 goto out; 4084 } 4085 4086 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); 4087 pipe_config = intel_atomic_get_crtc_state(state, crtc); 4088 if (IS_ERR(pipe_config)) { 4089 ret = PTR_ERR(pipe_config); 4090 goto out; 4091 } 4092 4093 pipe_config->pch_pfit.force_thru = enable; 4094 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && 4095 pipe_config->pch_pfit.enabled != enable) 4096 pipe_config->base.connectors_changed = true; 4097 4098 ret = drm_atomic_commit(state); 4099 out: 4100 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); 4101 drm_modeset_unlock_all(dev); 4102 drm_atomic_state_put(state); 4103 } 4104 4105 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, 4106 enum pipe pipe, 4107 enum intel_pipe_crc_source *source, 4108 uint32_t *val) 4109 { 4110 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 4111 *source = INTEL_PIPE_CRC_SOURCE_PF; 4112 4113 switch (*source) { 4114 case INTEL_PIPE_CRC_SOURCE_PLANE1: 4115 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 4116 break; 4117 case INTEL_PIPE_CRC_SOURCE_PLANE2: 4118 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 4119 break; 4120 case INTEL_PIPE_CRC_SOURCE_PF: 4121 if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 4122 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); 4123 4124 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 4125 break; 4126 case INTEL_PIPE_CRC_SOURCE_NONE: 4127 *val = 0; 4128 break; 4129 default: 4130 return -EINVAL; 4131 } 4132 4133 return 0; 4134 } 4135 4136 static int pipe_crc_set_source(struct drm_i915_private *dev_priv, 4137 enum pipe pipe, 4138 enum intel_pipe_crc_source source) 4139 { 4140 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 4141 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 4142 enum intel_display_power_domain power_domain; 4143 u32 val = 0; /* shut up gcc */ 4144 int ret; 4145 4146 if (pipe_crc->source == source) 4147 return 0; 4148 4149 /* forbid changing the source without going back to 'none' */ 4150 if (pipe_crc->source && source) 4151 return -EINVAL; 4152 4153 power_domain = POWER_DOMAIN_PIPE(pipe); 4154 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { 4155 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); 4156 return -EIO; 4157 } 4158 4159 if (IS_GEN2(dev_priv)) 4160 ret = i8xx_pipe_crc_ctl_reg(&source, &val); 4161 else if (INTEL_GEN(dev_priv) < 5) 4162 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4163 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4164 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4165 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) 4166 ret = ilk_pipe_crc_ctl_reg(&source, &val); 4167 else 4168 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val); 4169 4170 if (ret != 0) 4171 goto out; 4172 4173 /* none -> real source transition */ 4174 if (source) { 4175 struct intel_pipe_crc_entry *entries; 4176 4177 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", 4178 pipe_name(pipe), pipe_crc_source_name(source)); 4179 4180 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, 4181 sizeof(pipe_crc->entries[0]), 4182 GFP_KERNEL); 4183 if (!entries) { 4184 ret = -ENOMEM; 4185 goto out; 4186 } 4187 4188 /* 4189 * When IPS gets enabled, the pipe CRC changes. Since IPS gets 4190 * enabled and disabled dynamically based on package C states, 4191 * user space can't make reliable use of the CRCs, so let's just 4192 * completely disable it. 4193 */ 4194 hsw_disable_ips(crtc); 4195 4196 spin_lock_irq(&pipe_crc->lock); 4197 kfree(pipe_crc->entries); 4198 pipe_crc->entries = entries; 4199 pipe_crc->head = 0; 4200 pipe_crc->tail = 0; 4201 spin_unlock_irq(&pipe_crc->lock); 4202 } 4203 4204 pipe_crc->source = source; 4205 4206 I915_WRITE(PIPE_CRC_CTL(pipe), val); 4207 POSTING_READ(PIPE_CRC_CTL(pipe)); 4208 4209 /* real source -> none transition */ 4210 if (source == INTEL_PIPE_CRC_SOURCE_NONE) { 4211 struct intel_pipe_crc_entry *entries; 4212 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, 4213 pipe); 4214 4215 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", 4216 pipe_name(pipe)); 4217 4218 drm_modeset_lock(&crtc->base.mutex, NULL); 4219 if (crtc->base.state->active) 4220 intel_wait_for_vblank(dev_priv, pipe); 4221 drm_modeset_unlock(&crtc->base.mutex); 4222 4223 spin_lock_irq(&pipe_crc->lock); 4224 entries = pipe_crc->entries; 4225 pipe_crc->entries = NULL; 4226 pipe_crc->head = 0; 4227 pipe_crc->tail = 0; 4228 spin_unlock_irq(&pipe_crc->lock); 4229 4230 kfree(entries); 4231 4232 if (IS_G4X(dev_priv)) 4233 g4x_undo_pipe_scramble_reset(dev_priv, pipe); 4234 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4235 vlv_undo_pipe_scramble_reset(dev_priv, pipe); 4236 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) 4237 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); 4238 4239 hsw_enable_ips(crtc); 4240 } 4241 4242 ret = 0; 4243 4244 out: 4245 intel_display_power_put(dev_priv, power_domain); 4246 4247 return ret; 4248 } 4249 4250 /* 4251 * Parse pipe CRC command strings: 4252 * command: wsp* object wsp+ name wsp+ source wsp* 4253 * object: 'pipe' 4254 * name: (A | B | C) 4255 * source: (none | plane1 | plane2 | pf) 4256 * wsp: (#0x20 | #0x9 | #0xA)+ 4257 * 4258 * eg.: 4259 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A 4260 * "pipe A none" -> Stop CRC 4261 */ 4262 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) 4263 { 4264 int n_words = 0; 4265 4266 while (*buf) { 4267 char *end; 4268 4269 /* skip leading white space */ 4270 buf = skip_spaces(buf); 4271 if (!*buf) 4272 break; /* end of buffer */ 4273 4274 /* find end of word */ 4275 for (end = buf; *end && !isspace(*end); end++) 4276 ; 4277 4278 if (n_words == max_words) { 4279 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", 4280 max_words); 4281 return -EINVAL; /* ran out of words[] before bytes */ 4282 } 4283 4284 if (*end) 4285 *end++ = '\0'; 4286 words[n_words++] = buf; 4287 buf = end; 4288 } 4289 4290 return n_words; 4291 } 4292 4293 enum intel_pipe_crc_object { 4294 PIPE_CRC_OBJECT_PIPE, 4295 }; 4296 4297 static const char * const pipe_crc_objects[] = { 4298 "pipe", 4299 }; 4300 4301 static int 4302 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) 4303 { 4304 int i; 4305 4306 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) 4307 if (!strcmp(buf, pipe_crc_objects[i])) { 4308 *o = i; 4309 return 0; 4310 } 4311 4312 return -EINVAL; 4313 } 4314 4315 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) 4316 { 4317 const char name = buf[0]; 4318 4319 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) 4320 return -EINVAL; 4321 4322 *pipe = name - 'A'; 4323 4324 return 0; 4325 } 4326 4327 static int 4328 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 4329 { 4330 int i; 4331 4332 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) 4333 if (!strcmp(buf, pipe_crc_sources[i])) { 4334 *s = i; 4335 return 0; 4336 } 4337 4338 return -EINVAL; 4339 } 4340 4341 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, 4342 char *buf, size_t len) 4343 { 4344 #define N_WORDS 3 4345 int n_words; 4346 char *words[N_WORDS]; 4347 enum pipe pipe; 4348 enum intel_pipe_crc_object object; 4349 enum intel_pipe_crc_source source; 4350 4351 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); 4352 if (n_words != N_WORDS) { 4353 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", 4354 N_WORDS); 4355 return -EINVAL; 4356 } 4357 4358 if (display_crc_ctl_parse_object(words[0], &object) < 0) { 4359 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); 4360 return -EINVAL; 4361 } 4362 4363 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { 4364 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); 4365 return -EINVAL; 4366 } 4367 4368 if (display_crc_ctl_parse_source(words[2], &source) < 0) { 4369 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); 4370 return -EINVAL; 4371 } 4372 4373 return pipe_crc_set_source(dev_priv, pipe, source); 4374 } 4375 4376 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, 4377 size_t len, loff_t *offp) 4378 { 4379 struct seq_file *m = file->private_data; 4380 struct drm_i915_private *dev_priv = m->private; 4381 char *tmpbuf; 4382 int ret; 4383 4384 if (len == 0) 4385 return 0; 4386 4387 if (len > PAGE_SIZE - 1) { 4388 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", 4389 PAGE_SIZE); 4390 return -E2BIG; 4391 } 4392 4393 tmpbuf = kmalloc(len + 1, GFP_KERNEL); 4394 if (!tmpbuf) 4395 return -ENOMEM; 4396 4397 if (copy_from_user(tmpbuf, ubuf, len)) { 4398 ret = -EFAULT; 4399 goto out; 4400 } 4401 tmpbuf[len] = '\0'; 4402 4403 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); 4404 4405 out: 4406 kfree(tmpbuf); 4407 if (ret < 0) 4408 return ret; 4409 4410 *offp += len; 4411 return len; 4412 } 4413 4414 static const struct file_operations i915_display_crc_ctl_fops = { 4415 .owner = THIS_MODULE, 4416 .open = display_crc_ctl_open, 4417 .read = seq_read, 4418 .llseek = seq_lseek, 4419 .release = single_release, 4420 .write = display_crc_ctl_write 4421 }; 4422 4423 static ssize_t i915_displayport_test_active_write(struct file *file, 4424 const char __user *ubuf, 4425 size_t len, loff_t *offp) 4426 { 4427 char *input_buffer; 4428 int status = 0; 4429 struct drm_device *dev; 4430 struct drm_connector *connector; 4431 struct list_head *connector_list; 4432 struct intel_dp *intel_dp; 4433 int val = 0; 4434 4435 dev = ((struct seq_file *)file->private_data)->private; 4436 4437 connector_list = &dev->mode_config.connector_list; 4438 4439 if (len == 0) 4440 return 0; 4441 4442 input_buffer = kmalloc(len + 1, GFP_KERNEL); 4443 if (!input_buffer) 4444 return -ENOMEM; 4445 4446 if (copy_from_user(input_buffer, ubuf, len)) { 4447 status = -EFAULT; 4448 goto out; 4449 } 4450 4451 input_buffer[len] = '\0'; 4452 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); 4453 4454 list_for_each_entry(connector, connector_list, head) { 4455 if (connector->connector_type != 4456 DRM_MODE_CONNECTOR_DisplayPort) 4457 continue; 4458 4459 if (connector->status == connector_status_connected && 4460 connector->encoder != NULL) { 4461 intel_dp = enc_to_intel_dp(connector->encoder); 4462 status = kstrtoint(input_buffer, 10, &val); 4463 if (status < 0) 4464 goto out; 4465 DRM_DEBUG_DRIVER("Got %d for test active\n", val); 4466 /* To prevent erroneous activation of the compliance 4467 * testing code, only accept an actual value of 1 here 4468 */ 4469 if (val == 1) 4470 intel_dp->compliance_test_active = 1; 4471 else 4472 intel_dp->compliance_test_active = 0; 4473 } 4474 } 4475 out: 4476 kfree(input_buffer); 4477 if (status < 0) 4478 return status; 4479 4480 *offp += len; 4481 return len; 4482 } 4483 4484 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 4485 { 4486 struct drm_device *dev = m->private; 4487 struct drm_connector *connector; 4488 struct list_head *connector_list = &dev->mode_config.connector_list; 4489 struct intel_dp *intel_dp; 4490 4491 list_for_each_entry(connector, connector_list, head) { 4492 if (connector->connector_type != 4493 DRM_MODE_CONNECTOR_DisplayPort) 4494 continue; 4495 4496 if (connector->status == connector_status_connected && 4497 connector->encoder != NULL) { 4498 intel_dp = enc_to_intel_dp(connector->encoder); 4499 if (intel_dp->compliance_test_active) 4500 seq_puts(m, "1"); 4501 else 4502 seq_puts(m, "0"); 4503 } else 4504 seq_puts(m, "0"); 4505 } 4506 4507 return 0; 4508 } 4509 4510 static int i915_displayport_test_active_open(struct inode *inode, 4511 struct file *file) 4512 { 4513 struct drm_i915_private *dev_priv = inode->i_private; 4514 4515 return single_open(file, i915_displayport_test_active_show, 4516 &dev_priv->drm); 4517 } 4518 4519 static const struct file_operations i915_displayport_test_active_fops = { 4520 .owner = THIS_MODULE, 4521 .open = i915_displayport_test_active_open, 4522 .read = seq_read, 4523 .llseek = seq_lseek, 4524 .release = single_release, 4525 .write = i915_displayport_test_active_write 4526 }; 4527 4528 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 4529 { 4530 struct drm_device *dev = m->private; 4531 struct drm_connector *connector; 4532 struct list_head *connector_list = &dev->mode_config.connector_list; 4533 struct intel_dp *intel_dp; 4534 4535 list_for_each_entry(connector, connector_list, head) { 4536 if (connector->connector_type != 4537 DRM_MODE_CONNECTOR_DisplayPort) 4538 continue; 4539 4540 if (connector->status == connector_status_connected && 4541 connector->encoder != NULL) { 4542 intel_dp = enc_to_intel_dp(connector->encoder); 4543 seq_printf(m, "%lx", intel_dp->compliance_test_data); 4544 } else 4545 seq_puts(m, "0"); 4546 } 4547 4548 return 0; 4549 } 4550 static int i915_displayport_test_data_open(struct inode *inode, 4551 struct file *file) 4552 { 4553 struct drm_i915_private *dev_priv = inode->i_private; 4554 4555 return single_open(file, i915_displayport_test_data_show, 4556 &dev_priv->drm); 4557 } 4558 4559 static const struct file_operations i915_displayport_test_data_fops = { 4560 .owner = THIS_MODULE, 4561 .open = i915_displayport_test_data_open, 4562 .read = seq_read, 4563 .llseek = seq_lseek, 4564 .release = single_release 4565 }; 4566 4567 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 4568 { 4569 struct drm_device *dev = m->private; 4570 struct drm_connector *connector; 4571 struct list_head *connector_list = &dev->mode_config.connector_list; 4572 struct intel_dp *intel_dp; 4573 4574 list_for_each_entry(connector, connector_list, head) { 4575 if (connector->connector_type != 4576 DRM_MODE_CONNECTOR_DisplayPort) 4577 continue; 4578 4579 if (connector->status == connector_status_connected && 4580 connector->encoder != NULL) { 4581 intel_dp = enc_to_intel_dp(connector->encoder); 4582 seq_printf(m, "%02lx", intel_dp->compliance_test_type); 4583 } else 4584 seq_puts(m, "0"); 4585 } 4586 4587 return 0; 4588 } 4589 4590 static int i915_displayport_test_type_open(struct inode *inode, 4591 struct file *file) 4592 { 4593 struct drm_i915_private *dev_priv = inode->i_private; 4594 4595 return single_open(file, i915_displayport_test_type_show, 4596 &dev_priv->drm); 4597 } 4598 4599 static const struct file_operations i915_displayport_test_type_fops = { 4600 .owner = THIS_MODULE, 4601 .open = i915_displayport_test_type_open, 4602 .read = seq_read, 4603 .llseek = seq_lseek, 4604 .release = single_release 4605 }; 4606 4607 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 4608 { 4609 struct drm_i915_private *dev_priv = m->private; 4610 struct drm_device *dev = &dev_priv->drm; 4611 int level; 4612 int num_levels; 4613 4614 if (IS_CHERRYVIEW(dev_priv)) 4615 num_levels = 3; 4616 else if (IS_VALLEYVIEW(dev_priv)) 4617 num_levels = 1; 4618 else 4619 num_levels = ilk_wm_max_level(dev_priv) + 1; 4620 4621 drm_modeset_lock_all(dev); 4622 4623 for (level = 0; level < num_levels; level++) { 4624 unsigned int latency = wm[level]; 4625 4626 /* 4627 * - WM1+ latency values in 0.5us units 4628 * - latencies are in us on gen9/vlv/chv 4629 */ 4630 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) || 4631 IS_CHERRYVIEW(dev_priv)) 4632 latency *= 10; 4633 else if (level > 0) 4634 latency *= 5; 4635 4636 seq_printf(m, "WM%d %u (%u.%u usec)\n", 4637 level, wm[level], latency / 10, latency % 10); 4638 } 4639 4640 drm_modeset_unlock_all(dev); 4641 } 4642 4643 static int pri_wm_latency_show(struct seq_file *m, void *data) 4644 { 4645 struct drm_i915_private *dev_priv = m->private; 4646 const uint16_t *latencies; 4647 4648 if (INTEL_GEN(dev_priv) >= 9) 4649 latencies = dev_priv->wm.skl_latency; 4650 else 4651 latencies = dev_priv->wm.pri_latency; 4652 4653 wm_latency_show(m, latencies); 4654 4655 return 0; 4656 } 4657 4658 static int spr_wm_latency_show(struct seq_file *m, void *data) 4659 { 4660 struct drm_i915_private *dev_priv = m->private; 4661 const uint16_t *latencies; 4662 4663 if (INTEL_GEN(dev_priv) >= 9) 4664 latencies = dev_priv->wm.skl_latency; 4665 else 4666 latencies = dev_priv->wm.spr_latency; 4667 4668 wm_latency_show(m, latencies); 4669 4670 return 0; 4671 } 4672 4673 static int cur_wm_latency_show(struct seq_file *m, void *data) 4674 { 4675 struct drm_i915_private *dev_priv = m->private; 4676 const uint16_t *latencies; 4677 4678 if (INTEL_GEN(dev_priv) >= 9) 4679 latencies = dev_priv->wm.skl_latency; 4680 else 4681 latencies = dev_priv->wm.cur_latency; 4682 4683 wm_latency_show(m, latencies); 4684 4685 return 0; 4686 } 4687 4688 static int pri_wm_latency_open(struct inode *inode, struct file *file) 4689 { 4690 struct drm_i915_private *dev_priv = inode->i_private; 4691 4692 if (INTEL_GEN(dev_priv) < 5) 4693 return -ENODEV; 4694 4695 return single_open(file, pri_wm_latency_show, dev_priv); 4696 } 4697 4698 static int spr_wm_latency_open(struct inode *inode, struct file *file) 4699 { 4700 struct drm_i915_private *dev_priv = inode->i_private; 4701 4702 if (HAS_GMCH_DISPLAY(dev_priv)) 4703 return -ENODEV; 4704 4705 return single_open(file, spr_wm_latency_show, dev_priv); 4706 } 4707 4708 static int cur_wm_latency_open(struct inode *inode, struct file *file) 4709 { 4710 struct drm_i915_private *dev_priv = inode->i_private; 4711 4712 if (HAS_GMCH_DISPLAY(dev_priv)) 4713 return -ENODEV; 4714 4715 return single_open(file, cur_wm_latency_show, dev_priv); 4716 } 4717 4718 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 4719 size_t len, loff_t *offp, uint16_t wm[8]) 4720 { 4721 struct seq_file *m = file->private_data; 4722 struct drm_i915_private *dev_priv = m->private; 4723 struct drm_device *dev = &dev_priv->drm; 4724 uint16_t new[8] = { 0 }; 4725 int num_levels; 4726 int level; 4727 int ret; 4728 char tmp[32]; 4729 4730 if (IS_CHERRYVIEW(dev_priv)) 4731 num_levels = 3; 4732 else if (IS_VALLEYVIEW(dev_priv)) 4733 num_levels = 1; 4734 else 4735 num_levels = ilk_wm_max_level(dev_priv) + 1; 4736 4737 if (len >= sizeof(tmp)) 4738 return -EINVAL; 4739 4740 if (copy_from_user(tmp, ubuf, len)) 4741 return -EFAULT; 4742 4743 tmp[len] = '\0'; 4744 4745 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 4746 &new[0], &new[1], &new[2], &new[3], 4747 &new[4], &new[5], &new[6], &new[7]); 4748 if (ret != num_levels) 4749 return -EINVAL; 4750 4751 drm_modeset_lock_all(dev); 4752 4753 for (level = 0; level < num_levels; level++) 4754 wm[level] = new[level]; 4755 4756 drm_modeset_unlock_all(dev); 4757 4758 return len; 4759 } 4760 4761 4762 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 4763 size_t len, loff_t *offp) 4764 { 4765 struct seq_file *m = file->private_data; 4766 struct drm_i915_private *dev_priv = m->private; 4767 uint16_t *latencies; 4768 4769 if (INTEL_GEN(dev_priv) >= 9) 4770 latencies = dev_priv->wm.skl_latency; 4771 else 4772 latencies = dev_priv->wm.pri_latency; 4773 4774 return wm_latency_write(file, ubuf, len, offp, latencies); 4775 } 4776 4777 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 4778 size_t len, loff_t *offp) 4779 { 4780 struct seq_file *m = file->private_data; 4781 struct drm_i915_private *dev_priv = m->private; 4782 uint16_t *latencies; 4783 4784 if (INTEL_GEN(dev_priv) >= 9) 4785 latencies = dev_priv->wm.skl_latency; 4786 else 4787 latencies = dev_priv->wm.spr_latency; 4788 4789 return wm_latency_write(file, ubuf, len, offp, latencies); 4790 } 4791 4792 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 4793 size_t len, loff_t *offp) 4794 { 4795 struct seq_file *m = file->private_data; 4796 struct drm_i915_private *dev_priv = m->private; 4797 uint16_t *latencies; 4798 4799 if (INTEL_GEN(dev_priv) >= 9) 4800 latencies = dev_priv->wm.skl_latency; 4801 else 4802 latencies = dev_priv->wm.cur_latency; 4803 4804 return wm_latency_write(file, ubuf, len, offp, latencies); 4805 } 4806 4807 static const struct file_operations i915_pri_wm_latency_fops = { 4808 .owner = THIS_MODULE, 4809 .open = pri_wm_latency_open, 4810 .read = seq_read, 4811 .llseek = seq_lseek, 4812 .release = single_release, 4813 .write = pri_wm_latency_write 4814 }; 4815 4816 static const struct file_operations i915_spr_wm_latency_fops = { 4817 .owner = THIS_MODULE, 4818 .open = spr_wm_latency_open, 4819 .read = seq_read, 4820 .llseek = seq_lseek, 4821 .release = single_release, 4822 .write = spr_wm_latency_write 4823 }; 4824 4825 static const struct file_operations i915_cur_wm_latency_fops = { 4826 .owner = THIS_MODULE, 4827 .open = cur_wm_latency_open, 4828 .read = seq_read, 4829 .llseek = seq_lseek, 4830 .release = single_release, 4831 .write = cur_wm_latency_write 4832 }; 4833 4834 static int 4835 i915_wedged_get(void *data, u64 *val) 4836 { 4837 struct drm_i915_private *dev_priv = data; 4838 4839 *val = i915_terminally_wedged(&dev_priv->gpu_error); 4840 4841 return 0; 4842 } 4843 4844 static int 4845 i915_wedged_set(void *data, u64 val) 4846 { 4847 struct drm_i915_private *dev_priv = data; 4848 4849 /* 4850 * There is no safeguard against this debugfs entry colliding 4851 * with the hangcheck calling same i915_handle_error() in 4852 * parallel, causing an explosion. For now we assume that the 4853 * test harness is responsible enough not to inject gpu hangs 4854 * while it is writing to 'i915_wedged' 4855 */ 4856 4857 if (i915_reset_in_progress(&dev_priv->gpu_error)) 4858 return -EAGAIN; 4859 4860 i915_handle_error(dev_priv, val, 4861 "Manually setting wedged to %llu", val); 4862 4863 return 0; 4864 } 4865 4866 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 4867 i915_wedged_get, i915_wedged_set, 4868 "%llu\n"); 4869 4870 static int 4871 i915_ring_missed_irq_get(void *data, u64 *val) 4872 { 4873 struct drm_i915_private *dev_priv = data; 4874 4875 *val = dev_priv->gpu_error.missed_irq_rings; 4876 return 0; 4877 } 4878 4879 static int 4880 i915_ring_missed_irq_set(void *data, u64 val) 4881 { 4882 struct drm_i915_private *dev_priv = data; 4883 struct drm_device *dev = &dev_priv->drm; 4884 int ret; 4885 4886 /* Lock against concurrent debugfs callers */ 4887 ret = mutex_lock_interruptible(&dev->struct_mutex); 4888 if (ret) 4889 return ret; 4890 dev_priv->gpu_error.missed_irq_rings = val; 4891 mutex_unlock(&dev->struct_mutex); 4892 4893 return 0; 4894 } 4895 4896 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, 4897 i915_ring_missed_irq_get, i915_ring_missed_irq_set, 4898 "0x%08llx\n"); 4899 4900 static int 4901 i915_ring_test_irq_get(void *data, u64 *val) 4902 { 4903 struct drm_i915_private *dev_priv = data; 4904 4905 *val = dev_priv->gpu_error.test_irq_rings; 4906 4907 return 0; 4908 } 4909 4910 static int 4911 i915_ring_test_irq_set(void *data, u64 val) 4912 { 4913 struct drm_i915_private *dev_priv = data; 4914 4915 val &= INTEL_INFO(dev_priv)->ring_mask; 4916 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); 4917 dev_priv->gpu_error.test_irq_rings = val; 4918 4919 return 0; 4920 } 4921 4922 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, 4923 i915_ring_test_irq_get, i915_ring_test_irq_set, 4924 "0x%08llx\n"); 4925 4926 #define DROP_UNBOUND 0x1 4927 #define DROP_BOUND 0x2 4928 #define DROP_RETIRE 0x4 4929 #define DROP_ACTIVE 0x8 4930 #define DROP_FREED 0x10 4931 #define DROP_ALL (DROP_UNBOUND | \ 4932 DROP_BOUND | \ 4933 DROP_RETIRE | \ 4934 DROP_ACTIVE | \ 4935 DROP_FREED) 4936 static int 4937 i915_drop_caches_get(void *data, u64 *val) 4938 { 4939 *val = DROP_ALL; 4940 4941 return 0; 4942 } 4943 4944 static int 4945 i915_drop_caches_set(void *data, u64 val) 4946 { 4947 struct drm_i915_private *dev_priv = data; 4948 struct drm_device *dev = &dev_priv->drm; 4949 int ret; 4950 4951 DRM_DEBUG("Dropping caches: 0x%08llx\n", val); 4952 4953 /* No need to check and wait for gpu resets, only libdrm auto-restarts 4954 * on ioctls on -EAGAIN. */ 4955 ret = mutex_lock_interruptible(&dev->struct_mutex); 4956 if (ret) 4957 return ret; 4958 4959 if (val & DROP_ACTIVE) { 4960 ret = i915_gem_wait_for_idle(dev_priv, 4961 I915_WAIT_INTERRUPTIBLE | 4962 I915_WAIT_LOCKED); 4963 if (ret) 4964 goto unlock; 4965 } 4966 4967 if (val & (DROP_RETIRE | DROP_ACTIVE)) 4968 i915_gem_retire_requests(dev_priv); 4969 4970 if (val & DROP_BOUND) 4971 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); 4972 4973 if (val & DROP_UNBOUND) 4974 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); 4975 4976 unlock: 4977 mutex_unlock(&dev->struct_mutex); 4978 4979 if (val & DROP_FREED) { 4980 synchronize_rcu(); 4981 flush_work(&dev_priv->mm.free_work); 4982 } 4983 4984 return ret; 4985 } 4986 4987 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 4988 i915_drop_caches_get, i915_drop_caches_set, 4989 "0x%08llx\n"); 4990 4991 static int 4992 i915_max_freq_get(void *data, u64 *val) 4993 { 4994 struct drm_i915_private *dev_priv = data; 4995 4996 if (INTEL_GEN(dev_priv) < 6) 4997 return -ENODEV; 4998 4999 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); 5000 return 0; 5001 } 5002 5003 static int 5004 i915_max_freq_set(void *data, u64 val) 5005 { 5006 struct drm_i915_private *dev_priv = data; 5007 u32 hw_max, hw_min; 5008 int ret; 5009 5010 if (INTEL_GEN(dev_priv) < 6) 5011 return -ENODEV; 5012 5013 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); 5014 5015 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 5016 if (ret) 5017 return ret; 5018 5019 /* 5020 * Turbo will still be enabled, but won't go above the set value. 5021 */ 5022 val = intel_freq_opcode(dev_priv, val); 5023 5024 hw_max = dev_priv->rps.max_freq; 5025 hw_min = dev_priv->rps.min_freq; 5026 5027 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { 5028 mutex_unlock(&dev_priv->rps.hw_lock); 5029 return -EINVAL; 5030 } 5031 5032 dev_priv->rps.max_freq_softlimit = val; 5033 5034 intel_set_rps(dev_priv, val); 5035 5036 mutex_unlock(&dev_priv->rps.hw_lock); 5037 5038 return 0; 5039 } 5040 5041 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, 5042 i915_max_freq_get, i915_max_freq_set, 5043 "%llu\n"); 5044 5045 static int 5046 i915_min_freq_get(void *data, u64 *val) 5047 { 5048 struct drm_i915_private *dev_priv = data; 5049 5050 if (INTEL_GEN(dev_priv) < 6) 5051 return -ENODEV; 5052 5053 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); 5054 return 0; 5055 } 5056 5057 static int 5058 i915_min_freq_set(void *data, u64 val) 5059 { 5060 struct drm_i915_private *dev_priv = data; 5061 u32 hw_max, hw_min; 5062 int ret; 5063 5064 if (INTEL_GEN(dev_priv) < 6) 5065 return -ENODEV; 5066 5067 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); 5068 5069 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 5070 if (ret) 5071 return ret; 5072 5073 /* 5074 * Turbo will still be enabled, but won't go below the set value. 5075 */ 5076 val = intel_freq_opcode(dev_priv, val); 5077 5078 hw_max = dev_priv->rps.max_freq; 5079 hw_min = dev_priv->rps.min_freq; 5080 5081 if (val < hw_min || 5082 val > hw_max || val > dev_priv->rps.max_freq_softlimit) { 5083 mutex_unlock(&dev_priv->rps.hw_lock); 5084 return -EINVAL; 5085 } 5086 5087 dev_priv->rps.min_freq_softlimit = val; 5088 5089 intel_set_rps(dev_priv, val); 5090 5091 mutex_unlock(&dev_priv->rps.hw_lock); 5092 5093 return 0; 5094 } 5095 5096 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, 5097 i915_min_freq_get, i915_min_freq_set, 5098 "%llu\n"); 5099 5100 static int 5101 i915_cache_sharing_get(void *data, u64 *val) 5102 { 5103 struct drm_i915_private *dev_priv = data; 5104 u32 snpcr; 5105 5106 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 5107 return -ENODEV; 5108 5109 intel_runtime_pm_get(dev_priv); 5110 5111 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5112 5113 intel_runtime_pm_put(dev_priv); 5114 5115 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; 5116 5117 return 0; 5118 } 5119 5120 static int 5121 i915_cache_sharing_set(void *data, u64 val) 5122 { 5123 struct drm_i915_private *dev_priv = data; 5124 u32 snpcr; 5125 5126 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) 5127 return -ENODEV; 5128 5129 if (val > 3) 5130 return -EINVAL; 5131 5132 intel_runtime_pm_get(dev_priv); 5133 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); 5134 5135 /* Update the cache sharing policy here as well */ 5136 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5137 snpcr &= ~GEN6_MBC_SNPCR_MASK; 5138 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 5139 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 5140 5141 intel_runtime_pm_put(dev_priv); 5142 return 0; 5143 } 5144 5145 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 5146 i915_cache_sharing_get, i915_cache_sharing_set, 5147 "%llu\n"); 5148 5149 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, 5150 struct sseu_dev_info *sseu) 5151 { 5152 int ss_max = 2; 5153 int ss; 5154 u32 sig1[ss_max], sig2[ss_max]; 5155 5156 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); 5157 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); 5158 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); 5159 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); 5160 5161 for (ss = 0; ss < ss_max; ss++) { 5162 unsigned int eu_cnt; 5163 5164 if (sig1[ss] & CHV_SS_PG_ENABLE) 5165 /* skip disabled subslice */ 5166 continue; 5167 5168 sseu->slice_mask = BIT(0); 5169 sseu->subslice_mask |= BIT(ss); 5170 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + 5171 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + 5172 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + 5173 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); 5174 sseu->eu_total += eu_cnt; 5175 sseu->eu_per_subslice = max_t(unsigned int, 5176 sseu->eu_per_subslice, eu_cnt); 5177 } 5178 } 5179 5180 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 5181 struct sseu_dev_info *sseu) 5182 { 5183 int s_max = 3, ss_max = 4; 5184 int s, ss; 5185 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; 5186 5187 /* BXT has a single slice and at most 3 subslices. */ 5188 if (IS_BROXTON(dev_priv)) { 5189 s_max = 1; 5190 ss_max = 3; 5191 } 5192 5193 for (s = 0; s < s_max; s++) { 5194 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); 5195 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); 5196 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); 5197 } 5198 5199 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | 5200 GEN9_PGCTL_SSA_EU19_ACK | 5201 GEN9_PGCTL_SSA_EU210_ACK | 5202 GEN9_PGCTL_SSA_EU311_ACK; 5203 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | 5204 GEN9_PGCTL_SSB_EU19_ACK | 5205 GEN9_PGCTL_SSB_EU210_ACK | 5206 GEN9_PGCTL_SSB_EU311_ACK; 5207 5208 for (s = 0; s < s_max; s++) { 5209 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) 5210 /* skip disabled slice */ 5211 continue; 5212 5213 sseu->slice_mask |= BIT(s); 5214 5215 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 5216 sseu->subslice_mask = 5217 INTEL_INFO(dev_priv)->sseu.subslice_mask; 5218 5219 for (ss = 0; ss < ss_max; ss++) { 5220 unsigned int eu_cnt; 5221 5222 if (IS_BROXTON(dev_priv)) { 5223 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) 5224 /* skip disabled subslice */ 5225 continue; 5226 5227 sseu->subslice_mask |= BIT(ss); 5228 } 5229 5230 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & 5231 eu_mask[ss%2]); 5232 sseu->eu_total += eu_cnt; 5233 sseu->eu_per_subslice = max_t(unsigned int, 5234 sseu->eu_per_subslice, 5235 eu_cnt); 5236 } 5237 } 5238 } 5239 5240 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, 5241 struct sseu_dev_info *sseu) 5242 { 5243 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); 5244 int s; 5245 5246 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK; 5247 5248 if (sseu->slice_mask) { 5249 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; 5250 sseu->eu_per_subslice = 5251 INTEL_INFO(dev_priv)->sseu.eu_per_subslice; 5252 sseu->eu_total = sseu->eu_per_subslice * 5253 sseu_subslice_total(sseu); 5254 5255 /* subtract fused off EU(s) from enabled slice(s) */ 5256 for (s = 0; s < fls(sseu->slice_mask); s++) { 5257 u8 subslice_7eu = 5258 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s]; 5259 5260 sseu->eu_total -= hweight8(subslice_7eu); 5261 } 5262 } 5263 } 5264 5265 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, 5266 const struct sseu_dev_info *sseu) 5267 { 5268 struct drm_i915_private *dev_priv = node_to_i915(m->private); 5269 const char *type = is_available_info ? "Available" : "Enabled"; 5270 5271 seq_printf(m, " %s Slice Mask: %04x\n", type, 5272 sseu->slice_mask); 5273 seq_printf(m, " %s Slice Total: %u\n", type, 5274 hweight8(sseu->slice_mask)); 5275 seq_printf(m, " %s Subslice Total: %u\n", type, 5276 sseu_subslice_total(sseu)); 5277 seq_printf(m, " %s Subslice Mask: %04x\n", type, 5278 sseu->subslice_mask); 5279 seq_printf(m, " %s Subslice Per Slice: %u\n", type, 5280 hweight8(sseu->subslice_mask)); 5281 seq_printf(m, " %s EU Total: %u\n", type, 5282 sseu->eu_total); 5283 seq_printf(m, " %s EU Per Subslice: %u\n", type, 5284 sseu->eu_per_subslice); 5285 5286 if (!is_available_info) 5287 return; 5288 5289 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); 5290 if (HAS_POOLED_EU(dev_priv)) 5291 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); 5292 5293 seq_printf(m, " Has Slice Power Gating: %s\n", 5294 yesno(sseu->has_slice_pg)); 5295 seq_printf(m, " Has Subslice Power Gating: %s\n", 5296 yesno(sseu->has_subslice_pg)); 5297 seq_printf(m, " Has EU Power Gating: %s\n", 5298 yesno(sseu->has_eu_pg)); 5299 } 5300 5301 static int i915_sseu_status(struct seq_file *m, void *unused) 5302 { 5303 struct drm_i915_private *dev_priv = node_to_i915(m->private); 5304 struct sseu_dev_info sseu; 5305 5306 if (INTEL_GEN(dev_priv) < 8) 5307 return -ENODEV; 5308 5309 seq_puts(m, "SSEU Device Info\n"); 5310 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu); 5311 5312 seq_puts(m, "SSEU Device Status\n"); 5313 memset(&sseu, 0, sizeof(sseu)); 5314 5315 intel_runtime_pm_get(dev_priv); 5316 5317 if (IS_CHERRYVIEW(dev_priv)) { 5318 cherryview_sseu_device_status(dev_priv, &sseu); 5319 } else if (IS_BROADWELL(dev_priv)) { 5320 broadwell_sseu_device_status(dev_priv, &sseu); 5321 } else if (INTEL_GEN(dev_priv) >= 9) { 5322 gen9_sseu_device_status(dev_priv, &sseu); 5323 } 5324 5325 intel_runtime_pm_put(dev_priv); 5326 5327 i915_print_sseu_info(m, false, &sseu); 5328 5329 return 0; 5330 } 5331 5332 static int i915_forcewake_open(struct inode *inode, struct file *file) 5333 { 5334 struct drm_i915_private *dev_priv = inode->i_private; 5335 5336 if (INTEL_GEN(dev_priv) < 6) 5337 return 0; 5338 5339 intel_runtime_pm_get(dev_priv); 5340 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5341 5342 return 0; 5343 } 5344 5345 static int i915_forcewake_release(struct inode *inode, struct file *file) 5346 { 5347 struct drm_i915_private *dev_priv = inode->i_private; 5348 5349 if (INTEL_GEN(dev_priv) < 6) 5350 return 0; 5351 5352 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5353 intel_runtime_pm_put(dev_priv); 5354 5355 return 0; 5356 } 5357 5358 static const struct file_operations i915_forcewake_fops = { 5359 .owner = THIS_MODULE, 5360 .open = i915_forcewake_open, 5361 .release = i915_forcewake_release, 5362 }; 5363 5364 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) 5365 { 5366 struct dentry *ent; 5367 5368 ent = debugfs_create_file("i915_forcewake_user", 5369 S_IRUSR, 5370 root, to_i915(minor->dev), 5371 &i915_forcewake_fops); 5372 if (!ent) 5373 return -ENOMEM; 5374 5375 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); 5376 } 5377 5378 static int i915_debugfs_create(struct dentry *root, 5379 struct drm_minor *minor, 5380 const char *name, 5381 const struct file_operations *fops) 5382 { 5383 struct dentry *ent; 5384 5385 ent = debugfs_create_file(name, 5386 S_IRUGO | S_IWUSR, 5387 root, to_i915(minor->dev), 5388 fops); 5389 if (!ent) 5390 return -ENOMEM; 5391 5392 return drm_add_fake_info_node(minor, ent, fops); 5393 } 5394 5395 static const struct drm_info_list i915_debugfs_list[] = { 5396 {"i915_capabilities", i915_capabilities, 0}, 5397 {"i915_gem_objects", i915_gem_object_info, 0}, 5398 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 5399 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1}, 5400 {"i915_gem_stolen", i915_gem_stolen_list_info }, 5401 {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, 5402 {"i915_gem_request", i915_gem_request_info, 0}, 5403 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 5404 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 5405 {"i915_gem_interrupt", i915_interrupt_info, 0}, 5406 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, 5407 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, 5408 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, 5409 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, 5410 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, 5411 {"i915_guc_info", i915_guc_info, 0}, 5412 {"i915_guc_load_status", i915_guc_load_status_info, 0}, 5413 {"i915_guc_log_dump", i915_guc_log_dump, 0}, 5414 {"i915_frequency_info", i915_frequency_info, 0}, 5415 {"i915_hangcheck_info", i915_hangcheck_info, 0}, 5416 {"i915_drpc_info", i915_drpc_info, 0}, 5417 {"i915_emon_status", i915_emon_status, 0}, 5418 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 5419 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 5420 {"i915_fbc_status", i915_fbc_status, 0}, 5421 {"i915_ips_status", i915_ips_status, 0}, 5422 {"i915_sr_status", i915_sr_status, 0}, 5423 {"i915_opregion", i915_opregion, 0}, 5424 {"i915_vbt", i915_vbt, 0}, 5425 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 5426 {"i915_context_status", i915_context_status, 0}, 5427 {"i915_dump_lrc", i915_dump_lrc, 0}, 5428 {"i915_forcewake_domains", i915_forcewake_domains, 0}, 5429 {"i915_swizzle_info", i915_swizzle_info, 0}, 5430 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 5431 {"i915_llc", i915_llc, 0}, 5432 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 5433 {"i915_sink_crc_eDP1", i915_sink_crc, 0}, 5434 {"i915_energy_uJ", i915_energy_uJ, 0}, 5435 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 5436 {"i915_power_domain_info", i915_power_domain_info, 0}, 5437 {"i915_dmc_info", i915_dmc_info, 0}, 5438 {"i915_display_info", i915_display_info, 0}, 5439 {"i915_engine_info", i915_engine_info, 0}, 5440 {"i915_semaphore_status", i915_semaphore_status, 0}, 5441 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 5442 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 5443 {"i915_wa_registers", i915_wa_registers, 0}, 5444 {"i915_ddb_info", i915_ddb_info, 0}, 5445 {"i915_sseu_status", i915_sseu_status, 0}, 5446 {"i915_drrs_status", i915_drrs_status, 0}, 5447 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 5448 }; 5449 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 5450 5451 static const struct i915_debugfs_files { 5452 const char *name; 5453 const struct file_operations *fops; 5454 } i915_debugfs_files[] = { 5455 {"i915_wedged", &i915_wedged_fops}, 5456 {"i915_max_freq", &i915_max_freq_fops}, 5457 {"i915_min_freq", &i915_min_freq_fops}, 5458 {"i915_cache_sharing", &i915_cache_sharing_fops}, 5459 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, 5460 {"i915_ring_test_irq", &i915_ring_test_irq_fops}, 5461 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 5462 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 5463 {"i915_error_state", &i915_error_state_fops}, 5464 #endif 5465 {"i915_next_seqno", &i915_next_seqno_fops}, 5466 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, 5467 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 5468 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 5469 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 5470 {"i915_fbc_false_color", &i915_fbc_fc_fops}, 5471 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 5472 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 5473 {"i915_dp_test_active", &i915_displayport_test_active_fops}, 5474 {"i915_guc_log_control", &i915_guc_log_control_fops} 5475 }; 5476 5477 void intel_display_crc_init(struct drm_i915_private *dev_priv) 5478 { 5479 enum pipe pipe; 5480 5481 for_each_pipe(dev_priv, pipe) { 5482 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 5483 5484 pipe_crc->opened = false; 5485 spin_lock_init(&pipe_crc->lock); 5486 init_waitqueue_head(&pipe_crc->wq); 5487 } 5488 } 5489 5490 int i915_debugfs_register(struct drm_i915_private *dev_priv) 5491 { 5492 struct drm_minor *minor = dev_priv->drm.primary; 5493 int ret, i; 5494 5495 ret = i915_forcewake_create(minor->debugfs_root, minor); 5496 if (ret) 5497 return ret; 5498 5499 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5500 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); 5501 if (ret) 5502 return ret; 5503 } 5504 5505 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5506 ret = i915_debugfs_create(minor->debugfs_root, minor, 5507 i915_debugfs_files[i].name, 5508 i915_debugfs_files[i].fops); 5509 if (ret) 5510 return ret; 5511 } 5512 5513 return drm_debugfs_create_files(i915_debugfs_list, 5514 I915_DEBUGFS_ENTRIES, 5515 minor->debugfs_root, minor); 5516 } 5517 5518 void i915_debugfs_unregister(struct drm_i915_private *dev_priv) 5519 { 5520 struct drm_minor *minor = dev_priv->drm.primary; 5521 int i; 5522 5523 drm_debugfs_remove_files(i915_debugfs_list, 5524 I915_DEBUGFS_ENTRIES, minor); 5525 5526 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops, 5527 1, minor); 5528 5529 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5530 struct drm_info_list *info_list = 5531 (struct drm_info_list *)&i915_pipe_crc_data[i]; 5532 5533 drm_debugfs_remove_files(info_list, 1, minor); 5534 } 5535 5536 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5537 struct drm_info_list *info_list = 5538 (struct drm_info_list *)i915_debugfs_files[i].fops; 5539 5540 drm_debugfs_remove_files(info_list, 1, minor); 5541 } 5542 } 5543 5544 struct dpcd_block { 5545 /* DPCD dump start address. */ 5546 unsigned int offset; 5547 /* DPCD dump end address, inclusive. If unset, .size will be used. */ 5548 unsigned int end; 5549 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ 5550 size_t size; 5551 /* Only valid for eDP. */ 5552 bool edp; 5553 }; 5554 5555 static const struct dpcd_block i915_dpcd_debug[] = { 5556 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, 5557 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, 5558 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, 5559 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, 5560 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, 5561 { .offset = DP_SET_POWER }, 5562 { .offset = DP_EDP_DPCD_REV }, 5563 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, 5564 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, 5565 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, 5566 }; 5567 5568 static int i915_dpcd_show(struct seq_file *m, void *data) 5569 { 5570 struct drm_connector *connector = m->private; 5571 struct intel_dp *intel_dp = 5572 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5573 uint8_t buf[16]; 5574 ssize_t err; 5575 int i; 5576 5577 if (connector->status != connector_status_connected) 5578 return -ENODEV; 5579 5580 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { 5581 const struct dpcd_block *b = &i915_dpcd_debug[i]; 5582 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); 5583 5584 if (b->edp && 5585 connector->connector_type != DRM_MODE_CONNECTOR_eDP) 5586 continue; 5587 5588 /* low tech for now */ 5589 if (WARN_ON(size > sizeof(buf))) 5590 continue; 5591 5592 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); 5593 if (err <= 0) { 5594 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", 5595 size, b->offset, err); 5596 continue; 5597 } 5598 5599 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); 5600 } 5601 5602 return 0; 5603 } 5604 5605 static int i915_dpcd_open(struct inode *inode, struct file *file) 5606 { 5607 return single_open(file, i915_dpcd_show, inode->i_private); 5608 } 5609 5610 static const struct file_operations i915_dpcd_fops = { 5611 .owner = THIS_MODULE, 5612 .open = i915_dpcd_open, 5613 .read = seq_read, 5614 .llseek = seq_lseek, 5615 .release = single_release, 5616 }; 5617 5618 static int i915_panel_show(struct seq_file *m, void *data) 5619 { 5620 struct drm_connector *connector = m->private; 5621 struct intel_dp *intel_dp = 5622 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5623 5624 if (connector->status != connector_status_connected) 5625 return -ENODEV; 5626 5627 seq_printf(m, "Panel power up delay: %d\n", 5628 intel_dp->panel_power_up_delay); 5629 seq_printf(m, "Panel power down delay: %d\n", 5630 intel_dp->panel_power_down_delay); 5631 seq_printf(m, "Backlight on delay: %d\n", 5632 intel_dp->backlight_on_delay); 5633 seq_printf(m, "Backlight off delay: %d\n", 5634 intel_dp->backlight_off_delay); 5635 5636 return 0; 5637 } 5638 5639 static int i915_panel_open(struct inode *inode, struct file *file) 5640 { 5641 return single_open(file, i915_panel_show, inode->i_private); 5642 } 5643 5644 static const struct file_operations i915_panel_fops = { 5645 .owner = THIS_MODULE, 5646 .open = i915_panel_open, 5647 .read = seq_read, 5648 .llseek = seq_lseek, 5649 .release = single_release, 5650 }; 5651 5652 /** 5653 * i915_debugfs_connector_add - add i915 specific connector debugfs files 5654 * @connector: pointer to a registered drm_connector 5655 * 5656 * Cleanup will be done by drm_connector_unregister() through a call to 5657 * drm_debugfs_connector_remove(). 5658 * 5659 * Returns 0 on success, negative error codes on error. 5660 */ 5661 int i915_debugfs_connector_add(struct drm_connector *connector) 5662 { 5663 struct dentry *root = connector->debugfs_entry; 5664 5665 /* The connector must have been registered beforehands. */ 5666 if (!root) 5667 return -ENODEV; 5668 5669 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5670 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5671 debugfs_create_file("i915_dpcd", S_IRUGO, root, 5672 connector, &i915_dpcd_fops); 5673 5674 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5675 debugfs_create_file("i915_panel_timings", S_IRUGO, root, 5676 connector, &i915_panel_fops); 5677 5678 return 0; 5679 } 5680