1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 32 #include <drm/drm_debugfs.h> 33 34 #include "gem/i915_gem_context.h" 35 #include "gt/intel_gt.h" 36 #include "gt/intel_gt_buffer_pool.h" 37 #include "gt/intel_gt_clock_utils.h" 38 #include "gt/intel_gt_debugfs.h" 39 #include "gt/intel_gt_pm.h" 40 #include "gt/intel_gt_pm_debugfs.h" 41 #include "gt/intel_gt_requests.h" 42 #include "gt/intel_rc6.h" 43 #include "gt/intel_reset.h" 44 #include "gt/intel_rps.h" 45 #include "gt/intel_sseu_debugfs.h" 46 47 #include "i915_debugfs.h" 48 #include "i915_debugfs_params.h" 49 #include "i915_irq.h" 50 #include "i915_scheduler.h" 51 #include "intel_pm.h" 52 53 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 54 { 55 return to_i915(node->minor->dev); 56 } 57 58 static int i915_capabilities(struct seq_file *m, void *data) 59 { 60 struct drm_i915_private *i915 = node_to_i915(m->private); 61 struct drm_printer p = drm_seq_file_printer(m); 62 63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 64 65 intel_device_info_print_static(INTEL_INFO(i915), &p); 66 intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); 67 i915_print_iommu_status(i915, &p); 68 intel_gt_info_print(&to_gt(i915)->info, &p); 69 intel_driver_caps_print(&i915->caps, &p); 70 71 kernel_param_lock(THIS_MODULE); 72 i915_params_dump(&i915->params, &p); 73 kernel_param_unlock(THIS_MODULE); 74 75 return 0; 76 } 77 78 static char get_tiling_flag(struct drm_i915_gem_object *obj) 79 { 80 switch (i915_gem_object_get_tiling(obj)) { 81 default: 82 case I915_TILING_NONE: return ' '; 83 case I915_TILING_X: return 'X'; 84 case I915_TILING_Y: return 'Y'; 85 } 86 } 87 88 static char get_global_flag(struct drm_i915_gem_object *obj) 89 { 90 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 91 } 92 93 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 94 { 95 return obj->mm.mapping ? 'M' : ' '; 96 } 97 98 static const char * 99 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 100 { 101 size_t x = 0; 102 103 switch (page_sizes) { 104 case 0: 105 return ""; 106 case I915_GTT_PAGE_SIZE_4K: 107 return "4K"; 108 case I915_GTT_PAGE_SIZE_64K: 109 return "64K"; 110 case I915_GTT_PAGE_SIZE_2M: 111 return "2M"; 112 default: 113 if (!buf) 114 return "M"; 115 116 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 117 x += snprintf(buf + x, len - x, "2M, "); 118 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 119 x += snprintf(buf + x, len - x, "64K, "); 120 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 121 x += snprintf(buf + x, len - x, "4K, "); 122 buf[x-2] = '\0'; 123 124 return buf; 125 } 126 } 127 128 static const char *stringify_vma_type(const struct i915_vma *vma) 129 { 130 if (i915_vma_is_ggtt(vma)) 131 return "ggtt"; 132 133 if (i915_vma_is_dpt(vma)) 134 return "dpt"; 135 136 return "ppgtt"; 137 } 138 139 void 140 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 141 { 142 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 143 struct i915_vma *vma; 144 int pin_count = 0; 145 146 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 147 &obj->base, 148 get_tiling_flag(obj), 149 get_global_flag(obj), 150 get_pin_mapped_flag(obj), 151 obj->base.size / 1024, 152 obj->read_domains, 153 obj->write_domain, 154 i915_cache_level_str(dev_priv, obj->cache_level), 155 obj->mm.dirty ? " dirty" : "", 156 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 157 if (obj->base.name) 158 seq_printf(m, " (name: %d)", obj->base.name); 159 160 spin_lock(&obj->vma.lock); 161 list_for_each_entry(vma, &obj->vma.list, obj_link) { 162 if (!drm_mm_node_allocated(&vma->node)) 163 continue; 164 165 spin_unlock(&obj->vma.lock); 166 167 if (i915_vma_is_pinned(vma)) 168 pin_count++; 169 170 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 171 stringify_vma_type(vma), 172 vma->node.start, vma->node.size, 173 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); 174 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 175 switch (vma->ggtt_view.type) { 176 case I915_GGTT_VIEW_NORMAL: 177 seq_puts(m, ", normal"); 178 break; 179 180 case I915_GGTT_VIEW_PARTIAL: 181 seq_printf(m, ", partial [%08llx+%x]", 182 vma->ggtt_view.partial.offset << PAGE_SHIFT, 183 vma->ggtt_view.partial.size << PAGE_SHIFT); 184 break; 185 186 case I915_GGTT_VIEW_ROTATED: 187 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 188 vma->ggtt_view.rotated.plane[0].width, 189 vma->ggtt_view.rotated.plane[0].height, 190 vma->ggtt_view.rotated.plane[0].src_stride, 191 vma->ggtt_view.rotated.plane[0].dst_stride, 192 vma->ggtt_view.rotated.plane[0].offset, 193 vma->ggtt_view.rotated.plane[1].width, 194 vma->ggtt_view.rotated.plane[1].height, 195 vma->ggtt_view.rotated.plane[1].src_stride, 196 vma->ggtt_view.rotated.plane[1].dst_stride, 197 vma->ggtt_view.rotated.plane[1].offset); 198 break; 199 200 case I915_GGTT_VIEW_REMAPPED: 201 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 202 vma->ggtt_view.remapped.plane[0].width, 203 vma->ggtt_view.remapped.plane[0].height, 204 vma->ggtt_view.remapped.plane[0].src_stride, 205 vma->ggtt_view.remapped.plane[0].dst_stride, 206 vma->ggtt_view.remapped.plane[0].offset, 207 vma->ggtt_view.remapped.plane[1].width, 208 vma->ggtt_view.remapped.plane[1].height, 209 vma->ggtt_view.remapped.plane[1].src_stride, 210 vma->ggtt_view.remapped.plane[1].dst_stride, 211 vma->ggtt_view.remapped.plane[1].offset); 212 break; 213 214 default: 215 MISSING_CASE(vma->ggtt_view.type); 216 break; 217 } 218 } 219 if (vma->fence) 220 seq_printf(m, " , fence: %d", vma->fence->id); 221 seq_puts(m, ")"); 222 223 spin_lock(&obj->vma.lock); 224 } 225 spin_unlock(&obj->vma.lock); 226 227 seq_printf(m, " (pinned x %d)", pin_count); 228 if (i915_gem_object_is_stolen(obj)) 229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 230 if (i915_gem_object_is_framebuffer(obj)) 231 seq_printf(m, " (fb)"); 232 } 233 234 static int i915_gem_object_info(struct seq_file *m, void *data) 235 { 236 struct drm_i915_private *i915 = node_to_i915(m->private); 237 struct drm_printer p = drm_seq_file_printer(m); 238 struct intel_memory_region *mr; 239 enum intel_region_id id; 240 241 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 242 i915->mm.shrink_count, 243 atomic_read(&i915->mm.free_count), 244 i915->mm.shrink_memory); 245 for_each_memory_region(mr, i915, id) 246 intel_memory_region_debug(mr, &p); 247 248 return 0; 249 } 250 251 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 252 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 253 size_t count, loff_t *pos) 254 { 255 struct i915_gpu_coredump *error; 256 ssize_t ret; 257 void *buf; 258 259 error = file->private_data; 260 if (!error) 261 return 0; 262 263 /* Bounce buffer required because of kernfs __user API convenience. */ 264 buf = kmalloc(count, GFP_KERNEL); 265 if (!buf) 266 return -ENOMEM; 267 268 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 269 if (ret <= 0) 270 goto out; 271 272 if (!copy_to_user(ubuf, buf, ret)) 273 *pos += ret; 274 else 275 ret = -EFAULT; 276 277 out: 278 kfree(buf); 279 return ret; 280 } 281 282 static int gpu_state_release(struct inode *inode, struct file *file) 283 { 284 i915_gpu_coredump_put(file->private_data); 285 return 0; 286 } 287 288 static int i915_gpu_info_open(struct inode *inode, struct file *file) 289 { 290 struct drm_i915_private *i915 = inode->i_private; 291 struct i915_gpu_coredump *gpu; 292 intel_wakeref_t wakeref; 293 294 gpu = NULL; 295 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 296 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES); 297 if (IS_ERR(gpu)) 298 return PTR_ERR(gpu); 299 300 file->private_data = gpu; 301 return 0; 302 } 303 304 static const struct file_operations i915_gpu_info_fops = { 305 .owner = THIS_MODULE, 306 .open = i915_gpu_info_open, 307 .read = gpu_state_read, 308 .llseek = default_llseek, 309 .release = gpu_state_release, 310 }; 311 312 static ssize_t 313 i915_error_state_write(struct file *filp, 314 const char __user *ubuf, 315 size_t cnt, 316 loff_t *ppos) 317 { 318 struct i915_gpu_coredump *error = filp->private_data; 319 320 if (!error) 321 return 0; 322 323 drm_dbg(&error->i915->drm, "Resetting error state\n"); 324 i915_reset_error_state(error->i915); 325 326 return cnt; 327 } 328 329 static int i915_error_state_open(struct inode *inode, struct file *file) 330 { 331 struct i915_gpu_coredump *error; 332 333 error = i915_first_error_state(inode->i_private); 334 if (IS_ERR(error)) 335 return PTR_ERR(error); 336 337 file->private_data = error; 338 return 0; 339 } 340 341 static const struct file_operations i915_error_state_fops = { 342 .owner = THIS_MODULE, 343 .open = i915_error_state_open, 344 .read = gpu_state_read, 345 .write = i915_error_state_write, 346 .llseek = default_llseek, 347 .release = gpu_state_release, 348 }; 349 #endif 350 351 static int i915_frequency_info(struct seq_file *m, void *unused) 352 { 353 struct drm_i915_private *i915 = node_to_i915(m->private); 354 struct intel_gt *gt = to_gt(i915); 355 struct drm_printer p = drm_seq_file_printer(m); 356 357 intel_gt_pm_frequency_dump(gt, &p); 358 359 return 0; 360 } 361 362 static const char *swizzle_string(unsigned swizzle) 363 { 364 switch (swizzle) { 365 case I915_BIT_6_SWIZZLE_NONE: 366 return "none"; 367 case I915_BIT_6_SWIZZLE_9: 368 return "bit9"; 369 case I915_BIT_6_SWIZZLE_9_10: 370 return "bit9/bit10"; 371 case I915_BIT_6_SWIZZLE_9_11: 372 return "bit9/bit11"; 373 case I915_BIT_6_SWIZZLE_9_10_11: 374 return "bit9/bit10/bit11"; 375 case I915_BIT_6_SWIZZLE_9_17: 376 return "bit9/bit17"; 377 case I915_BIT_6_SWIZZLE_9_10_17: 378 return "bit9/bit10/bit17"; 379 case I915_BIT_6_SWIZZLE_UNKNOWN: 380 return "unknown"; 381 } 382 383 return "bug"; 384 } 385 386 static int i915_swizzle_info(struct seq_file *m, void *data) 387 { 388 struct drm_i915_private *dev_priv = node_to_i915(m->private); 389 struct intel_uncore *uncore = &dev_priv->uncore; 390 intel_wakeref_t wakeref; 391 392 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 393 swizzle_string(dev_priv->ggtt.bit_6_swizzle_x)); 394 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 395 swizzle_string(dev_priv->ggtt.bit_6_swizzle_y)); 396 397 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 398 seq_puts(m, "L-shaped memory detected\n"); 399 400 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 401 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 402 return 0; 403 404 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 405 406 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 407 seq_printf(m, "DDC = 0x%08x\n", 408 intel_uncore_read(uncore, DCC)); 409 seq_printf(m, "DDC2 = 0x%08x\n", 410 intel_uncore_read(uncore, DCC2)); 411 seq_printf(m, "C0DRB3 = 0x%04x\n", 412 intel_uncore_read16(uncore, C0DRB3_BW)); 413 seq_printf(m, "C1DRB3 = 0x%04x\n", 414 intel_uncore_read16(uncore, C1DRB3_BW)); 415 } else if (GRAPHICS_VER(dev_priv) >= 6) { 416 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 417 intel_uncore_read(uncore, MAD_DIMM_C0)); 418 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 419 intel_uncore_read(uncore, MAD_DIMM_C1)); 420 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 421 intel_uncore_read(uncore, MAD_DIMM_C2)); 422 seq_printf(m, "TILECTL = 0x%08x\n", 423 intel_uncore_read(uncore, TILECTL)); 424 if (GRAPHICS_VER(dev_priv) >= 8) 425 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 426 intel_uncore_read(uncore, GAMTARBMODE)); 427 else 428 seq_printf(m, "ARB_MODE = 0x%08x\n", 429 intel_uncore_read(uncore, ARB_MODE)); 430 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 431 intel_uncore_read(uncore, DISP_ARB_CTL)); 432 } 433 434 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 435 436 return 0; 437 } 438 439 static int i915_rps_boost_info(struct seq_file *m, void *data) 440 { 441 struct drm_i915_private *dev_priv = node_to_i915(m->private); 442 struct intel_rps *rps = &to_gt(dev_priv)->rps; 443 444 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 445 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 446 seq_printf(m, "GPU busy? %s\n", yesno(to_gt(dev_priv)->awake)); 447 seq_printf(m, "Boosts outstanding? %d\n", 448 atomic_read(&rps->num_waiters)); 449 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 450 seq_printf(m, "Frequency requested %d, actual %d\n", 451 intel_gpu_freq(rps, rps->cur_freq), 452 intel_rps_read_actual_frequency(rps)); 453 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 454 intel_gpu_freq(rps, rps->min_freq), 455 intel_gpu_freq(rps, rps->min_freq_softlimit), 456 intel_gpu_freq(rps, rps->max_freq_softlimit), 457 intel_gpu_freq(rps, rps->max_freq)); 458 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 459 intel_gpu_freq(rps, rps->idle_freq), 460 intel_gpu_freq(rps, rps->efficient_freq), 461 intel_gpu_freq(rps, rps->boost_freq)); 462 463 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 464 465 return 0; 466 } 467 468 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 469 { 470 struct drm_i915_private *dev_priv = node_to_i915(m->private); 471 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 472 473 if (!HAS_RUNTIME_PM(dev_priv)) 474 seq_puts(m, "Runtime power management not supported\n"); 475 476 seq_printf(m, "Runtime power status: %s\n", 477 enableddisabled(!dev_priv->power_domains.init_wakeref)); 478 479 seq_printf(m, "GPU idle: %s\n", yesno(!to_gt(dev_priv)->awake)); 480 seq_printf(m, "IRQs disabled: %s\n", 481 yesno(!intel_irqs_enabled(dev_priv))); 482 #ifdef CONFIG_PM 483 seq_printf(m, "Usage count: %d\n", 484 atomic_read(&dev_priv->drm.dev->power.usage_count)); 485 #else 486 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 487 #endif 488 seq_printf(m, "PCI device power state: %s [%d]\n", 489 pci_power_name(pdev->current_state), 490 pdev->current_state); 491 492 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 493 struct drm_printer p = drm_seq_file_printer(m); 494 495 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 496 } 497 498 return 0; 499 } 500 501 static int i915_engine_info(struct seq_file *m, void *unused) 502 { 503 struct drm_i915_private *i915 = node_to_i915(m->private); 504 struct intel_engine_cs *engine; 505 intel_wakeref_t wakeref; 506 struct drm_printer p; 507 508 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 509 510 seq_printf(m, "GT awake? %s [%d], %llums\n", 511 yesno(to_gt(i915)->awake), 512 atomic_read(&to_gt(i915)->wakeref.count), 513 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 514 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 515 to_gt(i915)->clock_frequency, 516 to_gt(i915)->clock_period_ns); 517 518 p = drm_seq_file_printer(m); 519 for_each_uabi_engine(engine, i915) 520 intel_engine_dump(engine, &p, "%s\n", engine->name); 521 522 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 523 524 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 525 526 return 0; 527 } 528 529 static int i915_wa_registers(struct seq_file *m, void *unused) 530 { 531 struct drm_i915_private *i915 = node_to_i915(m->private); 532 struct intel_engine_cs *engine; 533 534 for_each_uabi_engine(engine, i915) { 535 const struct i915_wa_list *wal = &engine->ctx_wa_list; 536 const struct i915_wa *wa; 537 unsigned int count; 538 539 count = wal->count; 540 if (!count) 541 continue; 542 543 seq_printf(m, "%s: Workarounds applied: %u\n", 544 engine->name, count); 545 546 for (wa = wal->list; count--; wa++) 547 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 548 i915_mmio_reg_offset(wa->reg), 549 wa->set, wa->clr); 550 551 seq_printf(m, "\n"); 552 } 553 554 return 0; 555 } 556 557 static int i915_wedged_get(void *data, u64 *val) 558 { 559 struct drm_i915_private *i915 = data; 560 561 return intel_gt_debugfs_reset_show(to_gt(i915), val); 562 } 563 564 static int i915_wedged_set(void *data, u64 val) 565 { 566 struct drm_i915_private *i915 = data; 567 568 return intel_gt_debugfs_reset_store(to_gt(i915), val); 569 } 570 571 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 572 i915_wedged_get, i915_wedged_set, 573 "%llu\n"); 574 575 static int 576 i915_perf_noa_delay_set(void *data, u64 val) 577 { 578 struct drm_i915_private *i915 = data; 579 580 /* 581 * This would lead to infinite waits as we're doing timestamp 582 * difference on the CS with only 32bits. 583 */ 584 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 585 return -EINVAL; 586 587 atomic64_set(&i915->perf.noa_programming_delay, val); 588 return 0; 589 } 590 591 static int 592 i915_perf_noa_delay_get(void *data, u64 *val) 593 { 594 struct drm_i915_private *i915 = data; 595 596 *val = atomic64_read(&i915->perf.noa_programming_delay); 597 return 0; 598 } 599 600 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 601 i915_perf_noa_delay_get, 602 i915_perf_noa_delay_set, 603 "%llu\n"); 604 605 #define DROP_UNBOUND BIT(0) 606 #define DROP_BOUND BIT(1) 607 #define DROP_RETIRE BIT(2) 608 #define DROP_ACTIVE BIT(3) 609 #define DROP_FREED BIT(4) 610 #define DROP_SHRINK_ALL BIT(5) 611 #define DROP_IDLE BIT(6) 612 #define DROP_RESET_ACTIVE BIT(7) 613 #define DROP_RESET_SEQNO BIT(8) 614 #define DROP_RCU BIT(9) 615 #define DROP_ALL (DROP_UNBOUND | \ 616 DROP_BOUND | \ 617 DROP_RETIRE | \ 618 DROP_ACTIVE | \ 619 DROP_FREED | \ 620 DROP_SHRINK_ALL |\ 621 DROP_IDLE | \ 622 DROP_RESET_ACTIVE | \ 623 DROP_RESET_SEQNO | \ 624 DROP_RCU) 625 static int 626 i915_drop_caches_get(void *data, u64 *val) 627 { 628 *val = DROP_ALL; 629 630 return 0; 631 } 632 static int 633 gt_drop_caches(struct intel_gt *gt, u64 val) 634 { 635 int ret; 636 637 if (val & DROP_RESET_ACTIVE && 638 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) 639 intel_gt_set_wedged(gt); 640 641 if (val & DROP_RETIRE) 642 intel_gt_retire_requests(gt); 643 644 if (val & (DROP_IDLE | DROP_ACTIVE)) { 645 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 646 if (ret) 647 return ret; 648 } 649 650 if (val & DROP_IDLE) { 651 ret = intel_gt_pm_wait_for_idle(gt); 652 if (ret) 653 return ret; 654 } 655 656 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 657 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 658 659 if (val & DROP_FREED) 660 intel_gt_flush_buffer_pool(gt); 661 662 return 0; 663 } 664 665 static int 666 i915_drop_caches_set(void *data, u64 val) 667 { 668 struct drm_i915_private *i915 = data; 669 unsigned int flags; 670 int ret; 671 672 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", 673 val, val & DROP_ALL); 674 675 ret = gt_drop_caches(to_gt(i915), val); 676 if (ret) 677 return ret; 678 679 fs_reclaim_acquire(GFP_KERNEL); 680 flags = memalloc_noreclaim_save(); 681 if (val & DROP_BOUND) 682 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 683 684 if (val & DROP_UNBOUND) 685 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 686 687 if (val & DROP_SHRINK_ALL) 688 i915_gem_shrink_all(i915); 689 memalloc_noreclaim_restore(flags); 690 fs_reclaim_release(GFP_KERNEL); 691 692 if (val & DROP_RCU) 693 rcu_barrier(); 694 695 if (val & DROP_FREED) 696 i915_gem_drain_freed_objects(i915); 697 698 return 0; 699 } 700 701 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 702 i915_drop_caches_get, i915_drop_caches_set, 703 "0x%08llx\n"); 704 705 static int i915_sseu_status(struct seq_file *m, void *unused) 706 { 707 struct drm_i915_private *i915 = node_to_i915(m->private); 708 struct intel_gt *gt = to_gt(i915); 709 710 return intel_sseu_status(m, gt); 711 } 712 713 static int i915_forcewake_open(struct inode *inode, struct file *file) 714 { 715 struct drm_i915_private *i915 = inode->i_private; 716 717 return intel_gt_pm_debugfs_forcewake_user_open(to_gt(i915)); 718 } 719 720 static int i915_forcewake_release(struct inode *inode, struct file *file) 721 { 722 struct drm_i915_private *i915 = inode->i_private; 723 724 return intel_gt_pm_debugfs_forcewake_user_release(to_gt(i915)); 725 } 726 727 static const struct file_operations i915_forcewake_fops = { 728 .owner = THIS_MODULE, 729 .open = i915_forcewake_open, 730 .release = i915_forcewake_release, 731 }; 732 733 static const struct drm_info_list i915_debugfs_list[] = { 734 {"i915_capabilities", i915_capabilities, 0}, 735 {"i915_gem_objects", i915_gem_object_info, 0}, 736 {"i915_frequency_info", i915_frequency_info, 0}, 737 {"i915_swizzle_info", i915_swizzle_info, 0}, 738 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 739 {"i915_engine_info", i915_engine_info, 0}, 740 {"i915_wa_registers", i915_wa_registers, 0}, 741 {"i915_sseu_status", i915_sseu_status, 0}, 742 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 743 }; 744 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 745 746 static const struct i915_debugfs_files { 747 const char *name; 748 const struct file_operations *fops; 749 } i915_debugfs_files[] = { 750 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 751 {"i915_wedged", &i915_wedged_fops}, 752 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 753 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 754 {"i915_error_state", &i915_error_state_fops}, 755 {"i915_gpu_info", &i915_gpu_info_fops}, 756 #endif 757 }; 758 759 void i915_debugfs_register(struct drm_i915_private *dev_priv) 760 { 761 struct drm_minor *minor = dev_priv->drm.primary; 762 int i; 763 764 i915_debugfs_params(dev_priv); 765 766 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 767 to_i915(minor->dev), &i915_forcewake_fops); 768 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 769 debugfs_create_file(i915_debugfs_files[i].name, 770 S_IRUGO | S_IWUSR, 771 minor->debugfs_root, 772 to_i915(minor->dev), 773 i915_debugfs_files[i].fops); 774 } 775 776 drm_debugfs_create_files(i915_debugfs_list, 777 I915_DEBUGFS_ENTRIES, 778 minor->debugfs_root, minor); 779 } 780