1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/circ_buf.h> 31 #include <linux/ctype.h> 32 #include <linux/debugfs.h> 33 #include <linux/slab.h> 34 #include <linux/export.h> 35 #include <linux/list_sort.h> 36 #include <asm/msr-index.h> 37 #include <drm/drmP.h> 38 #include "intel_drv.h" 39 #include "intel_ringbuffer.h" 40 #include <drm/i915_drm.h> 41 #include "i915_drv.h" 42 43 enum { 44 ACTIVE_LIST, 45 INACTIVE_LIST, 46 PINNED_LIST, 47 }; 48 49 /* As the drm_debugfs_init() routines are called before dev->dev_private is 50 * allocated we need to hook into the minor for release. */ 51 static int 52 drm_add_fake_info_node(struct drm_minor *minor, 53 struct dentry *ent, 54 const void *key) 55 { 56 struct drm_info_node *node; 57 58 node = kmalloc(sizeof(*node), GFP_KERNEL); 59 if (node == NULL) { 60 debugfs_remove(ent); 61 return -ENOMEM; 62 } 63 64 node->minor = minor; 65 node->dent = ent; 66 node->info_ent = (void *) key; 67 68 mutex_lock(&minor->debugfs_lock); 69 list_add(&node->list, &minor->debugfs_list); 70 mutex_unlock(&minor->debugfs_lock); 71 72 return 0; 73 } 74 75 static int i915_capabilities(struct seq_file *m, void *data) 76 { 77 struct drm_info_node *node = m->private; 78 struct drm_device *dev = node->minor->dev; 79 const struct intel_device_info *info = INTEL_INFO(dev); 80 81 seq_printf(m, "gen: %d\n", info->gen); 82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); 83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 84 #define SEP_SEMICOLON ; 85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); 86 #undef PRINT_FLAG 87 #undef SEP_SEMICOLON 88 89 return 0; 90 } 91 92 static const char *get_pin_flag(struct drm_i915_gem_object *obj) 93 { 94 if (obj->pin_display) 95 return "p"; 96 else 97 return " "; 98 } 99 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj) 101 { 102 switch (obj->tiling_mode) { 103 default: 104 case I915_TILING_NONE: return " "; 105 case I915_TILING_X: return "X"; 106 case I915_TILING_Y: return "Y"; 107 } 108 } 109 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj) 111 { 112 return i915_gem_obj_to_ggtt(obj) ? "g" : " "; 113 } 114 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj) 116 { 117 u64 size = 0; 118 struct i915_vma *vma; 119 120 list_for_each_entry(vma, &obj->vma_list, vma_link) { 121 if (i915_is_ggtt(vma->vm) && 122 drm_mm_node_allocated(&vma->node)) 123 size += vma->node.size; 124 } 125 126 return size; 127 } 128 129 static void 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 131 { 132 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 133 struct intel_engine_cs *ring; 134 struct i915_vma *vma; 135 int pin_count = 0; 136 int i; 137 138 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", 139 &obj->base, 140 obj->active ? "*" : " ", 141 get_pin_flag(obj), 142 get_tiling_flag(obj), 143 get_global_flag(obj), 144 obj->base.size / 1024, 145 obj->base.read_domains, 146 obj->base.write_domain); 147 for_each_ring(ring, dev_priv, i) 148 seq_printf(m, "%x ", 149 i915_gem_request_get_seqno(obj->last_read_req[i])); 150 seq_printf(m, "] %x %x%s%s%s", 151 i915_gem_request_get_seqno(obj->last_write_req), 152 i915_gem_request_get_seqno(obj->last_fenced_req), 153 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), 154 obj->dirty ? " dirty" : "", 155 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 156 if (obj->base.name) 157 seq_printf(m, " (name: %d)", obj->base.name); 158 list_for_each_entry(vma, &obj->vma_list, vma_link) { 159 if (vma->pin_count > 0) 160 pin_count++; 161 } 162 seq_printf(m, " (pinned x %d)", pin_count); 163 if (obj->pin_display) 164 seq_printf(m, " (display)"); 165 if (obj->fence_reg != I915_FENCE_REG_NONE) 166 seq_printf(m, " (fence: %d)", obj->fence_reg); 167 list_for_each_entry(vma, &obj->vma_list, vma_link) { 168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx", 169 i915_is_ggtt(vma->vm) ? "g" : "pp", 170 vma->node.start, vma->node.size); 171 if (i915_is_ggtt(vma->vm)) 172 seq_printf(m, ", type: %u)", vma->ggtt_view.type); 173 else 174 seq_puts(m, ")"); 175 } 176 if (obj->stolen) 177 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 178 if (obj->pin_display || obj->fault_mappable) { 179 char s[3], *t = s; 180 if (obj->pin_display) 181 *t++ = 'p'; 182 if (obj->fault_mappable) 183 *t++ = 'f'; 184 *t = '\0'; 185 seq_printf(m, " (%s mappable)", s); 186 } 187 if (obj->last_write_req != NULL) 188 seq_printf(m, " (%s)", 189 i915_gem_request_get_ring(obj->last_write_req)->name); 190 if (obj->frontbuffer_bits) 191 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); 192 } 193 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx) 195 { 196 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); 197 seq_putc(m, ctx->remap_slice ? 'R' : 'r'); 198 seq_putc(m, ' '); 199 } 200 201 static int i915_gem_object_list_info(struct seq_file *m, void *data) 202 { 203 struct drm_info_node *node = m->private; 204 uintptr_t list = (uintptr_t) node->info_ent->data; 205 struct list_head *head; 206 struct drm_device *dev = node->minor->dev; 207 struct drm_i915_private *dev_priv = dev->dev_private; 208 struct i915_address_space *vm = &dev_priv->gtt.base; 209 struct i915_vma *vma; 210 u64 total_obj_size, total_gtt_size; 211 int count, ret; 212 213 ret = mutex_lock_interruptible(&dev->struct_mutex); 214 if (ret) 215 return ret; 216 217 /* FIXME: the user of this interface might want more than just GGTT */ 218 switch (list) { 219 case ACTIVE_LIST: 220 seq_puts(m, "Active:\n"); 221 head = &vm->active_list; 222 break; 223 case INACTIVE_LIST: 224 seq_puts(m, "Inactive:\n"); 225 head = &vm->inactive_list; 226 break; 227 default: 228 mutex_unlock(&dev->struct_mutex); 229 return -EINVAL; 230 } 231 232 total_obj_size = total_gtt_size = count = 0; 233 list_for_each_entry(vma, head, mm_list) { 234 seq_printf(m, " "); 235 describe_obj(m, vma->obj); 236 seq_printf(m, "\n"); 237 total_obj_size += vma->obj->base.size; 238 total_gtt_size += vma->node.size; 239 count++; 240 } 241 mutex_unlock(&dev->struct_mutex); 242 243 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 244 count, total_obj_size, total_gtt_size); 245 return 0; 246 } 247 248 static int obj_rank_by_stolen(void *priv, 249 struct list_head *A, struct list_head *B) 250 { 251 struct drm_i915_gem_object *a = 252 container_of(A, struct drm_i915_gem_object, obj_exec_link); 253 struct drm_i915_gem_object *b = 254 container_of(B, struct drm_i915_gem_object, obj_exec_link); 255 256 if (a->stolen->start < b->stolen->start) 257 return -1; 258 if (a->stolen->start > b->stolen->start) 259 return 1; 260 return 0; 261 } 262 263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data) 264 { 265 struct drm_info_node *node = m->private; 266 struct drm_device *dev = node->minor->dev; 267 struct drm_i915_private *dev_priv = dev->dev_private; 268 struct drm_i915_gem_object *obj; 269 u64 total_obj_size, total_gtt_size; 270 LIST_HEAD(stolen); 271 int count, ret; 272 273 ret = mutex_lock_interruptible(&dev->struct_mutex); 274 if (ret) 275 return ret; 276 277 total_obj_size = total_gtt_size = count = 0; 278 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 279 if (obj->stolen == NULL) 280 continue; 281 282 list_add(&obj->obj_exec_link, &stolen); 283 284 total_obj_size += obj->base.size; 285 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 286 count++; 287 } 288 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 289 if (obj->stolen == NULL) 290 continue; 291 292 list_add(&obj->obj_exec_link, &stolen); 293 294 total_obj_size += obj->base.size; 295 count++; 296 } 297 list_sort(NULL, &stolen, obj_rank_by_stolen); 298 seq_puts(m, "Stolen:\n"); 299 while (!list_empty(&stolen)) { 300 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); 301 seq_puts(m, " "); 302 describe_obj(m, obj); 303 seq_putc(m, '\n'); 304 list_del_init(&obj->obj_exec_link); 305 } 306 mutex_unlock(&dev->struct_mutex); 307 308 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 309 count, total_obj_size, total_gtt_size); 310 return 0; 311 } 312 313 #define count_objects(list, member) do { \ 314 list_for_each_entry(obj, list, member) { \ 315 size += i915_gem_obj_total_ggtt_size(obj); \ 316 ++count; \ 317 if (obj->map_and_fenceable) { \ 318 mappable_size += i915_gem_obj_ggtt_size(obj); \ 319 ++mappable_count; \ 320 } \ 321 } \ 322 } while (0) 323 324 struct file_stats { 325 struct drm_i915_file_private *file_priv; 326 unsigned long count; 327 u64 total, unbound; 328 u64 global, shared; 329 u64 active, inactive; 330 }; 331 332 static int per_file_stats(int id, void *ptr, void *data) 333 { 334 struct drm_i915_gem_object *obj = ptr; 335 struct file_stats *stats = data; 336 struct i915_vma *vma; 337 338 stats->count++; 339 stats->total += obj->base.size; 340 341 if (obj->base.name || obj->base.dma_buf) 342 stats->shared += obj->base.size; 343 344 if (USES_FULL_PPGTT(obj->base.dev)) { 345 list_for_each_entry(vma, &obj->vma_list, vma_link) { 346 struct i915_hw_ppgtt *ppgtt; 347 348 if (!drm_mm_node_allocated(&vma->node)) 349 continue; 350 351 if (i915_is_ggtt(vma->vm)) { 352 stats->global += obj->base.size; 353 continue; 354 } 355 356 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); 357 if (ppgtt->file_priv != stats->file_priv) 358 continue; 359 360 if (obj->active) /* XXX per-vma statistic */ 361 stats->active += obj->base.size; 362 else 363 stats->inactive += obj->base.size; 364 365 return 0; 366 } 367 } else { 368 if (i915_gem_obj_ggtt_bound(obj)) { 369 stats->global += obj->base.size; 370 if (obj->active) 371 stats->active += obj->base.size; 372 else 373 stats->inactive += obj->base.size; 374 return 0; 375 } 376 } 377 378 if (!list_empty(&obj->global_list)) 379 stats->unbound += obj->base.size; 380 381 return 0; 382 } 383 384 #define print_file_stats(m, name, stats) do { \ 385 if (stats.count) \ 386 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \ 387 name, \ 388 stats.count, \ 389 stats.total, \ 390 stats.active, \ 391 stats.inactive, \ 392 stats.global, \ 393 stats.shared, \ 394 stats.unbound); \ 395 } while (0) 396 397 static void print_batch_pool_stats(struct seq_file *m, 398 struct drm_i915_private *dev_priv) 399 { 400 struct drm_i915_gem_object *obj; 401 struct file_stats stats; 402 struct intel_engine_cs *ring; 403 int i, j; 404 405 memset(&stats, 0, sizeof(stats)); 406 407 for_each_ring(ring, dev_priv, i) { 408 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { 409 list_for_each_entry(obj, 410 &ring->batch_pool.cache_list[j], 411 batch_pool_link) 412 per_file_stats(0, obj, &stats); 413 } 414 } 415 416 print_file_stats(m, "[k]batch pool", stats); 417 } 418 419 #define count_vmas(list, member) do { \ 420 list_for_each_entry(vma, list, member) { \ 421 size += i915_gem_obj_total_ggtt_size(vma->obj); \ 422 ++count; \ 423 if (vma->obj->map_and_fenceable) { \ 424 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ 425 ++mappable_count; \ 426 } \ 427 } \ 428 } while (0) 429 430 static int i915_gem_object_info(struct seq_file *m, void* data) 431 { 432 struct drm_info_node *node = m->private; 433 struct drm_device *dev = node->minor->dev; 434 struct drm_i915_private *dev_priv = dev->dev_private; 435 u32 count, mappable_count, purgeable_count; 436 u64 size, mappable_size, purgeable_size; 437 struct drm_i915_gem_object *obj; 438 struct i915_address_space *vm = &dev_priv->gtt.base; 439 struct drm_file *file; 440 struct i915_vma *vma; 441 int ret; 442 443 ret = mutex_lock_interruptible(&dev->struct_mutex); 444 if (ret) 445 return ret; 446 447 seq_printf(m, "%u objects, %zu bytes\n", 448 dev_priv->mm.object_count, 449 dev_priv->mm.object_memory); 450 451 size = count = mappable_size = mappable_count = 0; 452 count_objects(&dev_priv->mm.bound_list, global_list); 453 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n", 454 count, mappable_count, size, mappable_size); 455 456 size = count = mappable_size = mappable_count = 0; 457 count_vmas(&vm->active_list, mm_list); 458 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n", 459 count, mappable_count, size, mappable_size); 460 461 size = count = mappable_size = mappable_count = 0; 462 count_vmas(&vm->inactive_list, mm_list); 463 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n", 464 count, mappable_count, size, mappable_size); 465 466 size = count = purgeable_size = purgeable_count = 0; 467 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 468 size += obj->base.size, ++count; 469 if (obj->madv == I915_MADV_DONTNEED) 470 purgeable_size += obj->base.size, ++purgeable_count; 471 } 472 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size); 473 474 size = count = mappable_size = mappable_count = 0; 475 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 476 if (obj->fault_mappable) { 477 size += i915_gem_obj_ggtt_size(obj); 478 ++count; 479 } 480 if (obj->pin_display) { 481 mappable_size += i915_gem_obj_ggtt_size(obj); 482 ++mappable_count; 483 } 484 if (obj->madv == I915_MADV_DONTNEED) { 485 purgeable_size += obj->base.size; 486 ++purgeable_count; 487 } 488 } 489 seq_printf(m, "%u purgeable objects, %llu bytes\n", 490 purgeable_count, purgeable_size); 491 seq_printf(m, "%u pinned mappable objects, %llu bytes\n", 492 mappable_count, mappable_size); 493 seq_printf(m, "%u fault mappable objects, %llu bytes\n", 494 count, size); 495 496 seq_printf(m, "%llu [%llu] gtt total\n", 497 dev_priv->gtt.base.total, 498 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); 499 500 seq_putc(m, '\n'); 501 print_batch_pool_stats(m, dev_priv); 502 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 503 struct file_stats stats; 504 struct task_struct *task; 505 506 memset(&stats, 0, sizeof(stats)); 507 stats.file_priv = file->driver_priv; 508 spin_lock(&file->table_lock); 509 idr_for_each(&file->object_idr, per_file_stats, &stats); 510 spin_unlock(&file->table_lock); 511 /* 512 * Although we have a valid reference on file->pid, that does 513 * not guarantee that the task_struct who called get_pid() is 514 * still alive (e.g. get_pid(current) => fork() => exit()). 515 * Therefore, we need to protect this ->comm access using RCU. 516 */ 517 rcu_read_lock(); 518 task = pid_task(file->pid, PIDTYPE_PID); 519 print_file_stats(m, task ? task->comm : "<unknown>", stats); 520 rcu_read_unlock(); 521 } 522 523 mutex_unlock(&dev->struct_mutex); 524 525 return 0; 526 } 527 528 static int i915_gem_gtt_info(struct seq_file *m, void *data) 529 { 530 struct drm_info_node *node = m->private; 531 struct drm_device *dev = node->minor->dev; 532 uintptr_t list = (uintptr_t) node->info_ent->data; 533 struct drm_i915_private *dev_priv = dev->dev_private; 534 struct drm_i915_gem_object *obj; 535 u64 total_obj_size, total_gtt_size; 536 int count, ret; 537 538 ret = mutex_lock_interruptible(&dev->struct_mutex); 539 if (ret) 540 return ret; 541 542 total_obj_size = total_gtt_size = count = 0; 543 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 544 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) 545 continue; 546 547 seq_puts(m, " "); 548 describe_obj(m, obj); 549 seq_putc(m, '\n'); 550 total_obj_size += obj->base.size; 551 total_gtt_size += i915_gem_obj_total_ggtt_size(obj); 552 count++; 553 } 554 555 mutex_unlock(&dev->struct_mutex); 556 557 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n", 558 count, total_obj_size, total_gtt_size); 559 560 return 0; 561 } 562 563 static int i915_gem_pageflip_info(struct seq_file *m, void *data) 564 { 565 struct drm_info_node *node = m->private; 566 struct drm_device *dev = node->minor->dev; 567 struct drm_i915_private *dev_priv = dev->dev_private; 568 struct intel_crtc *crtc; 569 int ret; 570 571 ret = mutex_lock_interruptible(&dev->struct_mutex); 572 if (ret) 573 return ret; 574 575 for_each_intel_crtc(dev, crtc) { 576 const char pipe = pipe_name(crtc->pipe); 577 const char plane = plane_name(crtc->plane); 578 struct intel_unpin_work *work; 579 580 spin_lock_irq(&dev->event_lock); 581 work = crtc->unpin_work; 582 if (work == NULL) { 583 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 584 pipe, plane); 585 } else { 586 u32 addr; 587 588 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 589 seq_printf(m, "Flip queued on pipe %c (plane %c)\n", 590 pipe, plane); 591 } else { 592 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 593 pipe, plane); 594 } 595 if (work->flip_queued_req) { 596 struct intel_engine_cs *ring = 597 i915_gem_request_get_ring(work->flip_queued_req); 598 599 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", 600 ring->name, 601 i915_gem_request_get_seqno(work->flip_queued_req), 602 dev_priv->next_seqno, 603 ring->get_seqno(ring, true), 604 i915_gem_request_completed(work->flip_queued_req, true)); 605 } else 606 seq_printf(m, "Flip not associated with any ring\n"); 607 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", 608 work->flip_queued_vblank, 609 work->flip_ready_vblank, 610 drm_crtc_vblank_count(&crtc->base)); 611 if (work->enable_stall_check) 612 seq_puts(m, "Stall check enabled, "); 613 else 614 seq_puts(m, "Stall check waiting for page flip ioctl, "); 615 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 616 617 if (INTEL_INFO(dev)->gen >= 4) 618 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); 619 else 620 addr = I915_READ(DSPADDR(crtc->plane)); 621 seq_printf(m, "Current scanout address 0x%08x\n", addr); 622 623 if (work->pending_flip_obj) { 624 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); 625 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); 626 } 627 } 628 spin_unlock_irq(&dev->event_lock); 629 } 630 631 mutex_unlock(&dev->struct_mutex); 632 633 return 0; 634 } 635 636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data) 637 { 638 struct drm_info_node *node = m->private; 639 struct drm_device *dev = node->minor->dev; 640 struct drm_i915_private *dev_priv = dev->dev_private; 641 struct drm_i915_gem_object *obj; 642 struct intel_engine_cs *ring; 643 int total = 0; 644 int ret, i, j; 645 646 ret = mutex_lock_interruptible(&dev->struct_mutex); 647 if (ret) 648 return ret; 649 650 for_each_ring(ring, dev_priv, i) { 651 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { 652 int count; 653 654 count = 0; 655 list_for_each_entry(obj, 656 &ring->batch_pool.cache_list[j], 657 batch_pool_link) 658 count++; 659 seq_printf(m, "%s cache[%d]: %d objects\n", 660 ring->name, j, count); 661 662 list_for_each_entry(obj, 663 &ring->batch_pool.cache_list[j], 664 batch_pool_link) { 665 seq_puts(m, " "); 666 describe_obj(m, obj); 667 seq_putc(m, '\n'); 668 } 669 670 total += count; 671 } 672 } 673 674 seq_printf(m, "total: %d\n", total); 675 676 mutex_unlock(&dev->struct_mutex); 677 678 return 0; 679 } 680 681 static int i915_gem_request_info(struct seq_file *m, void *data) 682 { 683 struct drm_info_node *node = m->private; 684 struct drm_device *dev = node->minor->dev; 685 struct drm_i915_private *dev_priv = dev->dev_private; 686 struct intel_engine_cs *ring; 687 struct drm_i915_gem_request *req; 688 int ret, any, i; 689 690 ret = mutex_lock_interruptible(&dev->struct_mutex); 691 if (ret) 692 return ret; 693 694 any = 0; 695 for_each_ring(ring, dev_priv, i) { 696 int count; 697 698 count = 0; 699 list_for_each_entry(req, &ring->request_list, list) 700 count++; 701 if (count == 0) 702 continue; 703 704 seq_printf(m, "%s requests: %d\n", ring->name, count); 705 list_for_each_entry(req, &ring->request_list, list) { 706 struct task_struct *task; 707 708 rcu_read_lock(); 709 task = NULL; 710 if (req->pid) 711 task = pid_task(req->pid, PIDTYPE_PID); 712 seq_printf(m, " %x @ %d: %s [%d]\n", 713 req->seqno, 714 (int) (jiffies - req->emitted_jiffies), 715 task ? task->comm : "<unknown>", 716 task ? task->pid : -1); 717 rcu_read_unlock(); 718 } 719 720 any++; 721 } 722 mutex_unlock(&dev->struct_mutex); 723 724 if (any == 0) 725 seq_puts(m, "No requests\n"); 726 727 return 0; 728 } 729 730 static void i915_ring_seqno_info(struct seq_file *m, 731 struct intel_engine_cs *ring) 732 { 733 if (ring->get_seqno) { 734 seq_printf(m, "Current sequence (%s): %x\n", 735 ring->name, ring->get_seqno(ring, false)); 736 } 737 } 738 739 static int i915_gem_seqno_info(struct seq_file *m, void *data) 740 { 741 struct drm_info_node *node = m->private; 742 struct drm_device *dev = node->minor->dev; 743 struct drm_i915_private *dev_priv = dev->dev_private; 744 struct intel_engine_cs *ring; 745 int ret, i; 746 747 ret = mutex_lock_interruptible(&dev->struct_mutex); 748 if (ret) 749 return ret; 750 intel_runtime_pm_get(dev_priv); 751 752 for_each_ring(ring, dev_priv, i) 753 i915_ring_seqno_info(m, ring); 754 755 intel_runtime_pm_put(dev_priv); 756 mutex_unlock(&dev->struct_mutex); 757 758 return 0; 759 } 760 761 762 static int i915_interrupt_info(struct seq_file *m, void *data) 763 { 764 struct drm_info_node *node = m->private; 765 struct drm_device *dev = node->minor->dev; 766 struct drm_i915_private *dev_priv = dev->dev_private; 767 struct intel_engine_cs *ring; 768 int ret, i, pipe; 769 770 ret = mutex_lock_interruptible(&dev->struct_mutex); 771 if (ret) 772 return ret; 773 intel_runtime_pm_get(dev_priv); 774 775 if (IS_CHERRYVIEW(dev)) { 776 seq_printf(m, "Master Interrupt Control:\t%08x\n", 777 I915_READ(GEN8_MASTER_IRQ)); 778 779 seq_printf(m, "Display IER:\t%08x\n", 780 I915_READ(VLV_IER)); 781 seq_printf(m, "Display IIR:\t%08x\n", 782 I915_READ(VLV_IIR)); 783 seq_printf(m, "Display IIR_RW:\t%08x\n", 784 I915_READ(VLV_IIR_RW)); 785 seq_printf(m, "Display IMR:\t%08x\n", 786 I915_READ(VLV_IMR)); 787 for_each_pipe(dev_priv, pipe) 788 seq_printf(m, "Pipe %c stat:\t%08x\n", 789 pipe_name(pipe), 790 I915_READ(PIPESTAT(pipe))); 791 792 seq_printf(m, "Port hotplug:\t%08x\n", 793 I915_READ(PORT_HOTPLUG_EN)); 794 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 795 I915_READ(VLV_DPFLIPSTAT)); 796 seq_printf(m, "DPINVGTT:\t%08x\n", 797 I915_READ(DPINVGTT)); 798 799 for (i = 0; i < 4; i++) { 800 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 801 i, I915_READ(GEN8_GT_IMR(i))); 802 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 803 i, I915_READ(GEN8_GT_IIR(i))); 804 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 805 i, I915_READ(GEN8_GT_IER(i))); 806 } 807 808 seq_printf(m, "PCU interrupt mask:\t%08x\n", 809 I915_READ(GEN8_PCU_IMR)); 810 seq_printf(m, "PCU interrupt identity:\t%08x\n", 811 I915_READ(GEN8_PCU_IIR)); 812 seq_printf(m, "PCU interrupt enable:\t%08x\n", 813 I915_READ(GEN8_PCU_IER)); 814 } else if (INTEL_INFO(dev)->gen >= 8) { 815 seq_printf(m, "Master Interrupt Control:\t%08x\n", 816 I915_READ(GEN8_MASTER_IRQ)); 817 818 for (i = 0; i < 4; i++) { 819 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 820 i, I915_READ(GEN8_GT_IMR(i))); 821 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 822 i, I915_READ(GEN8_GT_IIR(i))); 823 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 824 i, I915_READ(GEN8_GT_IER(i))); 825 } 826 827 for_each_pipe(dev_priv, pipe) { 828 if (!intel_display_power_is_enabled(dev_priv, 829 POWER_DOMAIN_PIPE(pipe))) { 830 seq_printf(m, "Pipe %c power disabled\n", 831 pipe_name(pipe)); 832 continue; 833 } 834 seq_printf(m, "Pipe %c IMR:\t%08x\n", 835 pipe_name(pipe), 836 I915_READ(GEN8_DE_PIPE_IMR(pipe))); 837 seq_printf(m, "Pipe %c IIR:\t%08x\n", 838 pipe_name(pipe), 839 I915_READ(GEN8_DE_PIPE_IIR(pipe))); 840 seq_printf(m, "Pipe %c IER:\t%08x\n", 841 pipe_name(pipe), 842 I915_READ(GEN8_DE_PIPE_IER(pipe))); 843 } 844 845 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", 846 I915_READ(GEN8_DE_PORT_IMR)); 847 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", 848 I915_READ(GEN8_DE_PORT_IIR)); 849 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", 850 I915_READ(GEN8_DE_PORT_IER)); 851 852 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", 853 I915_READ(GEN8_DE_MISC_IMR)); 854 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", 855 I915_READ(GEN8_DE_MISC_IIR)); 856 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", 857 I915_READ(GEN8_DE_MISC_IER)); 858 859 seq_printf(m, "PCU interrupt mask:\t%08x\n", 860 I915_READ(GEN8_PCU_IMR)); 861 seq_printf(m, "PCU interrupt identity:\t%08x\n", 862 I915_READ(GEN8_PCU_IIR)); 863 seq_printf(m, "PCU interrupt enable:\t%08x\n", 864 I915_READ(GEN8_PCU_IER)); 865 } else if (IS_VALLEYVIEW(dev)) { 866 seq_printf(m, "Display IER:\t%08x\n", 867 I915_READ(VLV_IER)); 868 seq_printf(m, "Display IIR:\t%08x\n", 869 I915_READ(VLV_IIR)); 870 seq_printf(m, "Display IIR_RW:\t%08x\n", 871 I915_READ(VLV_IIR_RW)); 872 seq_printf(m, "Display IMR:\t%08x\n", 873 I915_READ(VLV_IMR)); 874 for_each_pipe(dev_priv, pipe) 875 seq_printf(m, "Pipe %c stat:\t%08x\n", 876 pipe_name(pipe), 877 I915_READ(PIPESTAT(pipe))); 878 879 seq_printf(m, "Master IER:\t%08x\n", 880 I915_READ(VLV_MASTER_IER)); 881 882 seq_printf(m, "Render IER:\t%08x\n", 883 I915_READ(GTIER)); 884 seq_printf(m, "Render IIR:\t%08x\n", 885 I915_READ(GTIIR)); 886 seq_printf(m, "Render IMR:\t%08x\n", 887 I915_READ(GTIMR)); 888 889 seq_printf(m, "PM IER:\t\t%08x\n", 890 I915_READ(GEN6_PMIER)); 891 seq_printf(m, "PM IIR:\t\t%08x\n", 892 I915_READ(GEN6_PMIIR)); 893 seq_printf(m, "PM IMR:\t\t%08x\n", 894 I915_READ(GEN6_PMIMR)); 895 896 seq_printf(m, "Port hotplug:\t%08x\n", 897 I915_READ(PORT_HOTPLUG_EN)); 898 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 899 I915_READ(VLV_DPFLIPSTAT)); 900 seq_printf(m, "DPINVGTT:\t%08x\n", 901 I915_READ(DPINVGTT)); 902 903 } else if (!HAS_PCH_SPLIT(dev)) { 904 seq_printf(m, "Interrupt enable: %08x\n", 905 I915_READ(IER)); 906 seq_printf(m, "Interrupt identity: %08x\n", 907 I915_READ(IIR)); 908 seq_printf(m, "Interrupt mask: %08x\n", 909 I915_READ(IMR)); 910 for_each_pipe(dev_priv, pipe) 911 seq_printf(m, "Pipe %c stat: %08x\n", 912 pipe_name(pipe), 913 I915_READ(PIPESTAT(pipe))); 914 } else { 915 seq_printf(m, "North Display Interrupt enable: %08x\n", 916 I915_READ(DEIER)); 917 seq_printf(m, "North Display Interrupt identity: %08x\n", 918 I915_READ(DEIIR)); 919 seq_printf(m, "North Display Interrupt mask: %08x\n", 920 I915_READ(DEIMR)); 921 seq_printf(m, "South Display Interrupt enable: %08x\n", 922 I915_READ(SDEIER)); 923 seq_printf(m, "South Display Interrupt identity: %08x\n", 924 I915_READ(SDEIIR)); 925 seq_printf(m, "South Display Interrupt mask: %08x\n", 926 I915_READ(SDEIMR)); 927 seq_printf(m, "Graphics Interrupt enable: %08x\n", 928 I915_READ(GTIER)); 929 seq_printf(m, "Graphics Interrupt identity: %08x\n", 930 I915_READ(GTIIR)); 931 seq_printf(m, "Graphics Interrupt mask: %08x\n", 932 I915_READ(GTIMR)); 933 } 934 for_each_ring(ring, dev_priv, i) { 935 if (INTEL_INFO(dev)->gen >= 6) { 936 seq_printf(m, 937 "Graphics Interrupt mask (%s): %08x\n", 938 ring->name, I915_READ_IMR(ring)); 939 } 940 i915_ring_seqno_info(m, ring); 941 } 942 intel_runtime_pm_put(dev_priv); 943 mutex_unlock(&dev->struct_mutex); 944 945 return 0; 946 } 947 948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 949 { 950 struct drm_info_node *node = m->private; 951 struct drm_device *dev = node->minor->dev; 952 struct drm_i915_private *dev_priv = dev->dev_private; 953 int i, ret; 954 955 ret = mutex_lock_interruptible(&dev->struct_mutex); 956 if (ret) 957 return ret; 958 959 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 960 for (i = 0; i < dev_priv->num_fence_regs; i++) { 961 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; 962 963 seq_printf(m, "Fence %d, pin count = %d, object = ", 964 i, dev_priv->fence_regs[i].pin_count); 965 if (obj == NULL) 966 seq_puts(m, "unused"); 967 else 968 describe_obj(m, obj); 969 seq_putc(m, '\n'); 970 } 971 972 mutex_unlock(&dev->struct_mutex); 973 return 0; 974 } 975 976 static int i915_hws_info(struct seq_file *m, void *data) 977 { 978 struct drm_info_node *node = m->private; 979 struct drm_device *dev = node->minor->dev; 980 struct drm_i915_private *dev_priv = dev->dev_private; 981 struct intel_engine_cs *ring; 982 const u32 *hws; 983 int i; 984 985 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; 986 hws = ring->status_page.page_addr; 987 if (hws == NULL) 988 return 0; 989 990 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 991 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 992 i * 4, 993 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 994 } 995 return 0; 996 } 997 998 static ssize_t 999 i915_error_state_write(struct file *filp, 1000 const char __user *ubuf, 1001 size_t cnt, 1002 loff_t *ppos) 1003 { 1004 struct i915_error_state_file_priv *error_priv = filp->private_data; 1005 struct drm_device *dev = error_priv->dev; 1006 int ret; 1007 1008 DRM_DEBUG_DRIVER("Resetting error state\n"); 1009 1010 ret = mutex_lock_interruptible(&dev->struct_mutex); 1011 if (ret) 1012 return ret; 1013 1014 i915_destroy_error_state(dev); 1015 mutex_unlock(&dev->struct_mutex); 1016 1017 return cnt; 1018 } 1019 1020 static int i915_error_state_open(struct inode *inode, struct file *file) 1021 { 1022 struct drm_device *dev = inode->i_private; 1023 struct i915_error_state_file_priv *error_priv; 1024 1025 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); 1026 if (!error_priv) 1027 return -ENOMEM; 1028 1029 error_priv->dev = dev; 1030 1031 i915_error_state_get(dev, error_priv); 1032 1033 file->private_data = error_priv; 1034 1035 return 0; 1036 } 1037 1038 static int i915_error_state_release(struct inode *inode, struct file *file) 1039 { 1040 struct i915_error_state_file_priv *error_priv = file->private_data; 1041 1042 i915_error_state_put(error_priv); 1043 kfree(error_priv); 1044 1045 return 0; 1046 } 1047 1048 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, 1049 size_t count, loff_t *pos) 1050 { 1051 struct i915_error_state_file_priv *error_priv = file->private_data; 1052 struct drm_i915_error_state_buf error_str; 1053 loff_t tmp_pos = 0; 1054 ssize_t ret_count = 0; 1055 int ret; 1056 1057 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); 1058 if (ret) 1059 return ret; 1060 1061 ret = i915_error_state_to_str(&error_str, error_priv); 1062 if (ret) 1063 goto out; 1064 1065 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, 1066 error_str.buf, 1067 error_str.bytes); 1068 1069 if (ret_count < 0) 1070 ret = ret_count; 1071 else 1072 *pos = error_str.start + ret_count; 1073 out: 1074 i915_error_state_buf_release(&error_str); 1075 return ret ?: ret_count; 1076 } 1077 1078 static const struct file_operations i915_error_state_fops = { 1079 .owner = THIS_MODULE, 1080 .open = i915_error_state_open, 1081 .read = i915_error_state_read, 1082 .write = i915_error_state_write, 1083 .llseek = default_llseek, 1084 .release = i915_error_state_release, 1085 }; 1086 1087 static int 1088 i915_next_seqno_get(void *data, u64 *val) 1089 { 1090 struct drm_device *dev = data; 1091 struct drm_i915_private *dev_priv = dev->dev_private; 1092 int ret; 1093 1094 ret = mutex_lock_interruptible(&dev->struct_mutex); 1095 if (ret) 1096 return ret; 1097 1098 *val = dev_priv->next_seqno; 1099 mutex_unlock(&dev->struct_mutex); 1100 1101 return 0; 1102 } 1103 1104 static int 1105 i915_next_seqno_set(void *data, u64 val) 1106 { 1107 struct drm_device *dev = data; 1108 int ret; 1109 1110 ret = mutex_lock_interruptible(&dev->struct_mutex); 1111 if (ret) 1112 return ret; 1113 1114 ret = i915_gem_set_seqno(dev, val); 1115 mutex_unlock(&dev->struct_mutex); 1116 1117 return ret; 1118 } 1119 1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 1121 i915_next_seqno_get, i915_next_seqno_set, 1122 "0x%llx\n"); 1123 1124 static int i915_frequency_info(struct seq_file *m, void *unused) 1125 { 1126 struct drm_info_node *node = m->private; 1127 struct drm_device *dev = node->minor->dev; 1128 struct drm_i915_private *dev_priv = dev->dev_private; 1129 int ret = 0; 1130 1131 intel_runtime_pm_get(dev_priv); 1132 1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 1134 1135 if (IS_GEN5(dev)) { 1136 u16 rgvswctl = I915_READ16(MEMSWCTL); 1137 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 1138 1139 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 1140 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 1141 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 1142 MEMSTAT_VID_SHIFT); 1143 seq_printf(m, "Current P-state: %d\n", 1144 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 1145 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1146 u32 freq_sts; 1147 1148 mutex_lock(&dev_priv->rps.hw_lock); 1149 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 1150 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 1151 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1152 1153 seq_printf(m, "actual GPU freq: %d MHz\n", 1154 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); 1155 1156 seq_printf(m, "current GPU freq: %d MHz\n", 1157 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1158 1159 seq_printf(m, "max GPU freq: %d MHz\n", 1160 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1161 1162 seq_printf(m, "min GPU freq: %d MHz\n", 1163 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1164 1165 seq_printf(m, "idle GPU freq: %d MHz\n", 1166 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1167 1168 seq_printf(m, 1169 "efficient (RPe) frequency: %d MHz\n", 1170 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1171 mutex_unlock(&dev_priv->rps.hw_lock); 1172 } else if (INTEL_INFO(dev)->gen >= 6) { 1173 u32 rp_state_limits; 1174 u32 gt_perf_status; 1175 u32 rp_state_cap; 1176 u32 rpmodectl, rpinclimit, rpdeclimit; 1177 u32 rpstat, cagf, reqf; 1178 u32 rpupei, rpcurup, rpprevup; 1179 u32 rpdownei, rpcurdown, rpprevdown; 1180 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 1181 int max_freq; 1182 1183 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 1184 if (IS_BROXTON(dev)) { 1185 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 1186 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); 1187 } else { 1188 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 1189 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 1190 } 1191 1192 /* RPSTAT1 is in the GT power well */ 1193 ret = mutex_lock_interruptible(&dev->struct_mutex); 1194 if (ret) 1195 goto out; 1196 1197 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1198 1199 reqf = I915_READ(GEN6_RPNSWREQ); 1200 if (IS_GEN9(dev)) 1201 reqf >>= 23; 1202 else { 1203 reqf &= ~GEN6_TURBO_DISABLE; 1204 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1205 reqf >>= 24; 1206 else 1207 reqf >>= 25; 1208 } 1209 reqf = intel_gpu_freq(dev_priv, reqf); 1210 1211 rpmodectl = I915_READ(GEN6_RP_CONTROL); 1212 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); 1213 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); 1214 1215 rpstat = I915_READ(GEN6_RPSTAT1); 1216 rpupei = I915_READ(GEN6_RP_CUR_UP_EI); 1217 rpcurup = I915_READ(GEN6_RP_CUR_UP); 1218 rpprevup = I915_READ(GEN6_RP_PREV_UP); 1219 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); 1220 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); 1221 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); 1222 if (IS_GEN9(dev)) 1223 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 1224 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1225 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 1226 else 1227 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 1228 cagf = intel_gpu_freq(dev_priv, cagf); 1229 1230 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1231 mutex_unlock(&dev->struct_mutex); 1232 1233 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1234 pm_ier = I915_READ(GEN6_PMIER); 1235 pm_imr = I915_READ(GEN6_PMIMR); 1236 pm_isr = I915_READ(GEN6_PMISR); 1237 pm_iir = I915_READ(GEN6_PMIIR); 1238 pm_mask = I915_READ(GEN6_PMINTRMSK); 1239 } else { 1240 pm_ier = I915_READ(GEN8_GT_IER(2)); 1241 pm_imr = I915_READ(GEN8_GT_IMR(2)); 1242 pm_isr = I915_READ(GEN8_GT_ISR(2)); 1243 pm_iir = I915_READ(GEN8_GT_IIR(2)); 1244 pm_mask = I915_READ(GEN6_PMINTRMSK); 1245 } 1246 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", 1247 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); 1248 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 1249 seq_printf(m, "Render p-state ratio: %d\n", 1250 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); 1251 seq_printf(m, "Render p-state VID: %d\n", 1252 gt_perf_status & 0xff); 1253 seq_printf(m, "Render p-state limit: %d\n", 1254 rp_state_limits & 0xff); 1255 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 1256 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 1257 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 1258 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 1259 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 1260 seq_printf(m, "CAGF: %dMHz\n", cagf); 1261 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & 1262 GEN6_CURICONT_MASK); 1263 seq_printf(m, "RP CUR UP: %dus\n", rpcurup & 1264 GEN6_CURBSYTAVG_MASK); 1265 seq_printf(m, "RP PREV UP: %dus\n", rpprevup & 1266 GEN6_CURBSYTAVG_MASK); 1267 seq_printf(m, "Up threshold: %d%%\n", 1268 dev_priv->rps.up_threshold); 1269 1270 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & 1271 GEN6_CURIAVG_MASK); 1272 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & 1273 GEN6_CURBSYTAVG_MASK); 1274 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & 1275 GEN6_CURBSYTAVG_MASK); 1276 seq_printf(m, "Down threshold: %d%%\n", 1277 dev_priv->rps.down_threshold); 1278 1279 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 : 1280 rp_state_cap >> 16) & 0xff; 1281 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? 1282 GEN9_FREQ_SCALER : 1); 1283 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 1284 intel_gpu_freq(dev_priv, max_freq)); 1285 1286 max_freq = (rp_state_cap & 0xff00) >> 8; 1287 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? 1288 GEN9_FREQ_SCALER : 1); 1289 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 1290 intel_gpu_freq(dev_priv, max_freq)); 1291 1292 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 : 1293 rp_state_cap >> 0) & 0xff; 1294 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? 1295 GEN9_FREQ_SCALER : 1); 1296 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1297 intel_gpu_freq(dev_priv, max_freq)); 1298 seq_printf(m, "Max overclocked frequency: %dMHz\n", 1299 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1300 1301 seq_printf(m, "Current freq: %d MHz\n", 1302 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1303 seq_printf(m, "Actual freq: %d MHz\n", cagf); 1304 seq_printf(m, "Idle freq: %d MHz\n", 1305 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1306 seq_printf(m, "Min freq: %d MHz\n", 1307 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1308 seq_printf(m, "Max freq: %d MHz\n", 1309 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1310 seq_printf(m, 1311 "efficient (RPe) frequency: %d MHz\n", 1312 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1313 } else { 1314 seq_puts(m, "no P-state info available\n"); 1315 } 1316 1317 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq); 1318 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); 1319 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); 1320 1321 out: 1322 intel_runtime_pm_put(dev_priv); 1323 return ret; 1324 } 1325 1326 static int i915_hangcheck_info(struct seq_file *m, void *unused) 1327 { 1328 struct drm_info_node *node = m->private; 1329 struct drm_device *dev = node->minor->dev; 1330 struct drm_i915_private *dev_priv = dev->dev_private; 1331 struct intel_engine_cs *ring; 1332 u64 acthd[I915_NUM_RINGS]; 1333 u32 seqno[I915_NUM_RINGS]; 1334 int i; 1335 1336 if (!i915.enable_hangcheck) { 1337 seq_printf(m, "Hangcheck disabled\n"); 1338 return 0; 1339 } 1340 1341 intel_runtime_pm_get(dev_priv); 1342 1343 for_each_ring(ring, dev_priv, i) { 1344 seqno[i] = ring->get_seqno(ring, false); 1345 acthd[i] = intel_ring_get_active_head(ring); 1346 } 1347 1348 intel_runtime_pm_put(dev_priv); 1349 1350 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { 1351 seq_printf(m, "Hangcheck active, fires in %dms\n", 1352 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - 1353 jiffies)); 1354 } else 1355 seq_printf(m, "Hangcheck inactive\n"); 1356 1357 for_each_ring(ring, dev_priv, i) { 1358 seq_printf(m, "%s:\n", ring->name); 1359 seq_printf(m, "\tseqno = %x [current %x]\n", 1360 ring->hangcheck.seqno, seqno[i]); 1361 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", 1362 (long long)ring->hangcheck.acthd, 1363 (long long)acthd[i]); 1364 seq_printf(m, "\tmax ACTHD = 0x%08llx\n", 1365 (long long)ring->hangcheck.max_acthd); 1366 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); 1367 seq_printf(m, "\taction = %d\n", ring->hangcheck.action); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int ironlake_drpc_info(struct seq_file *m) 1374 { 1375 struct drm_info_node *node = m->private; 1376 struct drm_device *dev = node->minor->dev; 1377 struct drm_i915_private *dev_priv = dev->dev_private; 1378 u32 rgvmodectl, rstdbyctl; 1379 u16 crstandvid; 1380 int ret; 1381 1382 ret = mutex_lock_interruptible(&dev->struct_mutex); 1383 if (ret) 1384 return ret; 1385 intel_runtime_pm_get(dev_priv); 1386 1387 rgvmodectl = I915_READ(MEMMODECTL); 1388 rstdbyctl = I915_READ(RSTDBYCTL); 1389 crstandvid = I915_READ16(CRSTANDVID); 1390 1391 intel_runtime_pm_put(dev_priv); 1392 mutex_unlock(&dev->struct_mutex); 1393 1394 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); 1395 seq_printf(m, "Boost freq: %d\n", 1396 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 1397 MEMMODE_BOOST_FREQ_SHIFT); 1398 seq_printf(m, "HW control enabled: %s\n", 1399 yesno(rgvmodectl & MEMMODE_HWIDLE_EN)); 1400 seq_printf(m, "SW control enabled: %s\n", 1401 yesno(rgvmodectl & MEMMODE_SWMODE_EN)); 1402 seq_printf(m, "Gated voltage change: %s\n", 1403 yesno(rgvmodectl & MEMMODE_RCLK_GATE)); 1404 seq_printf(m, "Starting frequency: P%d\n", 1405 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 1406 seq_printf(m, "Max P-state: P%d\n", 1407 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 1408 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 1409 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 1410 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 1411 seq_printf(m, "Render standby enabled: %s\n", 1412 yesno(!(rstdbyctl & RCX_SW_EXIT))); 1413 seq_puts(m, "Current RS state: "); 1414 switch (rstdbyctl & RSX_STATUS_MASK) { 1415 case RSX_STATUS_ON: 1416 seq_puts(m, "on\n"); 1417 break; 1418 case RSX_STATUS_RC1: 1419 seq_puts(m, "RC1\n"); 1420 break; 1421 case RSX_STATUS_RC1E: 1422 seq_puts(m, "RC1E\n"); 1423 break; 1424 case RSX_STATUS_RS1: 1425 seq_puts(m, "RS1\n"); 1426 break; 1427 case RSX_STATUS_RS2: 1428 seq_puts(m, "RS2 (RC6)\n"); 1429 break; 1430 case RSX_STATUS_RS3: 1431 seq_puts(m, "RC3 (RC6+)\n"); 1432 break; 1433 default: 1434 seq_puts(m, "unknown\n"); 1435 break; 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int i915_forcewake_domains(struct seq_file *m, void *data) 1442 { 1443 struct drm_info_node *node = m->private; 1444 struct drm_device *dev = node->minor->dev; 1445 struct drm_i915_private *dev_priv = dev->dev_private; 1446 struct intel_uncore_forcewake_domain *fw_domain; 1447 int i; 1448 1449 spin_lock_irq(&dev_priv->uncore.lock); 1450 for_each_fw_domain(fw_domain, dev_priv, i) { 1451 seq_printf(m, "%s.wake_count = %u\n", 1452 intel_uncore_forcewake_domain_to_str(i), 1453 fw_domain->wake_count); 1454 } 1455 spin_unlock_irq(&dev_priv->uncore.lock); 1456 1457 return 0; 1458 } 1459 1460 static int vlv_drpc_info(struct seq_file *m) 1461 { 1462 struct drm_info_node *node = m->private; 1463 struct drm_device *dev = node->minor->dev; 1464 struct drm_i915_private *dev_priv = dev->dev_private; 1465 u32 rpmodectl1, rcctl1, pw_status; 1466 1467 intel_runtime_pm_get(dev_priv); 1468 1469 pw_status = I915_READ(VLV_GTLC_PW_STATUS); 1470 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1471 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1472 1473 intel_runtime_pm_put(dev_priv); 1474 1475 seq_printf(m, "Video Turbo Mode: %s\n", 1476 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1477 seq_printf(m, "Turbo enabled: %s\n", 1478 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1479 seq_printf(m, "HW control enabled: %s\n", 1480 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1481 seq_printf(m, "SW control enabled: %s\n", 1482 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1483 GEN6_RP_MEDIA_SW_MODE)); 1484 seq_printf(m, "RC6 Enabled: %s\n", 1485 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 1486 GEN6_RC_CTL_EI_MODE(1)))); 1487 seq_printf(m, "Render Power Well: %s\n", 1488 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 1489 seq_printf(m, "Media Power Well: %s\n", 1490 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1491 1492 seq_printf(m, "Render RC6 residency since boot: %u\n", 1493 I915_READ(VLV_GT_RENDER_RC6)); 1494 seq_printf(m, "Media RC6 residency since boot: %u\n", 1495 I915_READ(VLV_GT_MEDIA_RC6)); 1496 1497 return i915_forcewake_domains(m, NULL); 1498 } 1499 1500 static int gen6_drpc_info(struct seq_file *m) 1501 { 1502 struct drm_info_node *node = m->private; 1503 struct drm_device *dev = node->minor->dev; 1504 struct drm_i915_private *dev_priv = dev->dev_private; 1505 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; 1506 unsigned forcewake_count; 1507 int count = 0, ret; 1508 1509 ret = mutex_lock_interruptible(&dev->struct_mutex); 1510 if (ret) 1511 return ret; 1512 intel_runtime_pm_get(dev_priv); 1513 1514 spin_lock_irq(&dev_priv->uncore.lock); 1515 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; 1516 spin_unlock_irq(&dev_priv->uncore.lock); 1517 1518 if (forcewake_count) { 1519 seq_puts(m, "RC information inaccurate because somebody " 1520 "holds a forcewake reference \n"); 1521 } else { 1522 /* NB: we cannot use forcewake, else we read the wrong values */ 1523 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1524 udelay(10); 1525 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1526 } 1527 1528 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); 1529 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); 1530 1531 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1532 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1533 mutex_unlock(&dev->struct_mutex); 1534 mutex_lock(&dev_priv->rps.hw_lock); 1535 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 1536 mutex_unlock(&dev_priv->rps.hw_lock); 1537 1538 intel_runtime_pm_put(dev_priv); 1539 1540 seq_printf(m, "Video Turbo Mode: %s\n", 1541 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1542 seq_printf(m, "HW control enabled: %s\n", 1543 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1544 seq_printf(m, "SW control enabled: %s\n", 1545 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1546 GEN6_RP_MEDIA_SW_MODE)); 1547 seq_printf(m, "RC1e Enabled: %s\n", 1548 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1549 seq_printf(m, "RC6 Enabled: %s\n", 1550 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1551 seq_printf(m, "Deep RC6 Enabled: %s\n", 1552 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1553 seq_printf(m, "Deepest RC6 Enabled: %s\n", 1554 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1555 seq_puts(m, "Current RC state: "); 1556 switch (gt_core_status & GEN6_RCn_MASK) { 1557 case GEN6_RC0: 1558 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1559 seq_puts(m, "Core Power Down\n"); 1560 else 1561 seq_puts(m, "on\n"); 1562 break; 1563 case GEN6_RC3: 1564 seq_puts(m, "RC3\n"); 1565 break; 1566 case GEN6_RC6: 1567 seq_puts(m, "RC6\n"); 1568 break; 1569 case GEN6_RC7: 1570 seq_puts(m, "RC7\n"); 1571 break; 1572 default: 1573 seq_puts(m, "Unknown\n"); 1574 break; 1575 } 1576 1577 seq_printf(m, "Core Power Down: %s\n", 1578 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1579 1580 /* Not exactly sure what this is */ 1581 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1582 I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1583 seq_printf(m, "RC6 residency since boot: %u\n", 1584 I915_READ(GEN6_GT_GFX_RC6)); 1585 seq_printf(m, "RC6+ residency since boot: %u\n", 1586 I915_READ(GEN6_GT_GFX_RC6p)); 1587 seq_printf(m, "RC6++ residency since boot: %u\n", 1588 I915_READ(GEN6_GT_GFX_RC6pp)); 1589 1590 seq_printf(m, "RC6 voltage: %dmV\n", 1591 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 1592 seq_printf(m, "RC6+ voltage: %dmV\n", 1593 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 1594 seq_printf(m, "RC6++ voltage: %dmV\n", 1595 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 1596 return 0; 1597 } 1598 1599 static int i915_drpc_info(struct seq_file *m, void *unused) 1600 { 1601 struct drm_info_node *node = m->private; 1602 struct drm_device *dev = node->minor->dev; 1603 1604 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 1605 return vlv_drpc_info(m); 1606 else if (INTEL_INFO(dev)->gen >= 6) 1607 return gen6_drpc_info(m); 1608 else 1609 return ironlake_drpc_info(m); 1610 } 1611 1612 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) 1613 { 1614 struct drm_info_node *node = m->private; 1615 struct drm_device *dev = node->minor->dev; 1616 struct drm_i915_private *dev_priv = dev->dev_private; 1617 1618 seq_printf(m, "FB tracking busy bits: 0x%08x\n", 1619 dev_priv->fb_tracking.busy_bits); 1620 1621 seq_printf(m, "FB tracking flip bits: 0x%08x\n", 1622 dev_priv->fb_tracking.flip_bits); 1623 1624 return 0; 1625 } 1626 1627 static int i915_fbc_status(struct seq_file *m, void *unused) 1628 { 1629 struct drm_info_node *node = m->private; 1630 struct drm_device *dev = node->minor->dev; 1631 struct drm_i915_private *dev_priv = dev->dev_private; 1632 1633 if (!HAS_FBC(dev)) { 1634 seq_puts(m, "FBC unsupported on this chipset\n"); 1635 return 0; 1636 } 1637 1638 intel_runtime_pm_get(dev_priv); 1639 mutex_lock(&dev_priv->fbc.lock); 1640 1641 if (intel_fbc_is_active(dev_priv)) 1642 seq_puts(m, "FBC enabled\n"); 1643 else 1644 seq_printf(m, "FBC disabled: %s\n", 1645 dev_priv->fbc.no_fbc_reason); 1646 1647 if (INTEL_INFO(dev_priv)->gen >= 7) 1648 seq_printf(m, "Compressing: %s\n", 1649 yesno(I915_READ(FBC_STATUS2) & 1650 FBC_COMPRESSION_MASK)); 1651 1652 mutex_unlock(&dev_priv->fbc.lock); 1653 intel_runtime_pm_put(dev_priv); 1654 1655 return 0; 1656 } 1657 1658 static int i915_fbc_fc_get(void *data, u64 *val) 1659 { 1660 struct drm_device *dev = data; 1661 struct drm_i915_private *dev_priv = dev->dev_private; 1662 1663 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) 1664 return -ENODEV; 1665 1666 *val = dev_priv->fbc.false_color; 1667 1668 return 0; 1669 } 1670 1671 static int i915_fbc_fc_set(void *data, u64 val) 1672 { 1673 struct drm_device *dev = data; 1674 struct drm_i915_private *dev_priv = dev->dev_private; 1675 u32 reg; 1676 1677 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) 1678 return -ENODEV; 1679 1680 mutex_lock(&dev_priv->fbc.lock); 1681 1682 reg = I915_READ(ILK_DPFC_CONTROL); 1683 dev_priv->fbc.false_color = val; 1684 1685 I915_WRITE(ILK_DPFC_CONTROL, val ? 1686 (reg | FBC_CTL_FALSE_COLOR) : 1687 (reg & ~FBC_CTL_FALSE_COLOR)); 1688 1689 mutex_unlock(&dev_priv->fbc.lock); 1690 return 0; 1691 } 1692 1693 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, 1694 i915_fbc_fc_get, i915_fbc_fc_set, 1695 "%llu\n"); 1696 1697 static int i915_ips_status(struct seq_file *m, void *unused) 1698 { 1699 struct drm_info_node *node = m->private; 1700 struct drm_device *dev = node->minor->dev; 1701 struct drm_i915_private *dev_priv = dev->dev_private; 1702 1703 if (!HAS_IPS(dev)) { 1704 seq_puts(m, "not supported\n"); 1705 return 0; 1706 } 1707 1708 intel_runtime_pm_get(dev_priv); 1709 1710 seq_printf(m, "Enabled by kernel parameter: %s\n", 1711 yesno(i915.enable_ips)); 1712 1713 if (INTEL_INFO(dev)->gen >= 8) { 1714 seq_puts(m, "Currently: unknown\n"); 1715 } else { 1716 if (I915_READ(IPS_CTL) & IPS_ENABLE) 1717 seq_puts(m, "Currently: enabled\n"); 1718 else 1719 seq_puts(m, "Currently: disabled\n"); 1720 } 1721 1722 intel_runtime_pm_put(dev_priv); 1723 1724 return 0; 1725 } 1726 1727 static int i915_sr_status(struct seq_file *m, void *unused) 1728 { 1729 struct drm_info_node *node = m->private; 1730 struct drm_device *dev = node->minor->dev; 1731 struct drm_i915_private *dev_priv = dev->dev_private; 1732 bool sr_enabled = false; 1733 1734 intel_runtime_pm_get(dev_priv); 1735 1736 if (HAS_PCH_SPLIT(dev)) 1737 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1738 else if (IS_CRESTLINE(dev) || IS_G4X(dev) || 1739 IS_I945G(dev) || IS_I945GM(dev)) 1740 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1741 else if (IS_I915GM(dev)) 1742 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1743 else if (IS_PINEVIEW(dev)) 1744 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1745 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 1746 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 1747 1748 intel_runtime_pm_put(dev_priv); 1749 1750 seq_printf(m, "self-refresh: %s\n", 1751 sr_enabled ? "enabled" : "disabled"); 1752 1753 return 0; 1754 } 1755 1756 static int i915_emon_status(struct seq_file *m, void *unused) 1757 { 1758 struct drm_info_node *node = m->private; 1759 struct drm_device *dev = node->minor->dev; 1760 struct drm_i915_private *dev_priv = dev->dev_private; 1761 unsigned long temp, chipset, gfx; 1762 int ret; 1763 1764 if (!IS_GEN5(dev)) 1765 return -ENODEV; 1766 1767 ret = mutex_lock_interruptible(&dev->struct_mutex); 1768 if (ret) 1769 return ret; 1770 1771 temp = i915_mch_val(dev_priv); 1772 chipset = i915_chipset_val(dev_priv); 1773 gfx = i915_gfx_val(dev_priv); 1774 mutex_unlock(&dev->struct_mutex); 1775 1776 seq_printf(m, "GMCH temp: %ld\n", temp); 1777 seq_printf(m, "Chipset power: %ld\n", chipset); 1778 seq_printf(m, "GFX power: %ld\n", gfx); 1779 seq_printf(m, "Total power: %ld\n", chipset + gfx); 1780 1781 return 0; 1782 } 1783 1784 static int i915_ring_freq_table(struct seq_file *m, void *unused) 1785 { 1786 struct drm_info_node *node = m->private; 1787 struct drm_device *dev = node->minor->dev; 1788 struct drm_i915_private *dev_priv = dev->dev_private; 1789 int ret = 0; 1790 int gpu_freq, ia_freq; 1791 unsigned int max_gpu_freq, min_gpu_freq; 1792 1793 if (!HAS_CORE_RING_FREQ(dev)) { 1794 seq_puts(m, "unsupported on this chipset\n"); 1795 return 0; 1796 } 1797 1798 intel_runtime_pm_get(dev_priv); 1799 1800 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 1801 1802 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 1803 if (ret) 1804 goto out; 1805 1806 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 1807 /* Convert GT frequency to 50 HZ units */ 1808 min_gpu_freq = 1809 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER; 1810 max_gpu_freq = 1811 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER; 1812 } else { 1813 min_gpu_freq = dev_priv->rps.min_freq_softlimit; 1814 max_gpu_freq = dev_priv->rps.max_freq_softlimit; 1815 } 1816 1817 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 1818 1819 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { 1820 ia_freq = gpu_freq; 1821 sandybridge_pcode_read(dev_priv, 1822 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1823 &ia_freq); 1824 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 1825 intel_gpu_freq(dev_priv, (gpu_freq * 1826 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ? 1827 GEN9_FREQ_SCALER : 1))), 1828 ((ia_freq >> 0) & 0xff) * 100, 1829 ((ia_freq >> 8) & 0xff) * 100); 1830 } 1831 1832 mutex_unlock(&dev_priv->rps.hw_lock); 1833 1834 out: 1835 intel_runtime_pm_put(dev_priv); 1836 return ret; 1837 } 1838 1839 static int i915_opregion(struct seq_file *m, void *unused) 1840 { 1841 struct drm_info_node *node = m->private; 1842 struct drm_device *dev = node->minor->dev; 1843 struct drm_i915_private *dev_priv = dev->dev_private; 1844 struct intel_opregion *opregion = &dev_priv->opregion; 1845 int ret; 1846 1847 ret = mutex_lock_interruptible(&dev->struct_mutex); 1848 if (ret) 1849 goto out; 1850 1851 if (opregion->header) 1852 seq_write(m, opregion->header, OPREGION_SIZE); 1853 1854 mutex_unlock(&dev->struct_mutex); 1855 1856 out: 1857 return 0; 1858 } 1859 1860 static int i915_vbt(struct seq_file *m, void *unused) 1861 { 1862 struct drm_info_node *node = m->private; 1863 struct drm_device *dev = node->minor->dev; 1864 struct drm_i915_private *dev_priv = dev->dev_private; 1865 struct intel_opregion *opregion = &dev_priv->opregion; 1866 1867 if (opregion->vbt) 1868 seq_write(m, opregion->vbt, opregion->vbt_size); 1869 1870 return 0; 1871 } 1872 1873 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 1874 { 1875 struct drm_info_node *node = m->private; 1876 struct drm_device *dev = node->minor->dev; 1877 struct intel_framebuffer *fbdev_fb = NULL; 1878 struct drm_framebuffer *drm_fb; 1879 1880 #ifdef CONFIG_DRM_FBDEV_EMULATION 1881 if (to_i915(dev)->fbdev) { 1882 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb); 1883 1884 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1885 fbdev_fb->base.width, 1886 fbdev_fb->base.height, 1887 fbdev_fb->base.depth, 1888 fbdev_fb->base.bits_per_pixel, 1889 fbdev_fb->base.modifier[0], 1890 atomic_read(&fbdev_fb->base.refcount.refcount)); 1891 describe_obj(m, fbdev_fb->obj); 1892 seq_putc(m, '\n'); 1893 } 1894 #endif 1895 1896 mutex_lock(&dev->mode_config.fb_lock); 1897 drm_for_each_fb(drm_fb, dev) { 1898 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 1899 if (fb == fbdev_fb) 1900 continue; 1901 1902 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1903 fb->base.width, 1904 fb->base.height, 1905 fb->base.depth, 1906 fb->base.bits_per_pixel, 1907 fb->base.modifier[0], 1908 atomic_read(&fb->base.refcount.refcount)); 1909 describe_obj(m, fb->obj); 1910 seq_putc(m, '\n'); 1911 } 1912 mutex_unlock(&dev->mode_config.fb_lock); 1913 1914 return 0; 1915 } 1916 1917 static void describe_ctx_ringbuf(struct seq_file *m, 1918 struct intel_ringbuffer *ringbuf) 1919 { 1920 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", 1921 ringbuf->space, ringbuf->head, ringbuf->tail, 1922 ringbuf->last_retired_head); 1923 } 1924 1925 static int i915_context_status(struct seq_file *m, void *unused) 1926 { 1927 struct drm_info_node *node = m->private; 1928 struct drm_device *dev = node->minor->dev; 1929 struct drm_i915_private *dev_priv = dev->dev_private; 1930 struct intel_engine_cs *ring; 1931 struct intel_context *ctx; 1932 int ret, i; 1933 1934 ret = mutex_lock_interruptible(&dev->struct_mutex); 1935 if (ret) 1936 return ret; 1937 1938 list_for_each_entry(ctx, &dev_priv->context_list, link) { 1939 if (!i915.enable_execlists && 1940 ctx->legacy_hw_ctx.rcs_state == NULL) 1941 continue; 1942 1943 seq_puts(m, "HW context "); 1944 describe_ctx(m, ctx); 1945 for_each_ring(ring, dev_priv, i) { 1946 if (ring->default_context == ctx) 1947 seq_printf(m, "(default context %s) ", 1948 ring->name); 1949 } 1950 1951 if (i915.enable_execlists) { 1952 seq_putc(m, '\n'); 1953 for_each_ring(ring, dev_priv, i) { 1954 struct drm_i915_gem_object *ctx_obj = 1955 ctx->engine[i].state; 1956 struct intel_ringbuffer *ringbuf = 1957 ctx->engine[i].ringbuf; 1958 1959 seq_printf(m, "%s: ", ring->name); 1960 if (ctx_obj) 1961 describe_obj(m, ctx_obj); 1962 if (ringbuf) 1963 describe_ctx_ringbuf(m, ringbuf); 1964 seq_putc(m, '\n'); 1965 } 1966 } else { 1967 describe_obj(m, ctx->legacy_hw_ctx.rcs_state); 1968 } 1969 1970 seq_putc(m, '\n'); 1971 } 1972 1973 mutex_unlock(&dev->struct_mutex); 1974 1975 return 0; 1976 } 1977 1978 static void i915_dump_lrc_obj(struct seq_file *m, 1979 struct intel_engine_cs *ring, 1980 struct drm_i915_gem_object *ctx_obj) 1981 { 1982 struct page *page; 1983 uint32_t *reg_state; 1984 int j; 1985 unsigned long ggtt_offset = 0; 1986 1987 if (ctx_obj == NULL) { 1988 seq_printf(m, "Context on %s with no gem object\n", 1989 ring->name); 1990 return; 1991 } 1992 1993 seq_printf(m, "CONTEXT: %s %u\n", ring->name, 1994 intel_execlists_ctx_id(ctx_obj)); 1995 1996 if (!i915_gem_obj_ggtt_bound(ctx_obj)) 1997 seq_puts(m, "\tNot bound in GGTT\n"); 1998 else 1999 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); 2000 2001 if (i915_gem_object_get_pages(ctx_obj)) { 2002 seq_puts(m, "\tFailed to get pages for context object\n"); 2003 return; 2004 } 2005 2006 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 2007 if (!WARN_ON(page == NULL)) { 2008 reg_state = kmap_atomic(page); 2009 2010 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { 2011 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", 2012 ggtt_offset + 4096 + (j * 4), 2013 reg_state[j], reg_state[j + 1], 2014 reg_state[j + 2], reg_state[j + 3]); 2015 } 2016 kunmap_atomic(reg_state); 2017 } 2018 2019 seq_putc(m, '\n'); 2020 } 2021 2022 static int i915_dump_lrc(struct seq_file *m, void *unused) 2023 { 2024 struct drm_info_node *node = (struct drm_info_node *) m->private; 2025 struct drm_device *dev = node->minor->dev; 2026 struct drm_i915_private *dev_priv = dev->dev_private; 2027 struct intel_engine_cs *ring; 2028 struct intel_context *ctx; 2029 int ret, i; 2030 2031 if (!i915.enable_execlists) { 2032 seq_printf(m, "Logical Ring Contexts are disabled\n"); 2033 return 0; 2034 } 2035 2036 ret = mutex_lock_interruptible(&dev->struct_mutex); 2037 if (ret) 2038 return ret; 2039 2040 list_for_each_entry(ctx, &dev_priv->context_list, link) { 2041 for_each_ring(ring, dev_priv, i) { 2042 if (ring->default_context != ctx) 2043 i915_dump_lrc_obj(m, ring, 2044 ctx->engine[i].state); 2045 } 2046 } 2047 2048 mutex_unlock(&dev->struct_mutex); 2049 2050 return 0; 2051 } 2052 2053 static int i915_execlists(struct seq_file *m, void *data) 2054 { 2055 struct drm_info_node *node = (struct drm_info_node *)m->private; 2056 struct drm_device *dev = node->minor->dev; 2057 struct drm_i915_private *dev_priv = dev->dev_private; 2058 struct intel_engine_cs *ring; 2059 u32 status_pointer; 2060 u8 read_pointer; 2061 u8 write_pointer; 2062 u32 status; 2063 u32 ctx_id; 2064 struct list_head *cursor; 2065 int ring_id, i; 2066 int ret; 2067 2068 if (!i915.enable_execlists) { 2069 seq_puts(m, "Logical Ring Contexts are disabled\n"); 2070 return 0; 2071 } 2072 2073 ret = mutex_lock_interruptible(&dev->struct_mutex); 2074 if (ret) 2075 return ret; 2076 2077 intel_runtime_pm_get(dev_priv); 2078 2079 for_each_ring(ring, dev_priv, ring_id) { 2080 struct drm_i915_gem_request *head_req = NULL; 2081 int count = 0; 2082 unsigned long flags; 2083 2084 seq_printf(m, "%s\n", ring->name); 2085 2086 status = I915_READ(RING_EXECLIST_STATUS_LO(ring)); 2087 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring)); 2088 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", 2089 status, ctx_id); 2090 2091 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 2092 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); 2093 2094 read_pointer = ring->next_context_status_buffer; 2095 write_pointer = status_pointer & 0x07; 2096 if (read_pointer > write_pointer) 2097 write_pointer += 6; 2098 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", 2099 read_pointer, write_pointer); 2100 2101 for (i = 0; i < 6; i++) { 2102 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i)); 2103 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i)); 2104 2105 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", 2106 i, status, ctx_id); 2107 } 2108 2109 spin_lock_irqsave(&ring->execlist_lock, flags); 2110 list_for_each(cursor, &ring->execlist_queue) 2111 count++; 2112 head_req = list_first_entry_or_null(&ring->execlist_queue, 2113 struct drm_i915_gem_request, execlist_link); 2114 spin_unlock_irqrestore(&ring->execlist_lock, flags); 2115 2116 seq_printf(m, "\t%d requests in queue\n", count); 2117 if (head_req) { 2118 struct drm_i915_gem_object *ctx_obj; 2119 2120 ctx_obj = head_req->ctx->engine[ring_id].state; 2121 seq_printf(m, "\tHead request id: %u\n", 2122 intel_execlists_ctx_id(ctx_obj)); 2123 seq_printf(m, "\tHead request tail: %u\n", 2124 head_req->tail); 2125 } 2126 2127 seq_putc(m, '\n'); 2128 } 2129 2130 intel_runtime_pm_put(dev_priv); 2131 mutex_unlock(&dev->struct_mutex); 2132 2133 return 0; 2134 } 2135 2136 static const char *swizzle_string(unsigned swizzle) 2137 { 2138 switch (swizzle) { 2139 case I915_BIT_6_SWIZZLE_NONE: 2140 return "none"; 2141 case I915_BIT_6_SWIZZLE_9: 2142 return "bit9"; 2143 case I915_BIT_6_SWIZZLE_9_10: 2144 return "bit9/bit10"; 2145 case I915_BIT_6_SWIZZLE_9_11: 2146 return "bit9/bit11"; 2147 case I915_BIT_6_SWIZZLE_9_10_11: 2148 return "bit9/bit10/bit11"; 2149 case I915_BIT_6_SWIZZLE_9_17: 2150 return "bit9/bit17"; 2151 case I915_BIT_6_SWIZZLE_9_10_17: 2152 return "bit9/bit10/bit17"; 2153 case I915_BIT_6_SWIZZLE_UNKNOWN: 2154 return "unknown"; 2155 } 2156 2157 return "bug"; 2158 } 2159 2160 static int i915_swizzle_info(struct seq_file *m, void *data) 2161 { 2162 struct drm_info_node *node = m->private; 2163 struct drm_device *dev = node->minor->dev; 2164 struct drm_i915_private *dev_priv = dev->dev_private; 2165 int ret; 2166 2167 ret = mutex_lock_interruptible(&dev->struct_mutex); 2168 if (ret) 2169 return ret; 2170 intel_runtime_pm_get(dev_priv); 2171 2172 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 2173 swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 2174 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 2175 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 2176 2177 if (IS_GEN3(dev) || IS_GEN4(dev)) { 2178 seq_printf(m, "DDC = 0x%08x\n", 2179 I915_READ(DCC)); 2180 seq_printf(m, "DDC2 = 0x%08x\n", 2181 I915_READ(DCC2)); 2182 seq_printf(m, "C0DRB3 = 0x%04x\n", 2183 I915_READ16(C0DRB3)); 2184 seq_printf(m, "C1DRB3 = 0x%04x\n", 2185 I915_READ16(C1DRB3)); 2186 } else if (INTEL_INFO(dev)->gen >= 6) { 2187 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 2188 I915_READ(MAD_DIMM_C0)); 2189 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 2190 I915_READ(MAD_DIMM_C1)); 2191 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 2192 I915_READ(MAD_DIMM_C2)); 2193 seq_printf(m, "TILECTL = 0x%08x\n", 2194 I915_READ(TILECTL)); 2195 if (INTEL_INFO(dev)->gen >= 8) 2196 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 2197 I915_READ(GAMTARBMODE)); 2198 else 2199 seq_printf(m, "ARB_MODE = 0x%08x\n", 2200 I915_READ(ARB_MODE)); 2201 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 2202 I915_READ(DISP_ARB_CTL)); 2203 } 2204 2205 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 2206 seq_puts(m, "L-shaped memory detected\n"); 2207 2208 intel_runtime_pm_put(dev_priv); 2209 mutex_unlock(&dev->struct_mutex); 2210 2211 return 0; 2212 } 2213 2214 static int per_file_ctx(int id, void *ptr, void *data) 2215 { 2216 struct intel_context *ctx = ptr; 2217 struct seq_file *m = data; 2218 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 2219 2220 if (!ppgtt) { 2221 seq_printf(m, " no ppgtt for context %d\n", 2222 ctx->user_handle); 2223 return 0; 2224 } 2225 2226 if (i915_gem_context_is_default(ctx)) 2227 seq_puts(m, " default context:\n"); 2228 else 2229 seq_printf(m, " context %d:\n", ctx->user_handle); 2230 ppgtt->debug_dump(ppgtt, m); 2231 2232 return 0; 2233 } 2234 2235 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) 2236 { 2237 struct drm_i915_private *dev_priv = dev->dev_private; 2238 struct intel_engine_cs *ring; 2239 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2240 int unused, i; 2241 2242 if (!ppgtt) 2243 return; 2244 2245 for_each_ring(ring, dev_priv, unused) { 2246 seq_printf(m, "%s\n", ring->name); 2247 for (i = 0; i < 4; i++) { 2248 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i)); 2249 pdp <<= 32; 2250 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i)); 2251 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); 2252 } 2253 } 2254 } 2255 2256 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 2257 { 2258 struct drm_i915_private *dev_priv = dev->dev_private; 2259 struct intel_engine_cs *ring; 2260 int i; 2261 2262 if (INTEL_INFO(dev)->gen == 6) 2263 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 2264 2265 for_each_ring(ring, dev_priv, i) { 2266 seq_printf(m, "%s\n", ring->name); 2267 if (INTEL_INFO(dev)->gen == 7) 2268 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); 2269 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); 2270 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); 2271 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); 2272 } 2273 if (dev_priv->mm.aliasing_ppgtt) { 2274 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2275 2276 seq_puts(m, "aliasing PPGTT:\n"); 2277 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset); 2278 2279 ppgtt->debug_dump(ppgtt, m); 2280 } 2281 2282 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 2283 } 2284 2285 static int i915_ppgtt_info(struct seq_file *m, void *data) 2286 { 2287 struct drm_info_node *node = m->private; 2288 struct drm_device *dev = node->minor->dev; 2289 struct drm_i915_private *dev_priv = dev->dev_private; 2290 struct drm_file *file; 2291 2292 int ret = mutex_lock_interruptible(&dev->struct_mutex); 2293 if (ret) 2294 return ret; 2295 intel_runtime_pm_get(dev_priv); 2296 2297 if (INTEL_INFO(dev)->gen >= 8) 2298 gen8_ppgtt_info(m, dev); 2299 else if (INTEL_INFO(dev)->gen >= 6) 2300 gen6_ppgtt_info(m, dev); 2301 2302 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2303 struct drm_i915_file_private *file_priv = file->driver_priv; 2304 struct task_struct *task; 2305 2306 task = get_pid_task(file->pid, PIDTYPE_PID); 2307 if (!task) { 2308 ret = -ESRCH; 2309 goto out_put; 2310 } 2311 seq_printf(m, "\nproc: %s\n", task->comm); 2312 put_task_struct(task); 2313 idr_for_each(&file_priv->context_idr, per_file_ctx, 2314 (void *)(unsigned long)m); 2315 } 2316 2317 out_put: 2318 intel_runtime_pm_put(dev_priv); 2319 mutex_unlock(&dev->struct_mutex); 2320 2321 return ret; 2322 } 2323 2324 static int count_irq_waiters(struct drm_i915_private *i915) 2325 { 2326 struct intel_engine_cs *ring; 2327 int count = 0; 2328 int i; 2329 2330 for_each_ring(ring, i915, i) 2331 count += ring->irq_refcount; 2332 2333 return count; 2334 } 2335 2336 static int i915_rps_boost_info(struct seq_file *m, void *data) 2337 { 2338 struct drm_info_node *node = m->private; 2339 struct drm_device *dev = node->minor->dev; 2340 struct drm_i915_private *dev_priv = dev->dev_private; 2341 struct drm_file *file; 2342 2343 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); 2344 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); 2345 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); 2346 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", 2347 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 2348 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 2349 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), 2350 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), 2351 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 2352 spin_lock(&dev_priv->rps.client_lock); 2353 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2354 struct drm_i915_file_private *file_priv = file->driver_priv; 2355 struct task_struct *task; 2356 2357 rcu_read_lock(); 2358 task = pid_task(file->pid, PIDTYPE_PID); 2359 seq_printf(m, "%s [%d]: %d boosts%s\n", 2360 task ? task->comm : "<unknown>", 2361 task ? task->pid : -1, 2362 file_priv->rps.boosts, 2363 list_empty(&file_priv->rps.link) ? "" : ", active"); 2364 rcu_read_unlock(); 2365 } 2366 seq_printf(m, "Semaphore boosts: %d%s\n", 2367 dev_priv->rps.semaphores.boosts, 2368 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); 2369 seq_printf(m, "MMIO flip boosts: %d%s\n", 2370 dev_priv->rps.mmioflips.boosts, 2371 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); 2372 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); 2373 spin_unlock(&dev_priv->rps.client_lock); 2374 2375 return 0; 2376 } 2377 2378 static int i915_llc(struct seq_file *m, void *data) 2379 { 2380 struct drm_info_node *node = m->private; 2381 struct drm_device *dev = node->minor->dev; 2382 struct drm_i915_private *dev_priv = dev->dev_private; 2383 2384 /* Size calculation for LLC is a bit of a pain. Ignore for now. */ 2385 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); 2386 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); 2387 2388 return 0; 2389 } 2390 2391 static int i915_guc_load_status_info(struct seq_file *m, void *data) 2392 { 2393 struct drm_info_node *node = m->private; 2394 struct drm_i915_private *dev_priv = node->minor->dev->dev_private; 2395 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw; 2396 u32 tmp, i; 2397 2398 if (!HAS_GUC_UCODE(dev_priv->dev)) 2399 return 0; 2400 2401 seq_printf(m, "GuC firmware status:\n"); 2402 seq_printf(m, "\tpath: %s\n", 2403 guc_fw->guc_fw_path); 2404 seq_printf(m, "\tfetch: %s\n", 2405 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status)); 2406 seq_printf(m, "\tload: %s\n", 2407 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); 2408 seq_printf(m, "\tversion wanted: %d.%d\n", 2409 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); 2410 seq_printf(m, "\tversion found: %d.%d\n", 2411 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found); 2412 seq_printf(m, "\theader: offset is %d; size = %d\n", 2413 guc_fw->header_offset, guc_fw->header_size); 2414 seq_printf(m, "\tuCode: offset is %d; size = %d\n", 2415 guc_fw->ucode_offset, guc_fw->ucode_size); 2416 seq_printf(m, "\tRSA: offset is %d; size = %d\n", 2417 guc_fw->rsa_offset, guc_fw->rsa_size); 2418 2419 tmp = I915_READ(GUC_STATUS); 2420 2421 seq_printf(m, "\nGuC status 0x%08x:\n", tmp); 2422 seq_printf(m, "\tBootrom status = 0x%x\n", 2423 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT); 2424 seq_printf(m, "\tuKernel status = 0x%x\n", 2425 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT); 2426 seq_printf(m, "\tMIA Core status = 0x%x\n", 2427 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT); 2428 seq_puts(m, "\nScratch registers:\n"); 2429 for (i = 0; i < 16; i++) 2430 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i))); 2431 2432 return 0; 2433 } 2434 2435 static void i915_guc_client_info(struct seq_file *m, 2436 struct drm_i915_private *dev_priv, 2437 struct i915_guc_client *client) 2438 { 2439 struct intel_engine_cs *ring; 2440 uint64_t tot = 0; 2441 uint32_t i; 2442 2443 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n", 2444 client->priority, client->ctx_index, client->proc_desc_offset); 2445 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n", 2446 client->doorbell_id, client->doorbell_offset, client->cookie); 2447 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n", 2448 client->wq_size, client->wq_offset, client->wq_tail); 2449 2450 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail); 2451 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail); 2452 seq_printf(m, "\tLast submission result: %d\n", client->retcode); 2453 2454 for_each_ring(ring, dev_priv, i) { 2455 seq_printf(m, "\tSubmissions: %llu %s\n", 2456 client->submissions[i], 2457 ring->name); 2458 tot += client->submissions[i]; 2459 } 2460 seq_printf(m, "\tTotal: %llu\n", tot); 2461 } 2462 2463 static int i915_guc_info(struct seq_file *m, void *data) 2464 { 2465 struct drm_info_node *node = m->private; 2466 struct drm_device *dev = node->minor->dev; 2467 struct drm_i915_private *dev_priv = dev->dev_private; 2468 struct intel_guc guc; 2469 struct i915_guc_client client = {}; 2470 struct intel_engine_cs *ring; 2471 enum intel_ring_id i; 2472 u64 total = 0; 2473 2474 if (!HAS_GUC_SCHED(dev_priv->dev)) 2475 return 0; 2476 2477 if (mutex_lock_interruptible(&dev->struct_mutex)) 2478 return 0; 2479 2480 /* Take a local copy of the GuC data, so we can dump it at leisure */ 2481 guc = dev_priv->guc; 2482 if (guc.execbuf_client) 2483 client = *guc.execbuf_client; 2484 2485 mutex_unlock(&dev->struct_mutex); 2486 2487 seq_printf(m, "GuC total action count: %llu\n", guc.action_count); 2488 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail); 2489 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd); 2490 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status); 2491 seq_printf(m, "GuC last action error code: %d\n", guc.action_err); 2492 2493 seq_printf(m, "\nGuC submissions:\n"); 2494 for_each_ring(ring, dev_priv, i) { 2495 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n", 2496 ring->name, guc.submissions[i], 2497 guc.last_seqno[i], guc.last_seqno[i]); 2498 total += guc.submissions[i]; 2499 } 2500 seq_printf(m, "\t%s: %llu\n", "Total", total); 2501 2502 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client); 2503 i915_guc_client_info(m, dev_priv, &client); 2504 2505 /* Add more as required ... */ 2506 2507 return 0; 2508 } 2509 2510 static int i915_guc_log_dump(struct seq_file *m, void *data) 2511 { 2512 struct drm_info_node *node = m->private; 2513 struct drm_device *dev = node->minor->dev; 2514 struct drm_i915_private *dev_priv = dev->dev_private; 2515 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj; 2516 u32 *log; 2517 int i = 0, pg; 2518 2519 if (!log_obj) 2520 return 0; 2521 2522 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) { 2523 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg)); 2524 2525 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4) 2526 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", 2527 *(log + i), *(log + i + 1), 2528 *(log + i + 2), *(log + i + 3)); 2529 2530 kunmap_atomic(log); 2531 } 2532 2533 seq_putc(m, '\n'); 2534 2535 return 0; 2536 } 2537 2538 static int i915_edp_psr_status(struct seq_file *m, void *data) 2539 { 2540 struct drm_info_node *node = m->private; 2541 struct drm_device *dev = node->minor->dev; 2542 struct drm_i915_private *dev_priv = dev->dev_private; 2543 u32 psrperf = 0; 2544 u32 stat[3]; 2545 enum pipe pipe; 2546 bool enabled = false; 2547 2548 if (!HAS_PSR(dev)) { 2549 seq_puts(m, "PSR not supported\n"); 2550 return 0; 2551 } 2552 2553 intel_runtime_pm_get(dev_priv); 2554 2555 mutex_lock(&dev_priv->psr.lock); 2556 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); 2557 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); 2558 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); 2559 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); 2560 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", 2561 dev_priv->psr.busy_frontbuffer_bits); 2562 seq_printf(m, "Re-enable work scheduled: %s\n", 2563 yesno(work_busy(&dev_priv->psr.work.work))); 2564 2565 if (HAS_DDI(dev)) 2566 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; 2567 else { 2568 for_each_pipe(dev_priv, pipe) { 2569 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & 2570 VLV_EDP_PSR_CURR_STATE_MASK; 2571 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2572 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2573 enabled = true; 2574 } 2575 } 2576 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); 2577 2578 if (!HAS_DDI(dev)) 2579 for_each_pipe(dev_priv, pipe) { 2580 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2581 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2582 seq_printf(m, " pipe %c", pipe_name(pipe)); 2583 } 2584 seq_puts(m, "\n"); 2585 2586 /* 2587 * VLV/CHV PSR has no kind of performance counter 2588 * SKL+ Perf counter is reset to 0 everytime DC state is entered 2589 */ 2590 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2591 psrperf = I915_READ(EDP_PSR_PERF_CNT) & 2592 EDP_PSR_PERF_CNT_MASK; 2593 2594 seq_printf(m, "Performance_Counter: %u\n", psrperf); 2595 } 2596 mutex_unlock(&dev_priv->psr.lock); 2597 2598 intel_runtime_pm_put(dev_priv); 2599 return 0; 2600 } 2601 2602 static int i915_sink_crc(struct seq_file *m, void *data) 2603 { 2604 struct drm_info_node *node = m->private; 2605 struct drm_device *dev = node->minor->dev; 2606 struct intel_encoder *encoder; 2607 struct intel_connector *connector; 2608 struct intel_dp *intel_dp = NULL; 2609 int ret; 2610 u8 crc[6]; 2611 2612 drm_modeset_lock_all(dev); 2613 for_each_intel_connector(dev, connector) { 2614 2615 if (connector->base.dpms != DRM_MODE_DPMS_ON) 2616 continue; 2617 2618 if (!connector->base.encoder) 2619 continue; 2620 2621 encoder = to_intel_encoder(connector->base.encoder); 2622 if (encoder->type != INTEL_OUTPUT_EDP) 2623 continue; 2624 2625 intel_dp = enc_to_intel_dp(&encoder->base); 2626 2627 ret = intel_dp_sink_crc(intel_dp, crc); 2628 if (ret) 2629 goto out; 2630 2631 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", 2632 crc[0], crc[1], crc[2], 2633 crc[3], crc[4], crc[5]); 2634 goto out; 2635 } 2636 ret = -ENODEV; 2637 out: 2638 drm_modeset_unlock_all(dev); 2639 return ret; 2640 } 2641 2642 static int i915_energy_uJ(struct seq_file *m, void *data) 2643 { 2644 struct drm_info_node *node = m->private; 2645 struct drm_device *dev = node->minor->dev; 2646 struct drm_i915_private *dev_priv = dev->dev_private; 2647 u64 power; 2648 u32 units; 2649 2650 if (INTEL_INFO(dev)->gen < 6) 2651 return -ENODEV; 2652 2653 intel_runtime_pm_get(dev_priv); 2654 2655 rdmsrl(MSR_RAPL_POWER_UNIT, power); 2656 power = (power & 0x1f00) >> 8; 2657 units = 1000000 / (1 << power); /* convert to uJ */ 2658 power = I915_READ(MCH_SECP_NRG_STTS); 2659 power *= units; 2660 2661 intel_runtime_pm_put(dev_priv); 2662 2663 seq_printf(m, "%llu", (long long unsigned)power); 2664 2665 return 0; 2666 } 2667 2668 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 2669 { 2670 struct drm_info_node *node = m->private; 2671 struct drm_device *dev = node->minor->dev; 2672 struct drm_i915_private *dev_priv = dev->dev_private; 2673 2674 if (!HAS_RUNTIME_PM(dev)) { 2675 seq_puts(m, "not supported\n"); 2676 return 0; 2677 } 2678 2679 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); 2680 seq_printf(m, "IRQs disabled: %s\n", 2681 yesno(!intel_irqs_enabled(dev_priv))); 2682 #ifdef CONFIG_PM 2683 seq_printf(m, "Usage count: %d\n", 2684 atomic_read(&dev->dev->power.usage_count)); 2685 #else 2686 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 2687 #endif 2688 2689 return 0; 2690 } 2691 2692 static int i915_power_domain_info(struct seq_file *m, void *unused) 2693 { 2694 struct drm_info_node *node = m->private; 2695 struct drm_device *dev = node->minor->dev; 2696 struct drm_i915_private *dev_priv = dev->dev_private; 2697 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2698 int i; 2699 2700 mutex_lock(&power_domains->lock); 2701 2702 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2703 for (i = 0; i < power_domains->power_well_count; i++) { 2704 struct i915_power_well *power_well; 2705 enum intel_display_power_domain power_domain; 2706 2707 power_well = &power_domains->power_wells[i]; 2708 seq_printf(m, "%-25s %d\n", power_well->name, 2709 power_well->count); 2710 2711 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; 2712 power_domain++) { 2713 if (!(BIT(power_domain) & power_well->domains)) 2714 continue; 2715 2716 seq_printf(m, " %-23s %d\n", 2717 intel_display_power_domain_str(power_domain), 2718 power_domains->domain_use_count[power_domain]); 2719 } 2720 } 2721 2722 mutex_unlock(&power_domains->lock); 2723 2724 return 0; 2725 } 2726 2727 static int i915_dmc_info(struct seq_file *m, void *unused) 2728 { 2729 struct drm_info_node *node = m->private; 2730 struct drm_device *dev = node->minor->dev; 2731 struct drm_i915_private *dev_priv = dev->dev_private; 2732 struct intel_csr *csr; 2733 2734 if (!HAS_CSR(dev)) { 2735 seq_puts(m, "not supported\n"); 2736 return 0; 2737 } 2738 2739 csr = &dev_priv->csr; 2740 2741 intel_runtime_pm_get(dev_priv); 2742 2743 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); 2744 seq_printf(m, "path: %s\n", csr->fw_path); 2745 2746 if (!csr->dmc_payload) 2747 goto out; 2748 2749 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), 2750 CSR_VERSION_MINOR(csr->version)); 2751 2752 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) { 2753 seq_printf(m, "DC3 -> DC5 count: %d\n", 2754 I915_READ(SKL_CSR_DC3_DC5_COUNT)); 2755 seq_printf(m, "DC5 -> DC6 count: %d\n", 2756 I915_READ(SKL_CSR_DC5_DC6_COUNT)); 2757 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) { 2758 seq_printf(m, "DC3 -> DC5 count: %d\n", 2759 I915_READ(BXT_CSR_DC3_DC5_COUNT)); 2760 } 2761 2762 out: 2763 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); 2764 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); 2765 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); 2766 2767 intel_runtime_pm_put(dev_priv); 2768 2769 return 0; 2770 } 2771 2772 static void intel_seq_print_mode(struct seq_file *m, int tabs, 2773 struct drm_display_mode *mode) 2774 { 2775 int i; 2776 2777 for (i = 0; i < tabs; i++) 2778 seq_putc(m, '\t'); 2779 2780 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", 2781 mode->base.id, mode->name, 2782 mode->vrefresh, mode->clock, 2783 mode->hdisplay, mode->hsync_start, 2784 mode->hsync_end, mode->htotal, 2785 mode->vdisplay, mode->vsync_start, 2786 mode->vsync_end, mode->vtotal, 2787 mode->type, mode->flags); 2788 } 2789 2790 static void intel_encoder_info(struct seq_file *m, 2791 struct intel_crtc *intel_crtc, 2792 struct intel_encoder *intel_encoder) 2793 { 2794 struct drm_info_node *node = m->private; 2795 struct drm_device *dev = node->minor->dev; 2796 struct drm_crtc *crtc = &intel_crtc->base; 2797 struct intel_connector *intel_connector; 2798 struct drm_encoder *encoder; 2799 2800 encoder = &intel_encoder->base; 2801 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", 2802 encoder->base.id, encoder->name); 2803 for_each_connector_on_encoder(dev, encoder, intel_connector) { 2804 struct drm_connector *connector = &intel_connector->base; 2805 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", 2806 connector->base.id, 2807 connector->name, 2808 drm_get_connector_status_name(connector->status)); 2809 if (connector->status == connector_status_connected) { 2810 struct drm_display_mode *mode = &crtc->mode; 2811 seq_printf(m, ", mode:\n"); 2812 intel_seq_print_mode(m, 2, mode); 2813 } else { 2814 seq_putc(m, '\n'); 2815 } 2816 } 2817 } 2818 2819 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2820 { 2821 struct drm_info_node *node = m->private; 2822 struct drm_device *dev = node->minor->dev; 2823 struct drm_crtc *crtc = &intel_crtc->base; 2824 struct intel_encoder *intel_encoder; 2825 struct drm_plane_state *plane_state = crtc->primary->state; 2826 struct drm_framebuffer *fb = plane_state->fb; 2827 2828 if (fb) 2829 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", 2830 fb->base.id, plane_state->src_x >> 16, 2831 plane_state->src_y >> 16, fb->width, fb->height); 2832 else 2833 seq_puts(m, "\tprimary plane disabled\n"); 2834 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 2835 intel_encoder_info(m, intel_crtc, intel_encoder); 2836 } 2837 2838 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) 2839 { 2840 struct drm_display_mode *mode = panel->fixed_mode; 2841 2842 seq_printf(m, "\tfixed mode:\n"); 2843 intel_seq_print_mode(m, 2, mode); 2844 } 2845 2846 static void intel_dp_info(struct seq_file *m, 2847 struct intel_connector *intel_connector) 2848 { 2849 struct intel_encoder *intel_encoder = intel_connector->encoder; 2850 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2851 2852 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 2853 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); 2854 if (intel_encoder->type == INTEL_OUTPUT_EDP) 2855 intel_panel_info(m, &intel_connector->panel); 2856 } 2857 2858 static void intel_dp_mst_info(struct seq_file *m, 2859 struct intel_connector *intel_connector) 2860 { 2861 struct intel_encoder *intel_encoder = intel_connector->encoder; 2862 struct intel_dp_mst_encoder *intel_mst = 2863 enc_to_mst(&intel_encoder->base); 2864 struct intel_digital_port *intel_dig_port = intel_mst->primary; 2865 struct intel_dp *intel_dp = &intel_dig_port->dp; 2866 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, 2867 intel_connector->port); 2868 2869 seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); 2870 } 2871 2872 static void intel_hdmi_info(struct seq_file *m, 2873 struct intel_connector *intel_connector) 2874 { 2875 struct intel_encoder *intel_encoder = intel_connector->encoder; 2876 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 2877 2878 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); 2879 } 2880 2881 static void intel_lvds_info(struct seq_file *m, 2882 struct intel_connector *intel_connector) 2883 { 2884 intel_panel_info(m, &intel_connector->panel); 2885 } 2886 2887 static void intel_connector_info(struct seq_file *m, 2888 struct drm_connector *connector) 2889 { 2890 struct intel_connector *intel_connector = to_intel_connector(connector); 2891 struct intel_encoder *intel_encoder = intel_connector->encoder; 2892 struct drm_display_mode *mode; 2893 2894 seq_printf(m, "connector %d: type %s, status: %s\n", 2895 connector->base.id, connector->name, 2896 drm_get_connector_status_name(connector->status)); 2897 if (connector->status == connector_status_connected) { 2898 seq_printf(m, "\tname: %s\n", connector->display_info.name); 2899 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 2900 connector->display_info.width_mm, 2901 connector->display_info.height_mm); 2902 seq_printf(m, "\tsubpixel order: %s\n", 2903 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 2904 seq_printf(m, "\tCEA rev: %d\n", 2905 connector->display_info.cea_rev); 2906 } 2907 if (intel_encoder) { 2908 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 2909 intel_encoder->type == INTEL_OUTPUT_EDP) 2910 intel_dp_info(m, intel_connector); 2911 else if (intel_encoder->type == INTEL_OUTPUT_HDMI) 2912 intel_hdmi_info(m, intel_connector); 2913 else if (intel_encoder->type == INTEL_OUTPUT_LVDS) 2914 intel_lvds_info(m, intel_connector); 2915 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST) 2916 intel_dp_mst_info(m, intel_connector); 2917 } 2918 2919 seq_printf(m, "\tmodes:\n"); 2920 list_for_each_entry(mode, &connector->modes, head) 2921 intel_seq_print_mode(m, 2, mode); 2922 } 2923 2924 static bool cursor_active(struct drm_device *dev, int pipe) 2925 { 2926 struct drm_i915_private *dev_priv = dev->dev_private; 2927 u32 state; 2928 2929 if (IS_845G(dev) || IS_I865G(dev)) 2930 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; 2931 else 2932 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 2933 2934 return state; 2935 } 2936 2937 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) 2938 { 2939 struct drm_i915_private *dev_priv = dev->dev_private; 2940 u32 pos; 2941 2942 pos = I915_READ(CURPOS(pipe)); 2943 2944 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; 2945 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) 2946 *x = -*x; 2947 2948 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; 2949 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) 2950 *y = -*y; 2951 2952 return cursor_active(dev, pipe); 2953 } 2954 2955 static const char *plane_type(enum drm_plane_type type) 2956 { 2957 switch (type) { 2958 case DRM_PLANE_TYPE_OVERLAY: 2959 return "OVL"; 2960 case DRM_PLANE_TYPE_PRIMARY: 2961 return "PRI"; 2962 case DRM_PLANE_TYPE_CURSOR: 2963 return "CUR"; 2964 /* 2965 * Deliberately omitting default: to generate compiler warnings 2966 * when a new drm_plane_type gets added. 2967 */ 2968 } 2969 2970 return "unknown"; 2971 } 2972 2973 static const char *plane_rotation(unsigned int rotation) 2974 { 2975 static char buf[48]; 2976 /* 2977 * According to doc only one DRM_ROTATE_ is allowed but this 2978 * will print them all to visualize if the values are misused 2979 */ 2980 snprintf(buf, sizeof(buf), 2981 "%s%s%s%s%s%s(0x%08x)", 2982 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "", 2983 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "", 2984 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "", 2985 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "", 2986 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "", 2987 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "", 2988 rotation); 2989 2990 return buf; 2991 } 2992 2993 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2994 { 2995 struct drm_info_node *node = m->private; 2996 struct drm_device *dev = node->minor->dev; 2997 struct intel_plane *intel_plane; 2998 2999 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 3000 struct drm_plane_state *state; 3001 struct drm_plane *plane = &intel_plane->base; 3002 3003 if (!plane->state) { 3004 seq_puts(m, "plane->state is NULL!\n"); 3005 continue; 3006 } 3007 3008 state = plane->state; 3009 3010 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n", 3011 plane->base.id, 3012 plane_type(intel_plane->base.type), 3013 state->crtc_x, state->crtc_y, 3014 state->crtc_w, state->crtc_h, 3015 (state->src_x >> 16), 3016 ((state->src_x & 0xffff) * 15625) >> 10, 3017 (state->src_y >> 16), 3018 ((state->src_y & 0xffff) * 15625) >> 10, 3019 (state->src_w >> 16), 3020 ((state->src_w & 0xffff) * 15625) >> 10, 3021 (state->src_h >> 16), 3022 ((state->src_h & 0xffff) * 15625) >> 10, 3023 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A", 3024 plane_rotation(state->rotation)); 3025 } 3026 } 3027 3028 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc) 3029 { 3030 struct intel_crtc_state *pipe_config; 3031 int num_scalers = intel_crtc->num_scalers; 3032 int i; 3033 3034 pipe_config = to_intel_crtc_state(intel_crtc->base.state); 3035 3036 /* Not all platformas have a scaler */ 3037 if (num_scalers) { 3038 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", 3039 num_scalers, 3040 pipe_config->scaler_state.scaler_users, 3041 pipe_config->scaler_state.scaler_id); 3042 3043 for (i = 0; i < SKL_NUM_SCALERS; i++) { 3044 struct intel_scaler *sc = 3045 &pipe_config->scaler_state.scalers[i]; 3046 3047 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", 3048 i, yesno(sc->in_use), sc->mode); 3049 } 3050 seq_puts(m, "\n"); 3051 } else { 3052 seq_puts(m, "\tNo scalers available on this platform\n"); 3053 } 3054 } 3055 3056 static int i915_display_info(struct seq_file *m, void *unused) 3057 { 3058 struct drm_info_node *node = m->private; 3059 struct drm_device *dev = node->minor->dev; 3060 struct drm_i915_private *dev_priv = dev->dev_private; 3061 struct intel_crtc *crtc; 3062 struct drm_connector *connector; 3063 3064 intel_runtime_pm_get(dev_priv); 3065 drm_modeset_lock_all(dev); 3066 seq_printf(m, "CRTC info\n"); 3067 seq_printf(m, "---------\n"); 3068 for_each_intel_crtc(dev, crtc) { 3069 bool active; 3070 struct intel_crtc_state *pipe_config; 3071 int x, y; 3072 3073 pipe_config = to_intel_crtc_state(crtc->base.state); 3074 3075 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", 3076 crtc->base.base.id, pipe_name(crtc->pipe), 3077 yesno(pipe_config->base.active), 3078 pipe_config->pipe_src_w, pipe_config->pipe_src_h, 3079 yesno(pipe_config->dither), pipe_config->pipe_bpp); 3080 3081 if (pipe_config->base.active) { 3082 intel_crtc_info(m, crtc); 3083 3084 active = cursor_position(dev, crtc->pipe, &x, &y); 3085 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", 3086 yesno(crtc->cursor_base), 3087 x, y, crtc->base.cursor->state->crtc_w, 3088 crtc->base.cursor->state->crtc_h, 3089 crtc->cursor_addr, yesno(active)); 3090 intel_scaler_info(m, crtc); 3091 intel_plane_info(m, crtc); 3092 } 3093 3094 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", 3095 yesno(!crtc->cpu_fifo_underrun_disabled), 3096 yesno(!crtc->pch_fifo_underrun_disabled)); 3097 } 3098 3099 seq_printf(m, "\n"); 3100 seq_printf(m, "Connector info\n"); 3101 seq_printf(m, "--------------\n"); 3102 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3103 intel_connector_info(m, connector); 3104 } 3105 drm_modeset_unlock_all(dev); 3106 intel_runtime_pm_put(dev_priv); 3107 3108 return 0; 3109 } 3110 3111 static int i915_semaphore_status(struct seq_file *m, void *unused) 3112 { 3113 struct drm_info_node *node = (struct drm_info_node *) m->private; 3114 struct drm_device *dev = node->minor->dev; 3115 struct drm_i915_private *dev_priv = dev->dev_private; 3116 struct intel_engine_cs *ring; 3117 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); 3118 int i, j, ret; 3119 3120 if (!i915_semaphore_is_enabled(dev)) { 3121 seq_puts(m, "Semaphores are disabled\n"); 3122 return 0; 3123 } 3124 3125 ret = mutex_lock_interruptible(&dev->struct_mutex); 3126 if (ret) 3127 return ret; 3128 intel_runtime_pm_get(dev_priv); 3129 3130 if (IS_BROADWELL(dev)) { 3131 struct page *page; 3132 uint64_t *seqno; 3133 3134 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); 3135 3136 seqno = (uint64_t *)kmap_atomic(page); 3137 for_each_ring(ring, dev_priv, i) { 3138 uint64_t offset; 3139 3140 seq_printf(m, "%s\n", ring->name); 3141 3142 seq_puts(m, " Last signal:"); 3143 for (j = 0; j < num_rings; j++) { 3144 offset = i * I915_NUM_RINGS + j; 3145 seq_printf(m, "0x%08llx (0x%02llx) ", 3146 seqno[offset], offset * 8); 3147 } 3148 seq_putc(m, '\n'); 3149 3150 seq_puts(m, " Last wait: "); 3151 for (j = 0; j < num_rings; j++) { 3152 offset = i + (j * I915_NUM_RINGS); 3153 seq_printf(m, "0x%08llx (0x%02llx) ", 3154 seqno[offset], offset * 8); 3155 } 3156 seq_putc(m, '\n'); 3157 3158 } 3159 kunmap_atomic(seqno); 3160 } else { 3161 seq_puts(m, " Last signal:"); 3162 for_each_ring(ring, dev_priv, i) 3163 for (j = 0; j < num_rings; j++) 3164 seq_printf(m, "0x%08x\n", 3165 I915_READ(ring->semaphore.mbox.signal[j])); 3166 seq_putc(m, '\n'); 3167 } 3168 3169 seq_puts(m, "\nSync seqno:\n"); 3170 for_each_ring(ring, dev_priv, i) { 3171 for (j = 0; j < num_rings; j++) { 3172 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); 3173 } 3174 seq_putc(m, '\n'); 3175 } 3176 seq_putc(m, '\n'); 3177 3178 intel_runtime_pm_put(dev_priv); 3179 mutex_unlock(&dev->struct_mutex); 3180 return 0; 3181 } 3182 3183 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 3184 { 3185 struct drm_info_node *node = (struct drm_info_node *) m->private; 3186 struct drm_device *dev = node->minor->dev; 3187 struct drm_i915_private *dev_priv = dev->dev_private; 3188 int i; 3189 3190 drm_modeset_lock_all(dev); 3191 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 3192 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 3193 3194 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); 3195 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", 3196 pll->config.crtc_mask, pll->active, yesno(pll->on)); 3197 seq_printf(m, " tracked hardware state:\n"); 3198 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); 3199 seq_printf(m, " dpll_md: 0x%08x\n", 3200 pll->config.hw_state.dpll_md); 3201 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); 3202 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); 3203 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); 3204 } 3205 drm_modeset_unlock_all(dev); 3206 3207 return 0; 3208 } 3209 3210 static int i915_wa_registers(struct seq_file *m, void *unused) 3211 { 3212 int i; 3213 int ret; 3214 struct drm_info_node *node = (struct drm_info_node *) m->private; 3215 struct drm_device *dev = node->minor->dev; 3216 struct drm_i915_private *dev_priv = dev->dev_private; 3217 3218 ret = mutex_lock_interruptible(&dev->struct_mutex); 3219 if (ret) 3220 return ret; 3221 3222 intel_runtime_pm_get(dev_priv); 3223 3224 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); 3225 for (i = 0; i < dev_priv->workarounds.count; ++i) { 3226 i915_reg_t addr; 3227 u32 mask, value, read; 3228 bool ok; 3229 3230 addr = dev_priv->workarounds.reg[i].addr; 3231 mask = dev_priv->workarounds.reg[i].mask; 3232 value = dev_priv->workarounds.reg[i].value; 3233 read = I915_READ(addr); 3234 ok = (value & mask) == (read & mask); 3235 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", 3236 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL"); 3237 } 3238 3239 intel_runtime_pm_put(dev_priv); 3240 mutex_unlock(&dev->struct_mutex); 3241 3242 return 0; 3243 } 3244 3245 static int i915_ddb_info(struct seq_file *m, void *unused) 3246 { 3247 struct drm_info_node *node = m->private; 3248 struct drm_device *dev = node->minor->dev; 3249 struct drm_i915_private *dev_priv = dev->dev_private; 3250 struct skl_ddb_allocation *ddb; 3251 struct skl_ddb_entry *entry; 3252 enum pipe pipe; 3253 int plane; 3254 3255 if (INTEL_INFO(dev)->gen < 9) 3256 return 0; 3257 3258 drm_modeset_lock_all(dev); 3259 3260 ddb = &dev_priv->wm.skl_hw.ddb; 3261 3262 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 3263 3264 for_each_pipe(dev_priv, pipe) { 3265 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 3266 3267 for_each_plane(dev_priv, pipe, plane) { 3268 entry = &ddb->plane[pipe][plane]; 3269 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, 3270 entry->start, entry->end, 3271 skl_ddb_entry_size(entry)); 3272 } 3273 3274 entry = &ddb->plane[pipe][PLANE_CURSOR]; 3275 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 3276 entry->end, skl_ddb_entry_size(entry)); 3277 } 3278 3279 drm_modeset_unlock_all(dev); 3280 3281 return 0; 3282 } 3283 3284 static void drrs_status_per_crtc(struct seq_file *m, 3285 struct drm_device *dev, struct intel_crtc *intel_crtc) 3286 { 3287 struct intel_encoder *intel_encoder; 3288 struct drm_i915_private *dev_priv = dev->dev_private; 3289 struct i915_drrs *drrs = &dev_priv->drrs; 3290 int vrefresh = 0; 3291 3292 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { 3293 /* Encoder connected on this CRTC */ 3294 switch (intel_encoder->type) { 3295 case INTEL_OUTPUT_EDP: 3296 seq_puts(m, "eDP:\n"); 3297 break; 3298 case INTEL_OUTPUT_DSI: 3299 seq_puts(m, "DSI:\n"); 3300 break; 3301 case INTEL_OUTPUT_HDMI: 3302 seq_puts(m, "HDMI:\n"); 3303 break; 3304 case INTEL_OUTPUT_DISPLAYPORT: 3305 seq_puts(m, "DP:\n"); 3306 break; 3307 default: 3308 seq_printf(m, "Other encoder (id=%d).\n", 3309 intel_encoder->type); 3310 return; 3311 } 3312 } 3313 3314 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) 3315 seq_puts(m, "\tVBT: DRRS_type: Static"); 3316 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) 3317 seq_puts(m, "\tVBT: DRRS_type: Seamless"); 3318 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) 3319 seq_puts(m, "\tVBT: DRRS_type: None"); 3320 else 3321 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); 3322 3323 seq_puts(m, "\n\n"); 3324 3325 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { 3326 struct intel_panel *panel; 3327 3328 mutex_lock(&drrs->mutex); 3329 /* DRRS Supported */ 3330 seq_puts(m, "\tDRRS Supported: Yes\n"); 3331 3332 /* disable_drrs() will make drrs->dp NULL */ 3333 if (!drrs->dp) { 3334 seq_puts(m, "Idleness DRRS: Disabled"); 3335 mutex_unlock(&drrs->mutex); 3336 return; 3337 } 3338 3339 panel = &drrs->dp->attached_connector->panel; 3340 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", 3341 drrs->busy_frontbuffer_bits); 3342 3343 seq_puts(m, "\n\t\t"); 3344 if (drrs->refresh_rate_type == DRRS_HIGH_RR) { 3345 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); 3346 vrefresh = panel->fixed_mode->vrefresh; 3347 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { 3348 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); 3349 vrefresh = panel->downclock_mode->vrefresh; 3350 } else { 3351 seq_printf(m, "DRRS_State: Unknown(%d)\n", 3352 drrs->refresh_rate_type); 3353 mutex_unlock(&drrs->mutex); 3354 return; 3355 } 3356 seq_printf(m, "\t\tVrefresh: %d", vrefresh); 3357 3358 seq_puts(m, "\n\t\t"); 3359 mutex_unlock(&drrs->mutex); 3360 } else { 3361 /* DRRS not supported. Print the VBT parameter*/ 3362 seq_puts(m, "\tDRRS Supported : No"); 3363 } 3364 seq_puts(m, "\n"); 3365 } 3366 3367 static int i915_drrs_status(struct seq_file *m, void *unused) 3368 { 3369 struct drm_info_node *node = m->private; 3370 struct drm_device *dev = node->minor->dev; 3371 struct intel_crtc *intel_crtc; 3372 int active_crtc_cnt = 0; 3373 3374 for_each_intel_crtc(dev, intel_crtc) { 3375 drm_modeset_lock(&intel_crtc->base.mutex, NULL); 3376 3377 if (intel_crtc->base.state->active) { 3378 active_crtc_cnt++; 3379 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); 3380 3381 drrs_status_per_crtc(m, dev, intel_crtc); 3382 } 3383 3384 drm_modeset_unlock(&intel_crtc->base.mutex); 3385 } 3386 3387 if (!active_crtc_cnt) 3388 seq_puts(m, "No active crtc found\n"); 3389 3390 return 0; 3391 } 3392 3393 struct pipe_crc_info { 3394 const char *name; 3395 struct drm_device *dev; 3396 enum pipe pipe; 3397 }; 3398 3399 static int i915_dp_mst_info(struct seq_file *m, void *unused) 3400 { 3401 struct drm_info_node *node = (struct drm_info_node *) m->private; 3402 struct drm_device *dev = node->minor->dev; 3403 struct drm_encoder *encoder; 3404 struct intel_encoder *intel_encoder; 3405 struct intel_digital_port *intel_dig_port; 3406 drm_modeset_lock_all(dev); 3407 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3408 intel_encoder = to_intel_encoder(encoder); 3409 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) 3410 continue; 3411 intel_dig_port = enc_to_dig_port(encoder); 3412 if (!intel_dig_port->dp.can_mst) 3413 continue; 3414 3415 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); 3416 } 3417 drm_modeset_unlock_all(dev); 3418 return 0; 3419 } 3420 3421 static int i915_pipe_crc_open(struct inode *inode, struct file *filep) 3422 { 3423 struct pipe_crc_info *info = inode->i_private; 3424 struct drm_i915_private *dev_priv = info->dev->dev_private; 3425 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3426 3427 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) 3428 return -ENODEV; 3429 3430 spin_lock_irq(&pipe_crc->lock); 3431 3432 if (pipe_crc->opened) { 3433 spin_unlock_irq(&pipe_crc->lock); 3434 return -EBUSY; /* already open */ 3435 } 3436 3437 pipe_crc->opened = true; 3438 filep->private_data = inode->i_private; 3439 3440 spin_unlock_irq(&pipe_crc->lock); 3441 3442 return 0; 3443 } 3444 3445 static int i915_pipe_crc_release(struct inode *inode, struct file *filep) 3446 { 3447 struct pipe_crc_info *info = inode->i_private; 3448 struct drm_i915_private *dev_priv = info->dev->dev_private; 3449 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3450 3451 spin_lock_irq(&pipe_crc->lock); 3452 pipe_crc->opened = false; 3453 spin_unlock_irq(&pipe_crc->lock); 3454 3455 return 0; 3456 } 3457 3458 /* (6 fields, 8 chars each, space separated (5) + '\n') */ 3459 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) 3460 /* account for \'0' */ 3461 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) 3462 3463 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) 3464 { 3465 assert_spin_locked(&pipe_crc->lock); 3466 return CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3467 INTEL_PIPE_CRC_ENTRIES_NR); 3468 } 3469 3470 static ssize_t 3471 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, 3472 loff_t *pos) 3473 { 3474 struct pipe_crc_info *info = filep->private_data; 3475 struct drm_device *dev = info->dev; 3476 struct drm_i915_private *dev_priv = dev->dev_private; 3477 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3478 char buf[PIPE_CRC_BUFFER_LEN]; 3479 int n_entries; 3480 ssize_t bytes_read; 3481 3482 /* 3483 * Don't allow user space to provide buffers not big enough to hold 3484 * a line of data. 3485 */ 3486 if (count < PIPE_CRC_LINE_LEN) 3487 return -EINVAL; 3488 3489 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) 3490 return 0; 3491 3492 /* nothing to read */ 3493 spin_lock_irq(&pipe_crc->lock); 3494 while (pipe_crc_data_count(pipe_crc) == 0) { 3495 int ret; 3496 3497 if (filep->f_flags & O_NONBLOCK) { 3498 spin_unlock_irq(&pipe_crc->lock); 3499 return -EAGAIN; 3500 } 3501 3502 ret = wait_event_interruptible_lock_irq(pipe_crc->wq, 3503 pipe_crc_data_count(pipe_crc), pipe_crc->lock); 3504 if (ret) { 3505 spin_unlock_irq(&pipe_crc->lock); 3506 return ret; 3507 } 3508 } 3509 3510 /* We now have one or more entries to read */ 3511 n_entries = count / PIPE_CRC_LINE_LEN; 3512 3513 bytes_read = 0; 3514 while (n_entries > 0) { 3515 struct intel_pipe_crc_entry *entry = 3516 &pipe_crc->entries[pipe_crc->tail]; 3517 int ret; 3518 3519 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3520 INTEL_PIPE_CRC_ENTRIES_NR) < 1) 3521 break; 3522 3523 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); 3524 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 3525 3526 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, 3527 "%8u %8x %8x %8x %8x %8x\n", 3528 entry->frame, entry->crc[0], 3529 entry->crc[1], entry->crc[2], 3530 entry->crc[3], entry->crc[4]); 3531 3532 spin_unlock_irq(&pipe_crc->lock); 3533 3534 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); 3535 if (ret == PIPE_CRC_LINE_LEN) 3536 return -EFAULT; 3537 3538 user_buf += PIPE_CRC_LINE_LEN; 3539 n_entries--; 3540 3541 spin_lock_irq(&pipe_crc->lock); 3542 } 3543 3544 spin_unlock_irq(&pipe_crc->lock); 3545 3546 return bytes_read; 3547 } 3548 3549 static const struct file_operations i915_pipe_crc_fops = { 3550 .owner = THIS_MODULE, 3551 .open = i915_pipe_crc_open, 3552 .read = i915_pipe_crc_read, 3553 .release = i915_pipe_crc_release, 3554 }; 3555 3556 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { 3557 { 3558 .name = "i915_pipe_A_crc", 3559 .pipe = PIPE_A, 3560 }, 3561 { 3562 .name = "i915_pipe_B_crc", 3563 .pipe = PIPE_B, 3564 }, 3565 { 3566 .name = "i915_pipe_C_crc", 3567 .pipe = PIPE_C, 3568 }, 3569 }; 3570 3571 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, 3572 enum pipe pipe) 3573 { 3574 struct drm_device *dev = minor->dev; 3575 struct dentry *ent; 3576 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; 3577 3578 info->dev = dev; 3579 ent = debugfs_create_file(info->name, S_IRUGO, root, info, 3580 &i915_pipe_crc_fops); 3581 if (!ent) 3582 return -ENOMEM; 3583 3584 return drm_add_fake_info_node(minor, ent, info); 3585 } 3586 3587 static const char * const pipe_crc_sources[] = { 3588 "none", 3589 "plane1", 3590 "plane2", 3591 "pf", 3592 "pipe", 3593 "TV", 3594 "DP-B", 3595 "DP-C", 3596 "DP-D", 3597 "auto", 3598 }; 3599 3600 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) 3601 { 3602 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); 3603 return pipe_crc_sources[source]; 3604 } 3605 3606 static int display_crc_ctl_show(struct seq_file *m, void *data) 3607 { 3608 struct drm_device *dev = m->private; 3609 struct drm_i915_private *dev_priv = dev->dev_private; 3610 int i; 3611 3612 for (i = 0; i < I915_MAX_PIPES; i++) 3613 seq_printf(m, "%c %s\n", pipe_name(i), 3614 pipe_crc_source_name(dev_priv->pipe_crc[i].source)); 3615 3616 return 0; 3617 } 3618 3619 static int display_crc_ctl_open(struct inode *inode, struct file *file) 3620 { 3621 struct drm_device *dev = inode->i_private; 3622 3623 return single_open(file, display_crc_ctl_show, dev); 3624 } 3625 3626 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3627 uint32_t *val) 3628 { 3629 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3630 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3631 3632 switch (*source) { 3633 case INTEL_PIPE_CRC_SOURCE_PIPE: 3634 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 3635 break; 3636 case INTEL_PIPE_CRC_SOURCE_NONE: 3637 *val = 0; 3638 break; 3639 default: 3640 return -EINVAL; 3641 } 3642 3643 return 0; 3644 } 3645 3646 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, 3647 enum intel_pipe_crc_source *source) 3648 { 3649 struct intel_encoder *encoder; 3650 struct intel_crtc *crtc; 3651 struct intel_digital_port *dig_port; 3652 int ret = 0; 3653 3654 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3655 3656 drm_modeset_lock_all(dev); 3657 for_each_intel_encoder(dev, encoder) { 3658 if (!encoder->base.crtc) 3659 continue; 3660 3661 crtc = to_intel_crtc(encoder->base.crtc); 3662 3663 if (crtc->pipe != pipe) 3664 continue; 3665 3666 switch (encoder->type) { 3667 case INTEL_OUTPUT_TVOUT: 3668 *source = INTEL_PIPE_CRC_SOURCE_TV; 3669 break; 3670 case INTEL_OUTPUT_DISPLAYPORT: 3671 case INTEL_OUTPUT_EDP: 3672 dig_port = enc_to_dig_port(&encoder->base); 3673 switch (dig_port->port) { 3674 case PORT_B: 3675 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 3676 break; 3677 case PORT_C: 3678 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 3679 break; 3680 case PORT_D: 3681 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 3682 break; 3683 default: 3684 WARN(1, "nonexisting DP port %c\n", 3685 port_name(dig_port->port)); 3686 break; 3687 } 3688 break; 3689 default: 3690 break; 3691 } 3692 } 3693 drm_modeset_unlock_all(dev); 3694 3695 return ret; 3696 } 3697 3698 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 3699 enum pipe pipe, 3700 enum intel_pipe_crc_source *source, 3701 uint32_t *val) 3702 { 3703 struct drm_i915_private *dev_priv = dev->dev_private; 3704 bool need_stable_symbols = false; 3705 3706 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3707 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); 3708 if (ret) 3709 return ret; 3710 } 3711 3712 switch (*source) { 3713 case INTEL_PIPE_CRC_SOURCE_PIPE: 3714 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 3715 break; 3716 case INTEL_PIPE_CRC_SOURCE_DP_B: 3717 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 3718 need_stable_symbols = true; 3719 break; 3720 case INTEL_PIPE_CRC_SOURCE_DP_C: 3721 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 3722 need_stable_symbols = true; 3723 break; 3724 case INTEL_PIPE_CRC_SOURCE_DP_D: 3725 if (!IS_CHERRYVIEW(dev)) 3726 return -EINVAL; 3727 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 3728 need_stable_symbols = true; 3729 break; 3730 case INTEL_PIPE_CRC_SOURCE_NONE: 3731 *val = 0; 3732 break; 3733 default: 3734 return -EINVAL; 3735 } 3736 3737 /* 3738 * When the pipe CRC tap point is after the transcoders we need 3739 * to tweak symbol-level features to produce a deterministic series of 3740 * symbols for a given frame. We need to reset those features only once 3741 * a frame (instead of every nth symbol): 3742 * - DC-balance: used to ensure a better clock recovery from the data 3743 * link (SDVO) 3744 * - DisplayPort scrambling: used for EMI reduction 3745 */ 3746 if (need_stable_symbols) { 3747 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3748 3749 tmp |= DC_BALANCE_RESET_VLV; 3750 switch (pipe) { 3751 case PIPE_A: 3752 tmp |= PIPE_A_SCRAMBLE_RESET; 3753 break; 3754 case PIPE_B: 3755 tmp |= PIPE_B_SCRAMBLE_RESET; 3756 break; 3757 case PIPE_C: 3758 tmp |= PIPE_C_SCRAMBLE_RESET; 3759 break; 3760 default: 3761 return -EINVAL; 3762 } 3763 I915_WRITE(PORT_DFT2_G4X, tmp); 3764 } 3765 3766 return 0; 3767 } 3768 3769 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, 3770 enum pipe pipe, 3771 enum intel_pipe_crc_source *source, 3772 uint32_t *val) 3773 { 3774 struct drm_i915_private *dev_priv = dev->dev_private; 3775 bool need_stable_symbols = false; 3776 3777 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3778 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); 3779 if (ret) 3780 return ret; 3781 } 3782 3783 switch (*source) { 3784 case INTEL_PIPE_CRC_SOURCE_PIPE: 3785 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 3786 break; 3787 case INTEL_PIPE_CRC_SOURCE_TV: 3788 if (!SUPPORTS_TV(dev)) 3789 return -EINVAL; 3790 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 3791 break; 3792 case INTEL_PIPE_CRC_SOURCE_DP_B: 3793 if (!IS_G4X(dev)) 3794 return -EINVAL; 3795 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; 3796 need_stable_symbols = true; 3797 break; 3798 case INTEL_PIPE_CRC_SOURCE_DP_C: 3799 if (!IS_G4X(dev)) 3800 return -EINVAL; 3801 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; 3802 need_stable_symbols = true; 3803 break; 3804 case INTEL_PIPE_CRC_SOURCE_DP_D: 3805 if (!IS_G4X(dev)) 3806 return -EINVAL; 3807 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; 3808 need_stable_symbols = true; 3809 break; 3810 case INTEL_PIPE_CRC_SOURCE_NONE: 3811 *val = 0; 3812 break; 3813 default: 3814 return -EINVAL; 3815 } 3816 3817 /* 3818 * When the pipe CRC tap point is after the transcoders we need 3819 * to tweak symbol-level features to produce a deterministic series of 3820 * symbols for a given frame. We need to reset those features only once 3821 * a frame (instead of every nth symbol): 3822 * - DC-balance: used to ensure a better clock recovery from the data 3823 * link (SDVO) 3824 * - DisplayPort scrambling: used for EMI reduction 3825 */ 3826 if (need_stable_symbols) { 3827 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3828 3829 WARN_ON(!IS_G4X(dev)); 3830 3831 I915_WRITE(PORT_DFT_I9XX, 3832 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); 3833 3834 if (pipe == PIPE_A) 3835 tmp |= PIPE_A_SCRAMBLE_RESET; 3836 else 3837 tmp |= PIPE_B_SCRAMBLE_RESET; 3838 3839 I915_WRITE(PORT_DFT2_G4X, tmp); 3840 } 3841 3842 return 0; 3843 } 3844 3845 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, 3846 enum pipe pipe) 3847 { 3848 struct drm_i915_private *dev_priv = dev->dev_private; 3849 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3850 3851 switch (pipe) { 3852 case PIPE_A: 3853 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3854 break; 3855 case PIPE_B: 3856 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3857 break; 3858 case PIPE_C: 3859 tmp &= ~PIPE_C_SCRAMBLE_RESET; 3860 break; 3861 default: 3862 return; 3863 } 3864 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 3865 tmp &= ~DC_BALANCE_RESET_VLV; 3866 I915_WRITE(PORT_DFT2_G4X, tmp); 3867 3868 } 3869 3870 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, 3871 enum pipe pipe) 3872 { 3873 struct drm_i915_private *dev_priv = dev->dev_private; 3874 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3875 3876 if (pipe == PIPE_A) 3877 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3878 else 3879 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3880 I915_WRITE(PORT_DFT2_G4X, tmp); 3881 3882 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { 3883 I915_WRITE(PORT_DFT_I9XX, 3884 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); 3885 } 3886 } 3887 3888 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3889 uint32_t *val) 3890 { 3891 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3892 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3893 3894 switch (*source) { 3895 case INTEL_PIPE_CRC_SOURCE_PLANE1: 3896 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 3897 break; 3898 case INTEL_PIPE_CRC_SOURCE_PLANE2: 3899 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 3900 break; 3901 case INTEL_PIPE_CRC_SOURCE_PIPE: 3902 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 3903 break; 3904 case INTEL_PIPE_CRC_SOURCE_NONE: 3905 *val = 0; 3906 break; 3907 default: 3908 return -EINVAL; 3909 } 3910 3911 return 0; 3912 } 3913 3914 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable) 3915 { 3916 struct drm_i915_private *dev_priv = dev->dev_private; 3917 struct intel_crtc *crtc = 3918 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); 3919 struct intel_crtc_state *pipe_config; 3920 struct drm_atomic_state *state; 3921 int ret = 0; 3922 3923 drm_modeset_lock_all(dev); 3924 state = drm_atomic_state_alloc(dev); 3925 if (!state) { 3926 ret = -ENOMEM; 3927 goto out; 3928 } 3929 3930 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base); 3931 pipe_config = intel_atomic_get_crtc_state(state, crtc); 3932 if (IS_ERR(pipe_config)) { 3933 ret = PTR_ERR(pipe_config); 3934 goto out; 3935 } 3936 3937 pipe_config->pch_pfit.force_thru = enable; 3938 if (pipe_config->cpu_transcoder == TRANSCODER_EDP && 3939 pipe_config->pch_pfit.enabled != enable) 3940 pipe_config->base.connectors_changed = true; 3941 3942 ret = drm_atomic_commit(state); 3943 out: 3944 drm_modeset_unlock_all(dev); 3945 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); 3946 if (ret) 3947 drm_atomic_state_free(state); 3948 } 3949 3950 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, 3951 enum pipe pipe, 3952 enum intel_pipe_crc_source *source, 3953 uint32_t *val) 3954 { 3955 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3956 *source = INTEL_PIPE_CRC_SOURCE_PF; 3957 3958 switch (*source) { 3959 case INTEL_PIPE_CRC_SOURCE_PLANE1: 3960 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 3961 break; 3962 case INTEL_PIPE_CRC_SOURCE_PLANE2: 3963 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 3964 break; 3965 case INTEL_PIPE_CRC_SOURCE_PF: 3966 if (IS_HASWELL(dev) && pipe == PIPE_A) 3967 hsw_trans_edp_pipe_A_crc_wa(dev, true); 3968 3969 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 3970 break; 3971 case INTEL_PIPE_CRC_SOURCE_NONE: 3972 *val = 0; 3973 break; 3974 default: 3975 return -EINVAL; 3976 } 3977 3978 return 0; 3979 } 3980 3981 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 3982 enum intel_pipe_crc_source source) 3983 { 3984 struct drm_i915_private *dev_priv = dev->dev_private; 3985 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 3986 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, 3987 pipe)); 3988 u32 val = 0; /* shut up gcc */ 3989 int ret; 3990 3991 if (pipe_crc->source == source) 3992 return 0; 3993 3994 /* forbid changing the source without going back to 'none' */ 3995 if (pipe_crc->source && source) 3996 return -EINVAL; 3997 3998 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { 3999 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); 4000 return -EIO; 4001 } 4002 4003 if (IS_GEN2(dev)) 4004 ret = i8xx_pipe_crc_ctl_reg(&source, &val); 4005 else if (INTEL_INFO(dev)->gen < 5) 4006 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); 4007 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 4008 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); 4009 else if (IS_GEN5(dev) || IS_GEN6(dev)) 4010 ret = ilk_pipe_crc_ctl_reg(&source, &val); 4011 else 4012 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); 4013 4014 if (ret != 0) 4015 return ret; 4016 4017 /* none -> real source transition */ 4018 if (source) { 4019 struct intel_pipe_crc_entry *entries; 4020 4021 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", 4022 pipe_name(pipe), pipe_crc_source_name(source)); 4023 4024 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, 4025 sizeof(pipe_crc->entries[0]), 4026 GFP_KERNEL); 4027 if (!entries) 4028 return -ENOMEM; 4029 4030 /* 4031 * When IPS gets enabled, the pipe CRC changes. Since IPS gets 4032 * enabled and disabled dynamically based on package C states, 4033 * user space can't make reliable use of the CRCs, so let's just 4034 * completely disable it. 4035 */ 4036 hsw_disable_ips(crtc); 4037 4038 spin_lock_irq(&pipe_crc->lock); 4039 kfree(pipe_crc->entries); 4040 pipe_crc->entries = entries; 4041 pipe_crc->head = 0; 4042 pipe_crc->tail = 0; 4043 spin_unlock_irq(&pipe_crc->lock); 4044 } 4045 4046 pipe_crc->source = source; 4047 4048 I915_WRITE(PIPE_CRC_CTL(pipe), val); 4049 POSTING_READ(PIPE_CRC_CTL(pipe)); 4050 4051 /* real source -> none transition */ 4052 if (source == INTEL_PIPE_CRC_SOURCE_NONE) { 4053 struct intel_pipe_crc_entry *entries; 4054 struct intel_crtc *crtc = 4055 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 4056 4057 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", 4058 pipe_name(pipe)); 4059 4060 drm_modeset_lock(&crtc->base.mutex, NULL); 4061 if (crtc->base.state->active) 4062 intel_wait_for_vblank(dev, pipe); 4063 drm_modeset_unlock(&crtc->base.mutex); 4064 4065 spin_lock_irq(&pipe_crc->lock); 4066 entries = pipe_crc->entries; 4067 pipe_crc->entries = NULL; 4068 pipe_crc->head = 0; 4069 pipe_crc->tail = 0; 4070 spin_unlock_irq(&pipe_crc->lock); 4071 4072 kfree(entries); 4073 4074 if (IS_G4X(dev)) 4075 g4x_undo_pipe_scramble_reset(dev, pipe); 4076 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 4077 vlv_undo_pipe_scramble_reset(dev, pipe); 4078 else if (IS_HASWELL(dev) && pipe == PIPE_A) 4079 hsw_trans_edp_pipe_A_crc_wa(dev, false); 4080 4081 hsw_enable_ips(crtc); 4082 } 4083 4084 return 0; 4085 } 4086 4087 /* 4088 * Parse pipe CRC command strings: 4089 * command: wsp* object wsp+ name wsp+ source wsp* 4090 * object: 'pipe' 4091 * name: (A | B | C) 4092 * source: (none | plane1 | plane2 | pf) 4093 * wsp: (#0x20 | #0x9 | #0xA)+ 4094 * 4095 * eg.: 4096 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A 4097 * "pipe A none" -> Stop CRC 4098 */ 4099 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) 4100 { 4101 int n_words = 0; 4102 4103 while (*buf) { 4104 char *end; 4105 4106 /* skip leading white space */ 4107 buf = skip_spaces(buf); 4108 if (!*buf) 4109 break; /* end of buffer */ 4110 4111 /* find end of word */ 4112 for (end = buf; *end && !isspace(*end); end++) 4113 ; 4114 4115 if (n_words == max_words) { 4116 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", 4117 max_words); 4118 return -EINVAL; /* ran out of words[] before bytes */ 4119 } 4120 4121 if (*end) 4122 *end++ = '\0'; 4123 words[n_words++] = buf; 4124 buf = end; 4125 } 4126 4127 return n_words; 4128 } 4129 4130 enum intel_pipe_crc_object { 4131 PIPE_CRC_OBJECT_PIPE, 4132 }; 4133 4134 static const char * const pipe_crc_objects[] = { 4135 "pipe", 4136 }; 4137 4138 static int 4139 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) 4140 { 4141 int i; 4142 4143 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) 4144 if (!strcmp(buf, pipe_crc_objects[i])) { 4145 *o = i; 4146 return 0; 4147 } 4148 4149 return -EINVAL; 4150 } 4151 4152 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) 4153 { 4154 const char name = buf[0]; 4155 4156 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) 4157 return -EINVAL; 4158 4159 *pipe = name - 'A'; 4160 4161 return 0; 4162 } 4163 4164 static int 4165 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 4166 { 4167 int i; 4168 4169 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) 4170 if (!strcmp(buf, pipe_crc_sources[i])) { 4171 *s = i; 4172 return 0; 4173 } 4174 4175 return -EINVAL; 4176 } 4177 4178 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) 4179 { 4180 #define N_WORDS 3 4181 int n_words; 4182 char *words[N_WORDS]; 4183 enum pipe pipe; 4184 enum intel_pipe_crc_object object; 4185 enum intel_pipe_crc_source source; 4186 4187 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); 4188 if (n_words != N_WORDS) { 4189 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", 4190 N_WORDS); 4191 return -EINVAL; 4192 } 4193 4194 if (display_crc_ctl_parse_object(words[0], &object) < 0) { 4195 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); 4196 return -EINVAL; 4197 } 4198 4199 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { 4200 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); 4201 return -EINVAL; 4202 } 4203 4204 if (display_crc_ctl_parse_source(words[2], &source) < 0) { 4205 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); 4206 return -EINVAL; 4207 } 4208 4209 return pipe_crc_set_source(dev, pipe, source); 4210 } 4211 4212 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, 4213 size_t len, loff_t *offp) 4214 { 4215 struct seq_file *m = file->private_data; 4216 struct drm_device *dev = m->private; 4217 char *tmpbuf; 4218 int ret; 4219 4220 if (len == 0) 4221 return 0; 4222 4223 if (len > PAGE_SIZE - 1) { 4224 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", 4225 PAGE_SIZE); 4226 return -E2BIG; 4227 } 4228 4229 tmpbuf = kmalloc(len + 1, GFP_KERNEL); 4230 if (!tmpbuf) 4231 return -ENOMEM; 4232 4233 if (copy_from_user(tmpbuf, ubuf, len)) { 4234 ret = -EFAULT; 4235 goto out; 4236 } 4237 tmpbuf[len] = '\0'; 4238 4239 ret = display_crc_ctl_parse(dev, tmpbuf, len); 4240 4241 out: 4242 kfree(tmpbuf); 4243 if (ret < 0) 4244 return ret; 4245 4246 *offp += len; 4247 return len; 4248 } 4249 4250 static const struct file_operations i915_display_crc_ctl_fops = { 4251 .owner = THIS_MODULE, 4252 .open = display_crc_ctl_open, 4253 .read = seq_read, 4254 .llseek = seq_lseek, 4255 .release = single_release, 4256 .write = display_crc_ctl_write 4257 }; 4258 4259 static ssize_t i915_displayport_test_active_write(struct file *file, 4260 const char __user *ubuf, 4261 size_t len, loff_t *offp) 4262 { 4263 char *input_buffer; 4264 int status = 0; 4265 struct drm_device *dev; 4266 struct drm_connector *connector; 4267 struct list_head *connector_list; 4268 struct intel_dp *intel_dp; 4269 int val = 0; 4270 4271 dev = ((struct seq_file *)file->private_data)->private; 4272 4273 connector_list = &dev->mode_config.connector_list; 4274 4275 if (len == 0) 4276 return 0; 4277 4278 input_buffer = kmalloc(len + 1, GFP_KERNEL); 4279 if (!input_buffer) 4280 return -ENOMEM; 4281 4282 if (copy_from_user(input_buffer, ubuf, len)) { 4283 status = -EFAULT; 4284 goto out; 4285 } 4286 4287 input_buffer[len] = '\0'; 4288 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); 4289 4290 list_for_each_entry(connector, connector_list, head) { 4291 4292 if (connector->connector_type != 4293 DRM_MODE_CONNECTOR_DisplayPort) 4294 continue; 4295 4296 if (connector->status == connector_status_connected && 4297 connector->encoder != NULL) { 4298 intel_dp = enc_to_intel_dp(connector->encoder); 4299 status = kstrtoint(input_buffer, 10, &val); 4300 if (status < 0) 4301 goto out; 4302 DRM_DEBUG_DRIVER("Got %d for test active\n", val); 4303 /* To prevent erroneous activation of the compliance 4304 * testing code, only accept an actual value of 1 here 4305 */ 4306 if (val == 1) 4307 intel_dp->compliance_test_active = 1; 4308 else 4309 intel_dp->compliance_test_active = 0; 4310 } 4311 } 4312 out: 4313 kfree(input_buffer); 4314 if (status < 0) 4315 return status; 4316 4317 *offp += len; 4318 return len; 4319 } 4320 4321 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 4322 { 4323 struct drm_device *dev = m->private; 4324 struct drm_connector *connector; 4325 struct list_head *connector_list = &dev->mode_config.connector_list; 4326 struct intel_dp *intel_dp; 4327 4328 list_for_each_entry(connector, connector_list, head) { 4329 4330 if (connector->connector_type != 4331 DRM_MODE_CONNECTOR_DisplayPort) 4332 continue; 4333 4334 if (connector->status == connector_status_connected && 4335 connector->encoder != NULL) { 4336 intel_dp = enc_to_intel_dp(connector->encoder); 4337 if (intel_dp->compliance_test_active) 4338 seq_puts(m, "1"); 4339 else 4340 seq_puts(m, "0"); 4341 } else 4342 seq_puts(m, "0"); 4343 } 4344 4345 return 0; 4346 } 4347 4348 static int i915_displayport_test_active_open(struct inode *inode, 4349 struct file *file) 4350 { 4351 struct drm_device *dev = inode->i_private; 4352 4353 return single_open(file, i915_displayport_test_active_show, dev); 4354 } 4355 4356 static const struct file_operations i915_displayport_test_active_fops = { 4357 .owner = THIS_MODULE, 4358 .open = i915_displayport_test_active_open, 4359 .read = seq_read, 4360 .llseek = seq_lseek, 4361 .release = single_release, 4362 .write = i915_displayport_test_active_write 4363 }; 4364 4365 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 4366 { 4367 struct drm_device *dev = m->private; 4368 struct drm_connector *connector; 4369 struct list_head *connector_list = &dev->mode_config.connector_list; 4370 struct intel_dp *intel_dp; 4371 4372 list_for_each_entry(connector, connector_list, head) { 4373 4374 if (connector->connector_type != 4375 DRM_MODE_CONNECTOR_DisplayPort) 4376 continue; 4377 4378 if (connector->status == connector_status_connected && 4379 connector->encoder != NULL) { 4380 intel_dp = enc_to_intel_dp(connector->encoder); 4381 seq_printf(m, "%lx", intel_dp->compliance_test_data); 4382 } else 4383 seq_puts(m, "0"); 4384 } 4385 4386 return 0; 4387 } 4388 static int i915_displayport_test_data_open(struct inode *inode, 4389 struct file *file) 4390 { 4391 struct drm_device *dev = inode->i_private; 4392 4393 return single_open(file, i915_displayport_test_data_show, dev); 4394 } 4395 4396 static const struct file_operations i915_displayport_test_data_fops = { 4397 .owner = THIS_MODULE, 4398 .open = i915_displayport_test_data_open, 4399 .read = seq_read, 4400 .llseek = seq_lseek, 4401 .release = single_release 4402 }; 4403 4404 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 4405 { 4406 struct drm_device *dev = m->private; 4407 struct drm_connector *connector; 4408 struct list_head *connector_list = &dev->mode_config.connector_list; 4409 struct intel_dp *intel_dp; 4410 4411 list_for_each_entry(connector, connector_list, head) { 4412 4413 if (connector->connector_type != 4414 DRM_MODE_CONNECTOR_DisplayPort) 4415 continue; 4416 4417 if (connector->status == connector_status_connected && 4418 connector->encoder != NULL) { 4419 intel_dp = enc_to_intel_dp(connector->encoder); 4420 seq_printf(m, "%02lx", intel_dp->compliance_test_type); 4421 } else 4422 seq_puts(m, "0"); 4423 } 4424 4425 return 0; 4426 } 4427 4428 static int i915_displayport_test_type_open(struct inode *inode, 4429 struct file *file) 4430 { 4431 struct drm_device *dev = inode->i_private; 4432 4433 return single_open(file, i915_displayport_test_type_show, dev); 4434 } 4435 4436 static const struct file_operations i915_displayport_test_type_fops = { 4437 .owner = THIS_MODULE, 4438 .open = i915_displayport_test_type_open, 4439 .read = seq_read, 4440 .llseek = seq_lseek, 4441 .release = single_release 4442 }; 4443 4444 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 4445 { 4446 struct drm_device *dev = m->private; 4447 int level; 4448 int num_levels; 4449 4450 if (IS_CHERRYVIEW(dev)) 4451 num_levels = 3; 4452 else if (IS_VALLEYVIEW(dev)) 4453 num_levels = 1; 4454 else 4455 num_levels = ilk_wm_max_level(dev) + 1; 4456 4457 drm_modeset_lock_all(dev); 4458 4459 for (level = 0; level < num_levels; level++) { 4460 unsigned int latency = wm[level]; 4461 4462 /* 4463 * - WM1+ latency values in 0.5us units 4464 * - latencies are in us on gen9/vlv/chv 4465 */ 4466 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) || 4467 IS_CHERRYVIEW(dev)) 4468 latency *= 10; 4469 else if (level > 0) 4470 latency *= 5; 4471 4472 seq_printf(m, "WM%d %u (%u.%u usec)\n", 4473 level, wm[level], latency / 10, latency % 10); 4474 } 4475 4476 drm_modeset_unlock_all(dev); 4477 } 4478 4479 static int pri_wm_latency_show(struct seq_file *m, void *data) 4480 { 4481 struct drm_device *dev = m->private; 4482 struct drm_i915_private *dev_priv = dev->dev_private; 4483 const uint16_t *latencies; 4484 4485 if (INTEL_INFO(dev)->gen >= 9) 4486 latencies = dev_priv->wm.skl_latency; 4487 else 4488 latencies = to_i915(dev)->wm.pri_latency; 4489 4490 wm_latency_show(m, latencies); 4491 4492 return 0; 4493 } 4494 4495 static int spr_wm_latency_show(struct seq_file *m, void *data) 4496 { 4497 struct drm_device *dev = m->private; 4498 struct drm_i915_private *dev_priv = dev->dev_private; 4499 const uint16_t *latencies; 4500 4501 if (INTEL_INFO(dev)->gen >= 9) 4502 latencies = dev_priv->wm.skl_latency; 4503 else 4504 latencies = to_i915(dev)->wm.spr_latency; 4505 4506 wm_latency_show(m, latencies); 4507 4508 return 0; 4509 } 4510 4511 static int cur_wm_latency_show(struct seq_file *m, void *data) 4512 { 4513 struct drm_device *dev = m->private; 4514 struct drm_i915_private *dev_priv = dev->dev_private; 4515 const uint16_t *latencies; 4516 4517 if (INTEL_INFO(dev)->gen >= 9) 4518 latencies = dev_priv->wm.skl_latency; 4519 else 4520 latencies = to_i915(dev)->wm.cur_latency; 4521 4522 wm_latency_show(m, latencies); 4523 4524 return 0; 4525 } 4526 4527 static int pri_wm_latency_open(struct inode *inode, struct file *file) 4528 { 4529 struct drm_device *dev = inode->i_private; 4530 4531 if (INTEL_INFO(dev)->gen < 5) 4532 return -ENODEV; 4533 4534 return single_open(file, pri_wm_latency_show, dev); 4535 } 4536 4537 static int spr_wm_latency_open(struct inode *inode, struct file *file) 4538 { 4539 struct drm_device *dev = inode->i_private; 4540 4541 if (HAS_GMCH_DISPLAY(dev)) 4542 return -ENODEV; 4543 4544 return single_open(file, spr_wm_latency_show, dev); 4545 } 4546 4547 static int cur_wm_latency_open(struct inode *inode, struct file *file) 4548 { 4549 struct drm_device *dev = inode->i_private; 4550 4551 if (HAS_GMCH_DISPLAY(dev)) 4552 return -ENODEV; 4553 4554 return single_open(file, cur_wm_latency_show, dev); 4555 } 4556 4557 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 4558 size_t len, loff_t *offp, uint16_t wm[8]) 4559 { 4560 struct seq_file *m = file->private_data; 4561 struct drm_device *dev = m->private; 4562 uint16_t new[8] = { 0 }; 4563 int num_levels; 4564 int level; 4565 int ret; 4566 char tmp[32]; 4567 4568 if (IS_CHERRYVIEW(dev)) 4569 num_levels = 3; 4570 else if (IS_VALLEYVIEW(dev)) 4571 num_levels = 1; 4572 else 4573 num_levels = ilk_wm_max_level(dev) + 1; 4574 4575 if (len >= sizeof(tmp)) 4576 return -EINVAL; 4577 4578 if (copy_from_user(tmp, ubuf, len)) 4579 return -EFAULT; 4580 4581 tmp[len] = '\0'; 4582 4583 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 4584 &new[0], &new[1], &new[2], &new[3], 4585 &new[4], &new[5], &new[6], &new[7]); 4586 if (ret != num_levels) 4587 return -EINVAL; 4588 4589 drm_modeset_lock_all(dev); 4590 4591 for (level = 0; level < num_levels; level++) 4592 wm[level] = new[level]; 4593 4594 drm_modeset_unlock_all(dev); 4595 4596 return len; 4597 } 4598 4599 4600 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 4601 size_t len, loff_t *offp) 4602 { 4603 struct seq_file *m = file->private_data; 4604 struct drm_device *dev = m->private; 4605 struct drm_i915_private *dev_priv = dev->dev_private; 4606 uint16_t *latencies; 4607 4608 if (INTEL_INFO(dev)->gen >= 9) 4609 latencies = dev_priv->wm.skl_latency; 4610 else 4611 latencies = to_i915(dev)->wm.pri_latency; 4612 4613 return wm_latency_write(file, ubuf, len, offp, latencies); 4614 } 4615 4616 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 4617 size_t len, loff_t *offp) 4618 { 4619 struct seq_file *m = file->private_data; 4620 struct drm_device *dev = m->private; 4621 struct drm_i915_private *dev_priv = dev->dev_private; 4622 uint16_t *latencies; 4623 4624 if (INTEL_INFO(dev)->gen >= 9) 4625 latencies = dev_priv->wm.skl_latency; 4626 else 4627 latencies = to_i915(dev)->wm.spr_latency; 4628 4629 return wm_latency_write(file, ubuf, len, offp, latencies); 4630 } 4631 4632 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 4633 size_t len, loff_t *offp) 4634 { 4635 struct seq_file *m = file->private_data; 4636 struct drm_device *dev = m->private; 4637 struct drm_i915_private *dev_priv = dev->dev_private; 4638 uint16_t *latencies; 4639 4640 if (INTEL_INFO(dev)->gen >= 9) 4641 latencies = dev_priv->wm.skl_latency; 4642 else 4643 latencies = to_i915(dev)->wm.cur_latency; 4644 4645 return wm_latency_write(file, ubuf, len, offp, latencies); 4646 } 4647 4648 static const struct file_operations i915_pri_wm_latency_fops = { 4649 .owner = THIS_MODULE, 4650 .open = pri_wm_latency_open, 4651 .read = seq_read, 4652 .llseek = seq_lseek, 4653 .release = single_release, 4654 .write = pri_wm_latency_write 4655 }; 4656 4657 static const struct file_operations i915_spr_wm_latency_fops = { 4658 .owner = THIS_MODULE, 4659 .open = spr_wm_latency_open, 4660 .read = seq_read, 4661 .llseek = seq_lseek, 4662 .release = single_release, 4663 .write = spr_wm_latency_write 4664 }; 4665 4666 static const struct file_operations i915_cur_wm_latency_fops = { 4667 .owner = THIS_MODULE, 4668 .open = cur_wm_latency_open, 4669 .read = seq_read, 4670 .llseek = seq_lseek, 4671 .release = single_release, 4672 .write = cur_wm_latency_write 4673 }; 4674 4675 static int 4676 i915_wedged_get(void *data, u64 *val) 4677 { 4678 struct drm_device *dev = data; 4679 struct drm_i915_private *dev_priv = dev->dev_private; 4680 4681 *val = atomic_read(&dev_priv->gpu_error.reset_counter); 4682 4683 return 0; 4684 } 4685 4686 static int 4687 i915_wedged_set(void *data, u64 val) 4688 { 4689 struct drm_device *dev = data; 4690 struct drm_i915_private *dev_priv = dev->dev_private; 4691 4692 /* 4693 * There is no safeguard against this debugfs entry colliding 4694 * with the hangcheck calling same i915_handle_error() in 4695 * parallel, causing an explosion. For now we assume that the 4696 * test harness is responsible enough not to inject gpu hangs 4697 * while it is writing to 'i915_wedged' 4698 */ 4699 4700 if (i915_reset_in_progress(&dev_priv->gpu_error)) 4701 return -EAGAIN; 4702 4703 intel_runtime_pm_get(dev_priv); 4704 4705 i915_handle_error(dev, val, 4706 "Manually setting wedged to %llu", val); 4707 4708 intel_runtime_pm_put(dev_priv); 4709 4710 return 0; 4711 } 4712 4713 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 4714 i915_wedged_get, i915_wedged_set, 4715 "%llu\n"); 4716 4717 static int 4718 i915_ring_stop_get(void *data, u64 *val) 4719 { 4720 struct drm_device *dev = data; 4721 struct drm_i915_private *dev_priv = dev->dev_private; 4722 4723 *val = dev_priv->gpu_error.stop_rings; 4724 4725 return 0; 4726 } 4727 4728 static int 4729 i915_ring_stop_set(void *data, u64 val) 4730 { 4731 struct drm_device *dev = data; 4732 struct drm_i915_private *dev_priv = dev->dev_private; 4733 int ret; 4734 4735 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); 4736 4737 ret = mutex_lock_interruptible(&dev->struct_mutex); 4738 if (ret) 4739 return ret; 4740 4741 dev_priv->gpu_error.stop_rings = val; 4742 mutex_unlock(&dev->struct_mutex); 4743 4744 return 0; 4745 } 4746 4747 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, 4748 i915_ring_stop_get, i915_ring_stop_set, 4749 "0x%08llx\n"); 4750 4751 static int 4752 i915_ring_missed_irq_get(void *data, u64 *val) 4753 { 4754 struct drm_device *dev = data; 4755 struct drm_i915_private *dev_priv = dev->dev_private; 4756 4757 *val = dev_priv->gpu_error.missed_irq_rings; 4758 return 0; 4759 } 4760 4761 static int 4762 i915_ring_missed_irq_set(void *data, u64 val) 4763 { 4764 struct drm_device *dev = data; 4765 struct drm_i915_private *dev_priv = dev->dev_private; 4766 int ret; 4767 4768 /* Lock against concurrent debugfs callers */ 4769 ret = mutex_lock_interruptible(&dev->struct_mutex); 4770 if (ret) 4771 return ret; 4772 dev_priv->gpu_error.missed_irq_rings = val; 4773 mutex_unlock(&dev->struct_mutex); 4774 4775 return 0; 4776 } 4777 4778 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, 4779 i915_ring_missed_irq_get, i915_ring_missed_irq_set, 4780 "0x%08llx\n"); 4781 4782 static int 4783 i915_ring_test_irq_get(void *data, u64 *val) 4784 { 4785 struct drm_device *dev = data; 4786 struct drm_i915_private *dev_priv = dev->dev_private; 4787 4788 *val = dev_priv->gpu_error.test_irq_rings; 4789 4790 return 0; 4791 } 4792 4793 static int 4794 i915_ring_test_irq_set(void *data, u64 val) 4795 { 4796 struct drm_device *dev = data; 4797 struct drm_i915_private *dev_priv = dev->dev_private; 4798 int ret; 4799 4800 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); 4801 4802 /* Lock against concurrent debugfs callers */ 4803 ret = mutex_lock_interruptible(&dev->struct_mutex); 4804 if (ret) 4805 return ret; 4806 4807 dev_priv->gpu_error.test_irq_rings = val; 4808 mutex_unlock(&dev->struct_mutex); 4809 4810 return 0; 4811 } 4812 4813 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, 4814 i915_ring_test_irq_get, i915_ring_test_irq_set, 4815 "0x%08llx\n"); 4816 4817 #define DROP_UNBOUND 0x1 4818 #define DROP_BOUND 0x2 4819 #define DROP_RETIRE 0x4 4820 #define DROP_ACTIVE 0x8 4821 #define DROP_ALL (DROP_UNBOUND | \ 4822 DROP_BOUND | \ 4823 DROP_RETIRE | \ 4824 DROP_ACTIVE) 4825 static int 4826 i915_drop_caches_get(void *data, u64 *val) 4827 { 4828 *val = DROP_ALL; 4829 4830 return 0; 4831 } 4832 4833 static int 4834 i915_drop_caches_set(void *data, u64 val) 4835 { 4836 struct drm_device *dev = data; 4837 struct drm_i915_private *dev_priv = dev->dev_private; 4838 int ret; 4839 4840 DRM_DEBUG("Dropping caches: 0x%08llx\n", val); 4841 4842 /* No need to check and wait for gpu resets, only libdrm auto-restarts 4843 * on ioctls on -EAGAIN. */ 4844 ret = mutex_lock_interruptible(&dev->struct_mutex); 4845 if (ret) 4846 return ret; 4847 4848 if (val & DROP_ACTIVE) { 4849 ret = i915_gpu_idle(dev); 4850 if (ret) 4851 goto unlock; 4852 } 4853 4854 if (val & (DROP_RETIRE | DROP_ACTIVE)) 4855 i915_gem_retire_requests(dev); 4856 4857 if (val & DROP_BOUND) 4858 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); 4859 4860 if (val & DROP_UNBOUND) 4861 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); 4862 4863 unlock: 4864 mutex_unlock(&dev->struct_mutex); 4865 4866 return ret; 4867 } 4868 4869 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 4870 i915_drop_caches_get, i915_drop_caches_set, 4871 "0x%08llx\n"); 4872 4873 static int 4874 i915_max_freq_get(void *data, u64 *val) 4875 { 4876 struct drm_device *dev = data; 4877 struct drm_i915_private *dev_priv = dev->dev_private; 4878 int ret; 4879 4880 if (INTEL_INFO(dev)->gen < 6) 4881 return -ENODEV; 4882 4883 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4884 4885 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4886 if (ret) 4887 return ret; 4888 4889 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); 4890 mutex_unlock(&dev_priv->rps.hw_lock); 4891 4892 return 0; 4893 } 4894 4895 static int 4896 i915_max_freq_set(void *data, u64 val) 4897 { 4898 struct drm_device *dev = data; 4899 struct drm_i915_private *dev_priv = dev->dev_private; 4900 u32 hw_max, hw_min; 4901 int ret; 4902 4903 if (INTEL_INFO(dev)->gen < 6) 4904 return -ENODEV; 4905 4906 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4907 4908 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); 4909 4910 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4911 if (ret) 4912 return ret; 4913 4914 /* 4915 * Turbo will still be enabled, but won't go above the set value. 4916 */ 4917 val = intel_freq_opcode(dev_priv, val); 4918 4919 hw_max = dev_priv->rps.max_freq; 4920 hw_min = dev_priv->rps.min_freq; 4921 4922 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { 4923 mutex_unlock(&dev_priv->rps.hw_lock); 4924 return -EINVAL; 4925 } 4926 4927 dev_priv->rps.max_freq_softlimit = val; 4928 4929 intel_set_rps(dev, val); 4930 4931 mutex_unlock(&dev_priv->rps.hw_lock); 4932 4933 return 0; 4934 } 4935 4936 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, 4937 i915_max_freq_get, i915_max_freq_set, 4938 "%llu\n"); 4939 4940 static int 4941 i915_min_freq_get(void *data, u64 *val) 4942 { 4943 struct drm_device *dev = data; 4944 struct drm_i915_private *dev_priv = dev->dev_private; 4945 int ret; 4946 4947 if (INTEL_INFO(dev)->gen < 6) 4948 return -ENODEV; 4949 4950 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4951 4952 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4953 if (ret) 4954 return ret; 4955 4956 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); 4957 mutex_unlock(&dev_priv->rps.hw_lock); 4958 4959 return 0; 4960 } 4961 4962 static int 4963 i915_min_freq_set(void *data, u64 val) 4964 { 4965 struct drm_device *dev = data; 4966 struct drm_i915_private *dev_priv = dev->dev_private; 4967 u32 hw_max, hw_min; 4968 int ret; 4969 4970 if (INTEL_INFO(dev)->gen < 6) 4971 return -ENODEV; 4972 4973 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4974 4975 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); 4976 4977 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4978 if (ret) 4979 return ret; 4980 4981 /* 4982 * Turbo will still be enabled, but won't go below the set value. 4983 */ 4984 val = intel_freq_opcode(dev_priv, val); 4985 4986 hw_max = dev_priv->rps.max_freq; 4987 hw_min = dev_priv->rps.min_freq; 4988 4989 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { 4990 mutex_unlock(&dev_priv->rps.hw_lock); 4991 return -EINVAL; 4992 } 4993 4994 dev_priv->rps.min_freq_softlimit = val; 4995 4996 intel_set_rps(dev, val); 4997 4998 mutex_unlock(&dev_priv->rps.hw_lock); 4999 5000 return 0; 5001 } 5002 5003 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, 5004 i915_min_freq_get, i915_min_freq_set, 5005 "%llu\n"); 5006 5007 static int 5008 i915_cache_sharing_get(void *data, u64 *val) 5009 { 5010 struct drm_device *dev = data; 5011 struct drm_i915_private *dev_priv = dev->dev_private; 5012 u32 snpcr; 5013 int ret; 5014 5015 if (!(IS_GEN6(dev) || IS_GEN7(dev))) 5016 return -ENODEV; 5017 5018 ret = mutex_lock_interruptible(&dev->struct_mutex); 5019 if (ret) 5020 return ret; 5021 intel_runtime_pm_get(dev_priv); 5022 5023 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5024 5025 intel_runtime_pm_put(dev_priv); 5026 mutex_unlock(&dev_priv->dev->struct_mutex); 5027 5028 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; 5029 5030 return 0; 5031 } 5032 5033 static int 5034 i915_cache_sharing_set(void *data, u64 val) 5035 { 5036 struct drm_device *dev = data; 5037 struct drm_i915_private *dev_priv = dev->dev_private; 5038 u32 snpcr; 5039 5040 if (!(IS_GEN6(dev) || IS_GEN7(dev))) 5041 return -ENODEV; 5042 5043 if (val > 3) 5044 return -EINVAL; 5045 5046 intel_runtime_pm_get(dev_priv); 5047 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); 5048 5049 /* Update the cache sharing policy here as well */ 5050 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5051 snpcr &= ~GEN6_MBC_SNPCR_MASK; 5052 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 5053 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 5054 5055 intel_runtime_pm_put(dev_priv); 5056 return 0; 5057 } 5058 5059 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 5060 i915_cache_sharing_get, i915_cache_sharing_set, 5061 "%llu\n"); 5062 5063 struct sseu_dev_status { 5064 unsigned int slice_total; 5065 unsigned int subslice_total; 5066 unsigned int subslice_per_slice; 5067 unsigned int eu_total; 5068 unsigned int eu_per_subslice; 5069 }; 5070 5071 static void cherryview_sseu_device_status(struct drm_device *dev, 5072 struct sseu_dev_status *stat) 5073 { 5074 struct drm_i915_private *dev_priv = dev->dev_private; 5075 int ss_max = 2; 5076 int ss; 5077 u32 sig1[ss_max], sig2[ss_max]; 5078 5079 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); 5080 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); 5081 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); 5082 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); 5083 5084 for (ss = 0; ss < ss_max; ss++) { 5085 unsigned int eu_cnt; 5086 5087 if (sig1[ss] & CHV_SS_PG_ENABLE) 5088 /* skip disabled subslice */ 5089 continue; 5090 5091 stat->slice_total = 1; 5092 stat->subslice_per_slice++; 5093 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + 5094 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + 5095 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + 5096 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); 5097 stat->eu_total += eu_cnt; 5098 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); 5099 } 5100 stat->subslice_total = stat->subslice_per_slice; 5101 } 5102 5103 static void gen9_sseu_device_status(struct drm_device *dev, 5104 struct sseu_dev_status *stat) 5105 { 5106 struct drm_i915_private *dev_priv = dev->dev_private; 5107 int s_max = 3, ss_max = 4; 5108 int s, ss; 5109 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; 5110 5111 /* BXT has a single slice and at most 3 subslices. */ 5112 if (IS_BROXTON(dev)) { 5113 s_max = 1; 5114 ss_max = 3; 5115 } 5116 5117 for (s = 0; s < s_max; s++) { 5118 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); 5119 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); 5120 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); 5121 } 5122 5123 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | 5124 GEN9_PGCTL_SSA_EU19_ACK | 5125 GEN9_PGCTL_SSA_EU210_ACK | 5126 GEN9_PGCTL_SSA_EU311_ACK; 5127 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | 5128 GEN9_PGCTL_SSB_EU19_ACK | 5129 GEN9_PGCTL_SSB_EU210_ACK | 5130 GEN9_PGCTL_SSB_EU311_ACK; 5131 5132 for (s = 0; s < s_max; s++) { 5133 unsigned int ss_cnt = 0; 5134 5135 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) 5136 /* skip disabled slice */ 5137 continue; 5138 5139 stat->slice_total++; 5140 5141 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 5142 ss_cnt = INTEL_INFO(dev)->subslice_per_slice; 5143 5144 for (ss = 0; ss < ss_max; ss++) { 5145 unsigned int eu_cnt; 5146 5147 if (IS_BROXTON(dev) && 5148 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) 5149 /* skip disabled subslice */ 5150 continue; 5151 5152 if (IS_BROXTON(dev)) 5153 ss_cnt++; 5154 5155 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & 5156 eu_mask[ss%2]); 5157 stat->eu_total += eu_cnt; 5158 stat->eu_per_subslice = max(stat->eu_per_subslice, 5159 eu_cnt); 5160 } 5161 5162 stat->subslice_total += ss_cnt; 5163 stat->subslice_per_slice = max(stat->subslice_per_slice, 5164 ss_cnt); 5165 } 5166 } 5167 5168 static void broadwell_sseu_device_status(struct drm_device *dev, 5169 struct sseu_dev_status *stat) 5170 { 5171 struct drm_i915_private *dev_priv = dev->dev_private; 5172 int s; 5173 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO); 5174 5175 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); 5176 5177 if (stat->slice_total) { 5178 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; 5179 stat->subslice_total = stat->slice_total * 5180 stat->subslice_per_slice; 5181 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; 5182 stat->eu_total = stat->eu_per_subslice * stat->subslice_total; 5183 5184 /* subtract fused off EU(s) from enabled slice(s) */ 5185 for (s = 0; s < stat->slice_total; s++) { 5186 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; 5187 5188 stat->eu_total -= hweight8(subslice_7eu); 5189 } 5190 } 5191 } 5192 5193 static int i915_sseu_status(struct seq_file *m, void *unused) 5194 { 5195 struct drm_info_node *node = (struct drm_info_node *) m->private; 5196 struct drm_device *dev = node->minor->dev; 5197 struct sseu_dev_status stat; 5198 5199 if (INTEL_INFO(dev)->gen < 8) 5200 return -ENODEV; 5201 5202 seq_puts(m, "SSEU Device Info\n"); 5203 seq_printf(m, " Available Slice Total: %u\n", 5204 INTEL_INFO(dev)->slice_total); 5205 seq_printf(m, " Available Subslice Total: %u\n", 5206 INTEL_INFO(dev)->subslice_total); 5207 seq_printf(m, " Available Subslice Per Slice: %u\n", 5208 INTEL_INFO(dev)->subslice_per_slice); 5209 seq_printf(m, " Available EU Total: %u\n", 5210 INTEL_INFO(dev)->eu_total); 5211 seq_printf(m, " Available EU Per Subslice: %u\n", 5212 INTEL_INFO(dev)->eu_per_subslice); 5213 seq_printf(m, " Has Slice Power Gating: %s\n", 5214 yesno(INTEL_INFO(dev)->has_slice_pg)); 5215 seq_printf(m, " Has Subslice Power Gating: %s\n", 5216 yesno(INTEL_INFO(dev)->has_subslice_pg)); 5217 seq_printf(m, " Has EU Power Gating: %s\n", 5218 yesno(INTEL_INFO(dev)->has_eu_pg)); 5219 5220 seq_puts(m, "SSEU Device Status\n"); 5221 memset(&stat, 0, sizeof(stat)); 5222 if (IS_CHERRYVIEW(dev)) { 5223 cherryview_sseu_device_status(dev, &stat); 5224 } else if (IS_BROADWELL(dev)) { 5225 broadwell_sseu_device_status(dev, &stat); 5226 } else if (INTEL_INFO(dev)->gen >= 9) { 5227 gen9_sseu_device_status(dev, &stat); 5228 } 5229 seq_printf(m, " Enabled Slice Total: %u\n", 5230 stat.slice_total); 5231 seq_printf(m, " Enabled Subslice Total: %u\n", 5232 stat.subslice_total); 5233 seq_printf(m, " Enabled Subslice Per Slice: %u\n", 5234 stat.subslice_per_slice); 5235 seq_printf(m, " Enabled EU Total: %u\n", 5236 stat.eu_total); 5237 seq_printf(m, " Enabled EU Per Subslice: %u\n", 5238 stat.eu_per_subslice); 5239 5240 return 0; 5241 } 5242 5243 static int i915_forcewake_open(struct inode *inode, struct file *file) 5244 { 5245 struct drm_device *dev = inode->i_private; 5246 struct drm_i915_private *dev_priv = dev->dev_private; 5247 5248 if (INTEL_INFO(dev)->gen < 6) 5249 return 0; 5250 5251 intel_runtime_pm_get(dev_priv); 5252 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5253 5254 return 0; 5255 } 5256 5257 static int i915_forcewake_release(struct inode *inode, struct file *file) 5258 { 5259 struct drm_device *dev = inode->i_private; 5260 struct drm_i915_private *dev_priv = dev->dev_private; 5261 5262 if (INTEL_INFO(dev)->gen < 6) 5263 return 0; 5264 5265 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5266 intel_runtime_pm_put(dev_priv); 5267 5268 return 0; 5269 } 5270 5271 static const struct file_operations i915_forcewake_fops = { 5272 .owner = THIS_MODULE, 5273 .open = i915_forcewake_open, 5274 .release = i915_forcewake_release, 5275 }; 5276 5277 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) 5278 { 5279 struct drm_device *dev = minor->dev; 5280 struct dentry *ent; 5281 5282 ent = debugfs_create_file("i915_forcewake_user", 5283 S_IRUSR, 5284 root, dev, 5285 &i915_forcewake_fops); 5286 if (!ent) 5287 return -ENOMEM; 5288 5289 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); 5290 } 5291 5292 static int i915_debugfs_create(struct dentry *root, 5293 struct drm_minor *minor, 5294 const char *name, 5295 const struct file_operations *fops) 5296 { 5297 struct drm_device *dev = minor->dev; 5298 struct dentry *ent; 5299 5300 ent = debugfs_create_file(name, 5301 S_IRUGO | S_IWUSR, 5302 root, dev, 5303 fops); 5304 if (!ent) 5305 return -ENOMEM; 5306 5307 return drm_add_fake_info_node(minor, ent, fops); 5308 } 5309 5310 static const struct drm_info_list i915_debugfs_list[] = { 5311 {"i915_capabilities", i915_capabilities, 0}, 5312 {"i915_gem_objects", i915_gem_object_info, 0}, 5313 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 5314 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, 5315 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 5316 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 5317 {"i915_gem_stolen", i915_gem_stolen_list_info }, 5318 {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, 5319 {"i915_gem_request", i915_gem_request_info, 0}, 5320 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 5321 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 5322 {"i915_gem_interrupt", i915_interrupt_info, 0}, 5323 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, 5324 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, 5325 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, 5326 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, 5327 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, 5328 {"i915_guc_info", i915_guc_info, 0}, 5329 {"i915_guc_load_status", i915_guc_load_status_info, 0}, 5330 {"i915_guc_log_dump", i915_guc_log_dump, 0}, 5331 {"i915_frequency_info", i915_frequency_info, 0}, 5332 {"i915_hangcheck_info", i915_hangcheck_info, 0}, 5333 {"i915_drpc_info", i915_drpc_info, 0}, 5334 {"i915_emon_status", i915_emon_status, 0}, 5335 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 5336 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, 5337 {"i915_fbc_status", i915_fbc_status, 0}, 5338 {"i915_ips_status", i915_ips_status, 0}, 5339 {"i915_sr_status", i915_sr_status, 0}, 5340 {"i915_opregion", i915_opregion, 0}, 5341 {"i915_vbt", i915_vbt, 0}, 5342 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 5343 {"i915_context_status", i915_context_status, 0}, 5344 {"i915_dump_lrc", i915_dump_lrc, 0}, 5345 {"i915_execlists", i915_execlists, 0}, 5346 {"i915_forcewake_domains", i915_forcewake_domains, 0}, 5347 {"i915_swizzle_info", i915_swizzle_info, 0}, 5348 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 5349 {"i915_llc", i915_llc, 0}, 5350 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 5351 {"i915_sink_crc_eDP1", i915_sink_crc, 0}, 5352 {"i915_energy_uJ", i915_energy_uJ, 0}, 5353 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 5354 {"i915_power_domain_info", i915_power_domain_info, 0}, 5355 {"i915_dmc_info", i915_dmc_info, 0}, 5356 {"i915_display_info", i915_display_info, 0}, 5357 {"i915_semaphore_status", i915_semaphore_status, 0}, 5358 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 5359 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 5360 {"i915_wa_registers", i915_wa_registers, 0}, 5361 {"i915_ddb_info", i915_ddb_info, 0}, 5362 {"i915_sseu_status", i915_sseu_status, 0}, 5363 {"i915_drrs_status", i915_drrs_status, 0}, 5364 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 5365 }; 5366 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 5367 5368 static const struct i915_debugfs_files { 5369 const char *name; 5370 const struct file_operations *fops; 5371 } i915_debugfs_files[] = { 5372 {"i915_wedged", &i915_wedged_fops}, 5373 {"i915_max_freq", &i915_max_freq_fops}, 5374 {"i915_min_freq", &i915_min_freq_fops}, 5375 {"i915_cache_sharing", &i915_cache_sharing_fops}, 5376 {"i915_ring_stop", &i915_ring_stop_fops}, 5377 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, 5378 {"i915_ring_test_irq", &i915_ring_test_irq_fops}, 5379 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 5380 {"i915_error_state", &i915_error_state_fops}, 5381 {"i915_next_seqno", &i915_next_seqno_fops}, 5382 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, 5383 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 5384 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 5385 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 5386 {"i915_fbc_false_color", &i915_fbc_fc_fops}, 5387 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 5388 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 5389 {"i915_dp_test_active", &i915_displayport_test_active_fops} 5390 }; 5391 5392 void intel_display_crc_init(struct drm_device *dev) 5393 { 5394 struct drm_i915_private *dev_priv = dev->dev_private; 5395 enum pipe pipe; 5396 5397 for_each_pipe(dev_priv, pipe) { 5398 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 5399 5400 pipe_crc->opened = false; 5401 spin_lock_init(&pipe_crc->lock); 5402 init_waitqueue_head(&pipe_crc->wq); 5403 } 5404 } 5405 5406 int i915_debugfs_init(struct drm_minor *minor) 5407 { 5408 int ret, i; 5409 5410 ret = i915_forcewake_create(minor->debugfs_root, minor); 5411 if (ret) 5412 return ret; 5413 5414 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5415 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); 5416 if (ret) 5417 return ret; 5418 } 5419 5420 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5421 ret = i915_debugfs_create(minor->debugfs_root, minor, 5422 i915_debugfs_files[i].name, 5423 i915_debugfs_files[i].fops); 5424 if (ret) 5425 return ret; 5426 } 5427 5428 return drm_debugfs_create_files(i915_debugfs_list, 5429 I915_DEBUGFS_ENTRIES, 5430 minor->debugfs_root, minor); 5431 } 5432 5433 void i915_debugfs_cleanup(struct drm_minor *minor) 5434 { 5435 int i; 5436 5437 drm_debugfs_remove_files(i915_debugfs_list, 5438 I915_DEBUGFS_ENTRIES, minor); 5439 5440 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, 5441 1, minor); 5442 5443 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5444 struct drm_info_list *info_list = 5445 (struct drm_info_list *)&i915_pipe_crc_data[i]; 5446 5447 drm_debugfs_remove_files(info_list, 1, minor); 5448 } 5449 5450 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5451 struct drm_info_list *info_list = 5452 (struct drm_info_list *) i915_debugfs_files[i].fops; 5453 5454 drm_debugfs_remove_files(info_list, 1, minor); 5455 } 5456 } 5457 5458 struct dpcd_block { 5459 /* DPCD dump start address. */ 5460 unsigned int offset; 5461 /* DPCD dump end address, inclusive. If unset, .size will be used. */ 5462 unsigned int end; 5463 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ 5464 size_t size; 5465 /* Only valid for eDP. */ 5466 bool edp; 5467 }; 5468 5469 static const struct dpcd_block i915_dpcd_debug[] = { 5470 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, 5471 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, 5472 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, 5473 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, 5474 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, 5475 { .offset = DP_SET_POWER }, 5476 { .offset = DP_EDP_DPCD_REV }, 5477 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, 5478 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, 5479 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, 5480 }; 5481 5482 static int i915_dpcd_show(struct seq_file *m, void *data) 5483 { 5484 struct drm_connector *connector = m->private; 5485 struct intel_dp *intel_dp = 5486 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5487 uint8_t buf[16]; 5488 ssize_t err; 5489 int i; 5490 5491 if (connector->status != connector_status_connected) 5492 return -ENODEV; 5493 5494 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { 5495 const struct dpcd_block *b = &i915_dpcd_debug[i]; 5496 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); 5497 5498 if (b->edp && 5499 connector->connector_type != DRM_MODE_CONNECTOR_eDP) 5500 continue; 5501 5502 /* low tech for now */ 5503 if (WARN_ON(size > sizeof(buf))) 5504 continue; 5505 5506 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); 5507 if (err <= 0) { 5508 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", 5509 size, b->offset, err); 5510 continue; 5511 } 5512 5513 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); 5514 } 5515 5516 return 0; 5517 } 5518 5519 static int i915_dpcd_open(struct inode *inode, struct file *file) 5520 { 5521 return single_open(file, i915_dpcd_show, inode->i_private); 5522 } 5523 5524 static const struct file_operations i915_dpcd_fops = { 5525 .owner = THIS_MODULE, 5526 .open = i915_dpcd_open, 5527 .read = seq_read, 5528 .llseek = seq_lseek, 5529 .release = single_release, 5530 }; 5531 5532 /** 5533 * i915_debugfs_connector_add - add i915 specific connector debugfs files 5534 * @connector: pointer to a registered drm_connector 5535 * 5536 * Cleanup will be done by drm_connector_unregister() through a call to 5537 * drm_debugfs_connector_remove(). 5538 * 5539 * Returns 0 on success, negative error codes on error. 5540 */ 5541 int i915_debugfs_connector_add(struct drm_connector *connector) 5542 { 5543 struct dentry *root = connector->debugfs_entry; 5544 5545 /* The connector must have been registered beforehands. */ 5546 if (!root) 5547 return -ENODEV; 5548 5549 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5550 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5551 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, 5552 &i915_dpcd_fops); 5553 5554 return 0; 5555 } 5556