1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 32 #include <drm/drm_debugfs.h> 33 34 #include "gem/i915_gem_context.h" 35 #include "gt/intel_gt_buffer_pool.h" 36 #include "gt/intel_gt_clock_utils.h" 37 #include "gt/intel_gt.h" 38 #include "gt/intel_gt_pm.h" 39 #include "gt/intel_gt_requests.h" 40 #include "gt/intel_reset.h" 41 #include "gt/intel_rc6.h" 42 #include "gt/intel_rps.h" 43 #include "gt/intel_sseu_debugfs.h" 44 45 #include "i915_debugfs.h" 46 #include "i915_debugfs_params.h" 47 #include "i915_irq.h" 48 #include "i915_scheduler.h" 49 #include "i915_trace.h" 50 #include "intel_pm.h" 51 #include "intel_sideband.h" 52 53 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 54 { 55 return to_i915(node->minor->dev); 56 } 57 58 static int i915_capabilities(struct seq_file *m, void *data) 59 { 60 struct drm_i915_private *i915 = node_to_i915(m->private); 61 struct drm_printer p = drm_seq_file_printer(m); 62 63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 64 65 intel_device_info_print_static(INTEL_INFO(i915), &p); 66 intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); 67 intel_gt_info_print(&i915->gt.info, &p); 68 intel_driver_caps_print(&i915->caps, &p); 69 70 kernel_param_lock(THIS_MODULE); 71 i915_params_dump(&i915->params, &p); 72 kernel_param_unlock(THIS_MODULE); 73 74 return 0; 75 } 76 77 static char get_tiling_flag(struct drm_i915_gem_object *obj) 78 { 79 switch (i915_gem_object_get_tiling(obj)) { 80 default: 81 case I915_TILING_NONE: return ' '; 82 case I915_TILING_X: return 'X'; 83 case I915_TILING_Y: return 'Y'; 84 } 85 } 86 87 static char get_global_flag(struct drm_i915_gem_object *obj) 88 { 89 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 90 } 91 92 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 93 { 94 return obj->mm.mapping ? 'M' : ' '; 95 } 96 97 static const char * 98 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 99 { 100 size_t x = 0; 101 102 switch (page_sizes) { 103 case 0: 104 return ""; 105 case I915_GTT_PAGE_SIZE_4K: 106 return "4K"; 107 case I915_GTT_PAGE_SIZE_64K: 108 return "64K"; 109 case I915_GTT_PAGE_SIZE_2M: 110 return "2M"; 111 default: 112 if (!buf) 113 return "M"; 114 115 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 116 x += snprintf(buf + x, len - x, "2M, "); 117 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 118 x += snprintf(buf + x, len - x, "64K, "); 119 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 120 x += snprintf(buf + x, len - x, "4K, "); 121 buf[x-2] = '\0'; 122 123 return buf; 124 } 125 } 126 127 void 128 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 129 { 130 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 131 struct intel_engine_cs *engine; 132 struct i915_vma *vma; 133 int pin_count = 0; 134 135 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 136 &obj->base, 137 get_tiling_flag(obj), 138 get_global_flag(obj), 139 get_pin_mapped_flag(obj), 140 obj->base.size / 1024, 141 obj->read_domains, 142 obj->write_domain, 143 i915_cache_level_str(dev_priv, obj->cache_level), 144 obj->mm.dirty ? " dirty" : "", 145 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 146 if (obj->base.name) 147 seq_printf(m, " (name: %d)", obj->base.name); 148 149 spin_lock(&obj->vma.lock); 150 list_for_each_entry(vma, &obj->vma.list, obj_link) { 151 if (!drm_mm_node_allocated(&vma->node)) 152 continue; 153 154 spin_unlock(&obj->vma.lock); 155 156 if (i915_vma_is_pinned(vma)) 157 pin_count++; 158 159 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", 160 i915_vma_is_ggtt(vma) ? "g" : "pp", 161 vma->node.start, vma->node.size, 162 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); 163 if (i915_vma_is_ggtt(vma)) { 164 switch (vma->ggtt_view.type) { 165 case I915_GGTT_VIEW_NORMAL: 166 seq_puts(m, ", normal"); 167 break; 168 169 case I915_GGTT_VIEW_PARTIAL: 170 seq_printf(m, ", partial [%08llx+%x]", 171 vma->ggtt_view.partial.offset << PAGE_SHIFT, 172 vma->ggtt_view.partial.size << PAGE_SHIFT); 173 break; 174 175 case I915_GGTT_VIEW_ROTATED: 176 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", 177 vma->ggtt_view.rotated.plane[0].width, 178 vma->ggtt_view.rotated.plane[0].height, 179 vma->ggtt_view.rotated.plane[0].stride, 180 vma->ggtt_view.rotated.plane[0].offset, 181 vma->ggtt_view.rotated.plane[1].width, 182 vma->ggtt_view.rotated.plane[1].height, 183 vma->ggtt_view.rotated.plane[1].stride, 184 vma->ggtt_view.rotated.plane[1].offset); 185 break; 186 187 case I915_GGTT_VIEW_REMAPPED: 188 seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", 189 vma->ggtt_view.remapped.plane[0].width, 190 vma->ggtt_view.remapped.plane[0].height, 191 vma->ggtt_view.remapped.plane[0].stride, 192 vma->ggtt_view.remapped.plane[0].offset, 193 vma->ggtt_view.remapped.plane[1].width, 194 vma->ggtt_view.remapped.plane[1].height, 195 vma->ggtt_view.remapped.plane[1].stride, 196 vma->ggtt_view.remapped.plane[1].offset); 197 break; 198 199 default: 200 MISSING_CASE(vma->ggtt_view.type); 201 break; 202 } 203 } 204 if (vma->fence) 205 seq_printf(m, " , fence: %d", vma->fence->id); 206 seq_puts(m, ")"); 207 208 spin_lock(&obj->vma.lock); 209 } 210 spin_unlock(&obj->vma.lock); 211 212 seq_printf(m, " (pinned x %d)", pin_count); 213 if (obj->stolen) 214 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 215 if (i915_gem_object_is_framebuffer(obj)) 216 seq_printf(m, " (fb)"); 217 218 engine = i915_gem_object_last_write_engine(obj); 219 if (engine) 220 seq_printf(m, " (%s)", engine->name); 221 } 222 223 struct file_stats { 224 struct i915_address_space *vm; 225 unsigned long count; 226 u64 total; 227 u64 active, inactive; 228 u64 closed; 229 }; 230 231 static int per_file_stats(int id, void *ptr, void *data) 232 { 233 struct drm_i915_gem_object *obj = ptr; 234 struct file_stats *stats = data; 235 struct i915_vma *vma; 236 237 if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount)) 238 return 0; 239 240 stats->count++; 241 stats->total += obj->base.size; 242 243 spin_lock(&obj->vma.lock); 244 if (!stats->vm) { 245 for_each_ggtt_vma(vma, obj) { 246 if (!drm_mm_node_allocated(&vma->node)) 247 continue; 248 249 if (i915_vma_is_active(vma)) 250 stats->active += vma->node.size; 251 else 252 stats->inactive += vma->node.size; 253 254 if (i915_vma_is_closed(vma)) 255 stats->closed += vma->node.size; 256 } 257 } else { 258 struct rb_node *p = obj->vma.tree.rb_node; 259 260 while (p) { 261 long cmp; 262 263 vma = rb_entry(p, typeof(*vma), obj_node); 264 cmp = i915_vma_compare(vma, stats->vm, NULL); 265 if (cmp == 0) { 266 if (drm_mm_node_allocated(&vma->node)) { 267 if (i915_vma_is_active(vma)) 268 stats->active += vma->node.size; 269 else 270 stats->inactive += vma->node.size; 271 272 if (i915_vma_is_closed(vma)) 273 stats->closed += vma->node.size; 274 } 275 break; 276 } 277 if (cmp < 0) 278 p = p->rb_right; 279 else 280 p = p->rb_left; 281 } 282 } 283 spin_unlock(&obj->vma.lock); 284 285 i915_gem_object_put(obj); 286 return 0; 287 } 288 289 #define print_file_stats(m, name, stats) do { \ 290 if (stats.count) \ 291 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu closed)\n", \ 292 name, \ 293 stats.count, \ 294 stats.total, \ 295 stats.active, \ 296 stats.inactive, \ 297 stats.closed); \ 298 } while (0) 299 300 static void print_context_stats(struct seq_file *m, 301 struct drm_i915_private *i915) 302 { 303 struct file_stats kstats = {}; 304 struct i915_gem_context *ctx, *cn; 305 306 spin_lock(&i915->gem.contexts.lock); 307 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) { 308 struct i915_gem_engines_iter it; 309 struct intel_context *ce; 310 311 if (!kref_get_unless_zero(&ctx->ref)) 312 continue; 313 314 spin_unlock(&i915->gem.contexts.lock); 315 316 for_each_gem_engine(ce, 317 i915_gem_context_lock_engines(ctx), it) { 318 if (intel_context_pin_if_active(ce)) { 319 rcu_read_lock(); 320 if (ce->state) 321 per_file_stats(0, 322 ce->state->obj, &kstats); 323 per_file_stats(0, ce->ring->vma->obj, &kstats); 324 rcu_read_unlock(); 325 intel_context_unpin(ce); 326 } 327 } 328 i915_gem_context_unlock_engines(ctx); 329 330 mutex_lock(&ctx->mutex); 331 if (!IS_ERR_OR_NULL(ctx->file_priv)) { 332 struct file_stats stats = { 333 .vm = rcu_access_pointer(ctx->vm), 334 }; 335 struct drm_file *file = ctx->file_priv->file; 336 struct task_struct *task; 337 char name[80]; 338 339 rcu_read_lock(); 340 idr_for_each(&file->object_idr, per_file_stats, &stats); 341 rcu_read_unlock(); 342 343 rcu_read_lock(); 344 task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID); 345 snprintf(name, sizeof(name), "%s", 346 task ? task->comm : "<unknown>"); 347 rcu_read_unlock(); 348 349 print_file_stats(m, name, stats); 350 } 351 mutex_unlock(&ctx->mutex); 352 353 spin_lock(&i915->gem.contexts.lock); 354 list_safe_reset_next(ctx, cn, link); 355 i915_gem_context_put(ctx); 356 } 357 spin_unlock(&i915->gem.contexts.lock); 358 359 print_file_stats(m, "[k]contexts", kstats); 360 } 361 362 static int i915_gem_object_info(struct seq_file *m, void *data) 363 { 364 struct drm_i915_private *i915 = node_to_i915(m->private); 365 struct intel_memory_region *mr; 366 enum intel_region_id id; 367 368 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 369 i915->mm.shrink_count, 370 atomic_read(&i915->mm.free_count), 371 i915->mm.shrink_memory); 372 for_each_memory_region(mr, i915, id) 373 seq_printf(m, "%s: total:%pa, available:%pa bytes\n", 374 mr->name, &mr->total, &mr->avail); 375 seq_putc(m, '\n'); 376 377 print_context_stats(m, i915); 378 379 return 0; 380 } 381 382 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 383 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 384 size_t count, loff_t *pos) 385 { 386 struct i915_gpu_coredump *error; 387 ssize_t ret; 388 void *buf; 389 390 error = file->private_data; 391 if (!error) 392 return 0; 393 394 /* Bounce buffer required because of kernfs __user API convenience. */ 395 buf = kmalloc(count, GFP_KERNEL); 396 if (!buf) 397 return -ENOMEM; 398 399 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 400 if (ret <= 0) 401 goto out; 402 403 if (!copy_to_user(ubuf, buf, ret)) 404 *pos += ret; 405 else 406 ret = -EFAULT; 407 408 out: 409 kfree(buf); 410 return ret; 411 } 412 413 static int gpu_state_release(struct inode *inode, struct file *file) 414 { 415 i915_gpu_coredump_put(file->private_data); 416 return 0; 417 } 418 419 static int i915_gpu_info_open(struct inode *inode, struct file *file) 420 { 421 struct drm_i915_private *i915 = inode->i_private; 422 struct i915_gpu_coredump *gpu; 423 intel_wakeref_t wakeref; 424 425 gpu = NULL; 426 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 427 gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES); 428 if (IS_ERR(gpu)) 429 return PTR_ERR(gpu); 430 431 file->private_data = gpu; 432 return 0; 433 } 434 435 static const struct file_operations i915_gpu_info_fops = { 436 .owner = THIS_MODULE, 437 .open = i915_gpu_info_open, 438 .read = gpu_state_read, 439 .llseek = default_llseek, 440 .release = gpu_state_release, 441 }; 442 443 static ssize_t 444 i915_error_state_write(struct file *filp, 445 const char __user *ubuf, 446 size_t cnt, 447 loff_t *ppos) 448 { 449 struct i915_gpu_coredump *error = filp->private_data; 450 451 if (!error) 452 return 0; 453 454 drm_dbg(&error->i915->drm, "Resetting error state\n"); 455 i915_reset_error_state(error->i915); 456 457 return cnt; 458 } 459 460 static int i915_error_state_open(struct inode *inode, struct file *file) 461 { 462 struct i915_gpu_coredump *error; 463 464 error = i915_first_error_state(inode->i_private); 465 if (IS_ERR(error)) 466 return PTR_ERR(error); 467 468 file->private_data = error; 469 return 0; 470 } 471 472 static const struct file_operations i915_error_state_fops = { 473 .owner = THIS_MODULE, 474 .open = i915_error_state_open, 475 .read = gpu_state_read, 476 .write = i915_error_state_write, 477 .llseek = default_llseek, 478 .release = gpu_state_release, 479 }; 480 #endif 481 482 static int i915_frequency_info(struct seq_file *m, void *unused) 483 { 484 struct drm_i915_private *dev_priv = node_to_i915(m->private); 485 struct intel_uncore *uncore = &dev_priv->uncore; 486 struct intel_rps *rps = &dev_priv->gt.rps; 487 intel_wakeref_t wakeref; 488 489 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 490 491 if (IS_GEN(dev_priv, 5)) { 492 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 493 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 494 495 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 496 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 497 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 498 MEMSTAT_VID_SHIFT); 499 seq_printf(m, "Current P-state: %d\n", 500 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 501 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 502 u32 rpmodectl, freq_sts; 503 504 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); 505 seq_printf(m, "Video Turbo Mode: %s\n", 506 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 507 seq_printf(m, "HW control enabled: %s\n", 508 yesno(rpmodectl & GEN6_RP_ENABLE)); 509 seq_printf(m, "SW control enabled: %s\n", 510 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 511 GEN6_RP_MEDIA_SW_MODE)); 512 513 vlv_punit_get(dev_priv); 514 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 515 vlv_punit_put(dev_priv); 516 517 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 518 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 519 520 seq_printf(m, "actual GPU freq: %d MHz\n", 521 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 522 523 seq_printf(m, "current GPU freq: %d MHz\n", 524 intel_gpu_freq(rps, rps->cur_freq)); 525 526 seq_printf(m, "max GPU freq: %d MHz\n", 527 intel_gpu_freq(rps, rps->max_freq)); 528 529 seq_printf(m, "min GPU freq: %d MHz\n", 530 intel_gpu_freq(rps, rps->min_freq)); 531 532 seq_printf(m, "idle GPU freq: %d MHz\n", 533 intel_gpu_freq(rps, rps->idle_freq)); 534 535 seq_printf(m, 536 "efficient (RPe) frequency: %d MHz\n", 537 intel_gpu_freq(rps, rps->efficient_freq)); 538 } else if (INTEL_GEN(dev_priv) >= 6) { 539 u32 rp_state_limits; 540 u32 gt_perf_status; 541 u32 rp_state_cap; 542 u32 rpmodectl, rpinclimit, rpdeclimit; 543 u32 rpstat, cagf, reqf; 544 u32 rpupei, rpcurup, rpprevup; 545 u32 rpdownei, rpcurdown, rpprevdown; 546 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 547 int max_freq; 548 549 rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS); 550 if (IS_GEN9_LP(dev_priv)) { 551 rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP); 552 gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS); 553 } else { 554 rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP); 555 gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS); 556 } 557 558 /* RPSTAT1 is in the GT power well */ 559 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 560 561 reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ); 562 if (INTEL_GEN(dev_priv) >= 9) 563 reqf >>= 23; 564 else { 565 reqf &= ~GEN6_TURBO_DISABLE; 566 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 567 reqf >>= 24; 568 else 569 reqf >>= 25; 570 } 571 reqf = intel_gpu_freq(rps, reqf); 572 573 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); 574 rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD); 575 rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD); 576 577 rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1); 578 rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 579 rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 580 rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 581 rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 582 rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 583 rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 584 cagf = intel_rps_read_actual_frequency(rps); 585 586 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 587 588 if (INTEL_GEN(dev_priv) >= 11) { 589 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 590 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 591 /* 592 * The equivalent to the PM ISR & IIR cannot be read 593 * without affecting the current state of the system 594 */ 595 pm_isr = 0; 596 pm_iir = 0; 597 } else if (INTEL_GEN(dev_priv) >= 8) { 598 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2)); 599 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2)); 600 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2)); 601 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2)); 602 } else { 603 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER); 604 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR); 605 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR); 606 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 607 } 608 pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK); 609 610 seq_printf(m, "Video Turbo Mode: %s\n", 611 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 612 seq_printf(m, "HW control enabled: %s\n", 613 yesno(rpmodectl & GEN6_RP_ENABLE)); 614 seq_printf(m, "SW control enabled: %s\n", 615 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 616 GEN6_RP_MEDIA_SW_MODE)); 617 618 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 619 pm_ier, pm_imr, pm_mask); 620 if (INTEL_GEN(dev_priv) <= 10) 621 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", 622 pm_isr, pm_iir); 623 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", 624 rps->pm_intrmsk_mbz); 625 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 626 seq_printf(m, "Render p-state ratio: %d\n", 627 (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 628 seq_printf(m, "Render p-state VID: %d\n", 629 gt_perf_status & 0xff); 630 seq_printf(m, "Render p-state limit: %d\n", 631 rp_state_limits & 0xff); 632 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 633 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 634 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 635 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 636 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 637 seq_printf(m, "CAGF: %dMHz\n", cagf); 638 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", 639 rpupei, 640 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); 641 seq_printf(m, "RP CUR UP: %d (%lldun)\n", 642 rpcurup, 643 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); 644 seq_printf(m, "RP PREV UP: %d (%lldns)\n", 645 rpprevup, 646 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); 647 seq_printf(m, "Up threshold: %d%%\n", 648 rps->power.up_threshold); 649 650 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", 651 rpdownei, 652 intel_gt_pm_interval_to_ns(&dev_priv->gt, 653 rpdownei)); 654 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", 655 rpcurdown, 656 intel_gt_pm_interval_to_ns(&dev_priv->gt, 657 rpcurdown)); 658 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", 659 rpprevdown, 660 intel_gt_pm_interval_to_ns(&dev_priv->gt, 661 rpprevdown)); 662 seq_printf(m, "Down threshold: %d%%\n", 663 rps->power.down_threshold); 664 665 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : 666 rp_state_cap >> 16) & 0xff; 667 max_freq *= (IS_GEN9_BC(dev_priv) || 668 INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 669 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 670 intel_gpu_freq(rps, max_freq)); 671 672 max_freq = (rp_state_cap & 0xff00) >> 8; 673 max_freq *= (IS_GEN9_BC(dev_priv) || 674 INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 675 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 676 intel_gpu_freq(rps, max_freq)); 677 678 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : 679 rp_state_cap >> 0) & 0xff; 680 max_freq *= (IS_GEN9_BC(dev_priv) || 681 INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 682 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 683 intel_gpu_freq(rps, max_freq)); 684 seq_printf(m, "Max overclocked frequency: %dMHz\n", 685 intel_gpu_freq(rps, rps->max_freq)); 686 687 seq_printf(m, "Current freq: %d MHz\n", 688 intel_gpu_freq(rps, rps->cur_freq)); 689 seq_printf(m, "Actual freq: %d MHz\n", cagf); 690 seq_printf(m, "Idle freq: %d MHz\n", 691 intel_gpu_freq(rps, rps->idle_freq)); 692 seq_printf(m, "Min freq: %d MHz\n", 693 intel_gpu_freq(rps, rps->min_freq)); 694 seq_printf(m, "Boost freq: %d MHz\n", 695 intel_gpu_freq(rps, rps->boost_freq)); 696 seq_printf(m, "Max freq: %d MHz\n", 697 intel_gpu_freq(rps, rps->max_freq)); 698 seq_printf(m, 699 "efficient (RPe) frequency: %d MHz\n", 700 intel_gpu_freq(rps, rps->efficient_freq)); 701 } else { 702 seq_puts(m, "no P-state info available\n"); 703 } 704 705 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); 706 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); 707 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); 708 709 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 710 return 0; 711 } 712 713 static const char *swizzle_string(unsigned swizzle) 714 { 715 switch (swizzle) { 716 case I915_BIT_6_SWIZZLE_NONE: 717 return "none"; 718 case I915_BIT_6_SWIZZLE_9: 719 return "bit9"; 720 case I915_BIT_6_SWIZZLE_9_10: 721 return "bit9/bit10"; 722 case I915_BIT_6_SWIZZLE_9_11: 723 return "bit9/bit11"; 724 case I915_BIT_6_SWIZZLE_9_10_11: 725 return "bit9/bit10/bit11"; 726 case I915_BIT_6_SWIZZLE_9_17: 727 return "bit9/bit17"; 728 case I915_BIT_6_SWIZZLE_9_10_17: 729 return "bit9/bit10/bit17"; 730 case I915_BIT_6_SWIZZLE_UNKNOWN: 731 return "unknown"; 732 } 733 734 return "bug"; 735 } 736 737 static int i915_swizzle_info(struct seq_file *m, void *data) 738 { 739 struct drm_i915_private *dev_priv = node_to_i915(m->private); 740 struct intel_uncore *uncore = &dev_priv->uncore; 741 intel_wakeref_t wakeref; 742 743 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 744 swizzle_string(dev_priv->ggtt.bit_6_swizzle_x)); 745 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 746 swizzle_string(dev_priv->ggtt.bit_6_swizzle_y)); 747 748 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 749 seq_puts(m, "L-shaped memory detected\n"); 750 751 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 752 if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 753 return 0; 754 755 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 756 757 if (IS_GEN_RANGE(dev_priv, 3, 4)) { 758 seq_printf(m, "DDC = 0x%08x\n", 759 intel_uncore_read(uncore, DCC)); 760 seq_printf(m, "DDC2 = 0x%08x\n", 761 intel_uncore_read(uncore, DCC2)); 762 seq_printf(m, "C0DRB3 = 0x%04x\n", 763 intel_uncore_read16(uncore, C0DRB3)); 764 seq_printf(m, "C1DRB3 = 0x%04x\n", 765 intel_uncore_read16(uncore, C1DRB3)); 766 } else if (INTEL_GEN(dev_priv) >= 6) { 767 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 768 intel_uncore_read(uncore, MAD_DIMM_C0)); 769 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 770 intel_uncore_read(uncore, MAD_DIMM_C1)); 771 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 772 intel_uncore_read(uncore, MAD_DIMM_C2)); 773 seq_printf(m, "TILECTL = 0x%08x\n", 774 intel_uncore_read(uncore, TILECTL)); 775 if (INTEL_GEN(dev_priv) >= 8) 776 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 777 intel_uncore_read(uncore, GAMTARBMODE)); 778 else 779 seq_printf(m, "ARB_MODE = 0x%08x\n", 780 intel_uncore_read(uncore, ARB_MODE)); 781 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 782 intel_uncore_read(uncore, DISP_ARB_CTL)); 783 } 784 785 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 786 787 return 0; 788 } 789 790 static int i915_rps_boost_info(struct seq_file *m, void *data) 791 { 792 struct drm_i915_private *dev_priv = node_to_i915(m->private); 793 struct intel_rps *rps = &dev_priv->gt.rps; 794 795 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 796 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 797 seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake)); 798 seq_printf(m, "Boosts outstanding? %d\n", 799 atomic_read(&rps->num_waiters)); 800 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 801 seq_printf(m, "Frequency requested %d, actual %d\n", 802 intel_gpu_freq(rps, rps->cur_freq), 803 intel_rps_read_actual_frequency(rps)); 804 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 805 intel_gpu_freq(rps, rps->min_freq), 806 intel_gpu_freq(rps, rps->min_freq_softlimit), 807 intel_gpu_freq(rps, rps->max_freq_softlimit), 808 intel_gpu_freq(rps, rps->max_freq)); 809 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 810 intel_gpu_freq(rps, rps->idle_freq), 811 intel_gpu_freq(rps, rps->efficient_freq), 812 intel_gpu_freq(rps, rps->boost_freq)); 813 814 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 815 816 return 0; 817 } 818 819 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 820 { 821 struct drm_i915_private *dev_priv = node_to_i915(m->private); 822 struct pci_dev *pdev = dev_priv->drm.pdev; 823 824 if (!HAS_RUNTIME_PM(dev_priv)) 825 seq_puts(m, "Runtime power management not supported\n"); 826 827 seq_printf(m, "Runtime power status: %s\n", 828 enableddisabled(!dev_priv->power_domains.init_wakeref)); 829 830 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); 831 seq_printf(m, "IRQs disabled: %s\n", 832 yesno(!intel_irqs_enabled(dev_priv))); 833 #ifdef CONFIG_PM 834 seq_printf(m, "Usage count: %d\n", 835 atomic_read(&dev_priv->drm.dev->power.usage_count)); 836 #else 837 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 838 #endif 839 seq_printf(m, "PCI device power state: %s [%d]\n", 840 pci_power_name(pdev->current_state), 841 pdev->current_state); 842 843 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 844 struct drm_printer p = drm_seq_file_printer(m); 845 846 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 847 } 848 849 return 0; 850 } 851 852 static int i915_engine_info(struct seq_file *m, void *unused) 853 { 854 struct drm_i915_private *i915 = node_to_i915(m->private); 855 struct intel_engine_cs *engine; 856 intel_wakeref_t wakeref; 857 struct drm_printer p; 858 859 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 860 861 seq_printf(m, "GT awake? %s [%d], %llums\n", 862 yesno(i915->gt.awake), 863 atomic_read(&i915->gt.wakeref.count), 864 ktime_to_ms(intel_gt_get_awake_time(&i915->gt))); 865 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 866 i915->gt.clock_frequency, 867 i915->gt.clock_period_ns); 868 869 p = drm_seq_file_printer(m); 870 for_each_uabi_engine(engine, i915) 871 intel_engine_dump(engine, &p, "%s\n", engine->name); 872 873 intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule); 874 875 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 876 877 return 0; 878 } 879 880 static int i915_wa_registers(struct seq_file *m, void *unused) 881 { 882 struct drm_i915_private *i915 = node_to_i915(m->private); 883 struct intel_engine_cs *engine; 884 885 for_each_uabi_engine(engine, i915) { 886 const struct i915_wa_list *wal = &engine->ctx_wa_list; 887 const struct i915_wa *wa; 888 unsigned int count; 889 890 count = wal->count; 891 if (!count) 892 continue; 893 894 seq_printf(m, "%s: Workarounds applied: %u\n", 895 engine->name, count); 896 897 for (wa = wal->list; count--; wa++) 898 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 899 i915_mmio_reg_offset(wa->reg), 900 wa->set, wa->clr); 901 902 seq_printf(m, "\n"); 903 } 904 905 return 0; 906 } 907 908 static int 909 i915_wedged_get(void *data, u64 *val) 910 { 911 struct drm_i915_private *i915 = data; 912 int ret = intel_gt_terminally_wedged(&i915->gt); 913 914 switch (ret) { 915 case -EIO: 916 *val = 1; 917 return 0; 918 case 0: 919 *val = 0; 920 return 0; 921 default: 922 return ret; 923 } 924 } 925 926 static int 927 i915_wedged_set(void *data, u64 val) 928 { 929 struct drm_i915_private *i915 = data; 930 931 /* Flush any previous reset before applying for a new one */ 932 wait_event(i915->gt.reset.queue, 933 !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags)); 934 935 intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE, 936 "Manually set wedged engine mask = %llx", val); 937 return 0; 938 } 939 940 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 941 i915_wedged_get, i915_wedged_set, 942 "%llu\n"); 943 944 static int 945 i915_perf_noa_delay_set(void *data, u64 val) 946 { 947 struct drm_i915_private *i915 = data; 948 949 /* 950 * This would lead to infinite waits as we're doing timestamp 951 * difference on the CS with only 32bits. 952 */ 953 if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX) 954 return -EINVAL; 955 956 atomic64_set(&i915->perf.noa_programming_delay, val); 957 return 0; 958 } 959 960 static int 961 i915_perf_noa_delay_get(void *data, u64 *val) 962 { 963 struct drm_i915_private *i915 = data; 964 965 *val = atomic64_read(&i915->perf.noa_programming_delay); 966 return 0; 967 } 968 969 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 970 i915_perf_noa_delay_get, 971 i915_perf_noa_delay_set, 972 "%llu\n"); 973 974 #define DROP_UNBOUND BIT(0) 975 #define DROP_BOUND BIT(1) 976 #define DROP_RETIRE BIT(2) 977 #define DROP_ACTIVE BIT(3) 978 #define DROP_FREED BIT(4) 979 #define DROP_SHRINK_ALL BIT(5) 980 #define DROP_IDLE BIT(6) 981 #define DROP_RESET_ACTIVE BIT(7) 982 #define DROP_RESET_SEQNO BIT(8) 983 #define DROP_RCU BIT(9) 984 #define DROP_ALL (DROP_UNBOUND | \ 985 DROP_BOUND | \ 986 DROP_RETIRE | \ 987 DROP_ACTIVE | \ 988 DROP_FREED | \ 989 DROP_SHRINK_ALL |\ 990 DROP_IDLE | \ 991 DROP_RESET_ACTIVE | \ 992 DROP_RESET_SEQNO | \ 993 DROP_RCU) 994 static int 995 i915_drop_caches_get(void *data, u64 *val) 996 { 997 *val = DROP_ALL; 998 999 return 0; 1000 } 1001 static int 1002 gt_drop_caches(struct intel_gt *gt, u64 val) 1003 { 1004 int ret; 1005 1006 if (val & DROP_RESET_ACTIVE && 1007 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) 1008 intel_gt_set_wedged(gt); 1009 1010 if (val & DROP_RETIRE) 1011 intel_gt_retire_requests(gt); 1012 1013 if (val & (DROP_IDLE | DROP_ACTIVE)) { 1014 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 1015 if (ret) 1016 return ret; 1017 } 1018 1019 if (val & DROP_IDLE) { 1020 ret = intel_gt_pm_wait_for_idle(gt); 1021 if (ret) 1022 return ret; 1023 } 1024 1025 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 1026 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 1027 1028 if (val & DROP_FREED) 1029 intel_gt_flush_buffer_pool(gt); 1030 1031 return 0; 1032 } 1033 1034 static int 1035 i915_drop_caches_set(void *data, u64 val) 1036 { 1037 struct drm_i915_private *i915 = data; 1038 int ret; 1039 1040 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", 1041 val, val & DROP_ALL); 1042 1043 ret = gt_drop_caches(&i915->gt, val); 1044 if (ret) 1045 return ret; 1046 1047 fs_reclaim_acquire(GFP_KERNEL); 1048 if (val & DROP_BOUND) 1049 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 1050 1051 if (val & DROP_UNBOUND) 1052 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 1053 1054 if (val & DROP_SHRINK_ALL) 1055 i915_gem_shrink_all(i915); 1056 fs_reclaim_release(GFP_KERNEL); 1057 1058 if (val & DROP_RCU) 1059 rcu_barrier(); 1060 1061 if (val & DROP_FREED) 1062 i915_gem_drain_freed_objects(i915); 1063 1064 return 0; 1065 } 1066 1067 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 1068 i915_drop_caches_get, i915_drop_caches_set, 1069 "0x%08llx\n"); 1070 1071 static int i915_sseu_status(struct seq_file *m, void *unused) 1072 { 1073 struct drm_i915_private *i915 = node_to_i915(m->private); 1074 struct intel_gt *gt = &i915->gt; 1075 1076 return intel_sseu_status(m, gt); 1077 } 1078 1079 static int i915_forcewake_open(struct inode *inode, struct file *file) 1080 { 1081 struct drm_i915_private *i915 = inode->i_private; 1082 struct intel_gt *gt = &i915->gt; 1083 1084 atomic_inc(>->user_wakeref); 1085 intel_gt_pm_get(gt); 1086 if (INTEL_GEN(i915) >= 6) 1087 intel_uncore_forcewake_user_get(gt->uncore); 1088 1089 return 0; 1090 } 1091 1092 static int i915_forcewake_release(struct inode *inode, struct file *file) 1093 { 1094 struct drm_i915_private *i915 = inode->i_private; 1095 struct intel_gt *gt = &i915->gt; 1096 1097 if (INTEL_GEN(i915) >= 6) 1098 intel_uncore_forcewake_user_put(&i915->uncore); 1099 intel_gt_pm_put(gt); 1100 atomic_dec(>->user_wakeref); 1101 1102 return 0; 1103 } 1104 1105 static const struct file_operations i915_forcewake_fops = { 1106 .owner = THIS_MODULE, 1107 .open = i915_forcewake_open, 1108 .release = i915_forcewake_release, 1109 }; 1110 1111 static const struct drm_info_list i915_debugfs_list[] = { 1112 {"i915_capabilities", i915_capabilities, 0}, 1113 {"i915_gem_objects", i915_gem_object_info, 0}, 1114 {"i915_frequency_info", i915_frequency_info, 0}, 1115 {"i915_swizzle_info", i915_swizzle_info, 0}, 1116 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 1117 {"i915_engine_info", i915_engine_info, 0}, 1118 {"i915_wa_registers", i915_wa_registers, 0}, 1119 {"i915_sseu_status", i915_sseu_status, 0}, 1120 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 1121 }; 1122 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 1123 1124 static const struct i915_debugfs_files { 1125 const char *name; 1126 const struct file_operations *fops; 1127 } i915_debugfs_files[] = { 1128 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 1129 {"i915_wedged", &i915_wedged_fops}, 1130 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 1131 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1132 {"i915_error_state", &i915_error_state_fops}, 1133 {"i915_gpu_info", &i915_gpu_info_fops}, 1134 #endif 1135 }; 1136 1137 void i915_debugfs_register(struct drm_i915_private *dev_priv) 1138 { 1139 struct drm_minor *minor = dev_priv->drm.primary; 1140 int i; 1141 1142 i915_debugfs_params(dev_priv); 1143 1144 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 1145 to_i915(minor->dev), &i915_forcewake_fops); 1146 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 1147 debugfs_create_file(i915_debugfs_files[i].name, 1148 S_IRUGO | S_IWUSR, 1149 minor->debugfs_root, 1150 to_i915(minor->dev), 1151 i915_debugfs_files[i].fops); 1152 } 1153 1154 drm_debugfs_create_files(i915_debugfs_list, 1155 I915_DEBUGFS_ENTRIES, 1156 minor->debugfs_root, minor); 1157 } 1158