1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 32 #include <drm/drm_debugfs.h> 33 34 #include "gem/i915_gem_context.h" 35 #include "gt/intel_gt_buffer_pool.h" 36 #include "gt/intel_gt_clock_utils.h" 37 #include "gt/intel_gt.h" 38 #include "gt/intel_gt_pm.h" 39 #include "gt/intel_gt_requests.h" 40 #include "gt/intel_reset.h" 41 #include "gt/intel_rc6.h" 42 #include "gt/intel_rps.h" 43 #include "gt/intel_sseu_debugfs.h" 44 45 #include "i915_debugfs.h" 46 #include "i915_debugfs_params.h" 47 #include "i915_irq.h" 48 #include "i915_scheduler.h" 49 #include "i915_trace.h" 50 #include "intel_pm.h" 51 #include "intel_sideband.h" 52 53 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 54 { 55 return to_i915(node->minor->dev); 56 } 57 58 static int i915_capabilities(struct seq_file *m, void *data) 59 { 60 struct drm_i915_private *i915 = node_to_i915(m->private); 61 struct drm_printer p = drm_seq_file_printer(m); 62 63 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 64 65 intel_device_info_print_static(INTEL_INFO(i915), &p); 66 intel_device_info_print_runtime(RUNTIME_INFO(i915), &p); 67 intel_gt_info_print(&i915->gt.info, &p); 68 intel_driver_caps_print(&i915->caps, &p); 69 70 kernel_param_lock(THIS_MODULE); 71 i915_params_dump(&i915->params, &p); 72 kernel_param_unlock(THIS_MODULE); 73 74 return 0; 75 } 76 77 static char get_tiling_flag(struct drm_i915_gem_object *obj) 78 { 79 switch (i915_gem_object_get_tiling(obj)) { 80 default: 81 case I915_TILING_NONE: return ' '; 82 case I915_TILING_X: return 'X'; 83 case I915_TILING_Y: return 'Y'; 84 } 85 } 86 87 static char get_global_flag(struct drm_i915_gem_object *obj) 88 { 89 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 90 } 91 92 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 93 { 94 return obj->mm.mapping ? 'M' : ' '; 95 } 96 97 static const char * 98 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 99 { 100 size_t x = 0; 101 102 switch (page_sizes) { 103 case 0: 104 return ""; 105 case I915_GTT_PAGE_SIZE_4K: 106 return "4K"; 107 case I915_GTT_PAGE_SIZE_64K: 108 return "64K"; 109 case I915_GTT_PAGE_SIZE_2M: 110 return "2M"; 111 default: 112 if (!buf) 113 return "M"; 114 115 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 116 x += snprintf(buf + x, len - x, "2M, "); 117 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 118 x += snprintf(buf + x, len - x, "64K, "); 119 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 120 x += snprintf(buf + x, len - x, "4K, "); 121 buf[x-2] = '\0'; 122 123 return buf; 124 } 125 } 126 127 static const char *stringify_vma_type(const struct i915_vma *vma) 128 { 129 if (i915_vma_is_ggtt(vma)) 130 return "ggtt"; 131 132 if (i915_vma_is_dpt(vma)) 133 return "dpt"; 134 135 return "ppgtt"; 136 } 137 138 void 139 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 140 { 141 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 142 struct intel_engine_cs *engine; 143 struct i915_vma *vma; 144 int pin_count = 0; 145 146 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 147 &obj->base, 148 get_tiling_flag(obj), 149 get_global_flag(obj), 150 get_pin_mapped_flag(obj), 151 obj->base.size / 1024, 152 obj->read_domains, 153 obj->write_domain, 154 i915_cache_level_str(dev_priv, obj->cache_level), 155 obj->mm.dirty ? " dirty" : "", 156 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 157 if (obj->base.name) 158 seq_printf(m, " (name: %d)", obj->base.name); 159 160 spin_lock(&obj->vma.lock); 161 list_for_each_entry(vma, &obj->vma.list, obj_link) { 162 if (!drm_mm_node_allocated(&vma->node)) 163 continue; 164 165 spin_unlock(&obj->vma.lock); 166 167 if (i915_vma_is_pinned(vma)) 168 pin_count++; 169 170 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 171 stringify_vma_type(vma), 172 vma->node.start, vma->node.size, 173 stringify_page_sizes(vma->page_sizes.gtt, NULL, 0)); 174 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 175 switch (vma->ggtt_view.type) { 176 case I915_GGTT_VIEW_NORMAL: 177 seq_puts(m, ", normal"); 178 break; 179 180 case I915_GGTT_VIEW_PARTIAL: 181 seq_printf(m, ", partial [%08llx+%x]", 182 vma->ggtt_view.partial.offset << PAGE_SHIFT, 183 vma->ggtt_view.partial.size << PAGE_SHIFT); 184 break; 185 186 case I915_GGTT_VIEW_ROTATED: 187 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 188 vma->ggtt_view.rotated.plane[0].width, 189 vma->ggtt_view.rotated.plane[0].height, 190 vma->ggtt_view.rotated.plane[0].src_stride, 191 vma->ggtt_view.rotated.plane[0].dst_stride, 192 vma->ggtt_view.rotated.plane[0].offset, 193 vma->ggtt_view.rotated.plane[1].width, 194 vma->ggtt_view.rotated.plane[1].height, 195 vma->ggtt_view.rotated.plane[1].src_stride, 196 vma->ggtt_view.rotated.plane[1].dst_stride, 197 vma->ggtt_view.rotated.plane[1].offset); 198 break; 199 200 case I915_GGTT_VIEW_REMAPPED: 201 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 202 vma->ggtt_view.remapped.plane[0].width, 203 vma->ggtt_view.remapped.plane[0].height, 204 vma->ggtt_view.remapped.plane[0].src_stride, 205 vma->ggtt_view.remapped.plane[0].dst_stride, 206 vma->ggtt_view.remapped.plane[0].offset, 207 vma->ggtt_view.remapped.plane[1].width, 208 vma->ggtt_view.remapped.plane[1].height, 209 vma->ggtt_view.remapped.plane[1].src_stride, 210 vma->ggtt_view.remapped.plane[1].dst_stride, 211 vma->ggtt_view.remapped.plane[1].offset); 212 break; 213 214 default: 215 MISSING_CASE(vma->ggtt_view.type); 216 break; 217 } 218 } 219 if (vma->fence) 220 seq_printf(m, " , fence: %d", vma->fence->id); 221 seq_puts(m, ")"); 222 223 spin_lock(&obj->vma.lock); 224 } 225 spin_unlock(&obj->vma.lock); 226 227 seq_printf(m, " (pinned x %d)", pin_count); 228 if (i915_gem_object_is_stolen(obj)) 229 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 230 if (i915_gem_object_is_framebuffer(obj)) 231 seq_printf(m, " (fb)"); 232 233 engine = i915_gem_object_last_write_engine(obj); 234 if (engine) 235 seq_printf(m, " (%s)", engine->name); 236 } 237 238 static int i915_gem_object_info(struct seq_file *m, void *data) 239 { 240 struct drm_i915_private *i915 = node_to_i915(m->private); 241 struct intel_memory_region *mr; 242 enum intel_region_id id; 243 244 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 245 i915->mm.shrink_count, 246 atomic_read(&i915->mm.free_count), 247 i915->mm.shrink_memory); 248 for_each_memory_region(mr, i915, id) 249 seq_printf(m, "%s: total:%pa, available:%pa bytes\n", 250 mr->name, &mr->total, &mr->avail); 251 252 return 0; 253 } 254 255 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 256 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 257 size_t count, loff_t *pos) 258 { 259 struct i915_gpu_coredump *error; 260 ssize_t ret; 261 void *buf; 262 263 error = file->private_data; 264 if (!error) 265 return 0; 266 267 /* Bounce buffer required because of kernfs __user API convenience. */ 268 buf = kmalloc(count, GFP_KERNEL); 269 if (!buf) 270 return -ENOMEM; 271 272 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 273 if (ret <= 0) 274 goto out; 275 276 if (!copy_to_user(ubuf, buf, ret)) 277 *pos += ret; 278 else 279 ret = -EFAULT; 280 281 out: 282 kfree(buf); 283 return ret; 284 } 285 286 static int gpu_state_release(struct inode *inode, struct file *file) 287 { 288 i915_gpu_coredump_put(file->private_data); 289 return 0; 290 } 291 292 static int i915_gpu_info_open(struct inode *inode, struct file *file) 293 { 294 struct drm_i915_private *i915 = inode->i_private; 295 struct i915_gpu_coredump *gpu; 296 intel_wakeref_t wakeref; 297 298 gpu = NULL; 299 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 300 gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES); 301 if (IS_ERR(gpu)) 302 return PTR_ERR(gpu); 303 304 file->private_data = gpu; 305 return 0; 306 } 307 308 static const struct file_operations i915_gpu_info_fops = { 309 .owner = THIS_MODULE, 310 .open = i915_gpu_info_open, 311 .read = gpu_state_read, 312 .llseek = default_llseek, 313 .release = gpu_state_release, 314 }; 315 316 static ssize_t 317 i915_error_state_write(struct file *filp, 318 const char __user *ubuf, 319 size_t cnt, 320 loff_t *ppos) 321 { 322 struct i915_gpu_coredump *error = filp->private_data; 323 324 if (!error) 325 return 0; 326 327 drm_dbg(&error->i915->drm, "Resetting error state\n"); 328 i915_reset_error_state(error->i915); 329 330 return cnt; 331 } 332 333 static int i915_error_state_open(struct inode *inode, struct file *file) 334 { 335 struct i915_gpu_coredump *error; 336 337 error = i915_first_error_state(inode->i_private); 338 if (IS_ERR(error)) 339 return PTR_ERR(error); 340 341 file->private_data = error; 342 return 0; 343 } 344 345 static const struct file_operations i915_error_state_fops = { 346 .owner = THIS_MODULE, 347 .open = i915_error_state_open, 348 .read = gpu_state_read, 349 .write = i915_error_state_write, 350 .llseek = default_llseek, 351 .release = gpu_state_release, 352 }; 353 #endif 354 355 static int i915_frequency_info(struct seq_file *m, void *unused) 356 { 357 struct drm_i915_private *dev_priv = node_to_i915(m->private); 358 struct intel_uncore *uncore = &dev_priv->uncore; 359 struct intel_rps *rps = &dev_priv->gt.rps; 360 intel_wakeref_t wakeref; 361 362 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 363 364 if (GRAPHICS_VER(dev_priv) == 5) { 365 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL); 366 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK); 367 368 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 369 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 370 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 371 MEMSTAT_VID_SHIFT); 372 seq_printf(m, "Current P-state: %d\n", 373 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 374 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 375 u32 rpmodectl, freq_sts; 376 377 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); 378 seq_printf(m, "Video Turbo Mode: %s\n", 379 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 380 seq_printf(m, "HW control enabled: %s\n", 381 yesno(rpmodectl & GEN6_RP_ENABLE)); 382 seq_printf(m, "SW control enabled: %s\n", 383 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 384 GEN6_RP_MEDIA_SW_MODE)); 385 386 vlv_punit_get(dev_priv); 387 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 388 vlv_punit_put(dev_priv); 389 390 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 391 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 392 393 seq_printf(m, "actual GPU freq: %d MHz\n", 394 intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); 395 396 seq_printf(m, "current GPU freq: %d MHz\n", 397 intel_gpu_freq(rps, rps->cur_freq)); 398 399 seq_printf(m, "max GPU freq: %d MHz\n", 400 intel_gpu_freq(rps, rps->max_freq)); 401 402 seq_printf(m, "min GPU freq: %d MHz\n", 403 intel_gpu_freq(rps, rps->min_freq)); 404 405 seq_printf(m, "idle GPU freq: %d MHz\n", 406 intel_gpu_freq(rps, rps->idle_freq)); 407 408 seq_printf(m, 409 "efficient (RPe) frequency: %d MHz\n", 410 intel_gpu_freq(rps, rps->efficient_freq)); 411 } else if (GRAPHICS_VER(dev_priv) >= 6) { 412 u32 rp_state_limits; 413 u32 gt_perf_status; 414 u32 rp_state_cap; 415 u32 rpmodectl, rpinclimit, rpdeclimit; 416 u32 rpstat, cagf, reqf; 417 u32 rpupei, rpcurup, rpprevup; 418 u32 rpdownei, rpcurdown, rpprevdown; 419 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 420 int max_freq; 421 422 rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS); 423 if (IS_GEN9_LP(dev_priv)) { 424 rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP); 425 gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS); 426 } else { 427 rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP); 428 gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS); 429 } 430 431 /* RPSTAT1 is in the GT power well */ 432 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); 433 434 reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ); 435 if (GRAPHICS_VER(dev_priv) >= 9) 436 reqf >>= 23; 437 else { 438 reqf &= ~GEN6_TURBO_DISABLE; 439 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 440 reqf >>= 24; 441 else 442 reqf >>= 25; 443 } 444 reqf = intel_gpu_freq(rps, reqf); 445 446 rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL); 447 rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD); 448 rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD); 449 450 rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1); 451 rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK; 452 rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK; 453 rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK; 454 rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK; 455 rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK; 456 rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK; 457 cagf = intel_rps_read_actual_frequency(rps); 458 459 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); 460 461 if (GRAPHICS_VER(dev_priv) >= 11) { 462 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE); 463 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK); 464 /* 465 * The equivalent to the PM ISR & IIR cannot be read 466 * without affecting the current state of the system 467 */ 468 pm_isr = 0; 469 pm_iir = 0; 470 } else if (GRAPHICS_VER(dev_priv) >= 8) { 471 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2)); 472 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2)); 473 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2)); 474 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2)); 475 } else { 476 pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER); 477 pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR); 478 pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR); 479 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); 480 } 481 pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK); 482 483 seq_printf(m, "Video Turbo Mode: %s\n", 484 yesno(rpmodectl & GEN6_RP_MEDIA_TURBO)); 485 seq_printf(m, "HW control enabled: %s\n", 486 yesno(rpmodectl & GEN6_RP_ENABLE)); 487 seq_printf(m, "SW control enabled: %s\n", 488 yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == 489 GEN6_RP_MEDIA_SW_MODE)); 490 491 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", 492 pm_ier, pm_imr, pm_mask); 493 if (GRAPHICS_VER(dev_priv) <= 10) 494 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", 495 pm_isr, pm_iir); 496 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", 497 rps->pm_intrmsk_mbz); 498 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 499 seq_printf(m, "Render p-state ratio: %d\n", 500 (gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); 501 seq_printf(m, "Render p-state VID: %d\n", 502 gt_perf_status & 0xff); 503 seq_printf(m, "Render p-state limit: %d\n", 504 rp_state_limits & 0xff); 505 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 506 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 507 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 508 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 509 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 510 seq_printf(m, "CAGF: %dMHz\n", cagf); 511 seq_printf(m, "RP CUR UP EI: %d (%lldns)\n", 512 rpupei, 513 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei)); 514 seq_printf(m, "RP CUR UP: %d (%lldun)\n", 515 rpcurup, 516 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup)); 517 seq_printf(m, "RP PREV UP: %d (%lldns)\n", 518 rpprevup, 519 intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup)); 520 seq_printf(m, "Up threshold: %d%%\n", 521 rps->power.up_threshold); 522 523 seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n", 524 rpdownei, 525 intel_gt_pm_interval_to_ns(&dev_priv->gt, 526 rpdownei)); 527 seq_printf(m, "RP CUR DOWN: %d (%lldns)\n", 528 rpcurdown, 529 intel_gt_pm_interval_to_ns(&dev_priv->gt, 530 rpcurdown)); 531 seq_printf(m, "RP PREV DOWN: %d (%lldns)\n", 532 rpprevdown, 533 intel_gt_pm_interval_to_ns(&dev_priv->gt, 534 rpprevdown)); 535 seq_printf(m, "Down threshold: %d%%\n", 536 rps->power.down_threshold); 537 538 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : 539 rp_state_cap >> 16) & 0xff; 540 max_freq *= (IS_GEN9_BC(dev_priv) || 541 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 542 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 543 intel_gpu_freq(rps, max_freq)); 544 545 max_freq = (rp_state_cap & 0xff00) >> 8; 546 max_freq *= (IS_GEN9_BC(dev_priv) || 547 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 548 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 549 intel_gpu_freq(rps, max_freq)); 550 551 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : 552 rp_state_cap >> 0) & 0xff; 553 max_freq *= (IS_GEN9_BC(dev_priv) || 554 GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); 555 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 556 intel_gpu_freq(rps, max_freq)); 557 seq_printf(m, "Max overclocked frequency: %dMHz\n", 558 intel_gpu_freq(rps, rps->max_freq)); 559 560 seq_printf(m, "Current freq: %d MHz\n", 561 intel_gpu_freq(rps, rps->cur_freq)); 562 seq_printf(m, "Actual freq: %d MHz\n", cagf); 563 seq_printf(m, "Idle freq: %d MHz\n", 564 intel_gpu_freq(rps, rps->idle_freq)); 565 seq_printf(m, "Min freq: %d MHz\n", 566 intel_gpu_freq(rps, rps->min_freq)); 567 seq_printf(m, "Boost freq: %d MHz\n", 568 intel_gpu_freq(rps, rps->boost_freq)); 569 seq_printf(m, "Max freq: %d MHz\n", 570 intel_gpu_freq(rps, rps->max_freq)); 571 seq_printf(m, 572 "efficient (RPe) frequency: %d MHz\n", 573 intel_gpu_freq(rps, rps->efficient_freq)); 574 } else { 575 seq_puts(m, "no P-state info available\n"); 576 } 577 578 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); 579 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); 580 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); 581 582 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 583 return 0; 584 } 585 586 static const char *swizzle_string(unsigned swizzle) 587 { 588 switch (swizzle) { 589 case I915_BIT_6_SWIZZLE_NONE: 590 return "none"; 591 case I915_BIT_6_SWIZZLE_9: 592 return "bit9"; 593 case I915_BIT_6_SWIZZLE_9_10: 594 return "bit9/bit10"; 595 case I915_BIT_6_SWIZZLE_9_11: 596 return "bit9/bit11"; 597 case I915_BIT_6_SWIZZLE_9_10_11: 598 return "bit9/bit10/bit11"; 599 case I915_BIT_6_SWIZZLE_9_17: 600 return "bit9/bit17"; 601 case I915_BIT_6_SWIZZLE_9_10_17: 602 return "bit9/bit10/bit17"; 603 case I915_BIT_6_SWIZZLE_UNKNOWN: 604 return "unknown"; 605 } 606 607 return "bug"; 608 } 609 610 static int i915_swizzle_info(struct seq_file *m, void *data) 611 { 612 struct drm_i915_private *dev_priv = node_to_i915(m->private); 613 struct intel_uncore *uncore = &dev_priv->uncore; 614 intel_wakeref_t wakeref; 615 616 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 617 swizzle_string(dev_priv->ggtt.bit_6_swizzle_x)); 618 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 619 swizzle_string(dev_priv->ggtt.bit_6_swizzle_y)); 620 621 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 622 seq_puts(m, "L-shaped memory detected\n"); 623 624 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 625 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 626 return 0; 627 628 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 629 630 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 631 seq_printf(m, "DDC = 0x%08x\n", 632 intel_uncore_read(uncore, DCC)); 633 seq_printf(m, "DDC2 = 0x%08x\n", 634 intel_uncore_read(uncore, DCC2)); 635 seq_printf(m, "C0DRB3 = 0x%04x\n", 636 intel_uncore_read16(uncore, C0DRB3_BW)); 637 seq_printf(m, "C1DRB3 = 0x%04x\n", 638 intel_uncore_read16(uncore, C1DRB3_BW)); 639 } else if (INTEL_GEN(dev_priv) >= 6) { 640 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 641 intel_uncore_read(uncore, MAD_DIMM_C0)); 642 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 643 intel_uncore_read(uncore, MAD_DIMM_C1)); 644 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 645 intel_uncore_read(uncore, MAD_DIMM_C2)); 646 seq_printf(m, "TILECTL = 0x%08x\n", 647 intel_uncore_read(uncore, TILECTL)); 648 if (GRAPHICS_VER(dev_priv) >= 8) 649 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 650 intel_uncore_read(uncore, GAMTARBMODE)); 651 else 652 seq_printf(m, "ARB_MODE = 0x%08x\n", 653 intel_uncore_read(uncore, ARB_MODE)); 654 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 655 intel_uncore_read(uncore, DISP_ARB_CTL)); 656 } 657 658 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 659 660 return 0; 661 } 662 663 static int i915_rps_boost_info(struct seq_file *m, void *data) 664 { 665 struct drm_i915_private *dev_priv = node_to_i915(m->private); 666 struct intel_rps *rps = &dev_priv->gt.rps; 667 668 seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps))); 669 seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps))); 670 seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake)); 671 seq_printf(m, "Boosts outstanding? %d\n", 672 atomic_read(&rps->num_waiters)); 673 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 674 seq_printf(m, "Frequency requested %d, actual %d\n", 675 intel_gpu_freq(rps, rps->cur_freq), 676 intel_rps_read_actual_frequency(rps)); 677 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 678 intel_gpu_freq(rps, rps->min_freq), 679 intel_gpu_freq(rps, rps->min_freq_softlimit), 680 intel_gpu_freq(rps, rps->max_freq_softlimit), 681 intel_gpu_freq(rps, rps->max_freq)); 682 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 683 intel_gpu_freq(rps, rps->idle_freq), 684 intel_gpu_freq(rps, rps->efficient_freq), 685 intel_gpu_freq(rps, rps->boost_freq)); 686 687 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 688 689 return 0; 690 } 691 692 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 693 { 694 struct drm_i915_private *dev_priv = node_to_i915(m->private); 695 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 696 697 if (!HAS_RUNTIME_PM(dev_priv)) 698 seq_puts(m, "Runtime power management not supported\n"); 699 700 seq_printf(m, "Runtime power status: %s\n", 701 enableddisabled(!dev_priv->power_domains.init_wakeref)); 702 703 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); 704 seq_printf(m, "IRQs disabled: %s\n", 705 yesno(!intel_irqs_enabled(dev_priv))); 706 #ifdef CONFIG_PM 707 seq_printf(m, "Usage count: %d\n", 708 atomic_read(&dev_priv->drm.dev->power.usage_count)); 709 #else 710 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 711 #endif 712 seq_printf(m, "PCI device power state: %s [%d]\n", 713 pci_power_name(pdev->current_state), 714 pdev->current_state); 715 716 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 717 struct drm_printer p = drm_seq_file_printer(m); 718 719 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 720 } 721 722 return 0; 723 } 724 725 static int i915_engine_info(struct seq_file *m, void *unused) 726 { 727 struct drm_i915_private *i915 = node_to_i915(m->private); 728 struct intel_engine_cs *engine; 729 intel_wakeref_t wakeref; 730 struct drm_printer p; 731 732 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 733 734 seq_printf(m, "GT awake? %s [%d], %llums\n", 735 yesno(i915->gt.awake), 736 atomic_read(&i915->gt.wakeref.count), 737 ktime_to_ms(intel_gt_get_awake_time(&i915->gt))); 738 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 739 i915->gt.clock_frequency, 740 i915->gt.clock_period_ns); 741 742 p = drm_seq_file_printer(m); 743 for_each_uabi_engine(engine, i915) 744 intel_engine_dump(engine, &p, "%s\n", engine->name); 745 746 intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule); 747 748 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 749 750 return 0; 751 } 752 753 static int i915_wa_registers(struct seq_file *m, void *unused) 754 { 755 struct drm_i915_private *i915 = node_to_i915(m->private); 756 struct intel_engine_cs *engine; 757 758 for_each_uabi_engine(engine, i915) { 759 const struct i915_wa_list *wal = &engine->ctx_wa_list; 760 const struct i915_wa *wa; 761 unsigned int count; 762 763 count = wal->count; 764 if (!count) 765 continue; 766 767 seq_printf(m, "%s: Workarounds applied: %u\n", 768 engine->name, count); 769 770 for (wa = wal->list; count--; wa++) 771 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 772 i915_mmio_reg_offset(wa->reg), 773 wa->set, wa->clr); 774 775 seq_printf(m, "\n"); 776 } 777 778 return 0; 779 } 780 781 static int 782 i915_wedged_get(void *data, u64 *val) 783 { 784 struct drm_i915_private *i915 = data; 785 int ret = intel_gt_terminally_wedged(&i915->gt); 786 787 switch (ret) { 788 case -EIO: 789 *val = 1; 790 return 0; 791 case 0: 792 *val = 0; 793 return 0; 794 default: 795 return ret; 796 } 797 } 798 799 static int 800 i915_wedged_set(void *data, u64 val) 801 { 802 struct drm_i915_private *i915 = data; 803 804 /* Flush any previous reset before applying for a new one */ 805 wait_event(i915->gt.reset.queue, 806 !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags)); 807 808 intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE, 809 "Manually set wedged engine mask = %llx", val); 810 return 0; 811 } 812 813 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 814 i915_wedged_get, i915_wedged_set, 815 "%llu\n"); 816 817 static int 818 i915_perf_noa_delay_set(void *data, u64 val) 819 { 820 struct drm_i915_private *i915 = data; 821 822 /* 823 * This would lead to infinite waits as we're doing timestamp 824 * difference on the CS with only 32bits. 825 */ 826 if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX) 827 return -EINVAL; 828 829 atomic64_set(&i915->perf.noa_programming_delay, val); 830 return 0; 831 } 832 833 static int 834 i915_perf_noa_delay_get(void *data, u64 *val) 835 { 836 struct drm_i915_private *i915 = data; 837 838 *val = atomic64_read(&i915->perf.noa_programming_delay); 839 return 0; 840 } 841 842 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 843 i915_perf_noa_delay_get, 844 i915_perf_noa_delay_set, 845 "%llu\n"); 846 847 #define DROP_UNBOUND BIT(0) 848 #define DROP_BOUND BIT(1) 849 #define DROP_RETIRE BIT(2) 850 #define DROP_ACTIVE BIT(3) 851 #define DROP_FREED BIT(4) 852 #define DROP_SHRINK_ALL BIT(5) 853 #define DROP_IDLE BIT(6) 854 #define DROP_RESET_ACTIVE BIT(7) 855 #define DROP_RESET_SEQNO BIT(8) 856 #define DROP_RCU BIT(9) 857 #define DROP_ALL (DROP_UNBOUND | \ 858 DROP_BOUND | \ 859 DROP_RETIRE | \ 860 DROP_ACTIVE | \ 861 DROP_FREED | \ 862 DROP_SHRINK_ALL |\ 863 DROP_IDLE | \ 864 DROP_RESET_ACTIVE | \ 865 DROP_RESET_SEQNO | \ 866 DROP_RCU) 867 static int 868 i915_drop_caches_get(void *data, u64 *val) 869 { 870 *val = DROP_ALL; 871 872 return 0; 873 } 874 static int 875 gt_drop_caches(struct intel_gt *gt, u64 val) 876 { 877 int ret; 878 879 if (val & DROP_RESET_ACTIVE && 880 wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT)) 881 intel_gt_set_wedged(gt); 882 883 if (val & DROP_RETIRE) 884 intel_gt_retire_requests(gt); 885 886 if (val & (DROP_IDLE | DROP_ACTIVE)) { 887 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 888 if (ret) 889 return ret; 890 } 891 892 if (val & DROP_IDLE) { 893 ret = intel_gt_pm_wait_for_idle(gt); 894 if (ret) 895 return ret; 896 } 897 898 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 899 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 900 901 if (val & DROP_FREED) 902 intel_gt_flush_buffer_pool(gt); 903 904 return 0; 905 } 906 907 static int 908 i915_drop_caches_set(void *data, u64 val) 909 { 910 struct drm_i915_private *i915 = data; 911 int ret; 912 913 DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n", 914 val, val & DROP_ALL); 915 916 ret = gt_drop_caches(&i915->gt, val); 917 if (ret) 918 return ret; 919 920 fs_reclaim_acquire(GFP_KERNEL); 921 if (val & DROP_BOUND) 922 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 923 924 if (val & DROP_UNBOUND) 925 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 926 927 if (val & DROP_SHRINK_ALL) 928 i915_gem_shrink_all(i915); 929 fs_reclaim_release(GFP_KERNEL); 930 931 if (val & DROP_RCU) 932 rcu_barrier(); 933 934 if (val & DROP_FREED) 935 i915_gem_drain_freed_objects(i915); 936 937 return 0; 938 } 939 940 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 941 i915_drop_caches_get, i915_drop_caches_set, 942 "0x%08llx\n"); 943 944 static int i915_sseu_status(struct seq_file *m, void *unused) 945 { 946 struct drm_i915_private *i915 = node_to_i915(m->private); 947 struct intel_gt *gt = &i915->gt; 948 949 return intel_sseu_status(m, gt); 950 } 951 952 static int i915_forcewake_open(struct inode *inode, struct file *file) 953 { 954 struct drm_i915_private *i915 = inode->i_private; 955 struct intel_gt *gt = &i915->gt; 956 957 atomic_inc(>->user_wakeref); 958 intel_gt_pm_get(gt); 959 if (GRAPHICS_VER(i915) >= 6) 960 intel_uncore_forcewake_user_get(gt->uncore); 961 962 return 0; 963 } 964 965 static int i915_forcewake_release(struct inode *inode, struct file *file) 966 { 967 struct drm_i915_private *i915 = inode->i_private; 968 struct intel_gt *gt = &i915->gt; 969 970 if (GRAPHICS_VER(i915) >= 6) 971 intel_uncore_forcewake_user_put(&i915->uncore); 972 intel_gt_pm_put(gt); 973 atomic_dec(>->user_wakeref); 974 975 return 0; 976 } 977 978 static const struct file_operations i915_forcewake_fops = { 979 .owner = THIS_MODULE, 980 .open = i915_forcewake_open, 981 .release = i915_forcewake_release, 982 }; 983 984 static const struct drm_info_list i915_debugfs_list[] = { 985 {"i915_capabilities", i915_capabilities, 0}, 986 {"i915_gem_objects", i915_gem_object_info, 0}, 987 {"i915_frequency_info", i915_frequency_info, 0}, 988 {"i915_swizzle_info", i915_swizzle_info, 0}, 989 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 990 {"i915_engine_info", i915_engine_info, 0}, 991 {"i915_wa_registers", i915_wa_registers, 0}, 992 {"i915_sseu_status", i915_sseu_status, 0}, 993 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 994 }; 995 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 996 997 static const struct i915_debugfs_files { 998 const char *name; 999 const struct file_operations *fops; 1000 } i915_debugfs_files[] = { 1001 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 1002 {"i915_wedged", &i915_wedged_fops}, 1003 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 1004 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1005 {"i915_error_state", &i915_error_state_fops}, 1006 {"i915_gpu_info", &i915_gpu_info_fops}, 1007 #endif 1008 }; 1009 1010 void i915_debugfs_register(struct drm_i915_private *dev_priv) 1011 { 1012 struct drm_minor *minor = dev_priv->drm.primary; 1013 int i; 1014 1015 i915_debugfs_params(dev_priv); 1016 1017 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 1018 to_i915(minor->dev), &i915_forcewake_fops); 1019 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 1020 debugfs_create_file(i915_debugfs_files[i].name, 1021 S_IRUGO | S_IWUSR, 1022 minor->debugfs_root, 1023 to_i915(minor->dev), 1024 i915_debugfs_files[i].fops); 1025 } 1026 1027 drm_debugfs_create_files(i915_debugfs_list, 1028 I915_DEBUGFS_ENTRIES, 1029 minor->debugfs_root, minor); 1030 } 1031