1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/sched/mm.h> 30 #include <linux/sort.h> 31 #include <linux/string_helpers.h> 32 33 #include <drm/drm_debugfs.h> 34 35 #include "gem/i915_gem_context.h" 36 #include "gt/intel_gt.h" 37 #include "gt/intel_gt_buffer_pool.h" 38 #include "gt/intel_gt_clock_utils.h" 39 #include "gt/intel_gt_debugfs.h" 40 #include "gt/intel_gt_pm.h" 41 #include "gt/intel_gt_pm_debugfs.h" 42 #include "gt/intel_gt_regs.h" 43 #include "gt/intel_gt_requests.h" 44 #include "gt/intel_rc6.h" 45 #include "gt/intel_reset.h" 46 #include "gt/intel_rps.h" 47 #include "gt/intel_sseu_debugfs.h" 48 49 #include "i915_debugfs.h" 50 #include "i915_debugfs_params.h" 51 #include "i915_driver.h" 52 #include "i915_irq.h" 53 #include "i915_scheduler.h" 54 #include "intel_mchbar_regs.h" 55 56 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) 57 { 58 return to_i915(node->minor->dev); 59 } 60 61 static int i915_capabilities(struct seq_file *m, void *data) 62 { 63 struct drm_i915_private *i915 = node_to_i915(m->private); 64 struct drm_printer p = drm_seq_file_printer(m); 65 66 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); 67 68 intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p); 69 i915_print_iommu_status(i915, &p); 70 intel_gt_info_print(&to_gt(i915)->info, &p); 71 intel_driver_caps_print(&i915->caps, &p); 72 73 kernel_param_lock(THIS_MODULE); 74 i915_params_dump(&i915->params, &p); 75 kernel_param_unlock(THIS_MODULE); 76 77 return 0; 78 } 79 80 static char get_tiling_flag(struct drm_i915_gem_object *obj) 81 { 82 switch (i915_gem_object_get_tiling(obj)) { 83 default: 84 case I915_TILING_NONE: return ' '; 85 case I915_TILING_X: return 'X'; 86 case I915_TILING_Y: return 'Y'; 87 } 88 } 89 90 static char get_global_flag(struct drm_i915_gem_object *obj) 91 { 92 return READ_ONCE(obj->userfault_count) ? 'g' : ' '; 93 } 94 95 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj) 96 { 97 return obj->mm.mapping ? 'M' : ' '; 98 } 99 100 static const char * 101 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len) 102 { 103 size_t x = 0; 104 105 switch (page_sizes) { 106 case 0: 107 return ""; 108 case I915_GTT_PAGE_SIZE_4K: 109 return "4K"; 110 case I915_GTT_PAGE_SIZE_64K: 111 return "64K"; 112 case I915_GTT_PAGE_SIZE_2M: 113 return "2M"; 114 default: 115 if (!buf) 116 return "M"; 117 118 if (page_sizes & I915_GTT_PAGE_SIZE_2M) 119 x += snprintf(buf + x, len - x, "2M, "); 120 if (page_sizes & I915_GTT_PAGE_SIZE_64K) 121 x += snprintf(buf + x, len - x, "64K, "); 122 if (page_sizes & I915_GTT_PAGE_SIZE_4K) 123 x += snprintf(buf + x, len - x, "4K, "); 124 buf[x-2] = '\0'; 125 126 return buf; 127 } 128 } 129 130 static const char *stringify_vma_type(const struct i915_vma *vma) 131 { 132 if (i915_vma_is_ggtt(vma)) 133 return "ggtt"; 134 135 if (i915_vma_is_dpt(vma)) 136 return "dpt"; 137 138 return "ppgtt"; 139 } 140 141 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) 142 { 143 struct drm_i915_private *i915 = obj_to_i915(obj); 144 145 if (IS_METEORLAKE(i915)) { 146 switch (obj->pat_index) { 147 case 0: return " WB"; 148 case 1: return " WT"; 149 case 2: return " UC"; 150 case 3: return " WB (1-Way Coh)"; 151 case 4: return " WB (2-Way Coh)"; 152 default: return " not defined"; 153 } 154 } else if (IS_PONTEVECCHIO(i915)) { 155 switch (obj->pat_index) { 156 case 0: return " UC"; 157 case 1: return " WC"; 158 case 2: return " WT"; 159 case 3: return " WB"; 160 case 4: return " WT (CLOS1)"; 161 case 5: return " WB (CLOS1)"; 162 case 6: return " WT (CLOS2)"; 163 case 7: return " WT (CLOS2)"; 164 default: return " not defined"; 165 } 166 } else if (GRAPHICS_VER(i915) >= 12) { 167 switch (obj->pat_index) { 168 case 0: return " WB"; 169 case 1: return " WC"; 170 case 2: return " WT"; 171 case 3: return " UC"; 172 default: return " not defined"; 173 } 174 } else { 175 switch (obj->pat_index) { 176 case 0: return " UC"; 177 case 1: return HAS_LLC(i915) ? 178 " LLC" : " snooped"; 179 case 2: return " L3+LLC"; 180 case 3: return " WT"; 181 default: return " not defined"; 182 } 183 } 184 } 185 186 void 187 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 188 { 189 struct i915_vma *vma; 190 int pin_count = 0; 191 192 seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s", 193 &obj->base, 194 get_tiling_flag(obj), 195 get_global_flag(obj), 196 get_pin_mapped_flag(obj), 197 obj->base.size / 1024, 198 obj->read_domains, 199 obj->write_domain, 200 i915_cache_level_str(obj), 201 obj->mm.dirty ? " dirty" : "", 202 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : ""); 203 if (obj->base.name) 204 seq_printf(m, " (name: %d)", obj->base.name); 205 206 spin_lock(&obj->vma.lock); 207 list_for_each_entry(vma, &obj->vma.list, obj_link) { 208 if (!drm_mm_node_allocated(&vma->node)) 209 continue; 210 211 spin_unlock(&obj->vma.lock); 212 213 if (i915_vma_is_pinned(vma)) 214 pin_count++; 215 216 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s", 217 stringify_vma_type(vma), 218 i915_vma_offset(vma), i915_vma_size(vma), 219 stringify_page_sizes(vma->resource->page_sizes_gtt, 220 NULL, 0)); 221 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) { 222 switch (vma->gtt_view.type) { 223 case I915_GTT_VIEW_NORMAL: 224 seq_puts(m, ", normal"); 225 break; 226 227 case I915_GTT_VIEW_PARTIAL: 228 seq_printf(m, ", partial [%08llx+%x]", 229 vma->gtt_view.partial.offset << PAGE_SHIFT, 230 vma->gtt_view.partial.size << PAGE_SHIFT); 231 break; 232 233 case I915_GTT_VIEW_ROTATED: 234 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 235 vma->gtt_view.rotated.plane[0].width, 236 vma->gtt_view.rotated.plane[0].height, 237 vma->gtt_view.rotated.plane[0].src_stride, 238 vma->gtt_view.rotated.plane[0].dst_stride, 239 vma->gtt_view.rotated.plane[0].offset, 240 vma->gtt_view.rotated.plane[1].width, 241 vma->gtt_view.rotated.plane[1].height, 242 vma->gtt_view.rotated.plane[1].src_stride, 243 vma->gtt_view.rotated.plane[1].dst_stride, 244 vma->gtt_view.rotated.plane[1].offset); 245 break; 246 247 case I915_GTT_VIEW_REMAPPED: 248 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]", 249 vma->gtt_view.remapped.plane[0].width, 250 vma->gtt_view.remapped.plane[0].height, 251 vma->gtt_view.remapped.plane[0].src_stride, 252 vma->gtt_view.remapped.plane[0].dst_stride, 253 vma->gtt_view.remapped.plane[0].offset, 254 vma->gtt_view.remapped.plane[1].width, 255 vma->gtt_view.remapped.plane[1].height, 256 vma->gtt_view.remapped.plane[1].src_stride, 257 vma->gtt_view.remapped.plane[1].dst_stride, 258 vma->gtt_view.remapped.plane[1].offset); 259 break; 260 261 default: 262 MISSING_CASE(vma->gtt_view.type); 263 break; 264 } 265 } 266 if (vma->fence) 267 seq_printf(m, " , fence: %d", vma->fence->id); 268 seq_puts(m, ")"); 269 270 spin_lock(&obj->vma.lock); 271 } 272 spin_unlock(&obj->vma.lock); 273 274 seq_printf(m, " (pinned x %d)", pin_count); 275 if (i915_gem_object_is_stolen(obj)) 276 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 277 if (i915_gem_object_is_framebuffer(obj)) 278 seq_printf(m, " (fb)"); 279 } 280 281 static int i915_gem_object_info(struct seq_file *m, void *data) 282 { 283 struct drm_i915_private *i915 = node_to_i915(m->private); 284 struct drm_printer p = drm_seq_file_printer(m); 285 struct intel_memory_region *mr; 286 enum intel_region_id id; 287 288 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", 289 i915->mm.shrink_count, 290 atomic_read(&i915->mm.free_count), 291 i915->mm.shrink_memory); 292 for_each_memory_region(mr, i915, id) 293 intel_memory_region_debug(mr, &p); 294 295 return 0; 296 } 297 298 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 299 static ssize_t gpu_state_read(struct file *file, char __user *ubuf, 300 size_t count, loff_t *pos) 301 { 302 struct i915_gpu_coredump *error; 303 ssize_t ret; 304 void *buf; 305 306 error = file->private_data; 307 if (!error) 308 return 0; 309 310 /* Bounce buffer required because of kernfs __user API convenience. */ 311 buf = kmalloc(count, GFP_KERNEL); 312 if (!buf) 313 return -ENOMEM; 314 315 ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count); 316 if (ret <= 0) 317 goto out; 318 319 if (!copy_to_user(ubuf, buf, ret)) 320 *pos += ret; 321 else 322 ret = -EFAULT; 323 324 out: 325 kfree(buf); 326 return ret; 327 } 328 329 static int gpu_state_release(struct inode *inode, struct file *file) 330 { 331 i915_gpu_coredump_put(file->private_data); 332 return 0; 333 } 334 335 static int i915_gpu_info_open(struct inode *inode, struct file *file) 336 { 337 struct drm_i915_private *i915 = inode->i_private; 338 struct i915_gpu_coredump *gpu; 339 intel_wakeref_t wakeref; 340 341 gpu = NULL; 342 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 343 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE); 344 345 if (IS_ERR(gpu)) 346 return PTR_ERR(gpu); 347 348 file->private_data = gpu; 349 return 0; 350 } 351 352 static const struct file_operations i915_gpu_info_fops = { 353 .owner = THIS_MODULE, 354 .open = i915_gpu_info_open, 355 .read = gpu_state_read, 356 .llseek = default_llseek, 357 .release = gpu_state_release, 358 }; 359 360 static ssize_t 361 i915_error_state_write(struct file *filp, 362 const char __user *ubuf, 363 size_t cnt, 364 loff_t *ppos) 365 { 366 struct i915_gpu_coredump *error = filp->private_data; 367 368 if (!error) 369 return 0; 370 371 drm_dbg(&error->i915->drm, "Resetting error state\n"); 372 i915_reset_error_state(error->i915); 373 374 return cnt; 375 } 376 377 static int i915_error_state_open(struct inode *inode, struct file *file) 378 { 379 struct i915_gpu_coredump *error; 380 381 error = i915_first_error_state(inode->i_private); 382 if (IS_ERR(error)) 383 return PTR_ERR(error); 384 385 file->private_data = error; 386 return 0; 387 } 388 389 static const struct file_operations i915_error_state_fops = { 390 .owner = THIS_MODULE, 391 .open = i915_error_state_open, 392 .read = gpu_state_read, 393 .write = i915_error_state_write, 394 .llseek = default_llseek, 395 .release = gpu_state_release, 396 }; 397 #endif 398 399 static int i915_frequency_info(struct seq_file *m, void *unused) 400 { 401 struct drm_i915_private *i915 = node_to_i915(m->private); 402 struct intel_gt *gt = to_gt(i915); 403 struct drm_printer p = drm_seq_file_printer(m); 404 405 intel_gt_pm_frequency_dump(gt, &p); 406 407 return 0; 408 } 409 410 static const char *swizzle_string(unsigned swizzle) 411 { 412 switch (swizzle) { 413 case I915_BIT_6_SWIZZLE_NONE: 414 return "none"; 415 case I915_BIT_6_SWIZZLE_9: 416 return "bit9"; 417 case I915_BIT_6_SWIZZLE_9_10: 418 return "bit9/bit10"; 419 case I915_BIT_6_SWIZZLE_9_11: 420 return "bit9/bit11"; 421 case I915_BIT_6_SWIZZLE_9_10_11: 422 return "bit9/bit10/bit11"; 423 case I915_BIT_6_SWIZZLE_9_17: 424 return "bit9/bit17"; 425 case I915_BIT_6_SWIZZLE_9_10_17: 426 return "bit9/bit10/bit17"; 427 case I915_BIT_6_SWIZZLE_UNKNOWN: 428 return "unknown"; 429 } 430 431 return "bug"; 432 } 433 434 static int i915_swizzle_info(struct seq_file *m, void *data) 435 { 436 struct drm_i915_private *dev_priv = node_to_i915(m->private); 437 struct intel_uncore *uncore = &dev_priv->uncore; 438 intel_wakeref_t wakeref; 439 440 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 441 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x)); 442 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 443 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y)); 444 445 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) 446 seq_puts(m, "L-shaped memory detected\n"); 447 448 /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */ 449 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) 450 return 0; 451 452 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 453 454 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) { 455 seq_printf(m, "DDC = 0x%08x\n", 456 intel_uncore_read(uncore, DCC)); 457 seq_printf(m, "DDC2 = 0x%08x\n", 458 intel_uncore_read(uncore, DCC2)); 459 seq_printf(m, "C0DRB3 = 0x%04x\n", 460 intel_uncore_read16(uncore, C0DRB3_BW)); 461 seq_printf(m, "C1DRB3 = 0x%04x\n", 462 intel_uncore_read16(uncore, C1DRB3_BW)); 463 } else if (GRAPHICS_VER(dev_priv) >= 6) { 464 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 465 intel_uncore_read(uncore, MAD_DIMM_C0)); 466 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 467 intel_uncore_read(uncore, MAD_DIMM_C1)); 468 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 469 intel_uncore_read(uncore, MAD_DIMM_C2)); 470 seq_printf(m, "TILECTL = 0x%08x\n", 471 intel_uncore_read(uncore, TILECTL)); 472 if (GRAPHICS_VER(dev_priv) >= 8) 473 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 474 intel_uncore_read(uncore, GAMTARBMODE)); 475 else 476 seq_printf(m, "ARB_MODE = 0x%08x\n", 477 intel_uncore_read(uncore, ARB_MODE)); 478 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 479 intel_uncore_read(uncore, DISP_ARB_CTL)); 480 } 481 482 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 483 484 return 0; 485 } 486 487 static int i915_rps_boost_info(struct seq_file *m, void *data) 488 { 489 struct drm_i915_private *dev_priv = node_to_i915(m->private); 490 struct intel_rps *rps = &to_gt(dev_priv)->rps; 491 492 seq_printf(m, "RPS enabled? %s\n", 493 str_yes_no(intel_rps_is_enabled(rps))); 494 seq_printf(m, "RPS active? %s\n", 495 str_yes_no(intel_rps_is_active(rps))); 496 seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake)); 497 seq_printf(m, "Boosts outstanding? %d\n", 498 atomic_read(&rps->num_waiters)); 499 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); 500 seq_printf(m, "Frequency requested %d, actual %d\n", 501 intel_gpu_freq(rps, rps->cur_freq), 502 intel_rps_read_actual_frequency(rps)); 503 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", 504 intel_gpu_freq(rps, rps->min_freq), 505 intel_gpu_freq(rps, rps->min_freq_softlimit), 506 intel_gpu_freq(rps, rps->max_freq_softlimit), 507 intel_gpu_freq(rps, rps->max_freq)); 508 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", 509 intel_gpu_freq(rps, rps->idle_freq), 510 intel_gpu_freq(rps, rps->efficient_freq), 511 intel_gpu_freq(rps, rps->boost_freq)); 512 513 seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts)); 514 515 return 0; 516 } 517 518 static int i915_runtime_pm_status(struct seq_file *m, void *unused) 519 { 520 struct drm_i915_private *dev_priv = node_to_i915(m->private); 521 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 522 523 if (!HAS_RUNTIME_PM(dev_priv)) 524 seq_puts(m, "Runtime power management not supported\n"); 525 526 seq_printf(m, "Runtime power status: %s\n", 527 str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref)); 528 529 seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake)); 530 seq_printf(m, "IRQs disabled: %s\n", 531 str_yes_no(!intel_irqs_enabled(dev_priv))); 532 #ifdef CONFIG_PM 533 seq_printf(m, "Usage count: %d\n", 534 atomic_read(&dev_priv->drm.dev->power.usage_count)); 535 #else 536 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); 537 #endif 538 seq_printf(m, "PCI device power state: %s [%d]\n", 539 pci_power_name(pdev->current_state), 540 pdev->current_state); 541 542 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) { 543 struct drm_printer p = drm_seq_file_printer(m); 544 545 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p); 546 } 547 548 return 0; 549 } 550 551 static int i915_engine_info(struct seq_file *m, void *unused) 552 { 553 struct drm_i915_private *i915 = node_to_i915(m->private); 554 struct intel_engine_cs *engine; 555 intel_wakeref_t wakeref; 556 struct drm_printer p; 557 558 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 559 560 seq_printf(m, "GT awake? %s [%d], %llums\n", 561 str_yes_no(to_gt(i915)->awake), 562 atomic_read(&to_gt(i915)->wakeref.count), 563 ktime_to_ms(intel_gt_get_awake_time(to_gt(i915)))); 564 seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n", 565 to_gt(i915)->clock_frequency, 566 to_gt(i915)->clock_period_ns); 567 568 p = drm_seq_file_printer(m); 569 for_each_uabi_engine(engine, i915) 570 intel_engine_dump(engine, &p, "%s\n", engine->name); 571 572 intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule); 573 574 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 575 576 return 0; 577 } 578 579 static int i915_wa_registers(struct seq_file *m, void *unused) 580 { 581 struct drm_i915_private *i915 = node_to_i915(m->private); 582 struct intel_engine_cs *engine; 583 584 for_each_uabi_engine(engine, i915) { 585 const struct i915_wa_list *wal = &engine->ctx_wa_list; 586 const struct i915_wa *wa; 587 unsigned int count; 588 589 count = wal->count; 590 if (!count) 591 continue; 592 593 seq_printf(m, "%s: Workarounds applied: %u\n", 594 engine->name, count); 595 596 for (wa = wal->list; count--; wa++) 597 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", 598 i915_mmio_reg_offset(wa->reg), 599 wa->set, wa->clr); 600 601 seq_printf(m, "\n"); 602 } 603 604 return 0; 605 } 606 607 static int i915_wedged_get(void *data, u64 *val) 608 { 609 struct drm_i915_private *i915 = data; 610 struct intel_gt *gt; 611 unsigned int i; 612 613 *val = 0; 614 615 for_each_gt(gt, i915, i) { 616 int ret; 617 618 ret = intel_gt_debugfs_reset_show(gt, val); 619 if (ret) 620 return ret; 621 622 /* at least one tile should be wedged */ 623 if (*val) 624 break; 625 } 626 627 return 0; 628 } 629 630 static int i915_wedged_set(void *data, u64 val) 631 { 632 struct drm_i915_private *i915 = data; 633 struct intel_gt *gt; 634 unsigned int i; 635 636 for_each_gt(gt, i915, i) 637 intel_gt_debugfs_reset_store(gt, val); 638 639 return 0; 640 } 641 642 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 643 i915_wedged_get, i915_wedged_set, 644 "%llu\n"); 645 646 static int 647 i915_perf_noa_delay_set(void *data, u64 val) 648 { 649 struct drm_i915_private *i915 = data; 650 651 /* 652 * This would lead to infinite waits as we're doing timestamp 653 * difference on the CS with only 32bits. 654 */ 655 if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX) 656 return -EINVAL; 657 658 atomic64_set(&i915->perf.noa_programming_delay, val); 659 return 0; 660 } 661 662 static int 663 i915_perf_noa_delay_get(void *data, u64 *val) 664 { 665 struct drm_i915_private *i915 = data; 666 667 *val = atomic64_read(&i915->perf.noa_programming_delay); 668 return 0; 669 } 670 671 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops, 672 i915_perf_noa_delay_get, 673 i915_perf_noa_delay_set, 674 "%llu\n"); 675 676 #define DROP_UNBOUND BIT(0) 677 #define DROP_BOUND BIT(1) 678 #define DROP_RETIRE BIT(2) 679 #define DROP_ACTIVE BIT(3) 680 #define DROP_FREED BIT(4) 681 #define DROP_SHRINK_ALL BIT(5) 682 #define DROP_IDLE BIT(6) 683 #define DROP_RESET_ACTIVE BIT(7) 684 #define DROP_RESET_SEQNO BIT(8) 685 #define DROP_RCU BIT(9) 686 #define DROP_ALL (DROP_UNBOUND | \ 687 DROP_BOUND | \ 688 DROP_RETIRE | \ 689 DROP_ACTIVE | \ 690 DROP_FREED | \ 691 DROP_SHRINK_ALL |\ 692 DROP_IDLE | \ 693 DROP_RESET_ACTIVE | \ 694 DROP_RESET_SEQNO | \ 695 DROP_RCU) 696 static int 697 i915_drop_caches_get(void *data, u64 *val) 698 { 699 *val = DROP_ALL; 700 701 return 0; 702 } 703 704 static int 705 gt_drop_caches(struct intel_gt *gt, u64 val) 706 { 707 int ret; 708 709 if (val & DROP_RESET_ACTIVE && 710 wait_for(intel_engines_are_idle(gt), 200)) 711 intel_gt_set_wedged(gt); 712 713 if (val & DROP_RETIRE) 714 intel_gt_retire_requests(gt); 715 716 if (val & (DROP_IDLE | DROP_ACTIVE)) { 717 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT); 718 if (ret) 719 return ret; 720 } 721 722 if (val & DROP_IDLE) { 723 ret = intel_gt_pm_wait_for_idle(gt); 724 if (ret) 725 return ret; 726 } 727 728 if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt)) 729 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL); 730 731 if (val & DROP_FREED) 732 intel_gt_flush_buffer_pool(gt); 733 734 return 0; 735 } 736 737 static int 738 i915_drop_caches_set(void *data, u64 val) 739 { 740 struct drm_i915_private *i915 = data; 741 unsigned int flags; 742 int ret; 743 744 drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n", 745 val, val & DROP_ALL); 746 747 ret = gt_drop_caches(to_gt(i915), val); 748 if (ret) 749 return ret; 750 751 fs_reclaim_acquire(GFP_KERNEL); 752 flags = memalloc_noreclaim_save(); 753 if (val & DROP_BOUND) 754 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND); 755 756 if (val & DROP_UNBOUND) 757 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND); 758 759 if (val & DROP_SHRINK_ALL) 760 i915_gem_shrink_all(i915); 761 memalloc_noreclaim_restore(flags); 762 fs_reclaim_release(GFP_KERNEL); 763 764 if (val & DROP_RCU) 765 rcu_barrier(); 766 767 if (val & DROP_FREED) 768 i915_gem_drain_freed_objects(i915); 769 770 return 0; 771 } 772 773 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 774 i915_drop_caches_get, i915_drop_caches_set, 775 "0x%08llx\n"); 776 777 static int i915_sseu_status(struct seq_file *m, void *unused) 778 { 779 struct drm_i915_private *i915 = node_to_i915(m->private); 780 struct intel_gt *gt = to_gt(i915); 781 782 return intel_sseu_status(m, gt); 783 } 784 785 static int i915_forcewake_open(struct inode *inode, struct file *file) 786 { 787 struct drm_i915_private *i915 = inode->i_private; 788 struct intel_gt *gt; 789 unsigned int i; 790 791 for_each_gt(gt, i915, i) 792 intel_gt_pm_debugfs_forcewake_user_open(gt); 793 794 return 0; 795 } 796 797 static int i915_forcewake_release(struct inode *inode, struct file *file) 798 { 799 struct drm_i915_private *i915 = inode->i_private; 800 struct intel_gt *gt; 801 unsigned int i; 802 803 for_each_gt(gt, i915, i) 804 intel_gt_pm_debugfs_forcewake_user_release(gt); 805 806 return 0; 807 } 808 809 static const struct file_operations i915_forcewake_fops = { 810 .owner = THIS_MODULE, 811 .open = i915_forcewake_open, 812 .release = i915_forcewake_release, 813 }; 814 815 static const struct drm_info_list i915_debugfs_list[] = { 816 {"i915_capabilities", i915_capabilities, 0}, 817 {"i915_gem_objects", i915_gem_object_info, 0}, 818 {"i915_frequency_info", i915_frequency_info, 0}, 819 {"i915_swizzle_info", i915_swizzle_info, 0}, 820 {"i915_runtime_pm_status", i915_runtime_pm_status, 0}, 821 {"i915_engine_info", i915_engine_info, 0}, 822 {"i915_wa_registers", i915_wa_registers, 0}, 823 {"i915_sseu_status", i915_sseu_status, 0}, 824 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 825 }; 826 827 static const struct i915_debugfs_files { 828 const char *name; 829 const struct file_operations *fops; 830 } i915_debugfs_files[] = { 831 {"i915_perf_noa_delay", &i915_perf_noa_delay_fops}, 832 {"i915_wedged", &i915_wedged_fops}, 833 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 834 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 835 {"i915_error_state", &i915_error_state_fops}, 836 {"i915_gpu_info", &i915_gpu_info_fops}, 837 #endif 838 }; 839 840 void i915_debugfs_register(struct drm_i915_private *dev_priv) 841 { 842 struct drm_minor *minor = dev_priv->drm.primary; 843 int i; 844 845 i915_debugfs_params(dev_priv); 846 847 debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root, 848 to_i915(minor->dev), &i915_forcewake_fops); 849 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 850 debugfs_create_file(i915_debugfs_files[i].name, 851 S_IRUGO | S_IWUSR, 852 minor->debugfs_root, 853 to_i915(minor->dev), 854 i915_debugfs_files[i].fops); 855 } 856 857 drm_debugfs_create_files(i915_debugfs_list, 858 ARRAY_SIZE(i915_debugfs_list), 859 minor->debugfs_root, minor); 860 } 861