1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * 27 */ 28 29 #include <linux/seq_file.h> 30 #include <linux/circ_buf.h> 31 #include <linux/ctype.h> 32 #include <linux/debugfs.h> 33 #include <linux/slab.h> 34 #include <linux/export.h> 35 #include <linux/list_sort.h> 36 #include <asm/msr-index.h> 37 #include <drm/drmP.h> 38 #include "intel_drv.h" 39 #include "intel_ringbuffer.h" 40 #include <drm/i915_drm.h> 41 #include "i915_drv.h" 42 43 enum { 44 ACTIVE_LIST, 45 INACTIVE_LIST, 46 PINNED_LIST, 47 }; 48 49 static const char *yesno(int v) 50 { 51 return v ? "yes" : "no"; 52 } 53 54 /* As the drm_debugfs_init() routines are called before dev->dev_private is 55 * allocated we need to hook into the minor for release. */ 56 static int 57 drm_add_fake_info_node(struct drm_minor *minor, 58 struct dentry *ent, 59 const void *key) 60 { 61 struct drm_info_node *node; 62 63 node = kmalloc(sizeof(*node), GFP_KERNEL); 64 if (node == NULL) { 65 debugfs_remove(ent); 66 return -ENOMEM; 67 } 68 69 node->minor = minor; 70 node->dent = ent; 71 node->info_ent = (void *) key; 72 73 mutex_lock(&minor->debugfs_lock); 74 list_add(&node->list, &minor->debugfs_list); 75 mutex_unlock(&minor->debugfs_lock); 76 77 return 0; 78 } 79 80 static int i915_capabilities(struct seq_file *m, void *data) 81 { 82 struct drm_info_node *node = m->private; 83 struct drm_device *dev = node->minor->dev; 84 const struct intel_device_info *info = INTEL_INFO(dev); 85 86 seq_printf(m, "gen: %d\n", info->gen); 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); 88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) 89 #define SEP_SEMICOLON ; 90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON); 91 #undef PRINT_FLAG 92 #undef SEP_SEMICOLON 93 94 return 0; 95 } 96 97 static const char *get_pin_flag(struct drm_i915_gem_object *obj) 98 { 99 if (obj->pin_display) 100 return "p"; 101 else 102 return " "; 103 } 104 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj) 106 { 107 switch (obj->tiling_mode) { 108 default: 109 case I915_TILING_NONE: return " "; 110 case I915_TILING_X: return "X"; 111 case I915_TILING_Y: return "Y"; 112 } 113 } 114 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj) 116 { 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " "; 118 } 119 120 static void 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 122 { 123 struct drm_i915_private *dev_priv = to_i915(obj->base.dev); 124 struct intel_engine_cs *ring; 125 struct i915_vma *vma; 126 int pin_count = 0; 127 int i; 128 129 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ", 130 &obj->base, 131 obj->active ? "*" : " ", 132 get_pin_flag(obj), 133 get_tiling_flag(obj), 134 get_global_flag(obj), 135 obj->base.size / 1024, 136 obj->base.read_domains, 137 obj->base.write_domain); 138 for_each_ring(ring, dev_priv, i) 139 seq_printf(m, "%x ", 140 i915_gem_request_get_seqno(obj->last_read_req[i])); 141 seq_printf(m, "] %x %x%s%s%s", 142 i915_gem_request_get_seqno(obj->last_write_req), 143 i915_gem_request_get_seqno(obj->last_fenced_req), 144 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level), 145 obj->dirty ? " dirty" : "", 146 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 147 if (obj->base.name) 148 seq_printf(m, " (name: %d)", obj->base.name); 149 list_for_each_entry(vma, &obj->vma_list, vma_link) { 150 if (vma->pin_count > 0) 151 pin_count++; 152 } 153 seq_printf(m, " (pinned x %d)", pin_count); 154 if (obj->pin_display) 155 seq_printf(m, " (display)"); 156 if (obj->fence_reg != I915_FENCE_REG_NONE) 157 seq_printf(m, " (fence: %d)", obj->fence_reg); 158 list_for_each_entry(vma, &obj->vma_list, vma_link) { 159 if (!i915_is_ggtt(vma->vm)) 160 seq_puts(m, " (pp"); 161 else 162 seq_puts(m, " (g"); 163 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)", 164 vma->node.start, vma->node.size, 165 vma->ggtt_view.type); 166 } 167 if (obj->stolen) 168 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); 169 if (obj->pin_display || obj->fault_mappable) { 170 char s[3], *t = s; 171 if (obj->pin_display) 172 *t++ = 'p'; 173 if (obj->fault_mappable) 174 *t++ = 'f'; 175 *t = '\0'; 176 seq_printf(m, " (%s mappable)", s); 177 } 178 if (obj->last_write_req != NULL) 179 seq_printf(m, " (%s)", 180 i915_gem_request_get_ring(obj->last_write_req)->name); 181 if (obj->frontbuffer_bits) 182 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); 183 } 184 185 static void describe_ctx(struct seq_file *m, struct intel_context *ctx) 186 { 187 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i'); 188 seq_putc(m, ctx->remap_slice ? 'R' : 'r'); 189 seq_putc(m, ' '); 190 } 191 192 static int i915_gem_object_list_info(struct seq_file *m, void *data) 193 { 194 struct drm_info_node *node = m->private; 195 uintptr_t list = (uintptr_t) node->info_ent->data; 196 struct list_head *head; 197 struct drm_device *dev = node->minor->dev; 198 struct drm_i915_private *dev_priv = dev->dev_private; 199 struct i915_address_space *vm = &dev_priv->gtt.base; 200 struct i915_vma *vma; 201 size_t total_obj_size, total_gtt_size; 202 int count, ret; 203 204 ret = mutex_lock_interruptible(&dev->struct_mutex); 205 if (ret) 206 return ret; 207 208 /* FIXME: the user of this interface might want more than just GGTT */ 209 switch (list) { 210 case ACTIVE_LIST: 211 seq_puts(m, "Active:\n"); 212 head = &vm->active_list; 213 break; 214 case INACTIVE_LIST: 215 seq_puts(m, "Inactive:\n"); 216 head = &vm->inactive_list; 217 break; 218 default: 219 mutex_unlock(&dev->struct_mutex); 220 return -EINVAL; 221 } 222 223 total_obj_size = total_gtt_size = count = 0; 224 list_for_each_entry(vma, head, mm_list) { 225 seq_printf(m, " "); 226 describe_obj(m, vma->obj); 227 seq_printf(m, "\n"); 228 total_obj_size += vma->obj->base.size; 229 total_gtt_size += vma->node.size; 230 count++; 231 } 232 mutex_unlock(&dev->struct_mutex); 233 234 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 235 count, total_obj_size, total_gtt_size); 236 return 0; 237 } 238 239 static int obj_rank_by_stolen(void *priv, 240 struct list_head *A, struct list_head *B) 241 { 242 struct drm_i915_gem_object *a = 243 container_of(A, struct drm_i915_gem_object, obj_exec_link); 244 struct drm_i915_gem_object *b = 245 container_of(B, struct drm_i915_gem_object, obj_exec_link); 246 247 return a->stolen->start - b->stolen->start; 248 } 249 250 static int i915_gem_stolen_list_info(struct seq_file *m, void *data) 251 { 252 struct drm_info_node *node = m->private; 253 struct drm_device *dev = node->minor->dev; 254 struct drm_i915_private *dev_priv = dev->dev_private; 255 struct drm_i915_gem_object *obj; 256 size_t total_obj_size, total_gtt_size; 257 LIST_HEAD(stolen); 258 int count, ret; 259 260 ret = mutex_lock_interruptible(&dev->struct_mutex); 261 if (ret) 262 return ret; 263 264 total_obj_size = total_gtt_size = count = 0; 265 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 266 if (obj->stolen == NULL) 267 continue; 268 269 list_add(&obj->obj_exec_link, &stolen); 270 271 total_obj_size += obj->base.size; 272 total_gtt_size += i915_gem_obj_ggtt_size(obj); 273 count++; 274 } 275 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 276 if (obj->stolen == NULL) 277 continue; 278 279 list_add(&obj->obj_exec_link, &stolen); 280 281 total_obj_size += obj->base.size; 282 count++; 283 } 284 list_sort(NULL, &stolen, obj_rank_by_stolen); 285 seq_puts(m, "Stolen:\n"); 286 while (!list_empty(&stolen)) { 287 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link); 288 seq_puts(m, " "); 289 describe_obj(m, obj); 290 seq_putc(m, '\n'); 291 list_del_init(&obj->obj_exec_link); 292 } 293 mutex_unlock(&dev->struct_mutex); 294 295 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 296 count, total_obj_size, total_gtt_size); 297 return 0; 298 } 299 300 #define count_objects(list, member) do { \ 301 list_for_each_entry(obj, list, member) { \ 302 size += i915_gem_obj_ggtt_size(obj); \ 303 ++count; \ 304 if (obj->map_and_fenceable) { \ 305 mappable_size += i915_gem_obj_ggtt_size(obj); \ 306 ++mappable_count; \ 307 } \ 308 } \ 309 } while (0) 310 311 struct file_stats { 312 struct drm_i915_file_private *file_priv; 313 int count; 314 size_t total, unbound; 315 size_t global, shared; 316 size_t active, inactive; 317 }; 318 319 static int per_file_stats(int id, void *ptr, void *data) 320 { 321 struct drm_i915_gem_object *obj = ptr; 322 struct file_stats *stats = data; 323 struct i915_vma *vma; 324 325 stats->count++; 326 stats->total += obj->base.size; 327 328 if (obj->base.name || obj->base.dma_buf) 329 stats->shared += obj->base.size; 330 331 if (USES_FULL_PPGTT(obj->base.dev)) { 332 list_for_each_entry(vma, &obj->vma_list, vma_link) { 333 struct i915_hw_ppgtt *ppgtt; 334 335 if (!drm_mm_node_allocated(&vma->node)) 336 continue; 337 338 if (i915_is_ggtt(vma->vm)) { 339 stats->global += obj->base.size; 340 continue; 341 } 342 343 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base); 344 if (ppgtt->file_priv != stats->file_priv) 345 continue; 346 347 if (obj->active) /* XXX per-vma statistic */ 348 stats->active += obj->base.size; 349 else 350 stats->inactive += obj->base.size; 351 352 return 0; 353 } 354 } else { 355 if (i915_gem_obj_ggtt_bound(obj)) { 356 stats->global += obj->base.size; 357 if (obj->active) 358 stats->active += obj->base.size; 359 else 360 stats->inactive += obj->base.size; 361 return 0; 362 } 363 } 364 365 if (!list_empty(&obj->global_list)) 366 stats->unbound += obj->base.size; 367 368 return 0; 369 } 370 371 #define print_file_stats(m, name, stats) do { \ 372 if (stats.count) \ 373 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \ 374 name, \ 375 stats.count, \ 376 stats.total, \ 377 stats.active, \ 378 stats.inactive, \ 379 stats.global, \ 380 stats.shared, \ 381 stats.unbound); \ 382 } while (0) 383 384 static void print_batch_pool_stats(struct seq_file *m, 385 struct drm_i915_private *dev_priv) 386 { 387 struct drm_i915_gem_object *obj; 388 struct file_stats stats; 389 struct intel_engine_cs *ring; 390 int i, j; 391 392 memset(&stats, 0, sizeof(stats)); 393 394 for_each_ring(ring, dev_priv, i) { 395 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { 396 list_for_each_entry(obj, 397 &ring->batch_pool.cache_list[j], 398 batch_pool_link) 399 per_file_stats(0, obj, &stats); 400 } 401 } 402 403 print_file_stats(m, "[k]batch pool", stats); 404 } 405 406 #define count_vmas(list, member) do { \ 407 list_for_each_entry(vma, list, member) { \ 408 size += i915_gem_obj_ggtt_size(vma->obj); \ 409 ++count; \ 410 if (vma->obj->map_and_fenceable) { \ 411 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \ 412 ++mappable_count; \ 413 } \ 414 } \ 415 } while (0) 416 417 static int i915_gem_object_info(struct seq_file *m, void* data) 418 { 419 struct drm_info_node *node = m->private; 420 struct drm_device *dev = node->minor->dev; 421 struct drm_i915_private *dev_priv = dev->dev_private; 422 u32 count, mappable_count, purgeable_count; 423 size_t size, mappable_size, purgeable_size; 424 struct drm_i915_gem_object *obj; 425 struct i915_address_space *vm = &dev_priv->gtt.base; 426 struct drm_file *file; 427 struct i915_vma *vma; 428 int ret; 429 430 ret = mutex_lock_interruptible(&dev->struct_mutex); 431 if (ret) 432 return ret; 433 434 seq_printf(m, "%u objects, %zu bytes\n", 435 dev_priv->mm.object_count, 436 dev_priv->mm.object_memory); 437 438 size = count = mappable_size = mappable_count = 0; 439 count_objects(&dev_priv->mm.bound_list, global_list); 440 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", 441 count, mappable_count, size, mappable_size); 442 443 size = count = mappable_size = mappable_count = 0; 444 count_vmas(&vm->active_list, mm_list); 445 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", 446 count, mappable_count, size, mappable_size); 447 448 size = count = mappable_size = mappable_count = 0; 449 count_vmas(&vm->inactive_list, mm_list); 450 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", 451 count, mappable_count, size, mappable_size); 452 453 size = count = purgeable_size = purgeable_count = 0; 454 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { 455 size += obj->base.size, ++count; 456 if (obj->madv == I915_MADV_DONTNEED) 457 purgeable_size += obj->base.size, ++purgeable_count; 458 } 459 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); 460 461 size = count = mappable_size = mappable_count = 0; 462 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 463 if (obj->fault_mappable) { 464 size += i915_gem_obj_ggtt_size(obj); 465 ++count; 466 } 467 if (obj->pin_display) { 468 mappable_size += i915_gem_obj_ggtt_size(obj); 469 ++mappable_count; 470 } 471 if (obj->madv == I915_MADV_DONTNEED) { 472 purgeable_size += obj->base.size; 473 ++purgeable_count; 474 } 475 } 476 seq_printf(m, "%u purgeable objects, %zu bytes\n", 477 purgeable_count, purgeable_size); 478 seq_printf(m, "%u pinned mappable objects, %zu bytes\n", 479 mappable_count, mappable_size); 480 seq_printf(m, "%u fault mappable objects, %zu bytes\n", 481 count, size); 482 483 seq_printf(m, "%zu [%lu] gtt total\n", 484 dev_priv->gtt.base.total, 485 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start); 486 487 seq_putc(m, '\n'); 488 print_batch_pool_stats(m, dev_priv); 489 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 490 struct file_stats stats; 491 struct task_struct *task; 492 493 memset(&stats, 0, sizeof(stats)); 494 stats.file_priv = file->driver_priv; 495 spin_lock(&file->table_lock); 496 idr_for_each(&file->object_idr, per_file_stats, &stats); 497 spin_unlock(&file->table_lock); 498 /* 499 * Although we have a valid reference on file->pid, that does 500 * not guarantee that the task_struct who called get_pid() is 501 * still alive (e.g. get_pid(current) => fork() => exit()). 502 * Therefore, we need to protect this ->comm access using RCU. 503 */ 504 rcu_read_lock(); 505 task = pid_task(file->pid, PIDTYPE_PID); 506 print_file_stats(m, task ? task->comm : "<unknown>", stats); 507 rcu_read_unlock(); 508 } 509 510 mutex_unlock(&dev->struct_mutex); 511 512 return 0; 513 } 514 515 static int i915_gem_gtt_info(struct seq_file *m, void *data) 516 { 517 struct drm_info_node *node = m->private; 518 struct drm_device *dev = node->minor->dev; 519 uintptr_t list = (uintptr_t) node->info_ent->data; 520 struct drm_i915_private *dev_priv = dev->dev_private; 521 struct drm_i915_gem_object *obj; 522 size_t total_obj_size, total_gtt_size; 523 int count, ret; 524 525 ret = mutex_lock_interruptible(&dev->struct_mutex); 526 if (ret) 527 return ret; 528 529 total_obj_size = total_gtt_size = count = 0; 530 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 531 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj)) 532 continue; 533 534 seq_puts(m, " "); 535 describe_obj(m, obj); 536 seq_putc(m, '\n'); 537 total_obj_size += obj->base.size; 538 total_gtt_size += i915_gem_obj_ggtt_size(obj); 539 count++; 540 } 541 542 mutex_unlock(&dev->struct_mutex); 543 544 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", 545 count, total_obj_size, total_gtt_size); 546 547 return 0; 548 } 549 550 static int i915_gem_pageflip_info(struct seq_file *m, void *data) 551 { 552 struct drm_info_node *node = m->private; 553 struct drm_device *dev = node->minor->dev; 554 struct drm_i915_private *dev_priv = dev->dev_private; 555 struct intel_crtc *crtc; 556 int ret; 557 558 ret = mutex_lock_interruptible(&dev->struct_mutex); 559 if (ret) 560 return ret; 561 562 for_each_intel_crtc(dev, crtc) { 563 const char pipe = pipe_name(crtc->pipe); 564 const char plane = plane_name(crtc->plane); 565 struct intel_unpin_work *work; 566 567 spin_lock_irq(&dev->event_lock); 568 work = crtc->unpin_work; 569 if (work == NULL) { 570 seq_printf(m, "No flip due on pipe %c (plane %c)\n", 571 pipe, plane); 572 } else { 573 u32 addr; 574 575 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 576 seq_printf(m, "Flip queued on pipe %c (plane %c)\n", 577 pipe, plane); 578 } else { 579 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", 580 pipe, plane); 581 } 582 if (work->flip_queued_req) { 583 struct intel_engine_cs *ring = 584 i915_gem_request_get_ring(work->flip_queued_req); 585 586 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n", 587 ring->name, 588 i915_gem_request_get_seqno(work->flip_queued_req), 589 dev_priv->next_seqno, 590 ring->get_seqno(ring, true), 591 i915_gem_request_completed(work->flip_queued_req, true)); 592 } else 593 seq_printf(m, "Flip not associated with any ring\n"); 594 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", 595 work->flip_queued_vblank, 596 work->flip_ready_vblank, 597 drm_crtc_vblank_count(&crtc->base)); 598 if (work->enable_stall_check) 599 seq_puts(m, "Stall check enabled, "); 600 else 601 seq_puts(m, "Stall check waiting for page flip ioctl, "); 602 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); 603 604 if (INTEL_INFO(dev)->gen >= 4) 605 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); 606 else 607 addr = I915_READ(DSPADDR(crtc->plane)); 608 seq_printf(m, "Current scanout address 0x%08x\n", addr); 609 610 if (work->pending_flip_obj) { 611 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); 612 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); 613 } 614 } 615 spin_unlock_irq(&dev->event_lock); 616 } 617 618 mutex_unlock(&dev->struct_mutex); 619 620 return 0; 621 } 622 623 static int i915_gem_batch_pool_info(struct seq_file *m, void *data) 624 { 625 struct drm_info_node *node = m->private; 626 struct drm_device *dev = node->minor->dev; 627 struct drm_i915_private *dev_priv = dev->dev_private; 628 struct drm_i915_gem_object *obj; 629 struct intel_engine_cs *ring; 630 int total = 0; 631 int ret, i, j; 632 633 ret = mutex_lock_interruptible(&dev->struct_mutex); 634 if (ret) 635 return ret; 636 637 for_each_ring(ring, dev_priv, i) { 638 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) { 639 int count; 640 641 count = 0; 642 list_for_each_entry(obj, 643 &ring->batch_pool.cache_list[j], 644 batch_pool_link) 645 count++; 646 seq_printf(m, "%s cache[%d]: %d objects\n", 647 ring->name, j, count); 648 649 list_for_each_entry(obj, 650 &ring->batch_pool.cache_list[j], 651 batch_pool_link) { 652 seq_puts(m, " "); 653 describe_obj(m, obj); 654 seq_putc(m, '\n'); 655 } 656 657 total += count; 658 } 659 } 660 661 seq_printf(m, "total: %d\n", total); 662 663 mutex_unlock(&dev->struct_mutex); 664 665 return 0; 666 } 667 668 static int i915_gem_request_info(struct seq_file *m, void *data) 669 { 670 struct drm_info_node *node = m->private; 671 struct drm_device *dev = node->minor->dev; 672 struct drm_i915_private *dev_priv = dev->dev_private; 673 struct intel_engine_cs *ring; 674 struct drm_i915_gem_request *req; 675 int ret, any, i; 676 677 ret = mutex_lock_interruptible(&dev->struct_mutex); 678 if (ret) 679 return ret; 680 681 any = 0; 682 for_each_ring(ring, dev_priv, i) { 683 int count; 684 685 count = 0; 686 list_for_each_entry(req, &ring->request_list, list) 687 count++; 688 if (count == 0) 689 continue; 690 691 seq_printf(m, "%s requests: %d\n", ring->name, count); 692 list_for_each_entry(req, &ring->request_list, list) { 693 struct task_struct *task; 694 695 rcu_read_lock(); 696 task = NULL; 697 if (req->pid) 698 task = pid_task(req->pid, PIDTYPE_PID); 699 seq_printf(m, " %x @ %d: %s [%d]\n", 700 req->seqno, 701 (int) (jiffies - req->emitted_jiffies), 702 task ? task->comm : "<unknown>", 703 task ? task->pid : -1); 704 rcu_read_unlock(); 705 } 706 707 any++; 708 } 709 mutex_unlock(&dev->struct_mutex); 710 711 if (any == 0) 712 seq_puts(m, "No requests\n"); 713 714 return 0; 715 } 716 717 static void i915_ring_seqno_info(struct seq_file *m, 718 struct intel_engine_cs *ring) 719 { 720 if (ring->get_seqno) { 721 seq_printf(m, "Current sequence (%s): %x\n", 722 ring->name, ring->get_seqno(ring, false)); 723 } 724 } 725 726 static int i915_gem_seqno_info(struct seq_file *m, void *data) 727 { 728 struct drm_info_node *node = m->private; 729 struct drm_device *dev = node->minor->dev; 730 struct drm_i915_private *dev_priv = dev->dev_private; 731 struct intel_engine_cs *ring; 732 int ret, i; 733 734 ret = mutex_lock_interruptible(&dev->struct_mutex); 735 if (ret) 736 return ret; 737 intel_runtime_pm_get(dev_priv); 738 739 for_each_ring(ring, dev_priv, i) 740 i915_ring_seqno_info(m, ring); 741 742 intel_runtime_pm_put(dev_priv); 743 mutex_unlock(&dev->struct_mutex); 744 745 return 0; 746 } 747 748 749 static int i915_interrupt_info(struct seq_file *m, void *data) 750 { 751 struct drm_info_node *node = m->private; 752 struct drm_device *dev = node->minor->dev; 753 struct drm_i915_private *dev_priv = dev->dev_private; 754 struct intel_engine_cs *ring; 755 int ret, i, pipe; 756 757 ret = mutex_lock_interruptible(&dev->struct_mutex); 758 if (ret) 759 return ret; 760 intel_runtime_pm_get(dev_priv); 761 762 if (IS_CHERRYVIEW(dev)) { 763 seq_printf(m, "Master Interrupt Control:\t%08x\n", 764 I915_READ(GEN8_MASTER_IRQ)); 765 766 seq_printf(m, "Display IER:\t%08x\n", 767 I915_READ(VLV_IER)); 768 seq_printf(m, "Display IIR:\t%08x\n", 769 I915_READ(VLV_IIR)); 770 seq_printf(m, "Display IIR_RW:\t%08x\n", 771 I915_READ(VLV_IIR_RW)); 772 seq_printf(m, "Display IMR:\t%08x\n", 773 I915_READ(VLV_IMR)); 774 for_each_pipe(dev_priv, pipe) 775 seq_printf(m, "Pipe %c stat:\t%08x\n", 776 pipe_name(pipe), 777 I915_READ(PIPESTAT(pipe))); 778 779 seq_printf(m, "Port hotplug:\t%08x\n", 780 I915_READ(PORT_HOTPLUG_EN)); 781 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 782 I915_READ(VLV_DPFLIPSTAT)); 783 seq_printf(m, "DPINVGTT:\t%08x\n", 784 I915_READ(DPINVGTT)); 785 786 for (i = 0; i < 4; i++) { 787 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 788 i, I915_READ(GEN8_GT_IMR(i))); 789 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 790 i, I915_READ(GEN8_GT_IIR(i))); 791 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 792 i, I915_READ(GEN8_GT_IER(i))); 793 } 794 795 seq_printf(m, "PCU interrupt mask:\t%08x\n", 796 I915_READ(GEN8_PCU_IMR)); 797 seq_printf(m, "PCU interrupt identity:\t%08x\n", 798 I915_READ(GEN8_PCU_IIR)); 799 seq_printf(m, "PCU interrupt enable:\t%08x\n", 800 I915_READ(GEN8_PCU_IER)); 801 } else if (INTEL_INFO(dev)->gen >= 8) { 802 seq_printf(m, "Master Interrupt Control:\t%08x\n", 803 I915_READ(GEN8_MASTER_IRQ)); 804 805 for (i = 0; i < 4; i++) { 806 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", 807 i, I915_READ(GEN8_GT_IMR(i))); 808 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", 809 i, I915_READ(GEN8_GT_IIR(i))); 810 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", 811 i, I915_READ(GEN8_GT_IER(i))); 812 } 813 814 for_each_pipe(dev_priv, pipe) { 815 if (!intel_display_power_is_enabled(dev_priv, 816 POWER_DOMAIN_PIPE(pipe))) { 817 seq_printf(m, "Pipe %c power disabled\n", 818 pipe_name(pipe)); 819 continue; 820 } 821 seq_printf(m, "Pipe %c IMR:\t%08x\n", 822 pipe_name(pipe), 823 I915_READ(GEN8_DE_PIPE_IMR(pipe))); 824 seq_printf(m, "Pipe %c IIR:\t%08x\n", 825 pipe_name(pipe), 826 I915_READ(GEN8_DE_PIPE_IIR(pipe))); 827 seq_printf(m, "Pipe %c IER:\t%08x\n", 828 pipe_name(pipe), 829 I915_READ(GEN8_DE_PIPE_IER(pipe))); 830 } 831 832 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", 833 I915_READ(GEN8_DE_PORT_IMR)); 834 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", 835 I915_READ(GEN8_DE_PORT_IIR)); 836 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", 837 I915_READ(GEN8_DE_PORT_IER)); 838 839 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", 840 I915_READ(GEN8_DE_MISC_IMR)); 841 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", 842 I915_READ(GEN8_DE_MISC_IIR)); 843 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", 844 I915_READ(GEN8_DE_MISC_IER)); 845 846 seq_printf(m, "PCU interrupt mask:\t%08x\n", 847 I915_READ(GEN8_PCU_IMR)); 848 seq_printf(m, "PCU interrupt identity:\t%08x\n", 849 I915_READ(GEN8_PCU_IIR)); 850 seq_printf(m, "PCU interrupt enable:\t%08x\n", 851 I915_READ(GEN8_PCU_IER)); 852 } else if (IS_VALLEYVIEW(dev)) { 853 seq_printf(m, "Display IER:\t%08x\n", 854 I915_READ(VLV_IER)); 855 seq_printf(m, "Display IIR:\t%08x\n", 856 I915_READ(VLV_IIR)); 857 seq_printf(m, "Display IIR_RW:\t%08x\n", 858 I915_READ(VLV_IIR_RW)); 859 seq_printf(m, "Display IMR:\t%08x\n", 860 I915_READ(VLV_IMR)); 861 for_each_pipe(dev_priv, pipe) 862 seq_printf(m, "Pipe %c stat:\t%08x\n", 863 pipe_name(pipe), 864 I915_READ(PIPESTAT(pipe))); 865 866 seq_printf(m, "Master IER:\t%08x\n", 867 I915_READ(VLV_MASTER_IER)); 868 869 seq_printf(m, "Render IER:\t%08x\n", 870 I915_READ(GTIER)); 871 seq_printf(m, "Render IIR:\t%08x\n", 872 I915_READ(GTIIR)); 873 seq_printf(m, "Render IMR:\t%08x\n", 874 I915_READ(GTIMR)); 875 876 seq_printf(m, "PM IER:\t\t%08x\n", 877 I915_READ(GEN6_PMIER)); 878 seq_printf(m, "PM IIR:\t\t%08x\n", 879 I915_READ(GEN6_PMIIR)); 880 seq_printf(m, "PM IMR:\t\t%08x\n", 881 I915_READ(GEN6_PMIMR)); 882 883 seq_printf(m, "Port hotplug:\t%08x\n", 884 I915_READ(PORT_HOTPLUG_EN)); 885 seq_printf(m, "DPFLIPSTAT:\t%08x\n", 886 I915_READ(VLV_DPFLIPSTAT)); 887 seq_printf(m, "DPINVGTT:\t%08x\n", 888 I915_READ(DPINVGTT)); 889 890 } else if (!HAS_PCH_SPLIT(dev)) { 891 seq_printf(m, "Interrupt enable: %08x\n", 892 I915_READ(IER)); 893 seq_printf(m, "Interrupt identity: %08x\n", 894 I915_READ(IIR)); 895 seq_printf(m, "Interrupt mask: %08x\n", 896 I915_READ(IMR)); 897 for_each_pipe(dev_priv, pipe) 898 seq_printf(m, "Pipe %c stat: %08x\n", 899 pipe_name(pipe), 900 I915_READ(PIPESTAT(pipe))); 901 } else { 902 seq_printf(m, "North Display Interrupt enable: %08x\n", 903 I915_READ(DEIER)); 904 seq_printf(m, "North Display Interrupt identity: %08x\n", 905 I915_READ(DEIIR)); 906 seq_printf(m, "North Display Interrupt mask: %08x\n", 907 I915_READ(DEIMR)); 908 seq_printf(m, "South Display Interrupt enable: %08x\n", 909 I915_READ(SDEIER)); 910 seq_printf(m, "South Display Interrupt identity: %08x\n", 911 I915_READ(SDEIIR)); 912 seq_printf(m, "South Display Interrupt mask: %08x\n", 913 I915_READ(SDEIMR)); 914 seq_printf(m, "Graphics Interrupt enable: %08x\n", 915 I915_READ(GTIER)); 916 seq_printf(m, "Graphics Interrupt identity: %08x\n", 917 I915_READ(GTIIR)); 918 seq_printf(m, "Graphics Interrupt mask: %08x\n", 919 I915_READ(GTIMR)); 920 } 921 for_each_ring(ring, dev_priv, i) { 922 if (INTEL_INFO(dev)->gen >= 6) { 923 seq_printf(m, 924 "Graphics Interrupt mask (%s): %08x\n", 925 ring->name, I915_READ_IMR(ring)); 926 } 927 i915_ring_seqno_info(m, ring); 928 } 929 intel_runtime_pm_put(dev_priv); 930 mutex_unlock(&dev->struct_mutex); 931 932 return 0; 933 } 934 935 static int i915_gem_fence_regs_info(struct seq_file *m, void *data) 936 { 937 struct drm_info_node *node = m->private; 938 struct drm_device *dev = node->minor->dev; 939 struct drm_i915_private *dev_priv = dev->dev_private; 940 int i, ret; 941 942 ret = mutex_lock_interruptible(&dev->struct_mutex); 943 if (ret) 944 return ret; 945 946 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); 947 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); 948 for (i = 0; i < dev_priv->num_fence_regs; i++) { 949 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; 950 951 seq_printf(m, "Fence %d, pin count = %d, object = ", 952 i, dev_priv->fence_regs[i].pin_count); 953 if (obj == NULL) 954 seq_puts(m, "unused"); 955 else 956 describe_obj(m, obj); 957 seq_putc(m, '\n'); 958 } 959 960 mutex_unlock(&dev->struct_mutex); 961 return 0; 962 } 963 964 static int i915_hws_info(struct seq_file *m, void *data) 965 { 966 struct drm_info_node *node = m->private; 967 struct drm_device *dev = node->minor->dev; 968 struct drm_i915_private *dev_priv = dev->dev_private; 969 struct intel_engine_cs *ring; 970 const u32 *hws; 971 int i; 972 973 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data]; 974 hws = ring->status_page.page_addr; 975 if (hws == NULL) 976 return 0; 977 978 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) { 979 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", 980 i * 4, 981 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]); 982 } 983 return 0; 984 } 985 986 static ssize_t 987 i915_error_state_write(struct file *filp, 988 const char __user *ubuf, 989 size_t cnt, 990 loff_t *ppos) 991 { 992 struct i915_error_state_file_priv *error_priv = filp->private_data; 993 struct drm_device *dev = error_priv->dev; 994 int ret; 995 996 DRM_DEBUG_DRIVER("Resetting error state\n"); 997 998 ret = mutex_lock_interruptible(&dev->struct_mutex); 999 if (ret) 1000 return ret; 1001 1002 i915_destroy_error_state(dev); 1003 mutex_unlock(&dev->struct_mutex); 1004 1005 return cnt; 1006 } 1007 1008 static int i915_error_state_open(struct inode *inode, struct file *file) 1009 { 1010 struct drm_device *dev = inode->i_private; 1011 struct i915_error_state_file_priv *error_priv; 1012 1013 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL); 1014 if (!error_priv) 1015 return -ENOMEM; 1016 1017 error_priv->dev = dev; 1018 1019 i915_error_state_get(dev, error_priv); 1020 1021 file->private_data = error_priv; 1022 1023 return 0; 1024 } 1025 1026 static int i915_error_state_release(struct inode *inode, struct file *file) 1027 { 1028 struct i915_error_state_file_priv *error_priv = file->private_data; 1029 1030 i915_error_state_put(error_priv); 1031 kfree(error_priv); 1032 1033 return 0; 1034 } 1035 1036 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf, 1037 size_t count, loff_t *pos) 1038 { 1039 struct i915_error_state_file_priv *error_priv = file->private_data; 1040 struct drm_i915_error_state_buf error_str; 1041 loff_t tmp_pos = 0; 1042 ssize_t ret_count = 0; 1043 int ret; 1044 1045 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos); 1046 if (ret) 1047 return ret; 1048 1049 ret = i915_error_state_to_str(&error_str, error_priv); 1050 if (ret) 1051 goto out; 1052 1053 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos, 1054 error_str.buf, 1055 error_str.bytes); 1056 1057 if (ret_count < 0) 1058 ret = ret_count; 1059 else 1060 *pos = error_str.start + ret_count; 1061 out: 1062 i915_error_state_buf_release(&error_str); 1063 return ret ?: ret_count; 1064 } 1065 1066 static const struct file_operations i915_error_state_fops = { 1067 .owner = THIS_MODULE, 1068 .open = i915_error_state_open, 1069 .read = i915_error_state_read, 1070 .write = i915_error_state_write, 1071 .llseek = default_llseek, 1072 .release = i915_error_state_release, 1073 }; 1074 1075 static int 1076 i915_next_seqno_get(void *data, u64 *val) 1077 { 1078 struct drm_device *dev = data; 1079 struct drm_i915_private *dev_priv = dev->dev_private; 1080 int ret; 1081 1082 ret = mutex_lock_interruptible(&dev->struct_mutex); 1083 if (ret) 1084 return ret; 1085 1086 *val = dev_priv->next_seqno; 1087 mutex_unlock(&dev->struct_mutex); 1088 1089 return 0; 1090 } 1091 1092 static int 1093 i915_next_seqno_set(void *data, u64 val) 1094 { 1095 struct drm_device *dev = data; 1096 int ret; 1097 1098 ret = mutex_lock_interruptible(&dev->struct_mutex); 1099 if (ret) 1100 return ret; 1101 1102 ret = i915_gem_set_seqno(dev, val); 1103 mutex_unlock(&dev->struct_mutex); 1104 1105 return ret; 1106 } 1107 1108 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 1109 i915_next_seqno_get, i915_next_seqno_set, 1110 "0x%llx\n"); 1111 1112 static int i915_frequency_info(struct seq_file *m, void *unused) 1113 { 1114 struct drm_info_node *node = m->private; 1115 struct drm_device *dev = node->minor->dev; 1116 struct drm_i915_private *dev_priv = dev->dev_private; 1117 int ret = 0; 1118 1119 intel_runtime_pm_get(dev_priv); 1120 1121 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 1122 1123 if (IS_GEN5(dev)) { 1124 u16 rgvswctl = I915_READ16(MEMSWCTL); 1125 u16 rgvstat = I915_READ16(MEMSTAT_ILK); 1126 1127 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); 1128 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); 1129 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> 1130 MEMSTAT_VID_SHIFT); 1131 seq_printf(m, "Current P-state: %d\n", 1132 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT); 1133 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) || 1134 IS_BROADWELL(dev) || IS_GEN9(dev)) { 1135 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 1136 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); 1137 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 1138 u32 rpmodectl, rpinclimit, rpdeclimit; 1139 u32 rpstat, cagf, reqf; 1140 u32 rpupei, rpcurup, rpprevup; 1141 u32 rpdownei, rpcurdown, rpprevdown; 1142 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask; 1143 int max_freq; 1144 1145 /* RPSTAT1 is in the GT power well */ 1146 ret = mutex_lock_interruptible(&dev->struct_mutex); 1147 if (ret) 1148 goto out; 1149 1150 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 1151 1152 reqf = I915_READ(GEN6_RPNSWREQ); 1153 if (IS_GEN9(dev)) 1154 reqf >>= 23; 1155 else { 1156 reqf &= ~GEN6_TURBO_DISABLE; 1157 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1158 reqf >>= 24; 1159 else 1160 reqf >>= 25; 1161 } 1162 reqf = intel_gpu_freq(dev_priv, reqf); 1163 1164 rpmodectl = I915_READ(GEN6_RP_CONTROL); 1165 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); 1166 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD); 1167 1168 rpstat = I915_READ(GEN6_RPSTAT1); 1169 rpupei = I915_READ(GEN6_RP_CUR_UP_EI); 1170 rpcurup = I915_READ(GEN6_RP_CUR_UP); 1171 rpprevup = I915_READ(GEN6_RP_PREV_UP); 1172 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); 1173 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); 1174 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); 1175 if (IS_GEN9(dev)) 1176 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; 1177 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1178 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 1179 else 1180 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 1181 cagf = intel_gpu_freq(dev_priv, cagf); 1182 1183 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 1184 mutex_unlock(&dev->struct_mutex); 1185 1186 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1187 pm_ier = I915_READ(GEN6_PMIER); 1188 pm_imr = I915_READ(GEN6_PMIMR); 1189 pm_isr = I915_READ(GEN6_PMISR); 1190 pm_iir = I915_READ(GEN6_PMIIR); 1191 pm_mask = I915_READ(GEN6_PMINTRMSK); 1192 } else { 1193 pm_ier = I915_READ(GEN8_GT_IER(2)); 1194 pm_imr = I915_READ(GEN8_GT_IMR(2)); 1195 pm_isr = I915_READ(GEN8_GT_ISR(2)); 1196 pm_iir = I915_READ(GEN8_GT_IIR(2)); 1197 pm_mask = I915_READ(GEN6_PMINTRMSK); 1198 } 1199 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", 1200 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask); 1201 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 1202 seq_printf(m, "Render p-state ratio: %d\n", 1203 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8); 1204 seq_printf(m, "Render p-state VID: %d\n", 1205 gt_perf_status & 0xff); 1206 seq_printf(m, "Render p-state limit: %d\n", 1207 rp_state_limits & 0xff); 1208 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 1209 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); 1210 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); 1211 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); 1212 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); 1213 seq_printf(m, "CAGF: %dMHz\n", cagf); 1214 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & 1215 GEN6_CURICONT_MASK); 1216 seq_printf(m, "RP CUR UP: %dus\n", rpcurup & 1217 GEN6_CURBSYTAVG_MASK); 1218 seq_printf(m, "RP PREV UP: %dus\n", rpprevup & 1219 GEN6_CURBSYTAVG_MASK); 1220 seq_printf(m, "Up threshold: %d%%\n", 1221 dev_priv->rps.up_threshold); 1222 1223 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & 1224 GEN6_CURIAVG_MASK); 1225 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & 1226 GEN6_CURBSYTAVG_MASK); 1227 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & 1228 GEN6_CURBSYTAVG_MASK); 1229 seq_printf(m, "Down threshold: %d%%\n", 1230 dev_priv->rps.down_threshold); 1231 1232 max_freq = (rp_state_cap & 0xff0000) >> 16; 1233 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); 1234 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 1235 intel_gpu_freq(dev_priv, max_freq)); 1236 1237 max_freq = (rp_state_cap & 0xff00) >> 8; 1238 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); 1239 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 1240 intel_gpu_freq(dev_priv, max_freq)); 1241 1242 max_freq = rp_state_cap & 0xff; 1243 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1); 1244 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1245 intel_gpu_freq(dev_priv, max_freq)); 1246 seq_printf(m, "Max overclocked frequency: %dMHz\n", 1247 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1248 1249 seq_printf(m, "Current freq: %d MHz\n", 1250 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1251 seq_printf(m, "Actual freq: %d MHz\n", cagf); 1252 seq_printf(m, "Idle freq: %d MHz\n", 1253 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1254 seq_printf(m, "Min freq: %d MHz\n", 1255 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1256 seq_printf(m, "Max freq: %d MHz\n", 1257 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1258 seq_printf(m, 1259 "efficient (RPe) frequency: %d MHz\n", 1260 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1261 } else if (IS_VALLEYVIEW(dev)) { 1262 u32 freq_sts; 1263 1264 mutex_lock(&dev_priv->rps.hw_lock); 1265 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 1266 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 1267 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1268 1269 seq_printf(m, "actual GPU freq: %d MHz\n", 1270 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); 1271 1272 seq_printf(m, "current GPU freq: %d MHz\n", 1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); 1274 1275 seq_printf(m, "max GPU freq: %d MHz\n", 1276 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1277 1278 seq_printf(m, "min GPU freq: %d MHz\n", 1279 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1280 1281 seq_printf(m, "idle GPU freq: %d MHz\n", 1282 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); 1283 1284 seq_printf(m, 1285 "efficient (RPe) frequency: %d MHz\n", 1286 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1287 mutex_unlock(&dev_priv->rps.hw_lock); 1288 } else { 1289 seq_puts(m, "no P-state info available\n"); 1290 } 1291 1292 out: 1293 intel_runtime_pm_put(dev_priv); 1294 return ret; 1295 } 1296 1297 static int i915_hangcheck_info(struct seq_file *m, void *unused) 1298 { 1299 struct drm_info_node *node = m->private; 1300 struct drm_device *dev = node->minor->dev; 1301 struct drm_i915_private *dev_priv = dev->dev_private; 1302 struct intel_engine_cs *ring; 1303 u64 acthd[I915_NUM_RINGS]; 1304 u32 seqno[I915_NUM_RINGS]; 1305 int i; 1306 1307 if (!i915.enable_hangcheck) { 1308 seq_printf(m, "Hangcheck disabled\n"); 1309 return 0; 1310 } 1311 1312 intel_runtime_pm_get(dev_priv); 1313 1314 for_each_ring(ring, dev_priv, i) { 1315 seqno[i] = ring->get_seqno(ring, false); 1316 acthd[i] = intel_ring_get_active_head(ring); 1317 } 1318 1319 intel_runtime_pm_put(dev_priv); 1320 1321 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) { 1322 seq_printf(m, "Hangcheck active, fires in %dms\n", 1323 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires - 1324 jiffies)); 1325 } else 1326 seq_printf(m, "Hangcheck inactive\n"); 1327 1328 for_each_ring(ring, dev_priv, i) { 1329 seq_printf(m, "%s:\n", ring->name); 1330 seq_printf(m, "\tseqno = %x [current %x]\n", 1331 ring->hangcheck.seqno, seqno[i]); 1332 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", 1333 (long long)ring->hangcheck.acthd, 1334 (long long)acthd[i]); 1335 seq_printf(m, "\tmax ACTHD = 0x%08llx\n", 1336 (long long)ring->hangcheck.max_acthd); 1337 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); 1338 seq_printf(m, "\taction = %d\n", ring->hangcheck.action); 1339 } 1340 1341 return 0; 1342 } 1343 1344 static int ironlake_drpc_info(struct seq_file *m) 1345 { 1346 struct drm_info_node *node = m->private; 1347 struct drm_device *dev = node->minor->dev; 1348 struct drm_i915_private *dev_priv = dev->dev_private; 1349 u32 rgvmodectl, rstdbyctl; 1350 u16 crstandvid; 1351 int ret; 1352 1353 ret = mutex_lock_interruptible(&dev->struct_mutex); 1354 if (ret) 1355 return ret; 1356 intel_runtime_pm_get(dev_priv); 1357 1358 rgvmodectl = I915_READ(MEMMODECTL); 1359 rstdbyctl = I915_READ(RSTDBYCTL); 1360 crstandvid = I915_READ16(CRSTANDVID); 1361 1362 intel_runtime_pm_put(dev_priv); 1363 mutex_unlock(&dev->struct_mutex); 1364 1365 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? 1366 "yes" : "no"); 1367 seq_printf(m, "Boost freq: %d\n", 1368 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >> 1369 MEMMODE_BOOST_FREQ_SHIFT); 1370 seq_printf(m, "HW control enabled: %s\n", 1371 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no"); 1372 seq_printf(m, "SW control enabled: %s\n", 1373 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no"); 1374 seq_printf(m, "Gated voltage change: %s\n", 1375 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no"); 1376 seq_printf(m, "Starting frequency: P%d\n", 1377 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT); 1378 seq_printf(m, "Max P-state: P%d\n", 1379 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT); 1380 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); 1381 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); 1382 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); 1383 seq_printf(m, "Render standby enabled: %s\n", 1384 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes"); 1385 seq_puts(m, "Current RS state: "); 1386 switch (rstdbyctl & RSX_STATUS_MASK) { 1387 case RSX_STATUS_ON: 1388 seq_puts(m, "on\n"); 1389 break; 1390 case RSX_STATUS_RC1: 1391 seq_puts(m, "RC1\n"); 1392 break; 1393 case RSX_STATUS_RC1E: 1394 seq_puts(m, "RC1E\n"); 1395 break; 1396 case RSX_STATUS_RS1: 1397 seq_puts(m, "RS1\n"); 1398 break; 1399 case RSX_STATUS_RS2: 1400 seq_puts(m, "RS2 (RC6)\n"); 1401 break; 1402 case RSX_STATUS_RS3: 1403 seq_puts(m, "RC3 (RC6+)\n"); 1404 break; 1405 default: 1406 seq_puts(m, "unknown\n"); 1407 break; 1408 } 1409 1410 return 0; 1411 } 1412 1413 static int i915_forcewake_domains(struct seq_file *m, void *data) 1414 { 1415 struct drm_info_node *node = m->private; 1416 struct drm_device *dev = node->minor->dev; 1417 struct drm_i915_private *dev_priv = dev->dev_private; 1418 struct intel_uncore_forcewake_domain *fw_domain; 1419 int i; 1420 1421 spin_lock_irq(&dev_priv->uncore.lock); 1422 for_each_fw_domain(fw_domain, dev_priv, i) { 1423 seq_printf(m, "%s.wake_count = %u\n", 1424 intel_uncore_forcewake_domain_to_str(i), 1425 fw_domain->wake_count); 1426 } 1427 spin_unlock_irq(&dev_priv->uncore.lock); 1428 1429 return 0; 1430 } 1431 1432 static int vlv_drpc_info(struct seq_file *m) 1433 { 1434 struct drm_info_node *node = m->private; 1435 struct drm_device *dev = node->minor->dev; 1436 struct drm_i915_private *dev_priv = dev->dev_private; 1437 u32 rpmodectl1, rcctl1, pw_status; 1438 1439 intel_runtime_pm_get(dev_priv); 1440 1441 pw_status = I915_READ(VLV_GTLC_PW_STATUS); 1442 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1443 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1444 1445 intel_runtime_pm_put(dev_priv); 1446 1447 seq_printf(m, "Video Turbo Mode: %s\n", 1448 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1449 seq_printf(m, "Turbo enabled: %s\n", 1450 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1451 seq_printf(m, "HW control enabled: %s\n", 1452 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1453 seq_printf(m, "SW control enabled: %s\n", 1454 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1455 GEN6_RP_MEDIA_SW_MODE)); 1456 seq_printf(m, "RC6 Enabled: %s\n", 1457 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | 1458 GEN6_RC_CTL_EI_MODE(1)))); 1459 seq_printf(m, "Render Power Well: %s\n", 1460 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down"); 1461 seq_printf(m, "Media Power Well: %s\n", 1462 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down"); 1463 1464 seq_printf(m, "Render RC6 residency since boot: %u\n", 1465 I915_READ(VLV_GT_RENDER_RC6)); 1466 seq_printf(m, "Media RC6 residency since boot: %u\n", 1467 I915_READ(VLV_GT_MEDIA_RC6)); 1468 1469 return i915_forcewake_domains(m, NULL); 1470 } 1471 1472 static int gen6_drpc_info(struct seq_file *m) 1473 { 1474 struct drm_info_node *node = m->private; 1475 struct drm_device *dev = node->minor->dev; 1476 struct drm_i915_private *dev_priv = dev->dev_private; 1477 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0; 1478 unsigned forcewake_count; 1479 int count = 0, ret; 1480 1481 ret = mutex_lock_interruptible(&dev->struct_mutex); 1482 if (ret) 1483 return ret; 1484 intel_runtime_pm_get(dev_priv); 1485 1486 spin_lock_irq(&dev_priv->uncore.lock); 1487 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count; 1488 spin_unlock_irq(&dev_priv->uncore.lock); 1489 1490 if (forcewake_count) { 1491 seq_puts(m, "RC information inaccurate because somebody " 1492 "holds a forcewake reference \n"); 1493 } else { 1494 /* NB: we cannot use forcewake, else we read the wrong values */ 1495 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) 1496 udelay(10); 1497 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); 1498 } 1499 1500 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS); 1501 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); 1502 1503 rpmodectl1 = I915_READ(GEN6_RP_CONTROL); 1504 rcctl1 = I915_READ(GEN6_RC_CONTROL); 1505 mutex_unlock(&dev->struct_mutex); 1506 mutex_lock(&dev_priv->rps.hw_lock); 1507 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 1508 mutex_unlock(&dev_priv->rps.hw_lock); 1509 1510 intel_runtime_pm_put(dev_priv); 1511 1512 seq_printf(m, "Video Turbo Mode: %s\n", 1513 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO)); 1514 seq_printf(m, "HW control enabled: %s\n", 1515 yesno(rpmodectl1 & GEN6_RP_ENABLE)); 1516 seq_printf(m, "SW control enabled: %s\n", 1517 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) == 1518 GEN6_RP_MEDIA_SW_MODE)); 1519 seq_printf(m, "RC1e Enabled: %s\n", 1520 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); 1521 seq_printf(m, "RC6 Enabled: %s\n", 1522 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); 1523 seq_printf(m, "Deep RC6 Enabled: %s\n", 1524 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE)); 1525 seq_printf(m, "Deepest RC6 Enabled: %s\n", 1526 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE)); 1527 seq_puts(m, "Current RC state: "); 1528 switch (gt_core_status & GEN6_RCn_MASK) { 1529 case GEN6_RC0: 1530 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK) 1531 seq_puts(m, "Core Power Down\n"); 1532 else 1533 seq_puts(m, "on\n"); 1534 break; 1535 case GEN6_RC3: 1536 seq_puts(m, "RC3\n"); 1537 break; 1538 case GEN6_RC6: 1539 seq_puts(m, "RC6\n"); 1540 break; 1541 case GEN6_RC7: 1542 seq_puts(m, "RC7\n"); 1543 break; 1544 default: 1545 seq_puts(m, "Unknown\n"); 1546 break; 1547 } 1548 1549 seq_printf(m, "Core Power Down: %s\n", 1550 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); 1551 1552 /* Not exactly sure what this is */ 1553 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", 1554 I915_READ(GEN6_GT_GFX_RC6_LOCKED)); 1555 seq_printf(m, "RC6 residency since boot: %u\n", 1556 I915_READ(GEN6_GT_GFX_RC6)); 1557 seq_printf(m, "RC6+ residency since boot: %u\n", 1558 I915_READ(GEN6_GT_GFX_RC6p)); 1559 seq_printf(m, "RC6++ residency since boot: %u\n", 1560 I915_READ(GEN6_GT_GFX_RC6pp)); 1561 1562 seq_printf(m, "RC6 voltage: %dmV\n", 1563 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); 1564 seq_printf(m, "RC6+ voltage: %dmV\n", 1565 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff))); 1566 seq_printf(m, "RC6++ voltage: %dmV\n", 1567 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff))); 1568 return 0; 1569 } 1570 1571 static int i915_drpc_info(struct seq_file *m, void *unused) 1572 { 1573 struct drm_info_node *node = m->private; 1574 struct drm_device *dev = node->minor->dev; 1575 1576 if (IS_VALLEYVIEW(dev)) 1577 return vlv_drpc_info(m); 1578 else if (INTEL_INFO(dev)->gen >= 6) 1579 return gen6_drpc_info(m); 1580 else 1581 return ironlake_drpc_info(m); 1582 } 1583 1584 static int i915_fbc_status(struct seq_file *m, void *unused) 1585 { 1586 struct drm_info_node *node = m->private; 1587 struct drm_device *dev = node->minor->dev; 1588 struct drm_i915_private *dev_priv = dev->dev_private; 1589 1590 if (!HAS_FBC(dev)) { 1591 seq_puts(m, "FBC unsupported on this chipset\n"); 1592 return 0; 1593 } 1594 1595 intel_runtime_pm_get(dev_priv); 1596 1597 if (intel_fbc_enabled(dev)) { 1598 seq_puts(m, "FBC enabled\n"); 1599 } else { 1600 seq_puts(m, "FBC disabled: "); 1601 switch (dev_priv->fbc.no_fbc_reason) { 1602 case FBC_OK: 1603 seq_puts(m, "FBC actived, but currently disabled in hardware"); 1604 break; 1605 case FBC_UNSUPPORTED: 1606 seq_puts(m, "unsupported by this chipset"); 1607 break; 1608 case FBC_NO_OUTPUT: 1609 seq_puts(m, "no outputs"); 1610 break; 1611 case FBC_STOLEN_TOO_SMALL: 1612 seq_puts(m, "not enough stolen memory"); 1613 break; 1614 case FBC_UNSUPPORTED_MODE: 1615 seq_puts(m, "mode not supported"); 1616 break; 1617 case FBC_MODE_TOO_LARGE: 1618 seq_puts(m, "mode too large"); 1619 break; 1620 case FBC_BAD_PLANE: 1621 seq_puts(m, "FBC unsupported on plane"); 1622 break; 1623 case FBC_NOT_TILED: 1624 seq_puts(m, "scanout buffer not tiled"); 1625 break; 1626 case FBC_MULTIPLE_PIPES: 1627 seq_puts(m, "multiple pipes are enabled"); 1628 break; 1629 case FBC_MODULE_PARAM: 1630 seq_puts(m, "disabled per module param (default off)"); 1631 break; 1632 case FBC_CHIP_DEFAULT: 1633 seq_puts(m, "disabled per chip default"); 1634 break; 1635 default: 1636 seq_puts(m, "unknown reason"); 1637 } 1638 seq_putc(m, '\n'); 1639 } 1640 1641 intel_runtime_pm_put(dev_priv); 1642 1643 return 0; 1644 } 1645 1646 static int i915_fbc_fc_get(void *data, u64 *val) 1647 { 1648 struct drm_device *dev = data; 1649 struct drm_i915_private *dev_priv = dev->dev_private; 1650 1651 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) 1652 return -ENODEV; 1653 1654 drm_modeset_lock_all(dev); 1655 *val = dev_priv->fbc.false_color; 1656 drm_modeset_unlock_all(dev); 1657 1658 return 0; 1659 } 1660 1661 static int i915_fbc_fc_set(void *data, u64 val) 1662 { 1663 struct drm_device *dev = data; 1664 struct drm_i915_private *dev_priv = dev->dev_private; 1665 u32 reg; 1666 1667 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) 1668 return -ENODEV; 1669 1670 drm_modeset_lock_all(dev); 1671 1672 reg = I915_READ(ILK_DPFC_CONTROL); 1673 dev_priv->fbc.false_color = val; 1674 1675 I915_WRITE(ILK_DPFC_CONTROL, val ? 1676 (reg | FBC_CTL_FALSE_COLOR) : 1677 (reg & ~FBC_CTL_FALSE_COLOR)); 1678 1679 drm_modeset_unlock_all(dev); 1680 return 0; 1681 } 1682 1683 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops, 1684 i915_fbc_fc_get, i915_fbc_fc_set, 1685 "%llu\n"); 1686 1687 static int i915_ips_status(struct seq_file *m, void *unused) 1688 { 1689 struct drm_info_node *node = m->private; 1690 struct drm_device *dev = node->minor->dev; 1691 struct drm_i915_private *dev_priv = dev->dev_private; 1692 1693 if (!HAS_IPS(dev)) { 1694 seq_puts(m, "not supported\n"); 1695 return 0; 1696 } 1697 1698 intel_runtime_pm_get(dev_priv); 1699 1700 seq_printf(m, "Enabled by kernel parameter: %s\n", 1701 yesno(i915.enable_ips)); 1702 1703 if (INTEL_INFO(dev)->gen >= 8) { 1704 seq_puts(m, "Currently: unknown\n"); 1705 } else { 1706 if (I915_READ(IPS_CTL) & IPS_ENABLE) 1707 seq_puts(m, "Currently: enabled\n"); 1708 else 1709 seq_puts(m, "Currently: disabled\n"); 1710 } 1711 1712 intel_runtime_pm_put(dev_priv); 1713 1714 return 0; 1715 } 1716 1717 static int i915_sr_status(struct seq_file *m, void *unused) 1718 { 1719 struct drm_info_node *node = m->private; 1720 struct drm_device *dev = node->minor->dev; 1721 struct drm_i915_private *dev_priv = dev->dev_private; 1722 bool sr_enabled = false; 1723 1724 intel_runtime_pm_get(dev_priv); 1725 1726 if (HAS_PCH_SPLIT(dev)) 1727 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; 1728 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) 1729 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; 1730 else if (IS_I915GM(dev)) 1731 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; 1732 else if (IS_PINEVIEW(dev)) 1733 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; 1734 1735 intel_runtime_pm_put(dev_priv); 1736 1737 seq_printf(m, "self-refresh: %s\n", 1738 sr_enabled ? "enabled" : "disabled"); 1739 1740 return 0; 1741 } 1742 1743 static int i915_emon_status(struct seq_file *m, void *unused) 1744 { 1745 struct drm_info_node *node = m->private; 1746 struct drm_device *dev = node->minor->dev; 1747 struct drm_i915_private *dev_priv = dev->dev_private; 1748 unsigned long temp, chipset, gfx; 1749 int ret; 1750 1751 if (!IS_GEN5(dev)) 1752 return -ENODEV; 1753 1754 ret = mutex_lock_interruptible(&dev->struct_mutex); 1755 if (ret) 1756 return ret; 1757 1758 temp = i915_mch_val(dev_priv); 1759 chipset = i915_chipset_val(dev_priv); 1760 gfx = i915_gfx_val(dev_priv); 1761 mutex_unlock(&dev->struct_mutex); 1762 1763 seq_printf(m, "GMCH temp: %ld\n", temp); 1764 seq_printf(m, "Chipset power: %ld\n", chipset); 1765 seq_printf(m, "GFX power: %ld\n", gfx); 1766 seq_printf(m, "Total power: %ld\n", chipset + gfx); 1767 1768 return 0; 1769 } 1770 1771 static int i915_ring_freq_table(struct seq_file *m, void *unused) 1772 { 1773 struct drm_info_node *node = m->private; 1774 struct drm_device *dev = node->minor->dev; 1775 struct drm_i915_private *dev_priv = dev->dev_private; 1776 int ret = 0; 1777 int gpu_freq, ia_freq; 1778 1779 if (!(IS_GEN6(dev) || IS_GEN7(dev))) { 1780 seq_puts(m, "unsupported on this chipset\n"); 1781 return 0; 1782 } 1783 1784 intel_runtime_pm_get(dev_priv); 1785 1786 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 1787 1788 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 1789 if (ret) 1790 goto out; 1791 1792 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n"); 1793 1794 for (gpu_freq = dev_priv->rps.min_freq_softlimit; 1795 gpu_freq <= dev_priv->rps.max_freq_softlimit; 1796 gpu_freq++) { 1797 ia_freq = gpu_freq; 1798 sandybridge_pcode_read(dev_priv, 1799 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1800 &ia_freq); 1801 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 1802 intel_gpu_freq(dev_priv, gpu_freq), 1803 ((ia_freq >> 0) & 0xff) * 100, 1804 ((ia_freq >> 8) & 0xff) * 100); 1805 } 1806 1807 mutex_unlock(&dev_priv->rps.hw_lock); 1808 1809 out: 1810 intel_runtime_pm_put(dev_priv); 1811 return ret; 1812 } 1813 1814 static int i915_opregion(struct seq_file *m, void *unused) 1815 { 1816 struct drm_info_node *node = m->private; 1817 struct drm_device *dev = node->minor->dev; 1818 struct drm_i915_private *dev_priv = dev->dev_private; 1819 struct intel_opregion *opregion = &dev_priv->opregion; 1820 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL); 1821 int ret; 1822 1823 if (data == NULL) 1824 return -ENOMEM; 1825 1826 ret = mutex_lock_interruptible(&dev->struct_mutex); 1827 if (ret) 1828 goto out; 1829 1830 if (opregion->header) { 1831 memcpy_fromio(data, opregion->header, OPREGION_SIZE); 1832 seq_write(m, data, OPREGION_SIZE); 1833 } 1834 1835 mutex_unlock(&dev->struct_mutex); 1836 1837 out: 1838 kfree(data); 1839 return 0; 1840 } 1841 1842 static int i915_gem_framebuffer_info(struct seq_file *m, void *data) 1843 { 1844 struct drm_info_node *node = m->private; 1845 struct drm_device *dev = node->minor->dev; 1846 struct intel_fbdev *ifbdev = NULL; 1847 struct intel_framebuffer *fb; 1848 1849 #ifdef CONFIG_DRM_I915_FBDEV 1850 struct drm_i915_private *dev_priv = dev->dev_private; 1851 1852 ifbdev = dev_priv->fbdev; 1853 fb = to_intel_framebuffer(ifbdev->helper.fb); 1854 1855 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1856 fb->base.width, 1857 fb->base.height, 1858 fb->base.depth, 1859 fb->base.bits_per_pixel, 1860 fb->base.modifier[0], 1861 atomic_read(&fb->base.refcount.refcount)); 1862 describe_obj(m, fb->obj); 1863 seq_putc(m, '\n'); 1864 #endif 1865 1866 mutex_lock(&dev->mode_config.fb_lock); 1867 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) { 1868 if (ifbdev && &fb->base == ifbdev->helper.fb) 1869 continue; 1870 1871 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", 1872 fb->base.width, 1873 fb->base.height, 1874 fb->base.depth, 1875 fb->base.bits_per_pixel, 1876 fb->base.modifier[0], 1877 atomic_read(&fb->base.refcount.refcount)); 1878 describe_obj(m, fb->obj); 1879 seq_putc(m, '\n'); 1880 } 1881 mutex_unlock(&dev->mode_config.fb_lock); 1882 1883 return 0; 1884 } 1885 1886 static void describe_ctx_ringbuf(struct seq_file *m, 1887 struct intel_ringbuffer *ringbuf) 1888 { 1889 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", 1890 ringbuf->space, ringbuf->head, ringbuf->tail, 1891 ringbuf->last_retired_head); 1892 } 1893 1894 static int i915_context_status(struct seq_file *m, void *unused) 1895 { 1896 struct drm_info_node *node = m->private; 1897 struct drm_device *dev = node->minor->dev; 1898 struct drm_i915_private *dev_priv = dev->dev_private; 1899 struct intel_engine_cs *ring; 1900 struct intel_context *ctx; 1901 int ret, i; 1902 1903 ret = mutex_lock_interruptible(&dev->struct_mutex); 1904 if (ret) 1905 return ret; 1906 1907 list_for_each_entry(ctx, &dev_priv->context_list, link) { 1908 if (!i915.enable_execlists && 1909 ctx->legacy_hw_ctx.rcs_state == NULL) 1910 continue; 1911 1912 seq_puts(m, "HW context "); 1913 describe_ctx(m, ctx); 1914 for_each_ring(ring, dev_priv, i) { 1915 if (ring->default_context == ctx) 1916 seq_printf(m, "(default context %s) ", 1917 ring->name); 1918 } 1919 1920 if (i915.enable_execlists) { 1921 seq_putc(m, '\n'); 1922 for_each_ring(ring, dev_priv, i) { 1923 struct drm_i915_gem_object *ctx_obj = 1924 ctx->engine[i].state; 1925 struct intel_ringbuffer *ringbuf = 1926 ctx->engine[i].ringbuf; 1927 1928 seq_printf(m, "%s: ", ring->name); 1929 if (ctx_obj) 1930 describe_obj(m, ctx_obj); 1931 if (ringbuf) 1932 describe_ctx_ringbuf(m, ringbuf); 1933 seq_putc(m, '\n'); 1934 } 1935 } else { 1936 describe_obj(m, ctx->legacy_hw_ctx.rcs_state); 1937 } 1938 1939 seq_putc(m, '\n'); 1940 } 1941 1942 mutex_unlock(&dev->struct_mutex); 1943 1944 return 0; 1945 } 1946 1947 static void i915_dump_lrc_obj(struct seq_file *m, 1948 struct intel_engine_cs *ring, 1949 struct drm_i915_gem_object *ctx_obj) 1950 { 1951 struct page *page; 1952 uint32_t *reg_state; 1953 int j; 1954 unsigned long ggtt_offset = 0; 1955 1956 if (ctx_obj == NULL) { 1957 seq_printf(m, "Context on %s with no gem object\n", 1958 ring->name); 1959 return; 1960 } 1961 1962 seq_printf(m, "CONTEXT: %s %u\n", ring->name, 1963 intel_execlists_ctx_id(ctx_obj)); 1964 1965 if (!i915_gem_obj_ggtt_bound(ctx_obj)) 1966 seq_puts(m, "\tNot bound in GGTT\n"); 1967 else 1968 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); 1969 1970 if (i915_gem_object_get_pages(ctx_obj)) { 1971 seq_puts(m, "\tFailed to get pages for context object\n"); 1972 return; 1973 } 1974 1975 page = i915_gem_object_get_page(ctx_obj, 1); 1976 if (!WARN_ON(page == NULL)) { 1977 reg_state = kmap_atomic(page); 1978 1979 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) { 1980 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", 1981 ggtt_offset + 4096 + (j * 4), 1982 reg_state[j], reg_state[j + 1], 1983 reg_state[j + 2], reg_state[j + 3]); 1984 } 1985 kunmap_atomic(reg_state); 1986 } 1987 1988 seq_putc(m, '\n'); 1989 } 1990 1991 static int i915_dump_lrc(struct seq_file *m, void *unused) 1992 { 1993 struct drm_info_node *node = (struct drm_info_node *) m->private; 1994 struct drm_device *dev = node->minor->dev; 1995 struct drm_i915_private *dev_priv = dev->dev_private; 1996 struct intel_engine_cs *ring; 1997 struct intel_context *ctx; 1998 int ret, i; 1999 2000 if (!i915.enable_execlists) { 2001 seq_printf(m, "Logical Ring Contexts are disabled\n"); 2002 return 0; 2003 } 2004 2005 ret = mutex_lock_interruptible(&dev->struct_mutex); 2006 if (ret) 2007 return ret; 2008 2009 list_for_each_entry(ctx, &dev_priv->context_list, link) { 2010 for_each_ring(ring, dev_priv, i) { 2011 if (ring->default_context != ctx) 2012 i915_dump_lrc_obj(m, ring, 2013 ctx->engine[i].state); 2014 } 2015 } 2016 2017 mutex_unlock(&dev->struct_mutex); 2018 2019 return 0; 2020 } 2021 2022 static int i915_execlists(struct seq_file *m, void *data) 2023 { 2024 struct drm_info_node *node = (struct drm_info_node *)m->private; 2025 struct drm_device *dev = node->minor->dev; 2026 struct drm_i915_private *dev_priv = dev->dev_private; 2027 struct intel_engine_cs *ring; 2028 u32 status_pointer; 2029 u8 read_pointer; 2030 u8 write_pointer; 2031 u32 status; 2032 u32 ctx_id; 2033 struct list_head *cursor; 2034 int ring_id, i; 2035 int ret; 2036 2037 if (!i915.enable_execlists) { 2038 seq_puts(m, "Logical Ring Contexts are disabled\n"); 2039 return 0; 2040 } 2041 2042 ret = mutex_lock_interruptible(&dev->struct_mutex); 2043 if (ret) 2044 return ret; 2045 2046 intel_runtime_pm_get(dev_priv); 2047 2048 for_each_ring(ring, dev_priv, ring_id) { 2049 struct drm_i915_gem_request *head_req = NULL; 2050 int count = 0; 2051 unsigned long flags; 2052 2053 seq_printf(m, "%s\n", ring->name); 2054 2055 status = I915_READ(RING_EXECLIST_STATUS(ring)); 2056 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4); 2057 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", 2058 status, ctx_id); 2059 2060 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 2061 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); 2062 2063 read_pointer = ring->next_context_status_buffer; 2064 write_pointer = status_pointer & 0x07; 2065 if (read_pointer > write_pointer) 2066 write_pointer += 6; 2067 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", 2068 read_pointer, write_pointer); 2069 2070 for (i = 0; i < 6; i++) { 2071 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i); 2072 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4); 2073 2074 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", 2075 i, status, ctx_id); 2076 } 2077 2078 spin_lock_irqsave(&ring->execlist_lock, flags); 2079 list_for_each(cursor, &ring->execlist_queue) 2080 count++; 2081 head_req = list_first_entry_or_null(&ring->execlist_queue, 2082 struct drm_i915_gem_request, execlist_link); 2083 spin_unlock_irqrestore(&ring->execlist_lock, flags); 2084 2085 seq_printf(m, "\t%d requests in queue\n", count); 2086 if (head_req) { 2087 struct drm_i915_gem_object *ctx_obj; 2088 2089 ctx_obj = head_req->ctx->engine[ring_id].state; 2090 seq_printf(m, "\tHead request id: %u\n", 2091 intel_execlists_ctx_id(ctx_obj)); 2092 seq_printf(m, "\tHead request tail: %u\n", 2093 head_req->tail); 2094 } 2095 2096 seq_putc(m, '\n'); 2097 } 2098 2099 intel_runtime_pm_put(dev_priv); 2100 mutex_unlock(&dev->struct_mutex); 2101 2102 return 0; 2103 } 2104 2105 static const char *swizzle_string(unsigned swizzle) 2106 { 2107 switch (swizzle) { 2108 case I915_BIT_6_SWIZZLE_NONE: 2109 return "none"; 2110 case I915_BIT_6_SWIZZLE_9: 2111 return "bit9"; 2112 case I915_BIT_6_SWIZZLE_9_10: 2113 return "bit9/bit10"; 2114 case I915_BIT_6_SWIZZLE_9_11: 2115 return "bit9/bit11"; 2116 case I915_BIT_6_SWIZZLE_9_10_11: 2117 return "bit9/bit10/bit11"; 2118 case I915_BIT_6_SWIZZLE_9_17: 2119 return "bit9/bit17"; 2120 case I915_BIT_6_SWIZZLE_9_10_17: 2121 return "bit9/bit10/bit17"; 2122 case I915_BIT_6_SWIZZLE_UNKNOWN: 2123 return "unknown"; 2124 } 2125 2126 return "bug"; 2127 } 2128 2129 static int i915_swizzle_info(struct seq_file *m, void *data) 2130 { 2131 struct drm_info_node *node = m->private; 2132 struct drm_device *dev = node->minor->dev; 2133 struct drm_i915_private *dev_priv = dev->dev_private; 2134 int ret; 2135 2136 ret = mutex_lock_interruptible(&dev->struct_mutex); 2137 if (ret) 2138 return ret; 2139 intel_runtime_pm_get(dev_priv); 2140 2141 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", 2142 swizzle_string(dev_priv->mm.bit_6_swizzle_x)); 2143 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", 2144 swizzle_string(dev_priv->mm.bit_6_swizzle_y)); 2145 2146 if (IS_GEN3(dev) || IS_GEN4(dev)) { 2147 seq_printf(m, "DDC = 0x%08x\n", 2148 I915_READ(DCC)); 2149 seq_printf(m, "DDC2 = 0x%08x\n", 2150 I915_READ(DCC2)); 2151 seq_printf(m, "C0DRB3 = 0x%04x\n", 2152 I915_READ16(C0DRB3)); 2153 seq_printf(m, "C1DRB3 = 0x%04x\n", 2154 I915_READ16(C1DRB3)); 2155 } else if (INTEL_INFO(dev)->gen >= 6) { 2156 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", 2157 I915_READ(MAD_DIMM_C0)); 2158 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", 2159 I915_READ(MAD_DIMM_C1)); 2160 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", 2161 I915_READ(MAD_DIMM_C2)); 2162 seq_printf(m, "TILECTL = 0x%08x\n", 2163 I915_READ(TILECTL)); 2164 if (INTEL_INFO(dev)->gen >= 8) 2165 seq_printf(m, "GAMTARBMODE = 0x%08x\n", 2166 I915_READ(GAMTARBMODE)); 2167 else 2168 seq_printf(m, "ARB_MODE = 0x%08x\n", 2169 I915_READ(ARB_MODE)); 2170 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", 2171 I915_READ(DISP_ARB_CTL)); 2172 } 2173 2174 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 2175 seq_puts(m, "L-shaped memory detected\n"); 2176 2177 intel_runtime_pm_put(dev_priv); 2178 mutex_unlock(&dev->struct_mutex); 2179 2180 return 0; 2181 } 2182 2183 static int per_file_ctx(int id, void *ptr, void *data) 2184 { 2185 struct intel_context *ctx = ptr; 2186 struct seq_file *m = data; 2187 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 2188 2189 if (!ppgtt) { 2190 seq_printf(m, " no ppgtt for context %d\n", 2191 ctx->user_handle); 2192 return 0; 2193 } 2194 2195 if (i915_gem_context_is_default(ctx)) 2196 seq_puts(m, " default context:\n"); 2197 else 2198 seq_printf(m, " context %d:\n", ctx->user_handle); 2199 ppgtt->debug_dump(ppgtt, m); 2200 2201 return 0; 2202 } 2203 2204 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev) 2205 { 2206 struct drm_i915_private *dev_priv = dev->dev_private; 2207 struct intel_engine_cs *ring; 2208 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2209 int unused, i; 2210 2211 if (!ppgtt) 2212 return; 2213 2214 for_each_ring(ring, dev_priv, unused) { 2215 seq_printf(m, "%s\n", ring->name); 2216 for (i = 0; i < 4; i++) { 2217 u32 offset = 0x270 + i * 8; 2218 u64 pdp = I915_READ(ring->mmio_base + offset + 4); 2219 pdp <<= 32; 2220 pdp |= I915_READ(ring->mmio_base + offset); 2221 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); 2222 } 2223 } 2224 } 2225 2226 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) 2227 { 2228 struct drm_i915_private *dev_priv = dev->dev_private; 2229 struct intel_engine_cs *ring; 2230 struct drm_file *file; 2231 int i; 2232 2233 if (INTEL_INFO(dev)->gen == 6) 2234 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); 2235 2236 for_each_ring(ring, dev_priv, i) { 2237 seq_printf(m, "%s\n", ring->name); 2238 if (INTEL_INFO(dev)->gen == 7) 2239 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); 2240 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); 2241 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); 2242 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); 2243 } 2244 if (dev_priv->mm.aliasing_ppgtt) { 2245 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2246 2247 seq_puts(m, "aliasing PPGTT:\n"); 2248 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset); 2249 2250 ppgtt->debug_dump(ppgtt, m); 2251 } 2252 2253 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2254 struct drm_i915_file_private *file_priv = file->driver_priv; 2255 2256 seq_printf(m, "proc: %s\n", 2257 get_pid_task(file->pid, PIDTYPE_PID)->comm); 2258 idr_for_each(&file_priv->context_idr, per_file_ctx, m); 2259 } 2260 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); 2261 } 2262 2263 static int i915_ppgtt_info(struct seq_file *m, void *data) 2264 { 2265 struct drm_info_node *node = m->private; 2266 struct drm_device *dev = node->minor->dev; 2267 struct drm_i915_private *dev_priv = dev->dev_private; 2268 2269 int ret = mutex_lock_interruptible(&dev->struct_mutex); 2270 if (ret) 2271 return ret; 2272 intel_runtime_pm_get(dev_priv); 2273 2274 if (INTEL_INFO(dev)->gen >= 8) 2275 gen8_ppgtt_info(m, dev); 2276 else if (INTEL_INFO(dev)->gen >= 6) 2277 gen6_ppgtt_info(m, dev); 2278 2279 intel_runtime_pm_put(dev_priv); 2280 mutex_unlock(&dev->struct_mutex); 2281 2282 return 0; 2283 } 2284 2285 static int count_irq_waiters(struct drm_i915_private *i915) 2286 { 2287 struct intel_engine_cs *ring; 2288 int count = 0; 2289 int i; 2290 2291 for_each_ring(ring, i915, i) 2292 count += ring->irq_refcount; 2293 2294 return count; 2295 } 2296 2297 static int i915_rps_boost_info(struct seq_file *m, void *data) 2298 { 2299 struct drm_info_node *node = m->private; 2300 struct drm_device *dev = node->minor->dev; 2301 struct drm_i915_private *dev_priv = dev->dev_private; 2302 struct drm_file *file; 2303 2304 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); 2305 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); 2306 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv)); 2307 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n", 2308 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 2309 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 2310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), 2311 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), 2312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 2313 spin_lock(&dev_priv->rps.client_lock); 2314 list_for_each_entry_reverse(file, &dev->filelist, lhead) { 2315 struct drm_i915_file_private *file_priv = file->driver_priv; 2316 struct task_struct *task; 2317 2318 rcu_read_lock(); 2319 task = pid_task(file->pid, PIDTYPE_PID); 2320 seq_printf(m, "%s [%d]: %d boosts%s\n", 2321 task ? task->comm : "<unknown>", 2322 task ? task->pid : -1, 2323 file_priv->rps.boosts, 2324 list_empty(&file_priv->rps.link) ? "" : ", active"); 2325 rcu_read_unlock(); 2326 } 2327 seq_printf(m, "Semaphore boosts: %d%s\n", 2328 dev_priv->rps.semaphores.boosts, 2329 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active"); 2330 seq_printf(m, "MMIO flip boosts: %d%s\n", 2331 dev_priv->rps.mmioflips.boosts, 2332 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); 2333 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); 2334 spin_unlock(&dev_priv->rps.client_lock); 2335 2336 return 0; 2337 } 2338 2339 static int i915_llc(struct seq_file *m, void *data) 2340 { 2341 struct drm_info_node *node = m->private; 2342 struct drm_device *dev = node->minor->dev; 2343 struct drm_i915_private *dev_priv = dev->dev_private; 2344 2345 /* Size calculation for LLC is a bit of a pain. Ignore for now. */ 2346 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); 2347 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); 2348 2349 return 0; 2350 } 2351 2352 static int i915_edp_psr_status(struct seq_file *m, void *data) 2353 { 2354 struct drm_info_node *node = m->private; 2355 struct drm_device *dev = node->minor->dev; 2356 struct drm_i915_private *dev_priv = dev->dev_private; 2357 u32 psrperf = 0; 2358 u32 stat[3]; 2359 enum pipe pipe; 2360 bool enabled = false; 2361 2362 if (!HAS_PSR(dev)) { 2363 seq_puts(m, "PSR not supported\n"); 2364 return 0; 2365 } 2366 2367 intel_runtime_pm_get(dev_priv); 2368 2369 mutex_lock(&dev_priv->psr.lock); 2370 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); 2371 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); 2372 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); 2373 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); 2374 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", 2375 dev_priv->psr.busy_frontbuffer_bits); 2376 seq_printf(m, "Re-enable work scheduled: %s\n", 2377 yesno(work_busy(&dev_priv->psr.work.work))); 2378 2379 if (HAS_DDI(dev)) 2380 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 2381 else { 2382 for_each_pipe(dev_priv, pipe) { 2383 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) & 2384 VLV_EDP_PSR_CURR_STATE_MASK; 2385 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2386 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2387 enabled = true; 2388 } 2389 } 2390 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); 2391 2392 if (!HAS_DDI(dev)) 2393 for_each_pipe(dev_priv, pipe) { 2394 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 2395 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE)) 2396 seq_printf(m, " pipe %c", pipe_name(pipe)); 2397 } 2398 seq_puts(m, "\n"); 2399 2400 /* CHV PSR has no kind of performance counter */ 2401 if (HAS_DDI(dev)) { 2402 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) & 2403 EDP_PSR_PERF_CNT_MASK; 2404 2405 seq_printf(m, "Performance_Counter: %u\n", psrperf); 2406 } 2407 mutex_unlock(&dev_priv->psr.lock); 2408 2409 intel_runtime_pm_put(dev_priv); 2410 return 0; 2411 } 2412 2413 static int i915_sink_crc(struct seq_file *m, void *data) 2414 { 2415 struct drm_info_node *node = m->private; 2416 struct drm_device *dev = node->minor->dev; 2417 struct intel_encoder *encoder; 2418 struct intel_connector *connector; 2419 struct intel_dp *intel_dp = NULL; 2420 int ret; 2421 u8 crc[6]; 2422 2423 drm_modeset_lock_all(dev); 2424 for_each_intel_connector(dev, connector) { 2425 2426 if (connector->base.dpms != DRM_MODE_DPMS_ON) 2427 continue; 2428 2429 if (!connector->base.encoder) 2430 continue; 2431 2432 encoder = to_intel_encoder(connector->base.encoder); 2433 if (encoder->type != INTEL_OUTPUT_EDP) 2434 continue; 2435 2436 intel_dp = enc_to_intel_dp(&encoder->base); 2437 2438 ret = intel_dp_sink_crc(intel_dp, crc); 2439 if (ret) 2440 goto out; 2441 2442 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", 2443 crc[0], crc[1], crc[2], 2444 crc[3], crc[4], crc[5]); 2445 goto out; 2446 } 2447 ret = -ENODEV; 2448 out: 2449 drm_modeset_unlock_all(dev); 2450 return ret; 2451 } 2452 2453 static int i915_energy_uJ(struct seq_file *m, void *data) 2454 { 2455 struct drm_info_node *node = m->private; 2456 struct drm_device *dev = node->minor->dev; 2457 struct drm_i915_private *dev_priv = dev->dev_private; 2458 u64 power; 2459 u32 units; 2460 2461 if (INTEL_INFO(dev)->gen < 6) 2462 return -ENODEV; 2463 2464 intel_runtime_pm_get(dev_priv); 2465 2466 rdmsrl(MSR_RAPL_POWER_UNIT, power); 2467 power = (power & 0x1f00) >> 8; 2468 units = 1000000 / (1 << power); /* convert to uJ */ 2469 power = I915_READ(MCH_SECP_NRG_STTS); 2470 power *= units; 2471 2472 intel_runtime_pm_put(dev_priv); 2473 2474 seq_printf(m, "%llu", (long long unsigned)power); 2475 2476 return 0; 2477 } 2478 2479 static int i915_pc8_status(struct seq_file *m, void *unused) 2480 { 2481 struct drm_info_node *node = m->private; 2482 struct drm_device *dev = node->minor->dev; 2483 struct drm_i915_private *dev_priv = dev->dev_private; 2484 2485 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 2486 seq_puts(m, "not supported\n"); 2487 return 0; 2488 } 2489 2490 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); 2491 seq_printf(m, "IRQs disabled: %s\n", 2492 yesno(!intel_irqs_enabled(dev_priv))); 2493 2494 return 0; 2495 } 2496 2497 static const char *power_domain_str(enum intel_display_power_domain domain) 2498 { 2499 switch (domain) { 2500 case POWER_DOMAIN_PIPE_A: 2501 return "PIPE_A"; 2502 case POWER_DOMAIN_PIPE_B: 2503 return "PIPE_B"; 2504 case POWER_DOMAIN_PIPE_C: 2505 return "PIPE_C"; 2506 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 2507 return "PIPE_A_PANEL_FITTER"; 2508 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 2509 return "PIPE_B_PANEL_FITTER"; 2510 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 2511 return "PIPE_C_PANEL_FITTER"; 2512 case POWER_DOMAIN_TRANSCODER_A: 2513 return "TRANSCODER_A"; 2514 case POWER_DOMAIN_TRANSCODER_B: 2515 return "TRANSCODER_B"; 2516 case POWER_DOMAIN_TRANSCODER_C: 2517 return "TRANSCODER_C"; 2518 case POWER_DOMAIN_TRANSCODER_EDP: 2519 return "TRANSCODER_EDP"; 2520 case POWER_DOMAIN_PORT_DDI_A_2_LANES: 2521 return "PORT_DDI_A_2_LANES"; 2522 case POWER_DOMAIN_PORT_DDI_A_4_LANES: 2523 return "PORT_DDI_A_4_LANES"; 2524 case POWER_DOMAIN_PORT_DDI_B_2_LANES: 2525 return "PORT_DDI_B_2_LANES"; 2526 case POWER_DOMAIN_PORT_DDI_B_4_LANES: 2527 return "PORT_DDI_B_4_LANES"; 2528 case POWER_DOMAIN_PORT_DDI_C_2_LANES: 2529 return "PORT_DDI_C_2_LANES"; 2530 case POWER_DOMAIN_PORT_DDI_C_4_LANES: 2531 return "PORT_DDI_C_4_LANES"; 2532 case POWER_DOMAIN_PORT_DDI_D_2_LANES: 2533 return "PORT_DDI_D_2_LANES"; 2534 case POWER_DOMAIN_PORT_DDI_D_4_LANES: 2535 return "PORT_DDI_D_4_LANES"; 2536 case POWER_DOMAIN_PORT_DSI: 2537 return "PORT_DSI"; 2538 case POWER_DOMAIN_PORT_CRT: 2539 return "PORT_CRT"; 2540 case POWER_DOMAIN_PORT_OTHER: 2541 return "PORT_OTHER"; 2542 case POWER_DOMAIN_VGA: 2543 return "VGA"; 2544 case POWER_DOMAIN_AUDIO: 2545 return "AUDIO"; 2546 case POWER_DOMAIN_PLLS: 2547 return "PLLS"; 2548 case POWER_DOMAIN_AUX_A: 2549 return "AUX_A"; 2550 case POWER_DOMAIN_AUX_B: 2551 return "AUX_B"; 2552 case POWER_DOMAIN_AUX_C: 2553 return "AUX_C"; 2554 case POWER_DOMAIN_AUX_D: 2555 return "AUX_D"; 2556 case POWER_DOMAIN_INIT: 2557 return "INIT"; 2558 default: 2559 MISSING_CASE(domain); 2560 return "?"; 2561 } 2562 } 2563 2564 static int i915_power_domain_info(struct seq_file *m, void *unused) 2565 { 2566 struct drm_info_node *node = m->private; 2567 struct drm_device *dev = node->minor->dev; 2568 struct drm_i915_private *dev_priv = dev->dev_private; 2569 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2570 int i; 2571 2572 mutex_lock(&power_domains->lock); 2573 2574 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); 2575 for (i = 0; i < power_domains->power_well_count; i++) { 2576 struct i915_power_well *power_well; 2577 enum intel_display_power_domain power_domain; 2578 2579 power_well = &power_domains->power_wells[i]; 2580 seq_printf(m, "%-25s %d\n", power_well->name, 2581 power_well->count); 2582 2583 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM; 2584 power_domain++) { 2585 if (!(BIT(power_domain) & power_well->domains)) 2586 continue; 2587 2588 seq_printf(m, " %-23s %d\n", 2589 power_domain_str(power_domain), 2590 power_domains->domain_use_count[power_domain]); 2591 } 2592 } 2593 2594 mutex_unlock(&power_domains->lock); 2595 2596 return 0; 2597 } 2598 2599 static void intel_seq_print_mode(struct seq_file *m, int tabs, 2600 struct drm_display_mode *mode) 2601 { 2602 int i; 2603 2604 for (i = 0; i < tabs; i++) 2605 seq_putc(m, '\t'); 2606 2607 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n", 2608 mode->base.id, mode->name, 2609 mode->vrefresh, mode->clock, 2610 mode->hdisplay, mode->hsync_start, 2611 mode->hsync_end, mode->htotal, 2612 mode->vdisplay, mode->vsync_start, 2613 mode->vsync_end, mode->vtotal, 2614 mode->type, mode->flags); 2615 } 2616 2617 static void intel_encoder_info(struct seq_file *m, 2618 struct intel_crtc *intel_crtc, 2619 struct intel_encoder *intel_encoder) 2620 { 2621 struct drm_info_node *node = m->private; 2622 struct drm_device *dev = node->minor->dev; 2623 struct drm_crtc *crtc = &intel_crtc->base; 2624 struct intel_connector *intel_connector; 2625 struct drm_encoder *encoder; 2626 2627 encoder = &intel_encoder->base; 2628 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", 2629 encoder->base.id, encoder->name); 2630 for_each_connector_on_encoder(dev, encoder, intel_connector) { 2631 struct drm_connector *connector = &intel_connector->base; 2632 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", 2633 connector->base.id, 2634 connector->name, 2635 drm_get_connector_status_name(connector->status)); 2636 if (connector->status == connector_status_connected) { 2637 struct drm_display_mode *mode = &crtc->mode; 2638 seq_printf(m, ", mode:\n"); 2639 intel_seq_print_mode(m, 2, mode); 2640 } else { 2641 seq_putc(m, '\n'); 2642 } 2643 } 2644 } 2645 2646 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) 2647 { 2648 struct drm_info_node *node = m->private; 2649 struct drm_device *dev = node->minor->dev; 2650 struct drm_crtc *crtc = &intel_crtc->base; 2651 struct intel_encoder *intel_encoder; 2652 2653 if (crtc->primary->fb) 2654 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", 2655 crtc->primary->fb->base.id, crtc->x, crtc->y, 2656 crtc->primary->fb->width, crtc->primary->fb->height); 2657 else 2658 seq_puts(m, "\tprimary plane disabled\n"); 2659 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 2660 intel_encoder_info(m, intel_crtc, intel_encoder); 2661 } 2662 2663 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) 2664 { 2665 struct drm_display_mode *mode = panel->fixed_mode; 2666 2667 seq_printf(m, "\tfixed mode:\n"); 2668 intel_seq_print_mode(m, 2, mode); 2669 } 2670 2671 static void intel_dp_info(struct seq_file *m, 2672 struct intel_connector *intel_connector) 2673 { 2674 struct intel_encoder *intel_encoder = intel_connector->encoder; 2675 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2676 2677 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); 2678 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : 2679 "no"); 2680 if (intel_encoder->type == INTEL_OUTPUT_EDP) 2681 intel_panel_info(m, &intel_connector->panel); 2682 } 2683 2684 static void intel_hdmi_info(struct seq_file *m, 2685 struct intel_connector *intel_connector) 2686 { 2687 struct intel_encoder *intel_encoder = intel_connector->encoder; 2688 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); 2689 2690 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : 2691 "no"); 2692 } 2693 2694 static void intel_lvds_info(struct seq_file *m, 2695 struct intel_connector *intel_connector) 2696 { 2697 intel_panel_info(m, &intel_connector->panel); 2698 } 2699 2700 static void intel_connector_info(struct seq_file *m, 2701 struct drm_connector *connector) 2702 { 2703 struct intel_connector *intel_connector = to_intel_connector(connector); 2704 struct intel_encoder *intel_encoder = intel_connector->encoder; 2705 struct drm_display_mode *mode; 2706 2707 seq_printf(m, "connector %d: type %s, status: %s\n", 2708 connector->base.id, connector->name, 2709 drm_get_connector_status_name(connector->status)); 2710 if (connector->status == connector_status_connected) { 2711 seq_printf(m, "\tname: %s\n", connector->display_info.name); 2712 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", 2713 connector->display_info.width_mm, 2714 connector->display_info.height_mm); 2715 seq_printf(m, "\tsubpixel order: %s\n", 2716 drm_get_subpixel_order_name(connector->display_info.subpixel_order)); 2717 seq_printf(m, "\tCEA rev: %d\n", 2718 connector->display_info.cea_rev); 2719 } 2720 if (intel_encoder) { 2721 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 2722 intel_encoder->type == INTEL_OUTPUT_EDP) 2723 intel_dp_info(m, intel_connector); 2724 else if (intel_encoder->type == INTEL_OUTPUT_HDMI) 2725 intel_hdmi_info(m, intel_connector); 2726 else if (intel_encoder->type == INTEL_OUTPUT_LVDS) 2727 intel_lvds_info(m, intel_connector); 2728 } 2729 2730 seq_printf(m, "\tmodes:\n"); 2731 list_for_each_entry(mode, &connector->modes, head) 2732 intel_seq_print_mode(m, 2, mode); 2733 } 2734 2735 static bool cursor_active(struct drm_device *dev, int pipe) 2736 { 2737 struct drm_i915_private *dev_priv = dev->dev_private; 2738 u32 state; 2739 2740 if (IS_845G(dev) || IS_I865G(dev)) 2741 state = I915_READ(_CURACNTR) & CURSOR_ENABLE; 2742 else 2743 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; 2744 2745 return state; 2746 } 2747 2748 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y) 2749 { 2750 struct drm_i915_private *dev_priv = dev->dev_private; 2751 u32 pos; 2752 2753 pos = I915_READ(CURPOS(pipe)); 2754 2755 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK; 2756 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT)) 2757 *x = -*x; 2758 2759 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK; 2760 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT)) 2761 *y = -*y; 2762 2763 return cursor_active(dev, pipe); 2764 } 2765 2766 static int i915_display_info(struct seq_file *m, void *unused) 2767 { 2768 struct drm_info_node *node = m->private; 2769 struct drm_device *dev = node->minor->dev; 2770 struct drm_i915_private *dev_priv = dev->dev_private; 2771 struct intel_crtc *crtc; 2772 struct drm_connector *connector; 2773 2774 intel_runtime_pm_get(dev_priv); 2775 drm_modeset_lock_all(dev); 2776 seq_printf(m, "CRTC info\n"); 2777 seq_printf(m, "---------\n"); 2778 for_each_intel_crtc(dev, crtc) { 2779 bool active; 2780 int x, y; 2781 2782 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", 2783 crtc->base.base.id, pipe_name(crtc->pipe), 2784 yesno(crtc->active), crtc->config->pipe_src_w, 2785 crtc->config->pipe_src_h); 2786 if (crtc->active) { 2787 intel_crtc_info(m, crtc); 2788 2789 active = cursor_position(dev, crtc->pipe, &x, &y); 2790 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", 2791 yesno(crtc->cursor_base), 2792 x, y, crtc->base.cursor->state->crtc_w, 2793 crtc->base.cursor->state->crtc_h, 2794 crtc->cursor_addr, yesno(active)); 2795 } 2796 2797 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", 2798 yesno(!crtc->cpu_fifo_underrun_disabled), 2799 yesno(!crtc->pch_fifo_underrun_disabled)); 2800 } 2801 2802 seq_printf(m, "\n"); 2803 seq_printf(m, "Connector info\n"); 2804 seq_printf(m, "--------------\n"); 2805 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 2806 intel_connector_info(m, connector); 2807 } 2808 drm_modeset_unlock_all(dev); 2809 intel_runtime_pm_put(dev_priv); 2810 2811 return 0; 2812 } 2813 2814 static int i915_semaphore_status(struct seq_file *m, void *unused) 2815 { 2816 struct drm_info_node *node = (struct drm_info_node *) m->private; 2817 struct drm_device *dev = node->minor->dev; 2818 struct drm_i915_private *dev_priv = dev->dev_private; 2819 struct intel_engine_cs *ring; 2820 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); 2821 int i, j, ret; 2822 2823 if (!i915_semaphore_is_enabled(dev)) { 2824 seq_puts(m, "Semaphores are disabled\n"); 2825 return 0; 2826 } 2827 2828 ret = mutex_lock_interruptible(&dev->struct_mutex); 2829 if (ret) 2830 return ret; 2831 intel_runtime_pm_get(dev_priv); 2832 2833 if (IS_BROADWELL(dev)) { 2834 struct page *page; 2835 uint64_t *seqno; 2836 2837 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0); 2838 2839 seqno = (uint64_t *)kmap_atomic(page); 2840 for_each_ring(ring, dev_priv, i) { 2841 uint64_t offset; 2842 2843 seq_printf(m, "%s\n", ring->name); 2844 2845 seq_puts(m, " Last signal:"); 2846 for (j = 0; j < num_rings; j++) { 2847 offset = i * I915_NUM_RINGS + j; 2848 seq_printf(m, "0x%08llx (0x%02llx) ", 2849 seqno[offset], offset * 8); 2850 } 2851 seq_putc(m, '\n'); 2852 2853 seq_puts(m, " Last wait: "); 2854 for (j = 0; j < num_rings; j++) { 2855 offset = i + (j * I915_NUM_RINGS); 2856 seq_printf(m, "0x%08llx (0x%02llx) ", 2857 seqno[offset], offset * 8); 2858 } 2859 seq_putc(m, '\n'); 2860 2861 } 2862 kunmap_atomic(seqno); 2863 } else { 2864 seq_puts(m, " Last signal:"); 2865 for_each_ring(ring, dev_priv, i) 2866 for (j = 0; j < num_rings; j++) 2867 seq_printf(m, "0x%08x\n", 2868 I915_READ(ring->semaphore.mbox.signal[j])); 2869 seq_putc(m, '\n'); 2870 } 2871 2872 seq_puts(m, "\nSync seqno:\n"); 2873 for_each_ring(ring, dev_priv, i) { 2874 for (j = 0; j < num_rings; j++) { 2875 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); 2876 } 2877 seq_putc(m, '\n'); 2878 } 2879 seq_putc(m, '\n'); 2880 2881 intel_runtime_pm_put(dev_priv); 2882 mutex_unlock(&dev->struct_mutex); 2883 return 0; 2884 } 2885 2886 static int i915_shared_dplls_info(struct seq_file *m, void *unused) 2887 { 2888 struct drm_info_node *node = (struct drm_info_node *) m->private; 2889 struct drm_device *dev = node->minor->dev; 2890 struct drm_i915_private *dev_priv = dev->dev_private; 2891 int i; 2892 2893 drm_modeset_lock_all(dev); 2894 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2895 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; 2896 2897 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); 2898 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", 2899 pll->config.crtc_mask, pll->active, yesno(pll->on)); 2900 seq_printf(m, " tracked hardware state:\n"); 2901 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); 2902 seq_printf(m, " dpll_md: 0x%08x\n", 2903 pll->config.hw_state.dpll_md); 2904 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); 2905 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); 2906 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); 2907 } 2908 drm_modeset_unlock_all(dev); 2909 2910 return 0; 2911 } 2912 2913 static int i915_wa_registers(struct seq_file *m, void *unused) 2914 { 2915 int i; 2916 int ret; 2917 struct drm_info_node *node = (struct drm_info_node *) m->private; 2918 struct drm_device *dev = node->minor->dev; 2919 struct drm_i915_private *dev_priv = dev->dev_private; 2920 2921 ret = mutex_lock_interruptible(&dev->struct_mutex); 2922 if (ret) 2923 return ret; 2924 2925 intel_runtime_pm_get(dev_priv); 2926 2927 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); 2928 for (i = 0; i < dev_priv->workarounds.count; ++i) { 2929 u32 addr, mask, value, read; 2930 bool ok; 2931 2932 addr = dev_priv->workarounds.reg[i].addr; 2933 mask = dev_priv->workarounds.reg[i].mask; 2934 value = dev_priv->workarounds.reg[i].value; 2935 read = I915_READ(addr); 2936 ok = (value & mask) == (read & mask); 2937 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", 2938 addr, value, mask, read, ok ? "OK" : "FAIL"); 2939 } 2940 2941 intel_runtime_pm_put(dev_priv); 2942 mutex_unlock(&dev->struct_mutex); 2943 2944 return 0; 2945 } 2946 2947 static int i915_ddb_info(struct seq_file *m, void *unused) 2948 { 2949 struct drm_info_node *node = m->private; 2950 struct drm_device *dev = node->minor->dev; 2951 struct drm_i915_private *dev_priv = dev->dev_private; 2952 struct skl_ddb_allocation *ddb; 2953 struct skl_ddb_entry *entry; 2954 enum pipe pipe; 2955 int plane; 2956 2957 if (INTEL_INFO(dev)->gen < 9) 2958 return 0; 2959 2960 drm_modeset_lock_all(dev); 2961 2962 ddb = &dev_priv->wm.skl_hw.ddb; 2963 2964 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); 2965 2966 for_each_pipe(dev_priv, pipe) { 2967 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); 2968 2969 for_each_plane(dev_priv, pipe, plane) { 2970 entry = &ddb->plane[pipe][plane]; 2971 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, 2972 entry->start, entry->end, 2973 skl_ddb_entry_size(entry)); 2974 } 2975 2976 entry = &ddb->cursor[pipe]; 2977 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, 2978 entry->end, skl_ddb_entry_size(entry)); 2979 } 2980 2981 drm_modeset_unlock_all(dev); 2982 2983 return 0; 2984 } 2985 2986 static void drrs_status_per_crtc(struct seq_file *m, 2987 struct drm_device *dev, struct intel_crtc *intel_crtc) 2988 { 2989 struct intel_encoder *intel_encoder; 2990 struct drm_i915_private *dev_priv = dev->dev_private; 2991 struct i915_drrs *drrs = &dev_priv->drrs; 2992 int vrefresh = 0; 2993 2994 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { 2995 /* Encoder connected on this CRTC */ 2996 switch (intel_encoder->type) { 2997 case INTEL_OUTPUT_EDP: 2998 seq_puts(m, "eDP:\n"); 2999 break; 3000 case INTEL_OUTPUT_DSI: 3001 seq_puts(m, "DSI:\n"); 3002 break; 3003 case INTEL_OUTPUT_HDMI: 3004 seq_puts(m, "HDMI:\n"); 3005 break; 3006 case INTEL_OUTPUT_DISPLAYPORT: 3007 seq_puts(m, "DP:\n"); 3008 break; 3009 default: 3010 seq_printf(m, "Other encoder (id=%d).\n", 3011 intel_encoder->type); 3012 return; 3013 } 3014 } 3015 3016 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT) 3017 seq_puts(m, "\tVBT: DRRS_type: Static"); 3018 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT) 3019 seq_puts(m, "\tVBT: DRRS_type: Seamless"); 3020 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED) 3021 seq_puts(m, "\tVBT: DRRS_type: None"); 3022 else 3023 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value"); 3024 3025 seq_puts(m, "\n\n"); 3026 3027 if (intel_crtc->config->has_drrs) { 3028 struct intel_panel *panel; 3029 3030 mutex_lock(&drrs->mutex); 3031 /* DRRS Supported */ 3032 seq_puts(m, "\tDRRS Supported: Yes\n"); 3033 3034 /* disable_drrs() will make drrs->dp NULL */ 3035 if (!drrs->dp) { 3036 seq_puts(m, "Idleness DRRS: Disabled"); 3037 mutex_unlock(&drrs->mutex); 3038 return; 3039 } 3040 3041 panel = &drrs->dp->attached_connector->panel; 3042 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", 3043 drrs->busy_frontbuffer_bits); 3044 3045 seq_puts(m, "\n\t\t"); 3046 if (drrs->refresh_rate_type == DRRS_HIGH_RR) { 3047 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); 3048 vrefresh = panel->fixed_mode->vrefresh; 3049 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { 3050 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); 3051 vrefresh = panel->downclock_mode->vrefresh; 3052 } else { 3053 seq_printf(m, "DRRS_State: Unknown(%d)\n", 3054 drrs->refresh_rate_type); 3055 mutex_unlock(&drrs->mutex); 3056 return; 3057 } 3058 seq_printf(m, "\t\tVrefresh: %d", vrefresh); 3059 3060 seq_puts(m, "\n\t\t"); 3061 mutex_unlock(&drrs->mutex); 3062 } else { 3063 /* DRRS not supported. Print the VBT parameter*/ 3064 seq_puts(m, "\tDRRS Supported : No"); 3065 } 3066 seq_puts(m, "\n"); 3067 } 3068 3069 static int i915_drrs_status(struct seq_file *m, void *unused) 3070 { 3071 struct drm_info_node *node = m->private; 3072 struct drm_device *dev = node->minor->dev; 3073 struct intel_crtc *intel_crtc; 3074 int active_crtc_cnt = 0; 3075 3076 for_each_intel_crtc(dev, intel_crtc) { 3077 drm_modeset_lock(&intel_crtc->base.mutex, NULL); 3078 3079 if (intel_crtc->active) { 3080 active_crtc_cnt++; 3081 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); 3082 3083 drrs_status_per_crtc(m, dev, intel_crtc); 3084 } 3085 3086 drm_modeset_unlock(&intel_crtc->base.mutex); 3087 } 3088 3089 if (!active_crtc_cnt) 3090 seq_puts(m, "No active crtc found\n"); 3091 3092 return 0; 3093 } 3094 3095 struct pipe_crc_info { 3096 const char *name; 3097 struct drm_device *dev; 3098 enum pipe pipe; 3099 }; 3100 3101 static int i915_dp_mst_info(struct seq_file *m, void *unused) 3102 { 3103 struct drm_info_node *node = (struct drm_info_node *) m->private; 3104 struct drm_device *dev = node->minor->dev; 3105 struct drm_encoder *encoder; 3106 struct intel_encoder *intel_encoder; 3107 struct intel_digital_port *intel_dig_port; 3108 drm_modeset_lock_all(dev); 3109 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3110 intel_encoder = to_intel_encoder(encoder); 3111 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT) 3112 continue; 3113 intel_dig_port = enc_to_dig_port(encoder); 3114 if (!intel_dig_port->dp.can_mst) 3115 continue; 3116 3117 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); 3118 } 3119 drm_modeset_unlock_all(dev); 3120 return 0; 3121 } 3122 3123 static int i915_pipe_crc_open(struct inode *inode, struct file *filep) 3124 { 3125 struct pipe_crc_info *info = inode->i_private; 3126 struct drm_i915_private *dev_priv = info->dev->dev_private; 3127 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3128 3129 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes) 3130 return -ENODEV; 3131 3132 spin_lock_irq(&pipe_crc->lock); 3133 3134 if (pipe_crc->opened) { 3135 spin_unlock_irq(&pipe_crc->lock); 3136 return -EBUSY; /* already open */ 3137 } 3138 3139 pipe_crc->opened = true; 3140 filep->private_data = inode->i_private; 3141 3142 spin_unlock_irq(&pipe_crc->lock); 3143 3144 return 0; 3145 } 3146 3147 static int i915_pipe_crc_release(struct inode *inode, struct file *filep) 3148 { 3149 struct pipe_crc_info *info = inode->i_private; 3150 struct drm_i915_private *dev_priv = info->dev->dev_private; 3151 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3152 3153 spin_lock_irq(&pipe_crc->lock); 3154 pipe_crc->opened = false; 3155 spin_unlock_irq(&pipe_crc->lock); 3156 3157 return 0; 3158 } 3159 3160 /* (6 fields, 8 chars each, space separated (5) + '\n') */ 3161 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) 3162 /* account for \'0' */ 3163 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) 3164 3165 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) 3166 { 3167 assert_spin_locked(&pipe_crc->lock); 3168 return CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3169 INTEL_PIPE_CRC_ENTRIES_NR); 3170 } 3171 3172 static ssize_t 3173 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, 3174 loff_t *pos) 3175 { 3176 struct pipe_crc_info *info = filep->private_data; 3177 struct drm_device *dev = info->dev; 3178 struct drm_i915_private *dev_priv = dev->dev_private; 3179 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 3180 char buf[PIPE_CRC_BUFFER_LEN]; 3181 int n_entries; 3182 ssize_t bytes_read; 3183 3184 /* 3185 * Don't allow user space to provide buffers not big enough to hold 3186 * a line of data. 3187 */ 3188 if (count < PIPE_CRC_LINE_LEN) 3189 return -EINVAL; 3190 3191 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) 3192 return 0; 3193 3194 /* nothing to read */ 3195 spin_lock_irq(&pipe_crc->lock); 3196 while (pipe_crc_data_count(pipe_crc) == 0) { 3197 int ret; 3198 3199 if (filep->f_flags & O_NONBLOCK) { 3200 spin_unlock_irq(&pipe_crc->lock); 3201 return -EAGAIN; 3202 } 3203 3204 ret = wait_event_interruptible_lock_irq(pipe_crc->wq, 3205 pipe_crc_data_count(pipe_crc), pipe_crc->lock); 3206 if (ret) { 3207 spin_unlock_irq(&pipe_crc->lock); 3208 return ret; 3209 } 3210 } 3211 3212 /* We now have one or more entries to read */ 3213 n_entries = count / PIPE_CRC_LINE_LEN; 3214 3215 bytes_read = 0; 3216 while (n_entries > 0) { 3217 struct intel_pipe_crc_entry *entry = 3218 &pipe_crc->entries[pipe_crc->tail]; 3219 int ret; 3220 3221 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, 3222 INTEL_PIPE_CRC_ENTRIES_NR) < 1) 3223 break; 3224 3225 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); 3226 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 3227 3228 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, 3229 "%8u %8x %8x %8x %8x %8x\n", 3230 entry->frame, entry->crc[0], 3231 entry->crc[1], entry->crc[2], 3232 entry->crc[3], entry->crc[4]); 3233 3234 spin_unlock_irq(&pipe_crc->lock); 3235 3236 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN); 3237 if (ret == PIPE_CRC_LINE_LEN) 3238 return -EFAULT; 3239 3240 user_buf += PIPE_CRC_LINE_LEN; 3241 n_entries--; 3242 3243 spin_lock_irq(&pipe_crc->lock); 3244 } 3245 3246 spin_unlock_irq(&pipe_crc->lock); 3247 3248 return bytes_read; 3249 } 3250 3251 static const struct file_operations i915_pipe_crc_fops = { 3252 .owner = THIS_MODULE, 3253 .open = i915_pipe_crc_open, 3254 .read = i915_pipe_crc_read, 3255 .release = i915_pipe_crc_release, 3256 }; 3257 3258 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { 3259 { 3260 .name = "i915_pipe_A_crc", 3261 .pipe = PIPE_A, 3262 }, 3263 { 3264 .name = "i915_pipe_B_crc", 3265 .pipe = PIPE_B, 3266 }, 3267 { 3268 .name = "i915_pipe_C_crc", 3269 .pipe = PIPE_C, 3270 }, 3271 }; 3272 3273 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor, 3274 enum pipe pipe) 3275 { 3276 struct drm_device *dev = minor->dev; 3277 struct dentry *ent; 3278 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe]; 3279 3280 info->dev = dev; 3281 ent = debugfs_create_file(info->name, S_IRUGO, root, info, 3282 &i915_pipe_crc_fops); 3283 if (!ent) 3284 return -ENOMEM; 3285 3286 return drm_add_fake_info_node(minor, ent, info); 3287 } 3288 3289 static const char * const pipe_crc_sources[] = { 3290 "none", 3291 "plane1", 3292 "plane2", 3293 "pf", 3294 "pipe", 3295 "TV", 3296 "DP-B", 3297 "DP-C", 3298 "DP-D", 3299 "auto", 3300 }; 3301 3302 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) 3303 { 3304 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); 3305 return pipe_crc_sources[source]; 3306 } 3307 3308 static int display_crc_ctl_show(struct seq_file *m, void *data) 3309 { 3310 struct drm_device *dev = m->private; 3311 struct drm_i915_private *dev_priv = dev->dev_private; 3312 int i; 3313 3314 for (i = 0; i < I915_MAX_PIPES; i++) 3315 seq_printf(m, "%c %s\n", pipe_name(i), 3316 pipe_crc_source_name(dev_priv->pipe_crc[i].source)); 3317 3318 return 0; 3319 } 3320 3321 static int display_crc_ctl_open(struct inode *inode, struct file *file) 3322 { 3323 struct drm_device *dev = inode->i_private; 3324 3325 return single_open(file, display_crc_ctl_show, dev); 3326 } 3327 3328 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3329 uint32_t *val) 3330 { 3331 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3332 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3333 3334 switch (*source) { 3335 case INTEL_PIPE_CRC_SOURCE_PIPE: 3336 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; 3337 break; 3338 case INTEL_PIPE_CRC_SOURCE_NONE: 3339 *val = 0; 3340 break; 3341 default: 3342 return -EINVAL; 3343 } 3344 3345 return 0; 3346 } 3347 3348 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe, 3349 enum intel_pipe_crc_source *source) 3350 { 3351 struct intel_encoder *encoder; 3352 struct intel_crtc *crtc; 3353 struct intel_digital_port *dig_port; 3354 int ret = 0; 3355 3356 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3357 3358 drm_modeset_lock_all(dev); 3359 for_each_intel_encoder(dev, encoder) { 3360 if (!encoder->base.crtc) 3361 continue; 3362 3363 crtc = to_intel_crtc(encoder->base.crtc); 3364 3365 if (crtc->pipe != pipe) 3366 continue; 3367 3368 switch (encoder->type) { 3369 case INTEL_OUTPUT_TVOUT: 3370 *source = INTEL_PIPE_CRC_SOURCE_TV; 3371 break; 3372 case INTEL_OUTPUT_DISPLAYPORT: 3373 case INTEL_OUTPUT_EDP: 3374 dig_port = enc_to_dig_port(&encoder->base); 3375 switch (dig_port->port) { 3376 case PORT_B: 3377 *source = INTEL_PIPE_CRC_SOURCE_DP_B; 3378 break; 3379 case PORT_C: 3380 *source = INTEL_PIPE_CRC_SOURCE_DP_C; 3381 break; 3382 case PORT_D: 3383 *source = INTEL_PIPE_CRC_SOURCE_DP_D; 3384 break; 3385 default: 3386 WARN(1, "nonexisting DP port %c\n", 3387 port_name(dig_port->port)); 3388 break; 3389 } 3390 break; 3391 default: 3392 break; 3393 } 3394 } 3395 drm_modeset_unlock_all(dev); 3396 3397 return ret; 3398 } 3399 3400 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev, 3401 enum pipe pipe, 3402 enum intel_pipe_crc_source *source, 3403 uint32_t *val) 3404 { 3405 struct drm_i915_private *dev_priv = dev->dev_private; 3406 bool need_stable_symbols = false; 3407 3408 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3409 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); 3410 if (ret) 3411 return ret; 3412 } 3413 3414 switch (*source) { 3415 case INTEL_PIPE_CRC_SOURCE_PIPE: 3416 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; 3417 break; 3418 case INTEL_PIPE_CRC_SOURCE_DP_B: 3419 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; 3420 need_stable_symbols = true; 3421 break; 3422 case INTEL_PIPE_CRC_SOURCE_DP_C: 3423 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; 3424 need_stable_symbols = true; 3425 break; 3426 case INTEL_PIPE_CRC_SOURCE_DP_D: 3427 if (!IS_CHERRYVIEW(dev)) 3428 return -EINVAL; 3429 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; 3430 need_stable_symbols = true; 3431 break; 3432 case INTEL_PIPE_CRC_SOURCE_NONE: 3433 *val = 0; 3434 break; 3435 default: 3436 return -EINVAL; 3437 } 3438 3439 /* 3440 * When the pipe CRC tap point is after the transcoders we need 3441 * to tweak symbol-level features to produce a deterministic series of 3442 * symbols for a given frame. We need to reset those features only once 3443 * a frame (instead of every nth symbol): 3444 * - DC-balance: used to ensure a better clock recovery from the data 3445 * link (SDVO) 3446 * - DisplayPort scrambling: used for EMI reduction 3447 */ 3448 if (need_stable_symbols) { 3449 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3450 3451 tmp |= DC_BALANCE_RESET_VLV; 3452 switch (pipe) { 3453 case PIPE_A: 3454 tmp |= PIPE_A_SCRAMBLE_RESET; 3455 break; 3456 case PIPE_B: 3457 tmp |= PIPE_B_SCRAMBLE_RESET; 3458 break; 3459 case PIPE_C: 3460 tmp |= PIPE_C_SCRAMBLE_RESET; 3461 break; 3462 default: 3463 return -EINVAL; 3464 } 3465 I915_WRITE(PORT_DFT2_G4X, tmp); 3466 } 3467 3468 return 0; 3469 } 3470 3471 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev, 3472 enum pipe pipe, 3473 enum intel_pipe_crc_source *source, 3474 uint32_t *val) 3475 { 3476 struct drm_i915_private *dev_priv = dev->dev_private; 3477 bool need_stable_symbols = false; 3478 3479 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { 3480 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source); 3481 if (ret) 3482 return ret; 3483 } 3484 3485 switch (*source) { 3486 case INTEL_PIPE_CRC_SOURCE_PIPE: 3487 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; 3488 break; 3489 case INTEL_PIPE_CRC_SOURCE_TV: 3490 if (!SUPPORTS_TV(dev)) 3491 return -EINVAL; 3492 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; 3493 break; 3494 case INTEL_PIPE_CRC_SOURCE_DP_B: 3495 if (!IS_G4X(dev)) 3496 return -EINVAL; 3497 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; 3498 need_stable_symbols = true; 3499 break; 3500 case INTEL_PIPE_CRC_SOURCE_DP_C: 3501 if (!IS_G4X(dev)) 3502 return -EINVAL; 3503 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; 3504 need_stable_symbols = true; 3505 break; 3506 case INTEL_PIPE_CRC_SOURCE_DP_D: 3507 if (!IS_G4X(dev)) 3508 return -EINVAL; 3509 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; 3510 need_stable_symbols = true; 3511 break; 3512 case INTEL_PIPE_CRC_SOURCE_NONE: 3513 *val = 0; 3514 break; 3515 default: 3516 return -EINVAL; 3517 } 3518 3519 /* 3520 * When the pipe CRC tap point is after the transcoders we need 3521 * to tweak symbol-level features to produce a deterministic series of 3522 * symbols for a given frame. We need to reset those features only once 3523 * a frame (instead of every nth symbol): 3524 * - DC-balance: used to ensure a better clock recovery from the data 3525 * link (SDVO) 3526 * - DisplayPort scrambling: used for EMI reduction 3527 */ 3528 if (need_stable_symbols) { 3529 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3530 3531 WARN_ON(!IS_G4X(dev)); 3532 3533 I915_WRITE(PORT_DFT_I9XX, 3534 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); 3535 3536 if (pipe == PIPE_A) 3537 tmp |= PIPE_A_SCRAMBLE_RESET; 3538 else 3539 tmp |= PIPE_B_SCRAMBLE_RESET; 3540 3541 I915_WRITE(PORT_DFT2_G4X, tmp); 3542 } 3543 3544 return 0; 3545 } 3546 3547 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev, 3548 enum pipe pipe) 3549 { 3550 struct drm_i915_private *dev_priv = dev->dev_private; 3551 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3552 3553 switch (pipe) { 3554 case PIPE_A: 3555 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3556 break; 3557 case PIPE_B: 3558 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3559 break; 3560 case PIPE_C: 3561 tmp &= ~PIPE_C_SCRAMBLE_RESET; 3562 break; 3563 default: 3564 return; 3565 } 3566 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) 3567 tmp &= ~DC_BALANCE_RESET_VLV; 3568 I915_WRITE(PORT_DFT2_G4X, tmp); 3569 3570 } 3571 3572 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev, 3573 enum pipe pipe) 3574 { 3575 struct drm_i915_private *dev_priv = dev->dev_private; 3576 uint32_t tmp = I915_READ(PORT_DFT2_G4X); 3577 3578 if (pipe == PIPE_A) 3579 tmp &= ~PIPE_A_SCRAMBLE_RESET; 3580 else 3581 tmp &= ~PIPE_B_SCRAMBLE_RESET; 3582 I915_WRITE(PORT_DFT2_G4X, tmp); 3583 3584 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { 3585 I915_WRITE(PORT_DFT_I9XX, 3586 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); 3587 } 3588 } 3589 3590 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 3591 uint32_t *val) 3592 { 3593 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3594 *source = INTEL_PIPE_CRC_SOURCE_PIPE; 3595 3596 switch (*source) { 3597 case INTEL_PIPE_CRC_SOURCE_PLANE1: 3598 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; 3599 break; 3600 case INTEL_PIPE_CRC_SOURCE_PLANE2: 3601 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; 3602 break; 3603 case INTEL_PIPE_CRC_SOURCE_PIPE: 3604 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; 3605 break; 3606 case INTEL_PIPE_CRC_SOURCE_NONE: 3607 *val = 0; 3608 break; 3609 default: 3610 return -EINVAL; 3611 } 3612 3613 return 0; 3614 } 3615 3616 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev) 3617 { 3618 struct drm_i915_private *dev_priv = dev->dev_private; 3619 struct intel_crtc *crtc = 3620 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); 3621 3622 drm_modeset_lock_all(dev); 3623 /* 3624 * If we use the eDP transcoder we need to make sure that we don't 3625 * bypass the pfit, since otherwise the pipe CRC source won't work. Only 3626 * relevant on hsw with pipe A when using the always-on power well 3627 * routing. 3628 */ 3629 if (crtc->config->cpu_transcoder == TRANSCODER_EDP && 3630 !crtc->config->pch_pfit.enabled) { 3631 crtc->config->pch_pfit.force_thru = true; 3632 3633 intel_display_power_get(dev_priv, 3634 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); 3635 3636 intel_crtc_reset(crtc); 3637 } 3638 drm_modeset_unlock_all(dev); 3639 } 3640 3641 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev) 3642 { 3643 struct drm_i915_private *dev_priv = dev->dev_private; 3644 struct intel_crtc *crtc = 3645 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); 3646 3647 drm_modeset_lock_all(dev); 3648 /* 3649 * If we use the eDP transcoder we need to make sure that we don't 3650 * bypass the pfit, since otherwise the pipe CRC source won't work. Only 3651 * relevant on hsw with pipe A when using the always-on power well 3652 * routing. 3653 */ 3654 if (crtc->config->pch_pfit.force_thru) { 3655 crtc->config->pch_pfit.force_thru = false; 3656 3657 intel_crtc_reset(crtc); 3658 3659 intel_display_power_put(dev_priv, 3660 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); 3661 } 3662 drm_modeset_unlock_all(dev); 3663 } 3664 3665 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev, 3666 enum pipe pipe, 3667 enum intel_pipe_crc_source *source, 3668 uint32_t *val) 3669 { 3670 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) 3671 *source = INTEL_PIPE_CRC_SOURCE_PF; 3672 3673 switch (*source) { 3674 case INTEL_PIPE_CRC_SOURCE_PLANE1: 3675 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; 3676 break; 3677 case INTEL_PIPE_CRC_SOURCE_PLANE2: 3678 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; 3679 break; 3680 case INTEL_PIPE_CRC_SOURCE_PF: 3681 if (IS_HASWELL(dev) && pipe == PIPE_A) 3682 hsw_trans_edp_pipe_A_crc_wa(dev); 3683 3684 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; 3685 break; 3686 case INTEL_PIPE_CRC_SOURCE_NONE: 3687 *val = 0; 3688 break; 3689 default: 3690 return -EINVAL; 3691 } 3692 3693 return 0; 3694 } 3695 3696 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 3697 enum intel_pipe_crc_source source) 3698 { 3699 struct drm_i915_private *dev_priv = dev->dev_private; 3700 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 3701 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, 3702 pipe)); 3703 u32 val = 0; /* shut up gcc */ 3704 int ret; 3705 3706 if (pipe_crc->source == source) 3707 return 0; 3708 3709 /* forbid changing the source without going back to 'none' */ 3710 if (pipe_crc->source && source) 3711 return -EINVAL; 3712 3713 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) { 3714 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); 3715 return -EIO; 3716 } 3717 3718 if (IS_GEN2(dev)) 3719 ret = i8xx_pipe_crc_ctl_reg(&source, &val); 3720 else if (INTEL_INFO(dev)->gen < 5) 3721 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); 3722 else if (IS_VALLEYVIEW(dev)) 3723 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); 3724 else if (IS_GEN5(dev) || IS_GEN6(dev)) 3725 ret = ilk_pipe_crc_ctl_reg(&source, &val); 3726 else 3727 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val); 3728 3729 if (ret != 0) 3730 return ret; 3731 3732 /* none -> real source transition */ 3733 if (source) { 3734 struct intel_pipe_crc_entry *entries; 3735 3736 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", 3737 pipe_name(pipe), pipe_crc_source_name(source)); 3738 3739 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, 3740 sizeof(pipe_crc->entries[0]), 3741 GFP_KERNEL); 3742 if (!entries) 3743 return -ENOMEM; 3744 3745 /* 3746 * When IPS gets enabled, the pipe CRC changes. Since IPS gets 3747 * enabled and disabled dynamically based on package C states, 3748 * user space can't make reliable use of the CRCs, so let's just 3749 * completely disable it. 3750 */ 3751 hsw_disable_ips(crtc); 3752 3753 spin_lock_irq(&pipe_crc->lock); 3754 kfree(pipe_crc->entries); 3755 pipe_crc->entries = entries; 3756 pipe_crc->head = 0; 3757 pipe_crc->tail = 0; 3758 spin_unlock_irq(&pipe_crc->lock); 3759 } 3760 3761 pipe_crc->source = source; 3762 3763 I915_WRITE(PIPE_CRC_CTL(pipe), val); 3764 POSTING_READ(PIPE_CRC_CTL(pipe)); 3765 3766 /* real source -> none transition */ 3767 if (source == INTEL_PIPE_CRC_SOURCE_NONE) { 3768 struct intel_pipe_crc_entry *entries; 3769 struct intel_crtc *crtc = 3770 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 3771 3772 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", 3773 pipe_name(pipe)); 3774 3775 drm_modeset_lock(&crtc->base.mutex, NULL); 3776 if (crtc->active) 3777 intel_wait_for_vblank(dev, pipe); 3778 drm_modeset_unlock(&crtc->base.mutex); 3779 3780 spin_lock_irq(&pipe_crc->lock); 3781 entries = pipe_crc->entries; 3782 pipe_crc->entries = NULL; 3783 pipe_crc->head = 0; 3784 pipe_crc->tail = 0; 3785 spin_unlock_irq(&pipe_crc->lock); 3786 3787 kfree(entries); 3788 3789 if (IS_G4X(dev)) 3790 g4x_undo_pipe_scramble_reset(dev, pipe); 3791 else if (IS_VALLEYVIEW(dev)) 3792 vlv_undo_pipe_scramble_reset(dev, pipe); 3793 else if (IS_HASWELL(dev) && pipe == PIPE_A) 3794 hsw_undo_trans_edp_pipe_A_crc_wa(dev); 3795 3796 hsw_enable_ips(crtc); 3797 } 3798 3799 return 0; 3800 } 3801 3802 /* 3803 * Parse pipe CRC command strings: 3804 * command: wsp* object wsp+ name wsp+ source wsp* 3805 * object: 'pipe' 3806 * name: (A | B | C) 3807 * source: (none | plane1 | plane2 | pf) 3808 * wsp: (#0x20 | #0x9 | #0xA)+ 3809 * 3810 * eg.: 3811 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A 3812 * "pipe A none" -> Stop CRC 3813 */ 3814 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) 3815 { 3816 int n_words = 0; 3817 3818 while (*buf) { 3819 char *end; 3820 3821 /* skip leading white space */ 3822 buf = skip_spaces(buf); 3823 if (!*buf) 3824 break; /* end of buffer */ 3825 3826 /* find end of word */ 3827 for (end = buf; *end && !isspace(*end); end++) 3828 ; 3829 3830 if (n_words == max_words) { 3831 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", 3832 max_words); 3833 return -EINVAL; /* ran out of words[] before bytes */ 3834 } 3835 3836 if (*end) 3837 *end++ = '\0'; 3838 words[n_words++] = buf; 3839 buf = end; 3840 } 3841 3842 return n_words; 3843 } 3844 3845 enum intel_pipe_crc_object { 3846 PIPE_CRC_OBJECT_PIPE, 3847 }; 3848 3849 static const char * const pipe_crc_objects[] = { 3850 "pipe", 3851 }; 3852 3853 static int 3854 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) 3855 { 3856 int i; 3857 3858 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) 3859 if (!strcmp(buf, pipe_crc_objects[i])) { 3860 *o = i; 3861 return 0; 3862 } 3863 3864 return -EINVAL; 3865 } 3866 3867 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) 3868 { 3869 const char name = buf[0]; 3870 3871 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) 3872 return -EINVAL; 3873 3874 *pipe = name - 'A'; 3875 3876 return 0; 3877 } 3878 3879 static int 3880 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) 3881 { 3882 int i; 3883 3884 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) 3885 if (!strcmp(buf, pipe_crc_sources[i])) { 3886 *s = i; 3887 return 0; 3888 } 3889 3890 return -EINVAL; 3891 } 3892 3893 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len) 3894 { 3895 #define N_WORDS 3 3896 int n_words; 3897 char *words[N_WORDS]; 3898 enum pipe pipe; 3899 enum intel_pipe_crc_object object; 3900 enum intel_pipe_crc_source source; 3901 3902 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); 3903 if (n_words != N_WORDS) { 3904 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", 3905 N_WORDS); 3906 return -EINVAL; 3907 } 3908 3909 if (display_crc_ctl_parse_object(words[0], &object) < 0) { 3910 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); 3911 return -EINVAL; 3912 } 3913 3914 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { 3915 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); 3916 return -EINVAL; 3917 } 3918 3919 if (display_crc_ctl_parse_source(words[2], &source) < 0) { 3920 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); 3921 return -EINVAL; 3922 } 3923 3924 return pipe_crc_set_source(dev, pipe, source); 3925 } 3926 3927 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, 3928 size_t len, loff_t *offp) 3929 { 3930 struct seq_file *m = file->private_data; 3931 struct drm_device *dev = m->private; 3932 char *tmpbuf; 3933 int ret; 3934 3935 if (len == 0) 3936 return 0; 3937 3938 if (len > PAGE_SIZE - 1) { 3939 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", 3940 PAGE_SIZE); 3941 return -E2BIG; 3942 } 3943 3944 tmpbuf = kmalloc(len + 1, GFP_KERNEL); 3945 if (!tmpbuf) 3946 return -ENOMEM; 3947 3948 if (copy_from_user(tmpbuf, ubuf, len)) { 3949 ret = -EFAULT; 3950 goto out; 3951 } 3952 tmpbuf[len] = '\0'; 3953 3954 ret = display_crc_ctl_parse(dev, tmpbuf, len); 3955 3956 out: 3957 kfree(tmpbuf); 3958 if (ret < 0) 3959 return ret; 3960 3961 *offp += len; 3962 return len; 3963 } 3964 3965 static const struct file_operations i915_display_crc_ctl_fops = { 3966 .owner = THIS_MODULE, 3967 .open = display_crc_ctl_open, 3968 .read = seq_read, 3969 .llseek = seq_lseek, 3970 .release = single_release, 3971 .write = display_crc_ctl_write 3972 }; 3973 3974 static ssize_t i915_displayport_test_active_write(struct file *file, 3975 const char __user *ubuf, 3976 size_t len, loff_t *offp) 3977 { 3978 char *input_buffer; 3979 int status = 0; 3980 struct seq_file *m; 3981 struct drm_device *dev; 3982 struct drm_connector *connector; 3983 struct list_head *connector_list; 3984 struct intel_dp *intel_dp; 3985 int val = 0; 3986 3987 m = file->private_data; 3988 if (!m) { 3989 status = -ENODEV; 3990 return status; 3991 } 3992 dev = m->private; 3993 3994 if (!dev) { 3995 status = -ENODEV; 3996 return status; 3997 } 3998 connector_list = &dev->mode_config.connector_list; 3999 4000 if (len == 0) 4001 return 0; 4002 4003 input_buffer = kmalloc(len + 1, GFP_KERNEL); 4004 if (!input_buffer) 4005 return -ENOMEM; 4006 4007 if (copy_from_user(input_buffer, ubuf, len)) { 4008 status = -EFAULT; 4009 goto out; 4010 } 4011 4012 input_buffer[len] = '\0'; 4013 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len); 4014 4015 list_for_each_entry(connector, connector_list, head) { 4016 4017 if (connector->connector_type != 4018 DRM_MODE_CONNECTOR_DisplayPort) 4019 continue; 4020 4021 if (connector->connector_type == 4022 DRM_MODE_CONNECTOR_DisplayPort && 4023 connector->status == connector_status_connected && 4024 connector->encoder != NULL) { 4025 intel_dp = enc_to_intel_dp(connector->encoder); 4026 status = kstrtoint(input_buffer, 10, &val); 4027 if (status < 0) 4028 goto out; 4029 DRM_DEBUG_DRIVER("Got %d for test active\n", val); 4030 /* To prevent erroneous activation of the compliance 4031 * testing code, only accept an actual value of 1 here 4032 */ 4033 if (val == 1) 4034 intel_dp->compliance_test_active = 1; 4035 else 4036 intel_dp->compliance_test_active = 0; 4037 } 4038 } 4039 out: 4040 kfree(input_buffer); 4041 if (status < 0) 4042 return status; 4043 4044 *offp += len; 4045 return len; 4046 } 4047 4048 static int i915_displayport_test_active_show(struct seq_file *m, void *data) 4049 { 4050 struct drm_device *dev = m->private; 4051 struct drm_connector *connector; 4052 struct list_head *connector_list = &dev->mode_config.connector_list; 4053 struct intel_dp *intel_dp; 4054 4055 if (!dev) 4056 return -ENODEV; 4057 4058 list_for_each_entry(connector, connector_list, head) { 4059 4060 if (connector->connector_type != 4061 DRM_MODE_CONNECTOR_DisplayPort) 4062 continue; 4063 4064 if (connector->status == connector_status_connected && 4065 connector->encoder != NULL) { 4066 intel_dp = enc_to_intel_dp(connector->encoder); 4067 if (intel_dp->compliance_test_active) 4068 seq_puts(m, "1"); 4069 else 4070 seq_puts(m, "0"); 4071 } else 4072 seq_puts(m, "0"); 4073 } 4074 4075 return 0; 4076 } 4077 4078 static int i915_displayport_test_active_open(struct inode *inode, 4079 struct file *file) 4080 { 4081 struct drm_device *dev = inode->i_private; 4082 4083 return single_open(file, i915_displayport_test_active_show, dev); 4084 } 4085 4086 static const struct file_operations i915_displayport_test_active_fops = { 4087 .owner = THIS_MODULE, 4088 .open = i915_displayport_test_active_open, 4089 .read = seq_read, 4090 .llseek = seq_lseek, 4091 .release = single_release, 4092 .write = i915_displayport_test_active_write 4093 }; 4094 4095 static int i915_displayport_test_data_show(struct seq_file *m, void *data) 4096 { 4097 struct drm_device *dev = m->private; 4098 struct drm_connector *connector; 4099 struct list_head *connector_list = &dev->mode_config.connector_list; 4100 struct intel_dp *intel_dp; 4101 4102 if (!dev) 4103 return -ENODEV; 4104 4105 list_for_each_entry(connector, connector_list, head) { 4106 4107 if (connector->connector_type != 4108 DRM_MODE_CONNECTOR_DisplayPort) 4109 continue; 4110 4111 if (connector->status == connector_status_connected && 4112 connector->encoder != NULL) { 4113 intel_dp = enc_to_intel_dp(connector->encoder); 4114 seq_printf(m, "%lx", intel_dp->compliance_test_data); 4115 } else 4116 seq_puts(m, "0"); 4117 } 4118 4119 return 0; 4120 } 4121 static int i915_displayport_test_data_open(struct inode *inode, 4122 struct file *file) 4123 { 4124 struct drm_device *dev = inode->i_private; 4125 4126 return single_open(file, i915_displayport_test_data_show, dev); 4127 } 4128 4129 static const struct file_operations i915_displayport_test_data_fops = { 4130 .owner = THIS_MODULE, 4131 .open = i915_displayport_test_data_open, 4132 .read = seq_read, 4133 .llseek = seq_lseek, 4134 .release = single_release 4135 }; 4136 4137 static int i915_displayport_test_type_show(struct seq_file *m, void *data) 4138 { 4139 struct drm_device *dev = m->private; 4140 struct drm_connector *connector; 4141 struct list_head *connector_list = &dev->mode_config.connector_list; 4142 struct intel_dp *intel_dp; 4143 4144 if (!dev) 4145 return -ENODEV; 4146 4147 list_for_each_entry(connector, connector_list, head) { 4148 4149 if (connector->connector_type != 4150 DRM_MODE_CONNECTOR_DisplayPort) 4151 continue; 4152 4153 if (connector->status == connector_status_connected && 4154 connector->encoder != NULL) { 4155 intel_dp = enc_to_intel_dp(connector->encoder); 4156 seq_printf(m, "%02lx", intel_dp->compliance_test_type); 4157 } else 4158 seq_puts(m, "0"); 4159 } 4160 4161 return 0; 4162 } 4163 4164 static int i915_displayport_test_type_open(struct inode *inode, 4165 struct file *file) 4166 { 4167 struct drm_device *dev = inode->i_private; 4168 4169 return single_open(file, i915_displayport_test_type_show, dev); 4170 } 4171 4172 static const struct file_operations i915_displayport_test_type_fops = { 4173 .owner = THIS_MODULE, 4174 .open = i915_displayport_test_type_open, 4175 .read = seq_read, 4176 .llseek = seq_lseek, 4177 .release = single_release 4178 }; 4179 4180 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) 4181 { 4182 struct drm_device *dev = m->private; 4183 int num_levels = ilk_wm_max_level(dev) + 1; 4184 int level; 4185 4186 drm_modeset_lock_all(dev); 4187 4188 for (level = 0; level < num_levels; level++) { 4189 unsigned int latency = wm[level]; 4190 4191 /* 4192 * - WM1+ latency values in 0.5us units 4193 * - latencies are in us on gen9 4194 */ 4195 if (INTEL_INFO(dev)->gen >= 9) 4196 latency *= 10; 4197 else if (level > 0) 4198 latency *= 5; 4199 4200 seq_printf(m, "WM%d %u (%u.%u usec)\n", 4201 level, wm[level], latency / 10, latency % 10); 4202 } 4203 4204 drm_modeset_unlock_all(dev); 4205 } 4206 4207 static int pri_wm_latency_show(struct seq_file *m, void *data) 4208 { 4209 struct drm_device *dev = m->private; 4210 struct drm_i915_private *dev_priv = dev->dev_private; 4211 const uint16_t *latencies; 4212 4213 if (INTEL_INFO(dev)->gen >= 9) 4214 latencies = dev_priv->wm.skl_latency; 4215 else 4216 latencies = to_i915(dev)->wm.pri_latency; 4217 4218 wm_latency_show(m, latencies); 4219 4220 return 0; 4221 } 4222 4223 static int spr_wm_latency_show(struct seq_file *m, void *data) 4224 { 4225 struct drm_device *dev = m->private; 4226 struct drm_i915_private *dev_priv = dev->dev_private; 4227 const uint16_t *latencies; 4228 4229 if (INTEL_INFO(dev)->gen >= 9) 4230 latencies = dev_priv->wm.skl_latency; 4231 else 4232 latencies = to_i915(dev)->wm.spr_latency; 4233 4234 wm_latency_show(m, latencies); 4235 4236 return 0; 4237 } 4238 4239 static int cur_wm_latency_show(struct seq_file *m, void *data) 4240 { 4241 struct drm_device *dev = m->private; 4242 struct drm_i915_private *dev_priv = dev->dev_private; 4243 const uint16_t *latencies; 4244 4245 if (INTEL_INFO(dev)->gen >= 9) 4246 latencies = dev_priv->wm.skl_latency; 4247 else 4248 latencies = to_i915(dev)->wm.cur_latency; 4249 4250 wm_latency_show(m, latencies); 4251 4252 return 0; 4253 } 4254 4255 static int pri_wm_latency_open(struct inode *inode, struct file *file) 4256 { 4257 struct drm_device *dev = inode->i_private; 4258 4259 if (HAS_GMCH_DISPLAY(dev)) 4260 return -ENODEV; 4261 4262 return single_open(file, pri_wm_latency_show, dev); 4263 } 4264 4265 static int spr_wm_latency_open(struct inode *inode, struct file *file) 4266 { 4267 struct drm_device *dev = inode->i_private; 4268 4269 if (HAS_GMCH_DISPLAY(dev)) 4270 return -ENODEV; 4271 4272 return single_open(file, spr_wm_latency_show, dev); 4273 } 4274 4275 static int cur_wm_latency_open(struct inode *inode, struct file *file) 4276 { 4277 struct drm_device *dev = inode->i_private; 4278 4279 if (HAS_GMCH_DISPLAY(dev)) 4280 return -ENODEV; 4281 4282 return single_open(file, cur_wm_latency_show, dev); 4283 } 4284 4285 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, 4286 size_t len, loff_t *offp, uint16_t wm[8]) 4287 { 4288 struct seq_file *m = file->private_data; 4289 struct drm_device *dev = m->private; 4290 uint16_t new[8] = { 0 }; 4291 int num_levels = ilk_wm_max_level(dev) + 1; 4292 int level; 4293 int ret; 4294 char tmp[32]; 4295 4296 if (len >= sizeof(tmp)) 4297 return -EINVAL; 4298 4299 if (copy_from_user(tmp, ubuf, len)) 4300 return -EFAULT; 4301 4302 tmp[len] = '\0'; 4303 4304 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", 4305 &new[0], &new[1], &new[2], &new[3], 4306 &new[4], &new[5], &new[6], &new[7]); 4307 if (ret != num_levels) 4308 return -EINVAL; 4309 4310 drm_modeset_lock_all(dev); 4311 4312 for (level = 0; level < num_levels; level++) 4313 wm[level] = new[level]; 4314 4315 drm_modeset_unlock_all(dev); 4316 4317 return len; 4318 } 4319 4320 4321 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, 4322 size_t len, loff_t *offp) 4323 { 4324 struct seq_file *m = file->private_data; 4325 struct drm_device *dev = m->private; 4326 struct drm_i915_private *dev_priv = dev->dev_private; 4327 uint16_t *latencies; 4328 4329 if (INTEL_INFO(dev)->gen >= 9) 4330 latencies = dev_priv->wm.skl_latency; 4331 else 4332 latencies = to_i915(dev)->wm.pri_latency; 4333 4334 return wm_latency_write(file, ubuf, len, offp, latencies); 4335 } 4336 4337 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, 4338 size_t len, loff_t *offp) 4339 { 4340 struct seq_file *m = file->private_data; 4341 struct drm_device *dev = m->private; 4342 struct drm_i915_private *dev_priv = dev->dev_private; 4343 uint16_t *latencies; 4344 4345 if (INTEL_INFO(dev)->gen >= 9) 4346 latencies = dev_priv->wm.skl_latency; 4347 else 4348 latencies = to_i915(dev)->wm.spr_latency; 4349 4350 return wm_latency_write(file, ubuf, len, offp, latencies); 4351 } 4352 4353 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, 4354 size_t len, loff_t *offp) 4355 { 4356 struct seq_file *m = file->private_data; 4357 struct drm_device *dev = m->private; 4358 struct drm_i915_private *dev_priv = dev->dev_private; 4359 uint16_t *latencies; 4360 4361 if (INTEL_INFO(dev)->gen >= 9) 4362 latencies = dev_priv->wm.skl_latency; 4363 else 4364 latencies = to_i915(dev)->wm.cur_latency; 4365 4366 return wm_latency_write(file, ubuf, len, offp, latencies); 4367 } 4368 4369 static const struct file_operations i915_pri_wm_latency_fops = { 4370 .owner = THIS_MODULE, 4371 .open = pri_wm_latency_open, 4372 .read = seq_read, 4373 .llseek = seq_lseek, 4374 .release = single_release, 4375 .write = pri_wm_latency_write 4376 }; 4377 4378 static const struct file_operations i915_spr_wm_latency_fops = { 4379 .owner = THIS_MODULE, 4380 .open = spr_wm_latency_open, 4381 .read = seq_read, 4382 .llseek = seq_lseek, 4383 .release = single_release, 4384 .write = spr_wm_latency_write 4385 }; 4386 4387 static const struct file_operations i915_cur_wm_latency_fops = { 4388 .owner = THIS_MODULE, 4389 .open = cur_wm_latency_open, 4390 .read = seq_read, 4391 .llseek = seq_lseek, 4392 .release = single_release, 4393 .write = cur_wm_latency_write 4394 }; 4395 4396 static int 4397 i915_wedged_get(void *data, u64 *val) 4398 { 4399 struct drm_device *dev = data; 4400 struct drm_i915_private *dev_priv = dev->dev_private; 4401 4402 *val = atomic_read(&dev_priv->gpu_error.reset_counter); 4403 4404 return 0; 4405 } 4406 4407 static int 4408 i915_wedged_set(void *data, u64 val) 4409 { 4410 struct drm_device *dev = data; 4411 struct drm_i915_private *dev_priv = dev->dev_private; 4412 4413 /* 4414 * There is no safeguard against this debugfs entry colliding 4415 * with the hangcheck calling same i915_handle_error() in 4416 * parallel, causing an explosion. For now we assume that the 4417 * test harness is responsible enough not to inject gpu hangs 4418 * while it is writing to 'i915_wedged' 4419 */ 4420 4421 if (i915_reset_in_progress(&dev_priv->gpu_error)) 4422 return -EAGAIN; 4423 4424 intel_runtime_pm_get(dev_priv); 4425 4426 i915_handle_error(dev, val, 4427 "Manually setting wedged to %llu", val); 4428 4429 intel_runtime_pm_put(dev_priv); 4430 4431 return 0; 4432 } 4433 4434 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops, 4435 i915_wedged_get, i915_wedged_set, 4436 "%llu\n"); 4437 4438 static int 4439 i915_ring_stop_get(void *data, u64 *val) 4440 { 4441 struct drm_device *dev = data; 4442 struct drm_i915_private *dev_priv = dev->dev_private; 4443 4444 *val = dev_priv->gpu_error.stop_rings; 4445 4446 return 0; 4447 } 4448 4449 static int 4450 i915_ring_stop_set(void *data, u64 val) 4451 { 4452 struct drm_device *dev = data; 4453 struct drm_i915_private *dev_priv = dev->dev_private; 4454 int ret; 4455 4456 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val); 4457 4458 ret = mutex_lock_interruptible(&dev->struct_mutex); 4459 if (ret) 4460 return ret; 4461 4462 dev_priv->gpu_error.stop_rings = val; 4463 mutex_unlock(&dev->struct_mutex); 4464 4465 return 0; 4466 } 4467 4468 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops, 4469 i915_ring_stop_get, i915_ring_stop_set, 4470 "0x%08llx\n"); 4471 4472 static int 4473 i915_ring_missed_irq_get(void *data, u64 *val) 4474 { 4475 struct drm_device *dev = data; 4476 struct drm_i915_private *dev_priv = dev->dev_private; 4477 4478 *val = dev_priv->gpu_error.missed_irq_rings; 4479 return 0; 4480 } 4481 4482 static int 4483 i915_ring_missed_irq_set(void *data, u64 val) 4484 { 4485 struct drm_device *dev = data; 4486 struct drm_i915_private *dev_priv = dev->dev_private; 4487 int ret; 4488 4489 /* Lock against concurrent debugfs callers */ 4490 ret = mutex_lock_interruptible(&dev->struct_mutex); 4491 if (ret) 4492 return ret; 4493 dev_priv->gpu_error.missed_irq_rings = val; 4494 mutex_unlock(&dev->struct_mutex); 4495 4496 return 0; 4497 } 4498 4499 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops, 4500 i915_ring_missed_irq_get, i915_ring_missed_irq_set, 4501 "0x%08llx\n"); 4502 4503 static int 4504 i915_ring_test_irq_get(void *data, u64 *val) 4505 { 4506 struct drm_device *dev = data; 4507 struct drm_i915_private *dev_priv = dev->dev_private; 4508 4509 *val = dev_priv->gpu_error.test_irq_rings; 4510 4511 return 0; 4512 } 4513 4514 static int 4515 i915_ring_test_irq_set(void *data, u64 val) 4516 { 4517 struct drm_device *dev = data; 4518 struct drm_i915_private *dev_priv = dev->dev_private; 4519 int ret; 4520 4521 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val); 4522 4523 /* Lock against concurrent debugfs callers */ 4524 ret = mutex_lock_interruptible(&dev->struct_mutex); 4525 if (ret) 4526 return ret; 4527 4528 dev_priv->gpu_error.test_irq_rings = val; 4529 mutex_unlock(&dev->struct_mutex); 4530 4531 return 0; 4532 } 4533 4534 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops, 4535 i915_ring_test_irq_get, i915_ring_test_irq_set, 4536 "0x%08llx\n"); 4537 4538 #define DROP_UNBOUND 0x1 4539 #define DROP_BOUND 0x2 4540 #define DROP_RETIRE 0x4 4541 #define DROP_ACTIVE 0x8 4542 #define DROP_ALL (DROP_UNBOUND | \ 4543 DROP_BOUND | \ 4544 DROP_RETIRE | \ 4545 DROP_ACTIVE) 4546 static int 4547 i915_drop_caches_get(void *data, u64 *val) 4548 { 4549 *val = DROP_ALL; 4550 4551 return 0; 4552 } 4553 4554 static int 4555 i915_drop_caches_set(void *data, u64 val) 4556 { 4557 struct drm_device *dev = data; 4558 struct drm_i915_private *dev_priv = dev->dev_private; 4559 int ret; 4560 4561 DRM_DEBUG("Dropping caches: 0x%08llx\n", val); 4562 4563 /* No need to check and wait for gpu resets, only libdrm auto-restarts 4564 * on ioctls on -EAGAIN. */ 4565 ret = mutex_lock_interruptible(&dev->struct_mutex); 4566 if (ret) 4567 return ret; 4568 4569 if (val & DROP_ACTIVE) { 4570 ret = i915_gpu_idle(dev); 4571 if (ret) 4572 goto unlock; 4573 } 4574 4575 if (val & (DROP_RETIRE | DROP_ACTIVE)) 4576 i915_gem_retire_requests(dev); 4577 4578 if (val & DROP_BOUND) 4579 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND); 4580 4581 if (val & DROP_UNBOUND) 4582 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND); 4583 4584 unlock: 4585 mutex_unlock(&dev->struct_mutex); 4586 4587 return ret; 4588 } 4589 4590 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops, 4591 i915_drop_caches_get, i915_drop_caches_set, 4592 "0x%08llx\n"); 4593 4594 static int 4595 i915_max_freq_get(void *data, u64 *val) 4596 { 4597 struct drm_device *dev = data; 4598 struct drm_i915_private *dev_priv = dev->dev_private; 4599 int ret; 4600 4601 if (INTEL_INFO(dev)->gen < 6) 4602 return -ENODEV; 4603 4604 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4605 4606 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4607 if (ret) 4608 return ret; 4609 4610 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit); 4611 mutex_unlock(&dev_priv->rps.hw_lock); 4612 4613 return 0; 4614 } 4615 4616 static int 4617 i915_max_freq_set(void *data, u64 val) 4618 { 4619 struct drm_device *dev = data; 4620 struct drm_i915_private *dev_priv = dev->dev_private; 4621 u32 hw_max, hw_min; 4622 int ret; 4623 4624 if (INTEL_INFO(dev)->gen < 6) 4625 return -ENODEV; 4626 4627 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4628 4629 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val); 4630 4631 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4632 if (ret) 4633 return ret; 4634 4635 /* 4636 * Turbo will still be enabled, but won't go above the set value. 4637 */ 4638 val = intel_freq_opcode(dev_priv, val); 4639 4640 hw_max = dev_priv->rps.max_freq; 4641 hw_min = dev_priv->rps.min_freq; 4642 4643 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) { 4644 mutex_unlock(&dev_priv->rps.hw_lock); 4645 return -EINVAL; 4646 } 4647 4648 dev_priv->rps.max_freq_softlimit = val; 4649 4650 intel_set_rps(dev, val); 4651 4652 mutex_unlock(&dev_priv->rps.hw_lock); 4653 4654 return 0; 4655 } 4656 4657 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops, 4658 i915_max_freq_get, i915_max_freq_set, 4659 "%llu\n"); 4660 4661 static int 4662 i915_min_freq_get(void *data, u64 *val) 4663 { 4664 struct drm_device *dev = data; 4665 struct drm_i915_private *dev_priv = dev->dev_private; 4666 int ret; 4667 4668 if (INTEL_INFO(dev)->gen < 6) 4669 return -ENODEV; 4670 4671 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4672 4673 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4674 if (ret) 4675 return ret; 4676 4677 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit); 4678 mutex_unlock(&dev_priv->rps.hw_lock); 4679 4680 return 0; 4681 } 4682 4683 static int 4684 i915_min_freq_set(void *data, u64 val) 4685 { 4686 struct drm_device *dev = data; 4687 struct drm_i915_private *dev_priv = dev->dev_private; 4688 u32 hw_max, hw_min; 4689 int ret; 4690 4691 if (INTEL_INFO(dev)->gen < 6) 4692 return -ENODEV; 4693 4694 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 4695 4696 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val); 4697 4698 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock); 4699 if (ret) 4700 return ret; 4701 4702 /* 4703 * Turbo will still be enabled, but won't go below the set value. 4704 */ 4705 val = intel_freq_opcode(dev_priv, val); 4706 4707 hw_max = dev_priv->rps.max_freq; 4708 hw_min = dev_priv->rps.min_freq; 4709 4710 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) { 4711 mutex_unlock(&dev_priv->rps.hw_lock); 4712 return -EINVAL; 4713 } 4714 4715 dev_priv->rps.min_freq_softlimit = val; 4716 4717 intel_set_rps(dev, val); 4718 4719 mutex_unlock(&dev_priv->rps.hw_lock); 4720 4721 return 0; 4722 } 4723 4724 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops, 4725 i915_min_freq_get, i915_min_freq_set, 4726 "%llu\n"); 4727 4728 static int 4729 i915_cache_sharing_get(void *data, u64 *val) 4730 { 4731 struct drm_device *dev = data; 4732 struct drm_i915_private *dev_priv = dev->dev_private; 4733 u32 snpcr; 4734 int ret; 4735 4736 if (!(IS_GEN6(dev) || IS_GEN7(dev))) 4737 return -ENODEV; 4738 4739 ret = mutex_lock_interruptible(&dev->struct_mutex); 4740 if (ret) 4741 return ret; 4742 intel_runtime_pm_get(dev_priv); 4743 4744 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 4745 4746 intel_runtime_pm_put(dev_priv); 4747 mutex_unlock(&dev_priv->dev->struct_mutex); 4748 4749 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT; 4750 4751 return 0; 4752 } 4753 4754 static int 4755 i915_cache_sharing_set(void *data, u64 val) 4756 { 4757 struct drm_device *dev = data; 4758 struct drm_i915_private *dev_priv = dev->dev_private; 4759 u32 snpcr; 4760 4761 if (!(IS_GEN6(dev) || IS_GEN7(dev))) 4762 return -ENODEV; 4763 4764 if (val > 3) 4765 return -EINVAL; 4766 4767 intel_runtime_pm_get(dev_priv); 4768 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val); 4769 4770 /* Update the cache sharing policy here as well */ 4771 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 4772 snpcr &= ~GEN6_MBC_SNPCR_MASK; 4773 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT); 4774 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 4775 4776 intel_runtime_pm_put(dev_priv); 4777 return 0; 4778 } 4779 4780 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, 4781 i915_cache_sharing_get, i915_cache_sharing_set, 4782 "%llu\n"); 4783 4784 struct sseu_dev_status { 4785 unsigned int slice_total; 4786 unsigned int subslice_total; 4787 unsigned int subslice_per_slice; 4788 unsigned int eu_total; 4789 unsigned int eu_per_subslice; 4790 }; 4791 4792 static void cherryview_sseu_device_status(struct drm_device *dev, 4793 struct sseu_dev_status *stat) 4794 { 4795 struct drm_i915_private *dev_priv = dev->dev_private; 4796 const int ss_max = 2; 4797 int ss; 4798 u32 sig1[ss_max], sig2[ss_max]; 4799 4800 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); 4801 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); 4802 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); 4803 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); 4804 4805 for (ss = 0; ss < ss_max; ss++) { 4806 unsigned int eu_cnt; 4807 4808 if (sig1[ss] & CHV_SS_PG_ENABLE) 4809 /* skip disabled subslice */ 4810 continue; 4811 4812 stat->slice_total = 1; 4813 stat->subslice_per_slice++; 4814 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + 4815 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + 4816 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + 4817 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); 4818 stat->eu_total += eu_cnt; 4819 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt); 4820 } 4821 stat->subslice_total = stat->subslice_per_slice; 4822 } 4823 4824 static void gen9_sseu_device_status(struct drm_device *dev, 4825 struct sseu_dev_status *stat) 4826 { 4827 struct drm_i915_private *dev_priv = dev->dev_private; 4828 int s_max = 3, ss_max = 4; 4829 int s, ss; 4830 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; 4831 4832 /* BXT has a single slice and at most 3 subslices. */ 4833 if (IS_BROXTON(dev)) { 4834 s_max = 1; 4835 ss_max = 3; 4836 } 4837 4838 for (s = 0; s < s_max; s++) { 4839 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s)); 4840 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s)); 4841 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s)); 4842 } 4843 4844 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK | 4845 GEN9_PGCTL_SSA_EU19_ACK | 4846 GEN9_PGCTL_SSA_EU210_ACK | 4847 GEN9_PGCTL_SSA_EU311_ACK; 4848 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK | 4849 GEN9_PGCTL_SSB_EU19_ACK | 4850 GEN9_PGCTL_SSB_EU210_ACK | 4851 GEN9_PGCTL_SSB_EU311_ACK; 4852 4853 for (s = 0; s < s_max; s++) { 4854 unsigned int ss_cnt = 0; 4855 4856 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) 4857 /* skip disabled slice */ 4858 continue; 4859 4860 stat->slice_total++; 4861 4862 if (IS_SKYLAKE(dev)) 4863 ss_cnt = INTEL_INFO(dev)->subslice_per_slice; 4864 4865 for (ss = 0; ss < ss_max; ss++) { 4866 unsigned int eu_cnt; 4867 4868 if (IS_BROXTON(dev) && 4869 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) 4870 /* skip disabled subslice */ 4871 continue; 4872 4873 if (IS_BROXTON(dev)) 4874 ss_cnt++; 4875 4876 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & 4877 eu_mask[ss%2]); 4878 stat->eu_total += eu_cnt; 4879 stat->eu_per_subslice = max(stat->eu_per_subslice, 4880 eu_cnt); 4881 } 4882 4883 stat->subslice_total += ss_cnt; 4884 stat->subslice_per_slice = max(stat->subslice_per_slice, 4885 ss_cnt); 4886 } 4887 } 4888 4889 static int i915_sseu_status(struct seq_file *m, void *unused) 4890 { 4891 struct drm_info_node *node = (struct drm_info_node *) m->private; 4892 struct drm_device *dev = node->minor->dev; 4893 struct sseu_dev_status stat; 4894 4895 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev)) 4896 return -ENODEV; 4897 4898 seq_puts(m, "SSEU Device Info\n"); 4899 seq_printf(m, " Available Slice Total: %u\n", 4900 INTEL_INFO(dev)->slice_total); 4901 seq_printf(m, " Available Subslice Total: %u\n", 4902 INTEL_INFO(dev)->subslice_total); 4903 seq_printf(m, " Available Subslice Per Slice: %u\n", 4904 INTEL_INFO(dev)->subslice_per_slice); 4905 seq_printf(m, " Available EU Total: %u\n", 4906 INTEL_INFO(dev)->eu_total); 4907 seq_printf(m, " Available EU Per Subslice: %u\n", 4908 INTEL_INFO(dev)->eu_per_subslice); 4909 seq_printf(m, " Has Slice Power Gating: %s\n", 4910 yesno(INTEL_INFO(dev)->has_slice_pg)); 4911 seq_printf(m, " Has Subslice Power Gating: %s\n", 4912 yesno(INTEL_INFO(dev)->has_subslice_pg)); 4913 seq_printf(m, " Has EU Power Gating: %s\n", 4914 yesno(INTEL_INFO(dev)->has_eu_pg)); 4915 4916 seq_puts(m, "SSEU Device Status\n"); 4917 memset(&stat, 0, sizeof(stat)); 4918 if (IS_CHERRYVIEW(dev)) { 4919 cherryview_sseu_device_status(dev, &stat); 4920 } else if (INTEL_INFO(dev)->gen >= 9) { 4921 gen9_sseu_device_status(dev, &stat); 4922 } 4923 seq_printf(m, " Enabled Slice Total: %u\n", 4924 stat.slice_total); 4925 seq_printf(m, " Enabled Subslice Total: %u\n", 4926 stat.subslice_total); 4927 seq_printf(m, " Enabled Subslice Per Slice: %u\n", 4928 stat.subslice_per_slice); 4929 seq_printf(m, " Enabled EU Total: %u\n", 4930 stat.eu_total); 4931 seq_printf(m, " Enabled EU Per Subslice: %u\n", 4932 stat.eu_per_subslice); 4933 4934 return 0; 4935 } 4936 4937 static int i915_forcewake_open(struct inode *inode, struct file *file) 4938 { 4939 struct drm_device *dev = inode->i_private; 4940 struct drm_i915_private *dev_priv = dev->dev_private; 4941 4942 if (INTEL_INFO(dev)->gen < 6) 4943 return 0; 4944 4945 intel_runtime_pm_get(dev_priv); 4946 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4947 4948 return 0; 4949 } 4950 4951 static int i915_forcewake_release(struct inode *inode, struct file *file) 4952 { 4953 struct drm_device *dev = inode->i_private; 4954 struct drm_i915_private *dev_priv = dev->dev_private; 4955 4956 if (INTEL_INFO(dev)->gen < 6) 4957 return 0; 4958 4959 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4960 intel_runtime_pm_put(dev_priv); 4961 4962 return 0; 4963 } 4964 4965 static const struct file_operations i915_forcewake_fops = { 4966 .owner = THIS_MODULE, 4967 .open = i915_forcewake_open, 4968 .release = i915_forcewake_release, 4969 }; 4970 4971 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) 4972 { 4973 struct drm_device *dev = minor->dev; 4974 struct dentry *ent; 4975 4976 ent = debugfs_create_file("i915_forcewake_user", 4977 S_IRUSR, 4978 root, dev, 4979 &i915_forcewake_fops); 4980 if (!ent) 4981 return -ENOMEM; 4982 4983 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); 4984 } 4985 4986 static int i915_debugfs_create(struct dentry *root, 4987 struct drm_minor *minor, 4988 const char *name, 4989 const struct file_operations *fops) 4990 { 4991 struct drm_device *dev = minor->dev; 4992 struct dentry *ent; 4993 4994 ent = debugfs_create_file(name, 4995 S_IRUGO | S_IWUSR, 4996 root, dev, 4997 fops); 4998 if (!ent) 4999 return -ENOMEM; 5000 5001 return drm_add_fake_info_node(minor, ent, fops); 5002 } 5003 5004 static const struct drm_info_list i915_debugfs_list[] = { 5005 {"i915_capabilities", i915_capabilities, 0}, 5006 {"i915_gem_objects", i915_gem_object_info, 0}, 5007 {"i915_gem_gtt", i915_gem_gtt_info, 0}, 5008 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST}, 5009 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 5010 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 5011 {"i915_gem_stolen", i915_gem_stolen_list_info }, 5012 {"i915_gem_pageflip", i915_gem_pageflip_info, 0}, 5013 {"i915_gem_request", i915_gem_request_info, 0}, 5014 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 5015 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 5016 {"i915_gem_interrupt", i915_interrupt_info, 0}, 5017 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS}, 5018 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS}, 5019 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS}, 5020 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, 5021 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, 5022 {"i915_frequency_info", i915_frequency_info, 0}, 5023 {"i915_hangcheck_info", i915_hangcheck_info, 0}, 5024 {"i915_drpc_info", i915_drpc_info, 0}, 5025 {"i915_emon_status", i915_emon_status, 0}, 5026 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 5027 {"i915_fbc_status", i915_fbc_status, 0}, 5028 {"i915_ips_status", i915_ips_status, 0}, 5029 {"i915_sr_status", i915_sr_status, 0}, 5030 {"i915_opregion", i915_opregion, 0}, 5031 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 5032 {"i915_context_status", i915_context_status, 0}, 5033 {"i915_dump_lrc", i915_dump_lrc, 0}, 5034 {"i915_execlists", i915_execlists, 0}, 5035 {"i915_forcewake_domains", i915_forcewake_domains, 0}, 5036 {"i915_swizzle_info", i915_swizzle_info, 0}, 5037 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 5038 {"i915_llc", i915_llc, 0}, 5039 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 5040 {"i915_sink_crc_eDP1", i915_sink_crc, 0}, 5041 {"i915_energy_uJ", i915_energy_uJ, 0}, 5042 {"i915_pc8_status", i915_pc8_status, 0}, 5043 {"i915_power_domain_info", i915_power_domain_info, 0}, 5044 {"i915_display_info", i915_display_info, 0}, 5045 {"i915_semaphore_status", i915_semaphore_status, 0}, 5046 {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, 5047 {"i915_dp_mst_info", i915_dp_mst_info, 0}, 5048 {"i915_wa_registers", i915_wa_registers, 0}, 5049 {"i915_ddb_info", i915_ddb_info, 0}, 5050 {"i915_sseu_status", i915_sseu_status, 0}, 5051 {"i915_drrs_status", i915_drrs_status, 0}, 5052 {"i915_rps_boost_info", i915_rps_boost_info, 0}, 5053 }; 5054 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 5055 5056 static const struct i915_debugfs_files { 5057 const char *name; 5058 const struct file_operations *fops; 5059 } i915_debugfs_files[] = { 5060 {"i915_wedged", &i915_wedged_fops}, 5061 {"i915_max_freq", &i915_max_freq_fops}, 5062 {"i915_min_freq", &i915_min_freq_fops}, 5063 {"i915_cache_sharing", &i915_cache_sharing_fops}, 5064 {"i915_ring_stop", &i915_ring_stop_fops}, 5065 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops}, 5066 {"i915_ring_test_irq", &i915_ring_test_irq_fops}, 5067 {"i915_gem_drop_caches", &i915_drop_caches_fops}, 5068 {"i915_error_state", &i915_error_state_fops}, 5069 {"i915_next_seqno", &i915_next_seqno_fops}, 5070 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops}, 5071 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, 5072 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, 5073 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, 5074 {"i915_fbc_false_color", &i915_fbc_fc_fops}, 5075 {"i915_dp_test_data", &i915_displayport_test_data_fops}, 5076 {"i915_dp_test_type", &i915_displayport_test_type_fops}, 5077 {"i915_dp_test_active", &i915_displayport_test_active_fops} 5078 }; 5079 5080 void intel_display_crc_init(struct drm_device *dev) 5081 { 5082 struct drm_i915_private *dev_priv = dev->dev_private; 5083 enum pipe pipe; 5084 5085 for_each_pipe(dev_priv, pipe) { 5086 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 5087 5088 pipe_crc->opened = false; 5089 spin_lock_init(&pipe_crc->lock); 5090 init_waitqueue_head(&pipe_crc->wq); 5091 } 5092 } 5093 5094 int i915_debugfs_init(struct drm_minor *minor) 5095 { 5096 int ret, i; 5097 5098 ret = i915_forcewake_create(minor->debugfs_root, minor); 5099 if (ret) 5100 return ret; 5101 5102 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5103 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i); 5104 if (ret) 5105 return ret; 5106 } 5107 5108 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5109 ret = i915_debugfs_create(minor->debugfs_root, minor, 5110 i915_debugfs_files[i].name, 5111 i915_debugfs_files[i].fops); 5112 if (ret) 5113 return ret; 5114 } 5115 5116 return drm_debugfs_create_files(i915_debugfs_list, 5117 I915_DEBUGFS_ENTRIES, 5118 minor->debugfs_root, minor); 5119 } 5120 5121 void i915_debugfs_cleanup(struct drm_minor *minor) 5122 { 5123 int i; 5124 5125 drm_debugfs_remove_files(i915_debugfs_list, 5126 I915_DEBUGFS_ENTRIES, minor); 5127 5128 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops, 5129 1, minor); 5130 5131 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { 5132 struct drm_info_list *info_list = 5133 (struct drm_info_list *)&i915_pipe_crc_data[i]; 5134 5135 drm_debugfs_remove_files(info_list, 1, minor); 5136 } 5137 5138 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) { 5139 struct drm_info_list *info_list = 5140 (struct drm_info_list *) i915_debugfs_files[i].fops; 5141 5142 drm_debugfs_remove_files(info_list, 1, minor); 5143 } 5144 } 5145 5146 struct dpcd_block { 5147 /* DPCD dump start address. */ 5148 unsigned int offset; 5149 /* DPCD dump end address, inclusive. If unset, .size will be used. */ 5150 unsigned int end; 5151 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */ 5152 size_t size; 5153 /* Only valid for eDP. */ 5154 bool edp; 5155 }; 5156 5157 static const struct dpcd_block i915_dpcd_debug[] = { 5158 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE }, 5159 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS }, 5160 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 }, 5161 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET }, 5162 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 }, 5163 { .offset = DP_SET_POWER }, 5164 { .offset = DP_EDP_DPCD_REV }, 5165 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 }, 5166 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB }, 5167 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET }, 5168 }; 5169 5170 static int i915_dpcd_show(struct seq_file *m, void *data) 5171 { 5172 struct drm_connector *connector = m->private; 5173 struct intel_dp *intel_dp = 5174 enc_to_intel_dp(&intel_attached_encoder(connector)->base); 5175 uint8_t buf[16]; 5176 ssize_t err; 5177 int i; 5178 5179 if (connector->status != connector_status_connected) 5180 return -ENODEV; 5181 5182 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) { 5183 const struct dpcd_block *b = &i915_dpcd_debug[i]; 5184 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1); 5185 5186 if (b->edp && 5187 connector->connector_type != DRM_MODE_CONNECTOR_eDP) 5188 continue; 5189 5190 /* low tech for now */ 5191 if (WARN_ON(size > sizeof(buf))) 5192 continue; 5193 5194 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size); 5195 if (err <= 0) { 5196 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n", 5197 size, b->offset, err); 5198 continue; 5199 } 5200 5201 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf); 5202 } 5203 5204 return 0; 5205 } 5206 5207 static int i915_dpcd_open(struct inode *inode, struct file *file) 5208 { 5209 return single_open(file, i915_dpcd_show, inode->i_private); 5210 } 5211 5212 static const struct file_operations i915_dpcd_fops = { 5213 .owner = THIS_MODULE, 5214 .open = i915_dpcd_open, 5215 .read = seq_read, 5216 .llseek = seq_lseek, 5217 .release = single_release, 5218 }; 5219 5220 /** 5221 * i915_debugfs_connector_add - add i915 specific connector debugfs files 5222 * @connector: pointer to a registered drm_connector 5223 * 5224 * Cleanup will be done by drm_connector_unregister() through a call to 5225 * drm_debugfs_connector_remove(). 5226 * 5227 * Returns 0 on success, negative error codes on error. 5228 */ 5229 int i915_debugfs_connector_add(struct drm_connector *connector) 5230 { 5231 struct dentry *root = connector->debugfs_entry; 5232 5233 /* The connector must have been registered beforehands. */ 5234 if (!root) 5235 return -ENODEV; 5236 5237 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5238 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5239 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector, 5240 &i915_dpcd_fops); 5241 5242 return 0; 5243 } 5244