1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include "gt/intel_engine.h" 29 30 #include "i915_drv.h" 31 32 /** 33 * DOC: batch buffer command parser 34 * 35 * Motivation: 36 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 37 * require userspace code to submit batches containing commands such as 38 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 39 * generations of the hardware will noop these commands in "unsecure" batches 40 * (which includes all userspace batches submitted via i915) even though the 41 * commands may be safe and represent the intended programming model of the 42 * device. 43 * 44 * The software command parser is similar in operation to the command parsing 45 * done in hardware for unsecure batches. However, the software parser allows 46 * some operations that would be noop'd by hardware, if the parser determines 47 * the operation is safe, and submits the batch as "secure" to prevent hardware 48 * parsing. 49 * 50 * Threats: 51 * At a high level, the hardware (and software) checks attempt to prevent 52 * granting userspace undue privileges. There are three categories of privilege. 53 * 54 * First, commands which are explicitly defined as privileged or which should 55 * only be used by the kernel driver. The parser generally rejects such 56 * commands, though it may allow some from the drm master process. 57 * 58 * Second, commands which access registers. To support correct/enhanced 59 * userspace functionality, particularly certain OpenGL extensions, the parser 60 * provides a whitelist of registers which userspace may safely access (for both 61 * normal and drm master processes). 62 * 63 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 64 * The parser always rejects such commands. 65 * 66 * The majority of the problematic commands fall in the MI_* range, with only a 67 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 68 * 69 * Implementation: 70 * Each engine maintains tables of commands and registers which the parser 71 * uses in scanning batch buffers submitted to that engine. 72 * 73 * Since the set of commands that the parser must check for is significantly 74 * smaller than the number of commands supported, the parser tables contain only 75 * those commands required by the parser. This generally works because command 76 * opcode ranges have standard command length encodings. So for commands that 77 * the parser does not need to check, it can easily skip them. This is 78 * implemented via a per-engine length decoding vfunc. 79 * 80 * Unfortunately, there are a number of commands that do not follow the standard 81 * length encoding for their opcode range, primarily amongst the MI_* commands. 82 * To handle this, the parser provides a way to define explicit "skip" entries 83 * in the per-engine command tables. 84 * 85 * Other command table entries map fairly directly to high level categories 86 * mentioned above: rejected, master-only, register whitelist. The parser 87 * implements a number of checks, including the privileged memory checks, via a 88 * general bitmasking mechanism. 89 */ 90 91 /* 92 * A command that requires special handling by the command parser. 93 */ 94 struct drm_i915_cmd_descriptor { 95 /* 96 * Flags describing how the command parser processes the command. 97 * 98 * CMD_DESC_FIXED: The command has a fixed length if this is set, 99 * a length mask if not set 100 * CMD_DESC_SKIP: The command is allowed but does not follow the 101 * standard length encoding for the opcode range in 102 * which it falls 103 * CMD_DESC_REJECT: The command is never allowed 104 * CMD_DESC_REGISTER: The command should be checked against the 105 * register whitelist for the appropriate ring 106 * CMD_DESC_MASTER: The command is allowed if the submitting process 107 * is the DRM master 108 */ 109 u32 flags; 110 #define CMD_DESC_FIXED (1<<0) 111 #define CMD_DESC_SKIP (1<<1) 112 #define CMD_DESC_REJECT (1<<2) 113 #define CMD_DESC_REGISTER (1<<3) 114 #define CMD_DESC_BITMASK (1<<4) 115 #define CMD_DESC_MASTER (1<<5) 116 117 /* 118 * The command's unique identification bits and the bitmask to get them. 119 * This isn't strictly the opcode field as defined in the spec and may 120 * also include type, subtype, and/or subop fields. 121 */ 122 struct { 123 u32 value; 124 u32 mask; 125 } cmd; 126 127 /* 128 * The command's length. The command is either fixed length (i.e. does 129 * not include a length field) or has a length field mask. The flag 130 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 131 * a length mask. All command entries in a command table must include 132 * length information. 133 */ 134 union { 135 u32 fixed; 136 u32 mask; 137 } length; 138 139 /* 140 * Describes where to find a register address in the command to check 141 * against the ring's register whitelist. Only valid if flags has the 142 * CMD_DESC_REGISTER bit set. 143 * 144 * A non-zero step value implies that the command may access multiple 145 * registers in sequence (e.g. LRI), in that case step gives the 146 * distance in dwords between individual offset fields. 147 */ 148 struct { 149 u32 offset; 150 u32 mask; 151 u32 step; 152 } reg; 153 154 #define MAX_CMD_DESC_BITMASKS 3 155 /* 156 * Describes command checks where a particular dword is masked and 157 * compared against an expected value. If the command does not match 158 * the expected value, the parser rejects it. Only valid if flags has 159 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 160 * are valid. 161 * 162 * If the check specifies a non-zero condition_mask then the parser 163 * only performs the check when the bits specified by condition_mask 164 * are non-zero. 165 */ 166 struct { 167 u32 offset; 168 u32 mask; 169 u32 expected; 170 u32 condition_offset; 171 u32 condition_mask; 172 } bits[MAX_CMD_DESC_BITMASKS]; 173 }; 174 175 /* 176 * A table of commands requiring special handling by the command parser. 177 * 178 * Each engine has an array of tables. Each table consists of an array of 179 * command descriptors, which must be sorted with command opcodes in 180 * ascending order. 181 */ 182 struct drm_i915_cmd_table { 183 const struct drm_i915_cmd_descriptor *table; 184 int count; 185 }; 186 187 #define STD_MI_OPCODE_SHIFT (32 - 9) 188 #define STD_3D_OPCODE_SHIFT (32 - 16) 189 #define STD_2D_OPCODE_SHIFT (32 - 10) 190 #define STD_MFX_OPCODE_SHIFT (32 - 16) 191 #define MIN_OPCODE_SHIFT 16 192 193 #define CMD(op, opm, f, lm, fl, ...) \ 194 { \ 195 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 196 .cmd = { (op), ~0u << (opm) }, \ 197 .length = { (lm) }, \ 198 __VA_ARGS__ \ 199 } 200 201 /* Convenience macros to compress the tables */ 202 #define SMI STD_MI_OPCODE_SHIFT 203 #define S3D STD_3D_OPCODE_SHIFT 204 #define S2D STD_2D_OPCODE_SHIFT 205 #define SMFX STD_MFX_OPCODE_SHIFT 206 #define F true 207 #define S CMD_DESC_SKIP 208 #define R CMD_DESC_REJECT 209 #define W CMD_DESC_REGISTER 210 #define B CMD_DESC_BITMASK 211 #define M CMD_DESC_MASTER 212 213 /* Command Mask Fixed Len Action 214 ---------------------------------------------------------- */ 215 static const struct drm_i915_cmd_descriptor common_cmds[] = { 216 CMD( MI_NOOP, SMI, F, 1, S ), 217 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 218 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 219 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 220 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 221 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 222 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 223 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 224 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 225 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 226 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 227 .reg = { .offset = 1, .mask = 0x007FFFFC }, 228 .bits = {{ 229 .offset = 0, 230 .mask = MI_GLOBAL_GTT, 231 .expected = 0, 232 }}, ), 233 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 234 .reg = { .offset = 1, .mask = 0x007FFFFC }, 235 .bits = {{ 236 .offset = 0, 237 .mask = MI_GLOBAL_GTT, 238 .expected = 0, 239 }}, ), 240 /* 241 * MI_BATCH_BUFFER_START requires some special handling. It's not 242 * really a 'skip' action but it doesn't seem like it's worth adding 243 * a new action. See i915_parse_cmds(). 244 */ 245 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 246 }; 247 248 static const struct drm_i915_cmd_descriptor render_cmds[] = { 249 CMD( MI_FLUSH, SMI, F, 1, S ), 250 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 251 CMD( MI_PREDICATE, SMI, F, 1, S ), 252 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 253 CMD( MI_SET_APPID, SMI, F, 1, S ), 254 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 255 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 256 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 257 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 258 .bits = {{ 259 .offset = 0, 260 .mask = MI_GLOBAL_GTT, 261 .expected = 0, 262 }}, ), 263 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 264 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 265 .bits = {{ 266 .offset = 0, 267 .mask = MI_GLOBAL_GTT, 268 .expected = 0, 269 }}, ), 270 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 271 .bits = {{ 272 .offset = 1, 273 .mask = MI_REPORT_PERF_COUNT_GGTT, 274 .expected = 0, 275 }}, ), 276 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 277 .bits = {{ 278 .offset = 0, 279 .mask = MI_GLOBAL_GTT, 280 .expected = 0, 281 }}, ), 282 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 283 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 284 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 285 .bits = {{ 286 .offset = 2, 287 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 288 .expected = 0, 289 }}, ), 290 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 291 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 292 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 293 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 294 .bits = {{ 295 .offset = 1, 296 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 297 .expected = 0, 298 }, 299 { 300 .offset = 1, 301 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 302 PIPE_CONTROL_STORE_DATA_INDEX), 303 .expected = 0, 304 .condition_offset = 1, 305 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 306 }}, ), 307 }; 308 309 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 310 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 311 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 312 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 313 CMD( MI_SET_APPID, SMI, F, 1, S ), 314 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 315 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 316 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 317 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 318 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 319 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 320 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 321 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 322 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 323 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 324 325 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 326 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 329 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 330 }; 331 332 static const struct drm_i915_cmd_descriptor video_cmds[] = { 333 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 334 CMD( MI_SET_APPID, SMI, F, 1, S ), 335 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 336 .bits = {{ 337 .offset = 0, 338 .mask = MI_GLOBAL_GTT, 339 .expected = 0, 340 }}, ), 341 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 342 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 343 .bits = {{ 344 .offset = 0, 345 .mask = MI_FLUSH_DW_NOTIFY, 346 .expected = 0, 347 }, 348 { 349 .offset = 1, 350 .mask = MI_FLUSH_DW_USE_GTT, 351 .expected = 0, 352 .condition_offset = 0, 353 .condition_mask = MI_FLUSH_DW_OP_MASK, 354 }, 355 { 356 .offset = 0, 357 .mask = MI_FLUSH_DW_STORE_INDEX, 358 .expected = 0, 359 .condition_offset = 0, 360 .condition_mask = MI_FLUSH_DW_OP_MASK, 361 }}, ), 362 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 363 .bits = {{ 364 .offset = 0, 365 .mask = MI_GLOBAL_GTT, 366 .expected = 0, 367 }}, ), 368 /* 369 * MFX_WAIT doesn't fit the way we handle length for most commands. 370 * It has a length field but it uses a non-standard length bias. 371 * It is always 1 dword though, so just treat it as fixed length. 372 */ 373 CMD( MFX_WAIT, SMFX, F, 1, S ), 374 }; 375 376 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 377 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 378 CMD( MI_SET_APPID, SMI, F, 1, S ), 379 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 380 .bits = {{ 381 .offset = 0, 382 .mask = MI_GLOBAL_GTT, 383 .expected = 0, 384 }}, ), 385 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 386 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 387 .bits = {{ 388 .offset = 0, 389 .mask = MI_FLUSH_DW_NOTIFY, 390 .expected = 0, 391 }, 392 { 393 .offset = 1, 394 .mask = MI_FLUSH_DW_USE_GTT, 395 .expected = 0, 396 .condition_offset = 0, 397 .condition_mask = MI_FLUSH_DW_OP_MASK, 398 }, 399 { 400 .offset = 0, 401 .mask = MI_FLUSH_DW_STORE_INDEX, 402 .expected = 0, 403 .condition_offset = 0, 404 .condition_mask = MI_FLUSH_DW_OP_MASK, 405 }}, ), 406 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 407 .bits = {{ 408 .offset = 0, 409 .mask = MI_GLOBAL_GTT, 410 .expected = 0, 411 }}, ), 412 }; 413 414 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 415 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 416 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 417 .bits = {{ 418 .offset = 0, 419 .mask = MI_GLOBAL_GTT, 420 .expected = 0, 421 }}, ), 422 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 423 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 424 .bits = {{ 425 .offset = 0, 426 .mask = MI_FLUSH_DW_NOTIFY, 427 .expected = 0, 428 }, 429 { 430 .offset = 1, 431 .mask = MI_FLUSH_DW_USE_GTT, 432 .expected = 0, 433 .condition_offset = 0, 434 .condition_mask = MI_FLUSH_DW_OP_MASK, 435 }, 436 { 437 .offset = 0, 438 .mask = MI_FLUSH_DW_STORE_INDEX, 439 .expected = 0, 440 .condition_offset = 0, 441 .condition_mask = MI_FLUSH_DW_OP_MASK, 442 }}, ), 443 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 444 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 445 }; 446 447 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 448 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 449 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 450 }; 451 452 static const struct drm_i915_cmd_descriptor noop_desc = 453 CMD(MI_NOOP, SMI, F, 1, S); 454 455 #undef CMD 456 #undef SMI 457 #undef S3D 458 #undef S2D 459 #undef SMFX 460 #undef F 461 #undef S 462 #undef R 463 #undef W 464 #undef B 465 #undef M 466 467 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 468 { common_cmds, ARRAY_SIZE(common_cmds) }, 469 { render_cmds, ARRAY_SIZE(render_cmds) }, 470 }; 471 472 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 473 { common_cmds, ARRAY_SIZE(common_cmds) }, 474 { render_cmds, ARRAY_SIZE(render_cmds) }, 475 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 476 }; 477 478 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 479 { common_cmds, ARRAY_SIZE(common_cmds) }, 480 { video_cmds, ARRAY_SIZE(video_cmds) }, 481 }; 482 483 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 484 { common_cmds, ARRAY_SIZE(common_cmds) }, 485 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 486 }; 487 488 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 489 { common_cmds, ARRAY_SIZE(common_cmds) }, 490 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 491 }; 492 493 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 494 { common_cmds, ARRAY_SIZE(common_cmds) }, 495 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 496 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 497 }; 498 499 /* 500 * Register whitelists, sorted by increasing register offset. 501 */ 502 503 /* 504 * An individual whitelist entry granting access to register addr. If 505 * mask is non-zero the argument of immediate register writes will be 506 * AND-ed with mask, and the command will be rejected if the result 507 * doesn't match value. 508 * 509 * Registers with non-zero mask are only allowed to be written using 510 * LRI. 511 */ 512 struct drm_i915_reg_descriptor { 513 i915_reg_t addr; 514 u32 mask; 515 u32 value; 516 }; 517 518 /* Convenience macro for adding 32-bit registers. */ 519 #define REG32(_reg, ...) \ 520 { .addr = (_reg), __VA_ARGS__ } 521 522 /* 523 * Convenience macro for adding 64-bit registers. 524 * 525 * Some registers that userspace accesses are 64 bits. The register 526 * access commands only allow 32-bit accesses. Hence, we have to include 527 * entries for both halves of the 64-bit registers. 528 */ 529 #define REG64(_reg) \ 530 { .addr = _reg }, \ 531 { .addr = _reg ## _UDW } 532 533 #define REG64_IDX(_reg, idx) \ 534 { .addr = _reg(idx) }, \ 535 { .addr = _reg ## _UDW(idx) } 536 537 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 538 REG64(GPGPU_THREADS_DISPATCHED), 539 REG64(HS_INVOCATION_COUNT), 540 REG64(DS_INVOCATION_COUNT), 541 REG64(IA_VERTICES_COUNT), 542 REG64(IA_PRIMITIVES_COUNT), 543 REG64(VS_INVOCATION_COUNT), 544 REG64(GS_INVOCATION_COUNT), 545 REG64(GS_PRIMITIVES_COUNT), 546 REG64(CL_INVOCATION_COUNT), 547 REG64(CL_PRIMITIVES_COUNT), 548 REG64(PS_INVOCATION_COUNT), 549 REG64(PS_DEPTH_COUNT), 550 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 551 REG64(MI_PREDICATE_SRC0), 552 REG64(MI_PREDICATE_SRC1), 553 REG32(GEN7_3DPRIM_END_OFFSET), 554 REG32(GEN7_3DPRIM_START_VERTEX), 555 REG32(GEN7_3DPRIM_VERTEX_COUNT), 556 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 557 REG32(GEN7_3DPRIM_START_INSTANCE), 558 REG32(GEN7_3DPRIM_BASE_VERTEX), 559 REG32(GEN7_GPGPU_DISPATCHDIMX), 560 REG32(GEN7_GPGPU_DISPATCHDIMY), 561 REG32(GEN7_GPGPU_DISPATCHDIMZ), 562 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 563 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 564 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 565 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 566 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 567 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 568 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 569 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 570 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 571 REG32(GEN7_SO_WRITE_OFFSET(0)), 572 REG32(GEN7_SO_WRITE_OFFSET(1)), 573 REG32(GEN7_SO_WRITE_OFFSET(2)), 574 REG32(GEN7_SO_WRITE_OFFSET(3)), 575 REG32(GEN7_L3SQCREG1), 576 REG32(GEN7_L3CNTLREG2), 577 REG32(GEN7_L3CNTLREG3), 578 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 579 }; 580 581 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 582 REG64_IDX(HSW_CS_GPR, 0), 583 REG64_IDX(HSW_CS_GPR, 1), 584 REG64_IDX(HSW_CS_GPR, 2), 585 REG64_IDX(HSW_CS_GPR, 3), 586 REG64_IDX(HSW_CS_GPR, 4), 587 REG64_IDX(HSW_CS_GPR, 5), 588 REG64_IDX(HSW_CS_GPR, 6), 589 REG64_IDX(HSW_CS_GPR, 7), 590 REG64_IDX(HSW_CS_GPR, 8), 591 REG64_IDX(HSW_CS_GPR, 9), 592 REG64_IDX(HSW_CS_GPR, 10), 593 REG64_IDX(HSW_CS_GPR, 11), 594 REG64_IDX(HSW_CS_GPR, 12), 595 REG64_IDX(HSW_CS_GPR, 13), 596 REG64_IDX(HSW_CS_GPR, 14), 597 REG64_IDX(HSW_CS_GPR, 15), 598 REG32(HSW_SCRATCH1, 599 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 600 .value = 0), 601 REG32(HSW_ROW_CHICKEN3, 602 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 603 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 604 .value = 0), 605 }; 606 607 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 608 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 609 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 610 REG32(BCS_SWCTRL), 611 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 612 }; 613 614 static const struct drm_i915_reg_descriptor ivb_master_regs[] = { 615 REG32(FORCEWAKE_MT), 616 REG32(DERRMR), 617 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), 618 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), 619 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), 620 }; 621 622 static const struct drm_i915_reg_descriptor hsw_master_regs[] = { 623 REG32(FORCEWAKE_MT), 624 REG32(DERRMR), 625 }; 626 627 #undef REG64 628 #undef REG32 629 630 struct drm_i915_reg_table { 631 const struct drm_i915_reg_descriptor *regs; 632 int num_regs; 633 bool master; 634 }; 635 636 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 637 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 638 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 639 }; 640 641 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 642 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 643 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 644 }; 645 646 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 647 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 648 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false }, 649 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 650 }; 651 652 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 653 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 654 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 655 }; 656 657 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 658 { 659 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 660 u32 subclient = 661 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 662 663 if (client == INSTR_MI_CLIENT) 664 return 0x3F; 665 else if (client == INSTR_RC_CLIENT) { 666 if (subclient == INSTR_MEDIA_SUBCLIENT) 667 return 0xFFFF; 668 else 669 return 0xFF; 670 } 671 672 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 673 return 0; 674 } 675 676 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 677 { 678 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 679 u32 subclient = 680 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 681 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 682 683 if (client == INSTR_MI_CLIENT) 684 return 0x3F; 685 else if (client == INSTR_RC_CLIENT) { 686 if (subclient == INSTR_MEDIA_SUBCLIENT) { 687 if (op == 6) 688 return 0xFFFF; 689 else 690 return 0xFFF; 691 } else 692 return 0xFF; 693 } 694 695 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 696 return 0; 697 } 698 699 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 700 { 701 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 702 703 if (client == INSTR_MI_CLIENT) 704 return 0x3F; 705 else if (client == INSTR_BC_CLIENT) 706 return 0xFF; 707 708 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 709 return 0; 710 } 711 712 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 713 const struct drm_i915_cmd_table *cmd_tables, 714 int cmd_table_count) 715 { 716 int i; 717 bool ret = true; 718 719 if (!cmd_tables || cmd_table_count == 0) 720 return true; 721 722 for (i = 0; i < cmd_table_count; i++) { 723 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 724 u32 previous = 0; 725 int j; 726 727 for (j = 0; j < table->count; j++) { 728 const struct drm_i915_cmd_descriptor *desc = 729 &table->table[j]; 730 u32 curr = desc->cmd.value & desc->cmd.mask; 731 732 if (curr < previous) { 733 DRM_ERROR("CMD: %s [%d] command table not sorted: " 734 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 735 engine->name, engine->id, 736 i, j, curr, previous); 737 ret = false; 738 } 739 740 previous = curr; 741 } 742 } 743 744 return ret; 745 } 746 747 static bool check_sorted(const struct intel_engine_cs *engine, 748 const struct drm_i915_reg_descriptor *reg_table, 749 int reg_count) 750 { 751 int i; 752 u32 previous = 0; 753 bool ret = true; 754 755 for (i = 0; i < reg_count; i++) { 756 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 757 758 if (curr < previous) { 759 DRM_ERROR("CMD: %s [%d] register table not sorted: " 760 "entry=%d reg=0x%08X prev=0x%08X\n", 761 engine->name, engine->id, 762 i, curr, previous); 763 ret = false; 764 } 765 766 previous = curr; 767 } 768 769 return ret; 770 } 771 772 static bool validate_regs_sorted(struct intel_engine_cs *engine) 773 { 774 int i; 775 const struct drm_i915_reg_table *table; 776 777 for (i = 0; i < engine->reg_table_count; i++) { 778 table = &engine->reg_tables[i]; 779 if (!check_sorted(engine, table->regs, table->num_regs)) 780 return false; 781 } 782 783 return true; 784 } 785 786 struct cmd_node { 787 const struct drm_i915_cmd_descriptor *desc; 788 struct hlist_node node; 789 }; 790 791 /* 792 * Different command ranges have different numbers of bits for the opcode. For 793 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 794 * problem is that, for example, MI commands use bits 22:16 for other fields 795 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 796 * we mask a command from a batch it could hash to the wrong bucket due to 797 * non-opcode bits being set. But if we don't include those bits, some 3D 798 * commands may hash to the same bucket due to not including opcode bits that 799 * make the command unique. For now, we will risk hashing to the same bucket. 800 */ 801 static inline u32 cmd_header_key(u32 x) 802 { 803 switch (x >> INSTR_CLIENT_SHIFT) { 804 default: 805 case INSTR_MI_CLIENT: 806 return x >> STD_MI_OPCODE_SHIFT; 807 case INSTR_RC_CLIENT: 808 return x >> STD_3D_OPCODE_SHIFT; 809 case INSTR_BC_CLIENT: 810 return x >> STD_2D_OPCODE_SHIFT; 811 } 812 } 813 814 static int init_hash_table(struct intel_engine_cs *engine, 815 const struct drm_i915_cmd_table *cmd_tables, 816 int cmd_table_count) 817 { 818 int i, j; 819 820 hash_init(engine->cmd_hash); 821 822 for (i = 0; i < cmd_table_count; i++) { 823 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 824 825 for (j = 0; j < table->count; j++) { 826 const struct drm_i915_cmd_descriptor *desc = 827 &table->table[j]; 828 struct cmd_node *desc_node = 829 kmalloc(sizeof(*desc_node), GFP_KERNEL); 830 831 if (!desc_node) 832 return -ENOMEM; 833 834 desc_node->desc = desc; 835 hash_add(engine->cmd_hash, &desc_node->node, 836 cmd_header_key(desc->cmd.value)); 837 } 838 } 839 840 return 0; 841 } 842 843 static void fini_hash_table(struct intel_engine_cs *engine) 844 { 845 struct hlist_node *tmp; 846 struct cmd_node *desc_node; 847 int i; 848 849 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 850 hash_del(&desc_node->node); 851 kfree(desc_node); 852 } 853 } 854 855 /** 856 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 857 * @engine: the engine to initialize 858 * 859 * Optionally initializes fields related to batch buffer command parsing in the 860 * struct intel_engine_cs based on whether the platform requires software 861 * command parsing. 862 */ 863 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 864 { 865 const struct drm_i915_cmd_table *cmd_tables; 866 int cmd_table_count; 867 int ret; 868 869 if (!IS_GEN(engine->i915, 7)) 870 return; 871 872 switch (engine->class) { 873 case RENDER_CLASS: 874 if (IS_HASWELL(engine->i915)) { 875 cmd_tables = hsw_render_ring_cmds; 876 cmd_table_count = 877 ARRAY_SIZE(hsw_render_ring_cmds); 878 } else { 879 cmd_tables = gen7_render_cmds; 880 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 881 } 882 883 if (IS_HASWELL(engine->i915)) { 884 engine->reg_tables = hsw_render_reg_tables; 885 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 886 } else { 887 engine->reg_tables = ivb_render_reg_tables; 888 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 889 } 890 891 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 892 break; 893 case VIDEO_DECODE_CLASS: 894 cmd_tables = gen7_video_cmds; 895 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 896 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 897 break; 898 case COPY_ENGINE_CLASS: 899 if (IS_HASWELL(engine->i915)) { 900 cmd_tables = hsw_blt_ring_cmds; 901 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 902 } else { 903 cmd_tables = gen7_blt_cmds; 904 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 905 } 906 907 if (IS_HASWELL(engine->i915)) { 908 engine->reg_tables = hsw_blt_reg_tables; 909 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 910 } else { 911 engine->reg_tables = ivb_blt_reg_tables; 912 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 913 } 914 915 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 916 break; 917 case VIDEO_ENHANCEMENT_CLASS: 918 cmd_tables = hsw_vebox_cmds; 919 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 920 /* VECS can use the same length_mask function as VCS */ 921 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 922 break; 923 default: 924 MISSING_CASE(engine->class); 925 return; 926 } 927 928 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 929 DRM_ERROR("%s: command descriptions are not sorted\n", 930 engine->name); 931 return; 932 } 933 if (!validate_regs_sorted(engine)) { 934 DRM_ERROR("%s: registers are not sorted\n", engine->name); 935 return; 936 } 937 938 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 939 if (ret) { 940 DRM_ERROR("%s: initialised failed!\n", engine->name); 941 fini_hash_table(engine); 942 return; 943 } 944 945 engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER; 946 } 947 948 /** 949 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 950 * @engine: the engine to clean up 951 * 952 * Releases any resources related to command parsing that may have been 953 * initialized for the specified engine. 954 */ 955 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 956 { 957 if (!intel_engine_needs_cmd_parser(engine)) 958 return; 959 960 fini_hash_table(engine); 961 } 962 963 static const struct drm_i915_cmd_descriptor* 964 find_cmd_in_table(struct intel_engine_cs *engine, 965 u32 cmd_header) 966 { 967 struct cmd_node *desc_node; 968 969 hash_for_each_possible(engine->cmd_hash, desc_node, node, 970 cmd_header_key(cmd_header)) { 971 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 972 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 973 return desc; 974 } 975 976 return NULL; 977 } 978 979 /* 980 * Returns a pointer to a descriptor for the command specified by cmd_header. 981 * 982 * The caller must supply space for a default descriptor via the default_desc 983 * parameter. If no descriptor for the specified command exists in the engine's 984 * command parser tables, this function fills in default_desc based on the 985 * engine's default length encoding and returns default_desc. 986 */ 987 static const struct drm_i915_cmd_descriptor* 988 find_cmd(struct intel_engine_cs *engine, 989 u32 cmd_header, 990 const struct drm_i915_cmd_descriptor *desc, 991 struct drm_i915_cmd_descriptor *default_desc) 992 { 993 u32 mask; 994 995 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 996 return desc; 997 998 desc = find_cmd_in_table(engine, cmd_header); 999 if (desc) 1000 return desc; 1001 1002 mask = engine->get_cmd_length_mask(cmd_header); 1003 if (!mask) 1004 return NULL; 1005 1006 default_desc->cmd.value = cmd_header; 1007 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 1008 default_desc->length.mask = mask; 1009 default_desc->flags = CMD_DESC_SKIP; 1010 return default_desc; 1011 } 1012 1013 static const struct drm_i915_reg_descriptor * 1014 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 1015 { 1016 int start = 0, end = count; 1017 while (start < end) { 1018 int mid = start + (end - start) / 2; 1019 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 1020 if (ret < 0) 1021 end = mid; 1022 else if (ret > 0) 1023 start = mid + 1; 1024 else 1025 return &table[mid]; 1026 } 1027 return NULL; 1028 } 1029 1030 static const struct drm_i915_reg_descriptor * 1031 find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr) 1032 { 1033 const struct drm_i915_reg_table *table = engine->reg_tables; 1034 int count = engine->reg_table_count; 1035 1036 for (; count > 0; ++table, --count) { 1037 if (!table->master || is_master) { 1038 const struct drm_i915_reg_descriptor *reg; 1039 1040 reg = __find_reg(table->regs, table->num_regs, addr); 1041 if (reg != NULL) 1042 return reg; 1043 } 1044 } 1045 1046 return NULL; 1047 } 1048 1049 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 1050 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 1051 struct drm_i915_gem_object *src_obj, 1052 u32 batch_start_offset, 1053 u32 batch_len, 1054 bool *needs_clflush_after) 1055 { 1056 unsigned int src_needs_clflush; 1057 unsigned int dst_needs_clflush; 1058 void *dst, *src; 1059 int ret; 1060 1061 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush); 1062 if (ret) 1063 return ERR_PTR(ret); 1064 1065 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB); 1066 i915_gem_object_finish_access(dst_obj); 1067 if (IS_ERR(dst)) 1068 return dst; 1069 1070 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush); 1071 if (ret) { 1072 i915_gem_object_unpin_map(dst_obj); 1073 return ERR_PTR(ret); 1074 } 1075 1076 src = ERR_PTR(-ENODEV); 1077 if (src_needs_clflush && 1078 i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) { 1079 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 1080 if (!IS_ERR(src)) { 1081 i915_memcpy_from_wc(dst, 1082 src + batch_start_offset, 1083 ALIGN(batch_len, 16)); 1084 i915_gem_object_unpin_map(src_obj); 1085 } 1086 } 1087 if (IS_ERR(src)) { 1088 void *ptr; 1089 int offset, n; 1090 1091 offset = offset_in_page(batch_start_offset); 1092 1093 /* We can avoid clflushing partial cachelines before the write 1094 * if we only every write full cache-lines. Since we know that 1095 * both the source and destination are in multiples of 1096 * PAGE_SIZE, we can simply round up to the next cacheline. 1097 * We don't care about copying too much here as we only 1098 * validate up to the end of the batch. 1099 */ 1100 if (dst_needs_clflush & CLFLUSH_BEFORE) 1101 batch_len = roundup(batch_len, 1102 boot_cpu_data.x86_clflush_size); 1103 1104 ptr = dst; 1105 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) { 1106 int len = min_t(int, batch_len, PAGE_SIZE - offset); 1107 1108 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1109 if (src_needs_clflush) 1110 drm_clflush_virt_range(src + offset, len); 1111 memcpy(ptr, src + offset, len); 1112 kunmap_atomic(src); 1113 1114 ptr += len; 1115 batch_len -= len; 1116 offset = 0; 1117 } 1118 } 1119 1120 i915_gem_object_finish_access(src_obj); 1121 1122 /* dst_obj is returned with vmap pinned */ 1123 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; 1124 1125 return dst; 1126 } 1127 1128 static bool check_cmd(const struct intel_engine_cs *engine, 1129 const struct drm_i915_cmd_descriptor *desc, 1130 const u32 *cmd, u32 length, 1131 const bool is_master) 1132 { 1133 if (desc->flags & CMD_DESC_SKIP) 1134 return true; 1135 1136 if (desc->flags & CMD_DESC_REJECT) { 1137 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1138 return false; 1139 } 1140 1141 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 1142 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 1143 *cmd); 1144 return false; 1145 } 1146 1147 if (desc->flags & CMD_DESC_REGISTER) { 1148 /* 1149 * Get the distance between individual register offset 1150 * fields if the command can perform more than one 1151 * access at a time. 1152 */ 1153 const u32 step = desc->reg.step ? desc->reg.step : length; 1154 u32 offset; 1155 1156 for (offset = desc->reg.offset; offset < length; 1157 offset += step) { 1158 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1159 const struct drm_i915_reg_descriptor *reg = 1160 find_reg(engine, is_master, reg_addr); 1161 1162 if (!reg) { 1163 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", 1164 reg_addr, *cmd, engine->name); 1165 return false; 1166 } 1167 1168 /* 1169 * Check the value written to the register against the 1170 * allowed mask/value pair given in the whitelist entry. 1171 */ 1172 if (reg->mask) { 1173 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1174 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1175 reg_addr); 1176 return false; 1177 } 1178 1179 if (desc->cmd.value == MI_LOAD_REGISTER_REG) { 1180 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n", 1181 reg_addr); 1182 return false; 1183 } 1184 1185 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1186 (offset + 2 > length || 1187 (cmd[offset + 1] & reg->mask) != reg->value)) { 1188 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1189 reg_addr); 1190 return false; 1191 } 1192 } 1193 } 1194 } 1195 1196 if (desc->flags & CMD_DESC_BITMASK) { 1197 int i; 1198 1199 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1200 u32 dword; 1201 1202 if (desc->bits[i].mask == 0) 1203 break; 1204 1205 if (desc->bits[i].condition_mask != 0) { 1206 u32 offset = 1207 desc->bits[i].condition_offset; 1208 u32 condition = cmd[offset] & 1209 desc->bits[i].condition_mask; 1210 1211 if (condition == 0) 1212 continue; 1213 } 1214 1215 if (desc->bits[i].offset >= length) { 1216 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", 1217 *cmd, engine->name); 1218 return false; 1219 } 1220 1221 dword = cmd[desc->bits[i].offset] & 1222 desc->bits[i].mask; 1223 1224 if (dword != desc->bits[i].expected) { 1225 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", 1226 *cmd, 1227 desc->bits[i].mask, 1228 desc->bits[i].expected, 1229 dword, engine->name); 1230 return false; 1231 } 1232 } 1233 } 1234 1235 return true; 1236 } 1237 1238 #define LENGTH_BIAS 2 1239 1240 /** 1241 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1242 * @engine: the engine on which the batch is to execute 1243 * @batch_obj: the batch buffer in question 1244 * @shadow_batch_obj: copy of the batch buffer in question 1245 * @batch_start_offset: byte offset in the batch at which execution starts 1246 * @batch_len: length of the commands in batch_obj 1247 * @is_master: is the submitting process the drm master? 1248 * 1249 * Parses the specified batch buffer looking for privilege violations as 1250 * described in the overview. 1251 * 1252 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1253 * if the batch appears legal but should use hardware parsing 1254 */ 1255 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1256 struct drm_i915_gem_object *batch_obj, 1257 struct drm_i915_gem_object *shadow_batch_obj, 1258 u32 batch_start_offset, 1259 u32 batch_len, 1260 bool is_master) 1261 { 1262 u32 *cmd, *batch_end; 1263 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1264 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1265 bool needs_clflush_after = false; 1266 int ret = 0; 1267 1268 cmd = copy_batch(shadow_batch_obj, batch_obj, 1269 batch_start_offset, batch_len, 1270 &needs_clflush_after); 1271 if (IS_ERR(cmd)) { 1272 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1273 return PTR_ERR(cmd); 1274 } 1275 1276 /* 1277 * We use the batch length as size because the shadow object is as 1278 * large or larger and copy_batch() will write MI_NOPs to the extra 1279 * space. Parsing should be faster in some cases this way. 1280 */ 1281 batch_end = cmd + (batch_len / sizeof(*batch_end)); 1282 do { 1283 u32 length; 1284 1285 if (*cmd == MI_BATCH_BUFFER_END) { 1286 if (needs_clflush_after) { 1287 void *ptr = page_mask_bits(shadow_batch_obj->mm.mapping); 1288 drm_clflush_virt_range(ptr, 1289 (void *)(cmd + 1) - ptr); 1290 } 1291 break; 1292 } 1293 1294 desc = find_cmd(engine, *cmd, desc, &default_desc); 1295 if (!desc) { 1296 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1297 *cmd); 1298 ret = -EINVAL; 1299 break; 1300 } 1301 1302 /* 1303 * If the batch buffer contains a chained batch, return an 1304 * error that tells the caller to abort and dispatch the 1305 * workload as a non-secure batch. 1306 */ 1307 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1308 ret = -EACCES; 1309 break; 1310 } 1311 1312 if (desc->flags & CMD_DESC_FIXED) 1313 length = desc->length.fixed; 1314 else 1315 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1316 1317 if ((batch_end - cmd) < length) { 1318 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1319 *cmd, 1320 length, 1321 batch_end - cmd); 1322 ret = -EINVAL; 1323 break; 1324 } 1325 1326 if (!check_cmd(engine, desc, cmd, length, is_master)) { 1327 ret = -EACCES; 1328 break; 1329 } 1330 1331 cmd += length; 1332 if (cmd >= batch_end) { 1333 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1334 ret = -EINVAL; 1335 break; 1336 } 1337 } while (1); 1338 1339 i915_gem_object_unpin_map(shadow_batch_obj); 1340 return ret; 1341 } 1342 1343 /** 1344 * i915_cmd_parser_get_version() - get the cmd parser version number 1345 * @dev_priv: i915 device private 1346 * 1347 * The cmd parser maintains a simple increasing integer version number suitable 1348 * for passing to userspace clients to determine what operations are permitted. 1349 * 1350 * Return: the current version number of the cmd parser 1351 */ 1352 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1353 { 1354 struct intel_engine_cs *engine; 1355 enum intel_engine_id id; 1356 bool active = false; 1357 1358 /* If the command parser is not enabled, report 0 - unsupported */ 1359 for_each_engine(engine, dev_priv, id) { 1360 if (intel_engine_needs_cmd_parser(engine)) { 1361 active = true; 1362 break; 1363 } 1364 } 1365 if (!active) 1366 return 0; 1367 1368 /* 1369 * Command parser version history 1370 * 1371 * 1. Initial version. Checks batches and reports violations, but leaves 1372 * hardware parsing enabled (so does not allow new use cases). 1373 * 2. Allow access to the MI_PREDICATE_SRC0 and 1374 * MI_PREDICATE_SRC1 registers. 1375 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1376 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1377 * 5. GPGPU dispatch compute indirect registers. 1378 * 6. TIMESTAMP register and Haswell CS GPR registers 1379 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1380 * 8. Don't report cmd_check() failures as EINVAL errors to userspace; 1381 * rely on the HW to NOOP disallowed commands as it would without 1382 * the parser enabled. 1383 * 9. Don't whitelist or handle oacontrol specially, as ownership 1384 * for oacontrol state is moving to i915-perf. 1385 */ 1386 return 9; 1387 } 1388