1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include "gt/intel_engine.h" 29 #include "gt/intel_engine_regs.h" 30 #include "gt/intel_gpu_commands.h" 31 #include "gt/intel_gt_regs.h" 32 33 #include "i915_cmd_parser.h" 34 #include "i915_drv.h" 35 #include "i915_memcpy.h" 36 #include "i915_reg.h" 37 38 /** 39 * DOC: batch buffer command parser 40 * 41 * Motivation: 42 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 43 * require userspace code to submit batches containing commands such as 44 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 45 * generations of the hardware will noop these commands in "unsecure" batches 46 * (which includes all userspace batches submitted via i915) even though the 47 * commands may be safe and represent the intended programming model of the 48 * device. 49 * 50 * The software command parser is similar in operation to the command parsing 51 * done in hardware for unsecure batches. However, the software parser allows 52 * some operations that would be noop'd by hardware, if the parser determines 53 * the operation is safe, and submits the batch as "secure" to prevent hardware 54 * parsing. 55 * 56 * Threats: 57 * At a high level, the hardware (and software) checks attempt to prevent 58 * granting userspace undue privileges. There are three categories of privilege. 59 * 60 * First, commands which are explicitly defined as privileged or which should 61 * only be used by the kernel driver. The parser rejects such commands 62 * 63 * Second, commands which access registers. To support correct/enhanced 64 * userspace functionality, particularly certain OpenGL extensions, the parser 65 * provides a whitelist of registers which userspace may safely access 66 * 67 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 68 * The parser always rejects such commands. 69 * 70 * The majority of the problematic commands fall in the MI_* range, with only a 71 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 72 * 73 * Implementation: 74 * Each engine maintains tables of commands and registers which the parser 75 * uses in scanning batch buffers submitted to that engine. 76 * 77 * Since the set of commands that the parser must check for is significantly 78 * smaller than the number of commands supported, the parser tables contain only 79 * those commands required by the parser. This generally works because command 80 * opcode ranges have standard command length encodings. So for commands that 81 * the parser does not need to check, it can easily skip them. This is 82 * implemented via a per-engine length decoding vfunc. 83 * 84 * Unfortunately, there are a number of commands that do not follow the standard 85 * length encoding for their opcode range, primarily amongst the MI_* commands. 86 * To handle this, the parser provides a way to define explicit "skip" entries 87 * in the per-engine command tables. 88 * 89 * Other command table entries map fairly directly to high level categories 90 * mentioned above: rejected, register whitelist. The parser implements a number 91 * of checks, including the privileged memory checks, via a general bitmasking 92 * mechanism. 93 */ 94 95 /* 96 * A command that requires special handling by the command parser. 97 */ 98 struct drm_i915_cmd_descriptor { 99 /* 100 * Flags describing how the command parser processes the command. 101 * 102 * CMD_DESC_FIXED: The command has a fixed length if this is set, 103 * a length mask if not set 104 * CMD_DESC_SKIP: The command is allowed but does not follow the 105 * standard length encoding for the opcode range in 106 * which it falls 107 * CMD_DESC_REJECT: The command is never allowed 108 * CMD_DESC_REGISTER: The command should be checked against the 109 * register whitelist for the appropriate ring 110 */ 111 u32 flags; 112 #define CMD_DESC_FIXED (1<<0) 113 #define CMD_DESC_SKIP (1<<1) 114 #define CMD_DESC_REJECT (1<<2) 115 #define CMD_DESC_REGISTER (1<<3) 116 #define CMD_DESC_BITMASK (1<<4) 117 118 /* 119 * The command's unique identification bits and the bitmask to get them. 120 * This isn't strictly the opcode field as defined in the spec and may 121 * also include type, subtype, and/or subop fields. 122 */ 123 struct { 124 u32 value; 125 u32 mask; 126 } cmd; 127 128 /* 129 * The command's length. The command is either fixed length (i.e. does 130 * not include a length field) or has a length field mask. The flag 131 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 132 * a length mask. All command entries in a command table must include 133 * length information. 134 */ 135 union { 136 u32 fixed; 137 u32 mask; 138 } length; 139 140 /* 141 * Describes where to find a register address in the command to check 142 * against the ring's register whitelist. Only valid if flags has the 143 * CMD_DESC_REGISTER bit set. 144 * 145 * A non-zero step value implies that the command may access multiple 146 * registers in sequence (e.g. LRI), in that case step gives the 147 * distance in dwords between individual offset fields. 148 */ 149 struct { 150 u32 offset; 151 u32 mask; 152 u32 step; 153 } reg; 154 155 #define MAX_CMD_DESC_BITMASKS 3 156 /* 157 * Describes command checks where a particular dword is masked and 158 * compared against an expected value. If the command does not match 159 * the expected value, the parser rejects it. Only valid if flags has 160 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 161 * are valid. 162 * 163 * If the check specifies a non-zero condition_mask then the parser 164 * only performs the check when the bits specified by condition_mask 165 * are non-zero. 166 */ 167 struct { 168 u32 offset; 169 u32 mask; 170 u32 expected; 171 u32 condition_offset; 172 u32 condition_mask; 173 } bits[MAX_CMD_DESC_BITMASKS]; 174 }; 175 176 /* 177 * A table of commands requiring special handling by the command parser. 178 * 179 * Each engine has an array of tables. Each table consists of an array of 180 * command descriptors, which must be sorted with command opcodes in 181 * ascending order. 182 */ 183 struct drm_i915_cmd_table { 184 const struct drm_i915_cmd_descriptor *table; 185 int count; 186 }; 187 188 #define STD_MI_OPCODE_SHIFT (32 - 9) 189 #define STD_3D_OPCODE_SHIFT (32 - 16) 190 #define STD_2D_OPCODE_SHIFT (32 - 10) 191 #define STD_MFX_OPCODE_SHIFT (32 - 16) 192 #define MIN_OPCODE_SHIFT 16 193 194 #define CMD(op, opm, f, lm, fl, ...) \ 195 { \ 196 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 197 .cmd = { (op & ~0u << (opm)), ~0u << (opm) }, \ 198 .length = { (lm) }, \ 199 __VA_ARGS__ \ 200 } 201 202 /* Convenience macros to compress the tables */ 203 #define SMI STD_MI_OPCODE_SHIFT 204 #define S3D STD_3D_OPCODE_SHIFT 205 #define S2D STD_2D_OPCODE_SHIFT 206 #define SMFX STD_MFX_OPCODE_SHIFT 207 #define F true 208 #define S CMD_DESC_SKIP 209 #define R CMD_DESC_REJECT 210 #define W CMD_DESC_REGISTER 211 #define B CMD_DESC_BITMASK 212 213 /* Command Mask Fixed Len Action 214 ---------------------------------------------------------- */ 215 static const struct drm_i915_cmd_descriptor gen7_common_cmds[] = { 216 CMD( MI_NOOP, SMI, F, 1, S ), 217 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 218 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, R ), 219 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 220 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 221 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 222 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 223 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 224 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 225 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 226 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 227 .reg = { .offset = 1, .mask = 0x007FFFFC }, 228 .bits = {{ 229 .offset = 0, 230 .mask = MI_GLOBAL_GTT, 231 .expected = 0, 232 }}, ), 233 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 234 .reg = { .offset = 1, .mask = 0x007FFFFC }, 235 .bits = {{ 236 .offset = 0, 237 .mask = MI_GLOBAL_GTT, 238 .expected = 0, 239 }}, ), 240 /* 241 * MI_BATCH_BUFFER_START requires some special handling. It's not 242 * really a 'skip' action but it doesn't seem like it's worth adding 243 * a new action. See intel_engine_cmd_parser(). 244 */ 245 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 246 }; 247 248 static const struct drm_i915_cmd_descriptor gen7_render_cmds[] = { 249 CMD( MI_FLUSH, SMI, F, 1, S ), 250 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 251 CMD( MI_PREDICATE, SMI, F, 1, S ), 252 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 253 CMD( MI_SET_APPID, SMI, F, 1, S ), 254 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 255 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 256 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 257 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 258 .bits = {{ 259 .offset = 0, 260 .mask = MI_GLOBAL_GTT, 261 .expected = 0, 262 }}, ), 263 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 264 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 265 .bits = {{ 266 .offset = 0, 267 .mask = MI_GLOBAL_GTT, 268 .expected = 0, 269 }}, ), 270 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 271 .bits = {{ 272 .offset = 1, 273 .mask = MI_REPORT_PERF_COUNT_GGTT, 274 .expected = 0, 275 }}, ), 276 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 277 .bits = {{ 278 .offset = 0, 279 .mask = MI_GLOBAL_GTT, 280 .expected = 0, 281 }}, ), 282 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 283 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 284 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 285 .bits = {{ 286 .offset = 2, 287 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 288 .expected = 0, 289 }}, ), 290 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 291 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 292 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 293 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 294 .bits = {{ 295 .offset = 1, 296 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 297 .expected = 0, 298 }, 299 { 300 .offset = 1, 301 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 302 PIPE_CONTROL_STORE_DATA_INDEX), 303 .expected = 0, 304 .condition_offset = 1, 305 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 306 }}, ), 307 }; 308 309 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 310 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 311 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 312 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 313 CMD( MI_SET_APPID, SMI, F, 1, S ), 314 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 315 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 316 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 317 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 318 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 319 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 320 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 321 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 322 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 323 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 324 325 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 326 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 327 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 328 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 329 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 330 }; 331 332 static const struct drm_i915_cmd_descriptor gen7_video_cmds[] = { 333 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 334 CMD( MI_SET_APPID, SMI, F, 1, S ), 335 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 336 .bits = {{ 337 .offset = 0, 338 .mask = MI_GLOBAL_GTT, 339 .expected = 0, 340 }}, ), 341 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 342 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 343 .bits = {{ 344 .offset = 0, 345 .mask = MI_FLUSH_DW_NOTIFY, 346 .expected = 0, 347 }, 348 { 349 .offset = 1, 350 .mask = MI_FLUSH_DW_USE_GTT, 351 .expected = 0, 352 .condition_offset = 0, 353 .condition_mask = MI_FLUSH_DW_OP_MASK, 354 }, 355 { 356 .offset = 0, 357 .mask = MI_FLUSH_DW_STORE_INDEX, 358 .expected = 0, 359 .condition_offset = 0, 360 .condition_mask = MI_FLUSH_DW_OP_MASK, 361 }}, ), 362 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 363 .bits = {{ 364 .offset = 0, 365 .mask = MI_GLOBAL_GTT, 366 .expected = 0, 367 }}, ), 368 /* 369 * MFX_WAIT doesn't fit the way we handle length for most commands. 370 * It has a length field but it uses a non-standard length bias. 371 * It is always 1 dword though, so just treat it as fixed length. 372 */ 373 CMD( MFX_WAIT, SMFX, F, 1, S ), 374 }; 375 376 static const struct drm_i915_cmd_descriptor gen7_vecs_cmds[] = { 377 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 378 CMD( MI_SET_APPID, SMI, F, 1, S ), 379 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 380 .bits = {{ 381 .offset = 0, 382 .mask = MI_GLOBAL_GTT, 383 .expected = 0, 384 }}, ), 385 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 386 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 387 .bits = {{ 388 .offset = 0, 389 .mask = MI_FLUSH_DW_NOTIFY, 390 .expected = 0, 391 }, 392 { 393 .offset = 1, 394 .mask = MI_FLUSH_DW_USE_GTT, 395 .expected = 0, 396 .condition_offset = 0, 397 .condition_mask = MI_FLUSH_DW_OP_MASK, 398 }, 399 { 400 .offset = 0, 401 .mask = MI_FLUSH_DW_STORE_INDEX, 402 .expected = 0, 403 .condition_offset = 0, 404 .condition_mask = MI_FLUSH_DW_OP_MASK, 405 }}, ), 406 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 407 .bits = {{ 408 .offset = 0, 409 .mask = MI_GLOBAL_GTT, 410 .expected = 0, 411 }}, ), 412 }; 413 414 static const struct drm_i915_cmd_descriptor gen7_blt_cmds[] = { 415 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 416 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 417 .bits = {{ 418 .offset = 0, 419 .mask = MI_GLOBAL_GTT, 420 .expected = 0, 421 }}, ), 422 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 423 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 424 .bits = {{ 425 .offset = 0, 426 .mask = MI_FLUSH_DW_NOTIFY, 427 .expected = 0, 428 }, 429 { 430 .offset = 1, 431 .mask = MI_FLUSH_DW_USE_GTT, 432 .expected = 0, 433 .condition_offset = 0, 434 .condition_mask = MI_FLUSH_DW_OP_MASK, 435 }, 436 { 437 .offset = 0, 438 .mask = MI_FLUSH_DW_STORE_INDEX, 439 .expected = 0, 440 .condition_offset = 0, 441 .condition_mask = MI_FLUSH_DW_OP_MASK, 442 }}, ), 443 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 444 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 445 }; 446 447 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 448 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, R ), 449 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 450 }; 451 452 /* 453 * For Gen9 we can still rely on the h/w to enforce cmd security, and only 454 * need to re-enforce the register access checks. We therefore only need to 455 * teach the cmdparser how to find the end of each command, and identify 456 * register accesses. The table doesn't need to reject any commands, and so 457 * the only commands listed here are: 458 * 1) Those that touch registers 459 * 2) Those that do not have the default 8-bit length 460 * 461 * Note that the default MI length mask chosen for this table is 0xFF, not 462 * the 0x3F used on older devices. This is because the vast majority of MI 463 * cmds on Gen9 use a standard 8-bit Length field. 464 * All the Gen9 blitter instructions are standard 0xFF length mask, and 465 * none allow access to non-general registers, so in fact no BLT cmds are 466 * included in the table at all. 467 * 468 */ 469 static const struct drm_i915_cmd_descriptor gen9_blt_cmds[] = { 470 CMD( MI_NOOP, SMI, F, 1, S ), 471 CMD( MI_USER_INTERRUPT, SMI, F, 1, S ), 472 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, S ), 473 CMD( MI_FLUSH, SMI, F, 1, S ), 474 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 475 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 476 CMD( MI_ARB_ON_OFF, SMI, F, 1, S ), 477 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 478 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, S ), 479 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, S ), 480 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, S ), 481 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 482 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 483 CMD( MI_UPDATE_GTT, SMI, !F, 0x3FF, S ), 484 CMD( MI_STORE_REGISTER_MEM_GEN8, SMI, F, 4, W, 485 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 486 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, S ), 487 CMD( MI_LOAD_REGISTER_MEM_GEN8, SMI, F, 4, W, 488 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 489 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 490 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 491 492 /* 493 * We allow BB_START but apply further checks. We just sanitize the 494 * basic fields here. 495 */ 496 #define MI_BB_START_OPERAND_MASK GENMASK(SMI-1, 0) 497 #define MI_BB_START_OPERAND_EXPECT (MI_BATCH_PPGTT_HSW | 1) 498 CMD( MI_BATCH_BUFFER_START_GEN8, SMI, !F, 0xFF, B, 499 .bits = {{ 500 .offset = 0, 501 .mask = MI_BB_START_OPERAND_MASK, 502 .expected = MI_BB_START_OPERAND_EXPECT, 503 }}, ), 504 }; 505 506 static const struct drm_i915_cmd_descriptor noop_desc = 507 CMD(MI_NOOP, SMI, F, 1, S); 508 509 #undef CMD 510 #undef SMI 511 #undef S3D 512 #undef S2D 513 #undef SMFX 514 #undef F 515 #undef S 516 #undef R 517 #undef W 518 #undef B 519 520 static const struct drm_i915_cmd_table gen7_render_cmd_table[] = { 521 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 522 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 523 }; 524 525 static const struct drm_i915_cmd_table hsw_render_ring_cmd_table[] = { 526 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 527 { gen7_render_cmds, ARRAY_SIZE(gen7_render_cmds) }, 528 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 529 }; 530 531 static const struct drm_i915_cmd_table gen7_video_cmd_table[] = { 532 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 533 { gen7_video_cmds, ARRAY_SIZE(gen7_video_cmds) }, 534 }; 535 536 static const struct drm_i915_cmd_table hsw_vebox_cmd_table[] = { 537 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 538 { gen7_vecs_cmds, ARRAY_SIZE(gen7_vecs_cmds) }, 539 }; 540 541 static const struct drm_i915_cmd_table gen7_blt_cmd_table[] = { 542 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 543 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 544 }; 545 546 static const struct drm_i915_cmd_table hsw_blt_ring_cmd_table[] = { 547 { gen7_common_cmds, ARRAY_SIZE(gen7_common_cmds) }, 548 { gen7_blt_cmds, ARRAY_SIZE(gen7_blt_cmds) }, 549 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 550 }; 551 552 static const struct drm_i915_cmd_table gen9_blt_cmd_table[] = { 553 { gen9_blt_cmds, ARRAY_SIZE(gen9_blt_cmds) }, 554 }; 555 556 557 /* 558 * Register whitelists, sorted by increasing register offset. 559 */ 560 561 /* 562 * An individual whitelist entry granting access to register addr. If 563 * mask is non-zero the argument of immediate register writes will be 564 * AND-ed with mask, and the command will be rejected if the result 565 * doesn't match value. 566 * 567 * Registers with non-zero mask are only allowed to be written using 568 * LRI. 569 */ 570 struct drm_i915_reg_descriptor { 571 i915_reg_t addr; 572 u32 mask; 573 u32 value; 574 }; 575 576 /* Convenience macro for adding 32-bit registers. */ 577 #define REG32(_reg, ...) \ 578 { .addr = (_reg), __VA_ARGS__ } 579 580 #define REG32_IDX(_reg, idx) \ 581 { .addr = _reg(idx) } 582 583 /* 584 * Convenience macro for adding 64-bit registers. 585 * 586 * Some registers that userspace accesses are 64 bits. The register 587 * access commands only allow 32-bit accesses. Hence, we have to include 588 * entries for both halves of the 64-bit registers. 589 */ 590 #define REG64(_reg) \ 591 { .addr = _reg }, \ 592 { .addr = _reg ## _UDW } 593 594 #define REG64_IDX(_reg, idx) \ 595 { .addr = _reg(idx) }, \ 596 { .addr = _reg ## _UDW(idx) } 597 598 #define REG64_BASE_IDX(_reg, base, idx) \ 599 { .addr = _reg(base, idx) }, \ 600 { .addr = _reg ## _UDW(base, idx) } 601 602 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 603 REG64(GPGPU_THREADS_DISPATCHED), 604 REG64(HS_INVOCATION_COUNT), 605 REG64(DS_INVOCATION_COUNT), 606 REG64(IA_VERTICES_COUNT), 607 REG64(IA_PRIMITIVES_COUNT), 608 REG64(VS_INVOCATION_COUNT), 609 REG64(GS_INVOCATION_COUNT), 610 REG64(GS_PRIMITIVES_COUNT), 611 REG64(CL_INVOCATION_COUNT), 612 REG64(CL_PRIMITIVES_COUNT), 613 REG64(PS_INVOCATION_COUNT), 614 REG64(PS_DEPTH_COUNT), 615 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 616 REG64_IDX(MI_PREDICATE_SRC0, RENDER_RING_BASE), 617 REG64_IDX(MI_PREDICATE_SRC1, RENDER_RING_BASE), 618 REG32(GEN7_3DPRIM_END_OFFSET), 619 REG32(GEN7_3DPRIM_START_VERTEX), 620 REG32(GEN7_3DPRIM_VERTEX_COUNT), 621 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 622 REG32(GEN7_3DPRIM_START_INSTANCE), 623 REG32(GEN7_3DPRIM_BASE_VERTEX), 624 REG32(GEN7_GPGPU_DISPATCHDIMX), 625 REG32(GEN7_GPGPU_DISPATCHDIMY), 626 REG32(GEN7_GPGPU_DISPATCHDIMZ), 627 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 628 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 629 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 630 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 631 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 632 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 633 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 634 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 635 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 636 REG32(GEN7_SO_WRITE_OFFSET(0)), 637 REG32(GEN7_SO_WRITE_OFFSET(1)), 638 REG32(GEN7_SO_WRITE_OFFSET(2)), 639 REG32(GEN7_SO_WRITE_OFFSET(3)), 640 REG32(GEN7_L3SQCREG1), 641 REG32(GEN7_L3CNTLREG2), 642 REG32(GEN7_L3CNTLREG3), 643 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 644 }; 645 646 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 647 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0), 648 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1), 649 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2), 650 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3), 651 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4), 652 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5), 653 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6), 654 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7), 655 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8), 656 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9), 657 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10), 658 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11), 659 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12), 660 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13), 661 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14), 662 REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15), 663 REG32(HSW_SCRATCH1, 664 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 665 .value = 0), 666 REG32(HSW_ROW_CHICKEN3, 667 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 668 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 669 .value = 0), 670 }; 671 672 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 673 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 674 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 675 REG32(BCS_SWCTRL), 676 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 677 }; 678 679 static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { 680 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 681 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 682 REG32(BCS_SWCTRL), 683 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 684 REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE), 685 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0), 686 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1), 687 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2), 688 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3), 689 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4), 690 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5), 691 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6), 692 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7), 693 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8), 694 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9), 695 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10), 696 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11), 697 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12), 698 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13), 699 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14), 700 REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15), 701 }; 702 703 #undef REG64 704 #undef REG32 705 706 struct drm_i915_reg_table { 707 const struct drm_i915_reg_descriptor *regs; 708 int num_regs; 709 }; 710 711 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 712 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 713 }; 714 715 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 716 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 717 }; 718 719 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 720 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs) }, 721 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs) }, 722 }; 723 724 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 725 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs) }, 726 }; 727 728 static const struct drm_i915_reg_table gen9_blt_reg_tables[] = { 729 { gen9_blt_regs, ARRAY_SIZE(gen9_blt_regs) }, 730 }; 731 732 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 733 { 734 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 735 u32 subclient = 736 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 737 738 if (client == INSTR_MI_CLIENT) 739 return 0x3F; 740 else if (client == INSTR_RC_CLIENT) { 741 if (subclient == INSTR_MEDIA_SUBCLIENT) 742 return 0xFFFF; 743 else 744 return 0xFF; 745 } 746 747 DRM_DEBUG("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 748 return 0; 749 } 750 751 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 752 { 753 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 754 u32 subclient = 755 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 756 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 757 758 if (client == INSTR_MI_CLIENT) 759 return 0x3F; 760 else if (client == INSTR_RC_CLIENT) { 761 if (subclient == INSTR_MEDIA_SUBCLIENT) { 762 if (op == 6) 763 return 0xFFFF; 764 else 765 return 0xFFF; 766 } else 767 return 0xFF; 768 } 769 770 DRM_DEBUG("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 771 return 0; 772 } 773 774 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 775 { 776 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 777 778 if (client == INSTR_MI_CLIENT) 779 return 0x3F; 780 else if (client == INSTR_BC_CLIENT) 781 return 0xFF; 782 783 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 784 return 0; 785 } 786 787 static u32 gen9_blt_get_cmd_length_mask(u32 cmd_header) 788 { 789 u32 client = cmd_header >> INSTR_CLIENT_SHIFT; 790 791 if (client == INSTR_MI_CLIENT || client == INSTR_BC_CLIENT) 792 return 0xFF; 793 794 DRM_DEBUG("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 795 return 0; 796 } 797 798 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 799 const struct drm_i915_cmd_table *cmd_tables, 800 int cmd_table_count) 801 { 802 int i; 803 bool ret = true; 804 805 if (!cmd_tables || cmd_table_count == 0) 806 return true; 807 808 for (i = 0; i < cmd_table_count; i++) { 809 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 810 u32 previous = 0; 811 int j; 812 813 for (j = 0; j < table->count; j++) { 814 const struct drm_i915_cmd_descriptor *desc = 815 &table->table[j]; 816 u32 curr = desc->cmd.value & desc->cmd.mask; 817 818 if (curr < previous) { 819 drm_err(&engine->i915->drm, 820 "CMD: %s [%d] command table not sorted: " 821 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 822 engine->name, engine->id, 823 i, j, curr, previous); 824 ret = false; 825 } 826 827 previous = curr; 828 } 829 } 830 831 return ret; 832 } 833 834 static bool check_sorted(const struct intel_engine_cs *engine, 835 const struct drm_i915_reg_descriptor *reg_table, 836 int reg_count) 837 { 838 int i; 839 u32 previous = 0; 840 bool ret = true; 841 842 for (i = 0; i < reg_count; i++) { 843 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 844 845 if (curr < previous) { 846 drm_err(&engine->i915->drm, 847 "CMD: %s [%d] register table not sorted: " 848 "entry=%d reg=0x%08X prev=0x%08X\n", 849 engine->name, engine->id, 850 i, curr, previous); 851 ret = false; 852 } 853 854 previous = curr; 855 } 856 857 return ret; 858 } 859 860 static bool validate_regs_sorted(struct intel_engine_cs *engine) 861 { 862 int i; 863 const struct drm_i915_reg_table *table; 864 865 for (i = 0; i < engine->reg_table_count; i++) { 866 table = &engine->reg_tables[i]; 867 if (!check_sorted(engine, table->regs, table->num_regs)) 868 return false; 869 } 870 871 return true; 872 } 873 874 struct cmd_node { 875 const struct drm_i915_cmd_descriptor *desc; 876 struct hlist_node node; 877 }; 878 879 /* 880 * Different command ranges have different numbers of bits for the opcode. For 881 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 882 * problem is that, for example, MI commands use bits 22:16 for other fields 883 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 884 * we mask a command from a batch it could hash to the wrong bucket due to 885 * non-opcode bits being set. But if we don't include those bits, some 3D 886 * commands may hash to the same bucket due to not including opcode bits that 887 * make the command unique. For now, we will risk hashing to the same bucket. 888 */ 889 static inline u32 cmd_header_key(u32 x) 890 { 891 switch (x >> INSTR_CLIENT_SHIFT) { 892 default: 893 case INSTR_MI_CLIENT: 894 return x >> STD_MI_OPCODE_SHIFT; 895 case INSTR_RC_CLIENT: 896 return x >> STD_3D_OPCODE_SHIFT; 897 case INSTR_BC_CLIENT: 898 return x >> STD_2D_OPCODE_SHIFT; 899 } 900 } 901 902 static int init_hash_table(struct intel_engine_cs *engine, 903 const struct drm_i915_cmd_table *cmd_tables, 904 int cmd_table_count) 905 { 906 int i, j; 907 908 hash_init(engine->cmd_hash); 909 910 for (i = 0; i < cmd_table_count; i++) { 911 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 912 913 for (j = 0; j < table->count; j++) { 914 const struct drm_i915_cmd_descriptor *desc = 915 &table->table[j]; 916 struct cmd_node *desc_node = 917 kmalloc(sizeof(*desc_node), GFP_KERNEL); 918 919 if (!desc_node) 920 return -ENOMEM; 921 922 desc_node->desc = desc; 923 hash_add(engine->cmd_hash, &desc_node->node, 924 cmd_header_key(desc->cmd.value)); 925 } 926 } 927 928 return 0; 929 } 930 931 static void fini_hash_table(struct intel_engine_cs *engine) 932 { 933 struct hlist_node *tmp; 934 struct cmd_node *desc_node; 935 int i; 936 937 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 938 hash_del(&desc_node->node); 939 kfree(desc_node); 940 } 941 } 942 943 /** 944 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 945 * @engine: the engine to initialize 946 * 947 * Optionally initializes fields related to batch buffer command parsing in the 948 * struct intel_engine_cs based on whether the platform requires software 949 * command parsing. 950 */ 951 int intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 952 { 953 const struct drm_i915_cmd_table *cmd_tables; 954 int cmd_table_count; 955 int ret; 956 957 if (GRAPHICS_VER(engine->i915) != 7 && !(GRAPHICS_VER(engine->i915) == 9 && 958 engine->class == COPY_ENGINE_CLASS)) 959 return 0; 960 961 switch (engine->class) { 962 case RENDER_CLASS: 963 if (IS_HASWELL(engine->i915)) { 964 cmd_tables = hsw_render_ring_cmd_table; 965 cmd_table_count = 966 ARRAY_SIZE(hsw_render_ring_cmd_table); 967 } else { 968 cmd_tables = gen7_render_cmd_table; 969 cmd_table_count = ARRAY_SIZE(gen7_render_cmd_table); 970 } 971 972 if (IS_HASWELL(engine->i915)) { 973 engine->reg_tables = hsw_render_reg_tables; 974 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 975 } else { 976 engine->reg_tables = ivb_render_reg_tables; 977 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 978 } 979 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 980 break; 981 case VIDEO_DECODE_CLASS: 982 cmd_tables = gen7_video_cmd_table; 983 cmd_table_count = ARRAY_SIZE(gen7_video_cmd_table); 984 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 985 break; 986 case COPY_ENGINE_CLASS: 987 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 988 if (GRAPHICS_VER(engine->i915) == 9) { 989 cmd_tables = gen9_blt_cmd_table; 990 cmd_table_count = ARRAY_SIZE(gen9_blt_cmd_table); 991 engine->get_cmd_length_mask = 992 gen9_blt_get_cmd_length_mask; 993 994 /* BCS Engine unsafe without parser */ 995 engine->flags |= I915_ENGINE_REQUIRES_CMD_PARSER; 996 } else if (IS_HASWELL(engine->i915)) { 997 cmd_tables = hsw_blt_ring_cmd_table; 998 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmd_table); 999 } else { 1000 cmd_tables = gen7_blt_cmd_table; 1001 cmd_table_count = ARRAY_SIZE(gen7_blt_cmd_table); 1002 } 1003 1004 if (GRAPHICS_VER(engine->i915) == 9) { 1005 engine->reg_tables = gen9_blt_reg_tables; 1006 engine->reg_table_count = 1007 ARRAY_SIZE(gen9_blt_reg_tables); 1008 } else if (IS_HASWELL(engine->i915)) { 1009 engine->reg_tables = hsw_blt_reg_tables; 1010 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 1011 } else { 1012 engine->reg_tables = ivb_blt_reg_tables; 1013 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 1014 } 1015 break; 1016 case VIDEO_ENHANCEMENT_CLASS: 1017 cmd_tables = hsw_vebox_cmd_table; 1018 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmd_table); 1019 /* VECS can use the same length_mask function as VCS */ 1020 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 1021 break; 1022 default: 1023 MISSING_CASE(engine->class); 1024 goto out; 1025 } 1026 1027 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 1028 drm_err(&engine->i915->drm, 1029 "%s: command descriptions are not sorted\n", 1030 engine->name); 1031 goto out; 1032 } 1033 if (!validate_regs_sorted(engine)) { 1034 drm_err(&engine->i915->drm, 1035 "%s: registers are not sorted\n", engine->name); 1036 goto out; 1037 } 1038 1039 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 1040 if (ret) { 1041 drm_err(&engine->i915->drm, 1042 "%s: initialised failed!\n", engine->name); 1043 fini_hash_table(engine); 1044 goto out; 1045 } 1046 1047 engine->flags |= I915_ENGINE_USING_CMD_PARSER; 1048 1049 out: 1050 if (intel_engine_requires_cmd_parser(engine) && 1051 !intel_engine_using_cmd_parser(engine)) 1052 return -EINVAL; 1053 1054 return 0; 1055 } 1056 1057 /** 1058 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 1059 * @engine: the engine to clean up 1060 * 1061 * Releases any resources related to command parsing that may have been 1062 * initialized for the specified engine. 1063 */ 1064 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 1065 { 1066 if (!intel_engine_using_cmd_parser(engine)) 1067 return; 1068 1069 fini_hash_table(engine); 1070 } 1071 1072 static const struct drm_i915_cmd_descriptor* 1073 find_cmd_in_table(struct intel_engine_cs *engine, 1074 u32 cmd_header) 1075 { 1076 struct cmd_node *desc_node; 1077 1078 hash_for_each_possible(engine->cmd_hash, desc_node, node, 1079 cmd_header_key(cmd_header)) { 1080 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 1081 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1082 return desc; 1083 } 1084 1085 return NULL; 1086 } 1087 1088 /* 1089 * Returns a pointer to a descriptor for the command specified by cmd_header. 1090 * 1091 * The caller must supply space for a default descriptor via the default_desc 1092 * parameter. If no descriptor for the specified command exists in the engine's 1093 * command parser tables, this function fills in default_desc based on the 1094 * engine's default length encoding and returns default_desc. 1095 */ 1096 static const struct drm_i915_cmd_descriptor* 1097 find_cmd(struct intel_engine_cs *engine, 1098 u32 cmd_header, 1099 const struct drm_i915_cmd_descriptor *desc, 1100 struct drm_i915_cmd_descriptor *default_desc) 1101 { 1102 u32 mask; 1103 1104 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 1105 return desc; 1106 1107 desc = find_cmd_in_table(engine, cmd_header); 1108 if (desc) 1109 return desc; 1110 1111 mask = engine->get_cmd_length_mask(cmd_header); 1112 if (!mask) 1113 return NULL; 1114 1115 default_desc->cmd.value = cmd_header; 1116 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 1117 default_desc->length.mask = mask; 1118 default_desc->flags = CMD_DESC_SKIP; 1119 return default_desc; 1120 } 1121 1122 static const struct drm_i915_reg_descriptor * 1123 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 1124 { 1125 int start = 0, end = count; 1126 while (start < end) { 1127 int mid = start + (end - start) / 2; 1128 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 1129 if (ret < 0) 1130 end = mid; 1131 else if (ret > 0) 1132 start = mid + 1; 1133 else 1134 return &table[mid]; 1135 } 1136 return NULL; 1137 } 1138 1139 static const struct drm_i915_reg_descriptor * 1140 find_reg(const struct intel_engine_cs *engine, u32 addr) 1141 { 1142 const struct drm_i915_reg_table *table = engine->reg_tables; 1143 const struct drm_i915_reg_descriptor *reg = NULL; 1144 int count = engine->reg_table_count; 1145 1146 for (; !reg && (count > 0); ++table, --count) 1147 reg = __find_reg(table->regs, table->num_regs, addr); 1148 1149 return reg; 1150 } 1151 1152 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 1153 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 1154 struct drm_i915_gem_object *src_obj, 1155 unsigned long offset, unsigned long length, 1156 bool *needs_clflush_after) 1157 { 1158 unsigned int src_needs_clflush; 1159 unsigned int dst_needs_clflush; 1160 void *dst, *src; 1161 int ret; 1162 1163 ret = i915_gem_object_prepare_write(dst_obj, &dst_needs_clflush); 1164 if (ret) 1165 return ERR_PTR(ret); 1166 1167 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB); 1168 i915_gem_object_finish_access(dst_obj); 1169 if (IS_ERR(dst)) 1170 return dst; 1171 1172 ret = i915_gem_object_prepare_read(src_obj, &src_needs_clflush); 1173 if (ret) { 1174 i915_gem_object_unpin_map(dst_obj); 1175 return ERR_PTR(ret); 1176 } 1177 1178 src = ERR_PTR(-ENODEV); 1179 if (src_needs_clflush && i915_has_memcpy_from_wc()) { 1180 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 1181 if (!IS_ERR(src)) { 1182 i915_unaligned_memcpy_from_wc(dst, 1183 src + offset, 1184 length); 1185 i915_gem_object_unpin_map(src_obj); 1186 } 1187 } 1188 if (IS_ERR(src)) { 1189 unsigned long x, n, remain; 1190 void *ptr; 1191 1192 /* 1193 * We can avoid clflushing partial cachelines before the write 1194 * if we only every write full cache-lines. Since we know that 1195 * both the source and destination are in multiples of 1196 * PAGE_SIZE, we can simply round up to the next cacheline. 1197 * We don't care about copying too much here as we only 1198 * validate up to the end of the batch. 1199 */ 1200 remain = length; 1201 if (dst_needs_clflush & CLFLUSH_BEFORE) 1202 remain = round_up(remain, 1203 boot_cpu_data.x86_clflush_size); 1204 1205 ptr = dst; 1206 x = offset_in_page(offset); 1207 for (n = offset >> PAGE_SHIFT; remain; n++) { 1208 int len = min(remain, PAGE_SIZE - x); 1209 1210 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1211 if (src_needs_clflush) 1212 drm_clflush_virt_range(src + x, len); 1213 memcpy(ptr, src + x, len); 1214 kunmap_atomic(src); 1215 1216 ptr += len; 1217 remain -= len; 1218 x = 0; 1219 } 1220 } 1221 1222 i915_gem_object_finish_access(src_obj); 1223 1224 memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32)); 1225 1226 /* dst_obj is returned with vmap pinned */ 1227 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; 1228 1229 return dst; 1230 } 1231 1232 static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc, 1233 const u32 cmd) 1234 { 1235 return desc->cmd.value == (cmd & desc->cmd.mask); 1236 } 1237 1238 static bool check_cmd(const struct intel_engine_cs *engine, 1239 const struct drm_i915_cmd_descriptor *desc, 1240 const u32 *cmd, u32 length) 1241 { 1242 if (desc->flags & CMD_DESC_SKIP) 1243 return true; 1244 1245 if (desc->flags & CMD_DESC_REJECT) { 1246 DRM_DEBUG("CMD: Rejected command: 0x%08X\n", *cmd); 1247 return false; 1248 } 1249 1250 if (desc->flags & CMD_DESC_REGISTER) { 1251 /* 1252 * Get the distance between individual register offset 1253 * fields if the command can perform more than one 1254 * access at a time. 1255 */ 1256 const u32 step = desc->reg.step ? desc->reg.step : length; 1257 u32 offset; 1258 1259 for (offset = desc->reg.offset; offset < length; 1260 offset += step) { 1261 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1262 const struct drm_i915_reg_descriptor *reg = 1263 find_reg(engine, reg_addr); 1264 1265 if (!reg) { 1266 DRM_DEBUG("CMD: Rejected register 0x%08X in command: 0x%08X (%s)\n", 1267 reg_addr, *cmd, engine->name); 1268 return false; 1269 } 1270 1271 /* 1272 * Check the value written to the register against the 1273 * allowed mask/value pair given in the whitelist entry. 1274 */ 1275 if (reg->mask) { 1276 if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) { 1277 DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n", 1278 reg_addr); 1279 return false; 1280 } 1281 1282 if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) { 1283 DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n", 1284 reg_addr); 1285 return false; 1286 } 1287 1288 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) && 1289 (offset + 2 > length || 1290 (cmd[offset + 1] & reg->mask) != reg->value)) { 1291 DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n", 1292 reg_addr); 1293 return false; 1294 } 1295 } 1296 } 1297 } 1298 1299 if (desc->flags & CMD_DESC_BITMASK) { 1300 int i; 1301 1302 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1303 u32 dword; 1304 1305 if (desc->bits[i].mask == 0) 1306 break; 1307 1308 if (desc->bits[i].condition_mask != 0) { 1309 u32 offset = 1310 desc->bits[i].condition_offset; 1311 u32 condition = cmd[offset] & 1312 desc->bits[i].condition_mask; 1313 1314 if (condition == 0) 1315 continue; 1316 } 1317 1318 if (desc->bits[i].offset >= length) { 1319 DRM_DEBUG("CMD: Rejected command 0x%08X, too short to check bitmask (%s)\n", 1320 *cmd, engine->name); 1321 return false; 1322 } 1323 1324 dword = cmd[desc->bits[i].offset] & 1325 desc->bits[i].mask; 1326 1327 if (dword != desc->bits[i].expected) { 1328 DRM_DEBUG("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (%s)\n", 1329 *cmd, 1330 desc->bits[i].mask, 1331 desc->bits[i].expected, 1332 dword, engine->name); 1333 return false; 1334 } 1335 } 1336 } 1337 1338 return true; 1339 } 1340 1341 static int check_bbstart(u32 *cmd, u32 offset, u32 length, 1342 u32 batch_length, 1343 u64 batch_addr, 1344 u64 shadow_addr, 1345 const unsigned long *jump_whitelist) 1346 { 1347 u64 jump_offset, jump_target; 1348 u32 target_cmd_offset, target_cmd_index; 1349 1350 /* For igt compatibility on older platforms */ 1351 if (!jump_whitelist) { 1352 DRM_DEBUG("CMD: Rejecting BB_START for ggtt based submission\n"); 1353 return -EACCES; 1354 } 1355 1356 if (length != 3) { 1357 DRM_DEBUG("CMD: Recursive BB_START with bad length(%u)\n", 1358 length); 1359 return -EINVAL; 1360 } 1361 1362 jump_target = *(u64 *)(cmd + 1); 1363 jump_offset = jump_target - batch_addr; 1364 1365 /* 1366 * Any underflow of jump_target is guaranteed to be outside the range 1367 * of a u32, so >= test catches both too large and too small 1368 */ 1369 if (jump_offset >= batch_length) { 1370 DRM_DEBUG("CMD: BB_START to 0x%llx jumps out of BB\n", 1371 jump_target); 1372 return -EINVAL; 1373 } 1374 1375 /* 1376 * This cannot overflow a u32 because we already checked jump_offset 1377 * is within the BB, and the batch_length is a u32 1378 */ 1379 target_cmd_offset = lower_32_bits(jump_offset); 1380 target_cmd_index = target_cmd_offset / sizeof(u32); 1381 1382 *(u64 *)(cmd + 1) = shadow_addr + target_cmd_offset; 1383 1384 if (target_cmd_index == offset) 1385 return 0; 1386 1387 if (IS_ERR(jump_whitelist)) 1388 return PTR_ERR(jump_whitelist); 1389 1390 if (!test_bit(target_cmd_index, jump_whitelist)) { 1391 DRM_DEBUG("CMD: BB_START to 0x%llx not a previously executed cmd\n", 1392 jump_target); 1393 return -EINVAL; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static unsigned long *alloc_whitelist(u32 batch_length) 1400 { 1401 unsigned long *jmp; 1402 1403 /* 1404 * We expect batch_length to be less than 256KiB for known users, 1405 * i.e. we need at most an 8KiB bitmap allocation which should be 1406 * reasonably cheap due to kmalloc caches. 1407 */ 1408 1409 /* Prefer to report transient allocation failure rather than hit oom */ 1410 jmp = bitmap_zalloc(DIV_ROUND_UP(batch_length, sizeof(u32)), 1411 GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN); 1412 if (!jmp) 1413 return ERR_PTR(-ENOMEM); 1414 1415 return jmp; 1416 } 1417 1418 #define LENGTH_BIAS 2 1419 1420 /** 1421 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations 1422 * @engine: the engine on which the batch is to execute 1423 * @batch: the batch buffer in question 1424 * @batch_offset: byte offset in the batch at which execution starts 1425 * @batch_length: length of the commands in batch_obj 1426 * @shadow: validated copy of the batch buffer in question 1427 * @trampoline: true if we need to trampoline into privileged execution 1428 * 1429 * Parses the specified batch buffer looking for privilege violations as 1430 * described in the overview. 1431 * 1432 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1433 * if the batch appears legal but should use hardware parsing 1434 */ 1435 1436 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1437 struct i915_vma *batch, 1438 unsigned long batch_offset, 1439 unsigned long batch_length, 1440 struct i915_vma *shadow, 1441 bool trampoline) 1442 { 1443 u32 *cmd, *batch_end, offset = 0; 1444 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1445 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1446 bool needs_clflush_after = false; 1447 unsigned long *jump_whitelist; 1448 u64 batch_addr, shadow_addr; 1449 int ret = 0; 1450 1451 GEM_BUG_ON(!IS_ALIGNED(batch_offset, sizeof(*cmd))); 1452 GEM_BUG_ON(!IS_ALIGNED(batch_length, sizeof(*cmd))); 1453 GEM_BUG_ON(range_overflows_t(u64, batch_offset, batch_length, 1454 batch->size)); 1455 GEM_BUG_ON(!batch_length); 1456 1457 cmd = copy_batch(shadow->obj, batch->obj, 1458 batch_offset, batch_length, 1459 &needs_clflush_after); 1460 if (IS_ERR(cmd)) { 1461 DRM_DEBUG("CMD: Failed to copy batch\n"); 1462 return PTR_ERR(cmd); 1463 } 1464 1465 jump_whitelist = NULL; 1466 if (!trampoline) 1467 /* Defer failure until attempted use */ 1468 jump_whitelist = alloc_whitelist(batch_length); 1469 1470 shadow_addr = gen8_canonical_addr(shadow->node.start); 1471 batch_addr = gen8_canonical_addr(batch->node.start + batch_offset); 1472 1473 /* 1474 * We use the batch length as size because the shadow object is as 1475 * large or larger and copy_batch() will write MI_NOPs to the extra 1476 * space. Parsing should be faster in some cases this way. 1477 */ 1478 batch_end = cmd + batch_length / sizeof(*batch_end); 1479 do { 1480 u32 length; 1481 1482 if (*cmd == MI_BATCH_BUFFER_END) 1483 break; 1484 1485 desc = find_cmd(engine, *cmd, desc, &default_desc); 1486 if (!desc) { 1487 DRM_DEBUG("CMD: Unrecognized command: 0x%08X\n", *cmd); 1488 ret = -EINVAL; 1489 break; 1490 } 1491 1492 if (desc->flags & CMD_DESC_FIXED) 1493 length = desc->length.fixed; 1494 else 1495 length = (*cmd & desc->length.mask) + LENGTH_BIAS; 1496 1497 if ((batch_end - cmd) < length) { 1498 DRM_DEBUG("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1499 *cmd, 1500 length, 1501 batch_end - cmd); 1502 ret = -EINVAL; 1503 break; 1504 } 1505 1506 if (!check_cmd(engine, desc, cmd, length)) { 1507 ret = -EACCES; 1508 break; 1509 } 1510 1511 if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) { 1512 ret = check_bbstart(cmd, offset, length, batch_length, 1513 batch_addr, shadow_addr, 1514 jump_whitelist); 1515 break; 1516 } 1517 1518 if (!IS_ERR_OR_NULL(jump_whitelist)) 1519 __set_bit(offset, jump_whitelist); 1520 1521 cmd += length; 1522 offset += length; 1523 if (cmd >= batch_end) { 1524 DRM_DEBUG("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1525 ret = -EINVAL; 1526 break; 1527 } 1528 } while (1); 1529 1530 if (trampoline) { 1531 /* 1532 * With the trampoline, the shadow is executed twice. 1533 * 1534 * 1 - starting at offset 0, in privileged mode 1535 * 2 - starting at offset batch_len, as non-privileged 1536 * 1537 * Only if the batch is valid and safe to execute, do we 1538 * allow the first privileged execution to proceed. If not, 1539 * we terminate the first batch and use the second batchbuffer 1540 * entry to chain to the original unsafe non-privileged batch, 1541 * leaving it to the HW to validate. 1542 */ 1543 *batch_end = MI_BATCH_BUFFER_END; 1544 1545 if (ret) { 1546 /* Batch unsafe to execute with privileges, cancel! */ 1547 cmd = page_mask_bits(shadow->obj->mm.mapping); 1548 *cmd = MI_BATCH_BUFFER_END; 1549 1550 /* If batch is unsafe but valid, jump to the original */ 1551 if (ret == -EACCES) { 1552 unsigned int flags; 1553 1554 flags = MI_BATCH_NON_SECURE_I965; 1555 if (IS_HASWELL(engine->i915)) 1556 flags = MI_BATCH_NON_SECURE_HSW; 1557 1558 GEM_BUG_ON(!IS_GRAPHICS_VER(engine->i915, 6, 7)); 1559 __gen6_emit_bb_start(batch_end, 1560 batch_addr, 1561 flags); 1562 1563 ret = 0; /* allow execution */ 1564 } 1565 } 1566 } 1567 1568 i915_gem_object_flush_map(shadow->obj); 1569 1570 if (!IS_ERR_OR_NULL(jump_whitelist)) 1571 kfree(jump_whitelist); 1572 i915_gem_object_unpin_map(shadow->obj); 1573 return ret; 1574 } 1575 1576 /** 1577 * i915_cmd_parser_get_version() - get the cmd parser version number 1578 * @dev_priv: i915 device private 1579 * 1580 * The cmd parser maintains a simple increasing integer version number suitable 1581 * for passing to userspace clients to determine what operations are permitted. 1582 * 1583 * Return: the current version number of the cmd parser 1584 */ 1585 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1586 { 1587 struct intel_engine_cs *engine; 1588 bool active = false; 1589 1590 /* If the command parser is not enabled, report 0 - unsupported */ 1591 for_each_uabi_engine(engine, dev_priv) { 1592 if (intel_engine_using_cmd_parser(engine)) { 1593 active = true; 1594 break; 1595 } 1596 } 1597 if (!active) 1598 return 0; 1599 1600 /* 1601 * Command parser version history 1602 * 1603 * 1. Initial version. Checks batches and reports violations, but leaves 1604 * hardware parsing enabled (so does not allow new use cases). 1605 * 2. Allow access to the MI_PREDICATE_SRC0 and 1606 * MI_PREDICATE_SRC1 registers. 1607 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1608 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1609 * 5. GPGPU dispatch compute indirect registers. 1610 * 6. TIMESTAMP register and Haswell CS GPR registers 1611 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1612 * 8. Don't report cmd_check() failures as EINVAL errors to userspace; 1613 * rely on the HW to NOOP disallowed commands as it would without 1614 * the parser enabled. 1615 * 9. Don't whitelist or handle oacontrol specially, as ownership 1616 * for oacontrol state is moving to i915-perf. 1617 * 10. Support for Gen9 BCS Parsing 1618 */ 1619 return 10; 1620 } 1621