xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/vgpu.c (revision f25a49ab)
182d375d1SZhi Wang /*
282d375d1SZhi Wang  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
382d375d1SZhi Wang  *
482d375d1SZhi Wang  * Permission is hereby granted, free of charge, to any person obtaining a
582d375d1SZhi Wang  * copy of this software and associated documentation files (the "Software"),
682d375d1SZhi Wang  * to deal in the Software without restriction, including without limitation
782d375d1SZhi Wang  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
882d375d1SZhi Wang  * and/or sell copies of the Software, and to permit persons to whom the
982d375d1SZhi Wang  * Software is furnished to do so, subject to the following conditions:
1082d375d1SZhi Wang  *
1182d375d1SZhi Wang  * The above copyright notice and this permission notice (including the next
1282d375d1SZhi Wang  * paragraph) shall be included in all copies or substantial portions of the
1382d375d1SZhi Wang  * Software.
1482d375d1SZhi Wang  *
1582d375d1SZhi Wang  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1682d375d1SZhi Wang  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1782d375d1SZhi Wang  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1882d375d1SZhi Wang  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1982d375d1SZhi Wang  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2082d375d1SZhi Wang  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2182d375d1SZhi Wang  * SOFTWARE.
2282d375d1SZhi Wang  *
2382d375d1SZhi Wang  * Authors:
2482d375d1SZhi Wang  *    Eddie Dong <eddie.dong@intel.com>
2582d375d1SZhi Wang  *    Kevin Tian <kevin.tian@intel.com>
2682d375d1SZhi Wang  *
2782d375d1SZhi Wang  * Contributors:
2882d375d1SZhi Wang  *    Ping Gao <ping.a.gao@intel.com>
2982d375d1SZhi Wang  *    Zhi Wang <zhi.a.wang@intel.com>
3082d375d1SZhi Wang  *    Bing Niu <bing.niu@intel.com>
3182d375d1SZhi Wang  *
3282d375d1SZhi Wang  */
3382d375d1SZhi Wang 
3482d375d1SZhi Wang #include "i915_drv.h"
35feddf6e8SZhenyu Wang #include "gvt.h"
36feddf6e8SZhenyu Wang #include "i915_pvinfo.h"
3782d375d1SZhi Wang 
3823736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu)
3982d375d1SZhi Wang {
4082d375d1SZhi Wang 	/* setup the ballooning information */
4190551a12SZhenyu Wang 	vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
4290551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
4390551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
4490551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
4590551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
46a2ae95afSWeinan Li 
4790551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
4890551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
49a2ae95afSWeinan Li 
5090551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
5182d375d1SZhi Wang 		vgpu_aperture_gmadr_base(vgpu);
5290551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
5382d375d1SZhi Wang 		vgpu_aperture_sz(vgpu);
5490551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
5582d375d1SZhi Wang 		vgpu_hidden_gmadr_base(vgpu);
5690551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
5782d375d1SZhi Wang 		vgpu_hidden_sz(vgpu);
5882d375d1SZhi Wang 
5990551a12SZhenyu Wang 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
6082d375d1SZhi Wang 
611c6ccad8STina Zhang 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
621c6ccad8STina Zhang 	vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
631c6ccad8STina Zhang 
6482d375d1SZhi Wang 	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
6582d375d1SZhi Wang 	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
6682d375d1SZhi Wang 		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
6782d375d1SZhi Wang 	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
6882d375d1SZhi Wang 		vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
6982d375d1SZhi Wang 	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
7082d375d1SZhi Wang 
7182d375d1SZhi Wang 	WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
7282d375d1SZhi Wang }
7382d375d1SZhi Wang 
74bc90d097SPing Gao #define VGPU_MAX_WEIGHT 16
75bc90d097SPing Gao #define VGPU_WEIGHT(vgpu_num)	\
76bc90d097SPing Gao 	(VGPU_MAX_WEIGHT / (vgpu_num))
77bc90d097SPing Gao 
78191020b6SZhenyu Wang static struct {
79191020b6SZhenyu Wang 	unsigned int low_mm;
80191020b6SZhenyu Wang 	unsigned int high_mm;
81191020b6SZhenyu Wang 	unsigned int fence;
82bc90d097SPing Gao 
83bc90d097SPing Gao 	/* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
84bc90d097SPing Gao 	 * with a weight of 4 on a contended host, different vGPU type has
85bc90d097SPing Gao 	 * different weight set. Legal weights range from 1 to 16.
86bc90d097SPing Gao 	 */
87bc90d097SPing Gao 	unsigned int weight;
88d1a513beSZhenyu Wang 	enum intel_vgpu_edid edid;
89191020b6SZhenyu Wang 	char *name;
90191020b6SZhenyu Wang } vgpu_types[] = {
91191020b6SZhenyu Wang /* Fixed vGPU type table */
92bc90d097SPing Gao 	{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
93bc90d097SPing Gao 	{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
94bc90d097SPing Gao 	{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
95bc90d097SPing Gao 	{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
96191020b6SZhenyu Wang };
97191020b6SZhenyu Wang 
9882d375d1SZhi Wang /**
991f31c829SZhenyu Wang  * intel_gvt_init_vgpu_types - initialize vGPU type list
1001f31c829SZhenyu Wang  * @gvt : GVT device
1011f31c829SZhenyu Wang  *
1021f31c829SZhenyu Wang  * Initialize vGPU type list based on available resource.
1031f31c829SZhenyu Wang  *
1041f31c829SZhenyu Wang  */
1051f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
1061f31c829SZhenyu Wang {
1071f31c829SZhenyu Wang 	unsigned int num_types;
1082d6ceb8eSZhenyu Wang 	unsigned int i, low_avail, high_avail;
1091f31c829SZhenyu Wang 	unsigned int min_low;
1101f31c829SZhenyu Wang 
1111f31c829SZhenyu Wang 	/* vGPU type name is defined as GVTg_Vx_y which contains
112191020b6SZhenyu Wang 	 * physical GPU generation type (e.g V4 as BDW server, V5 as
113191020b6SZhenyu Wang 	 * SKL server).
1141f31c829SZhenyu Wang 	 *
1151f31c829SZhenyu Wang 	 * Depend on physical SKU resource, might see vGPU types like
1161f31c829SZhenyu Wang 	 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
1171f31c829SZhenyu Wang 	 * different types of vGPU on same physical GPU depending on
1181f31c829SZhenyu Wang 	 * available resource. Each vGPU type will have "avail_instance"
1191f31c829SZhenyu Wang 	 * to indicate how many vGPU instance can be created for this
1201f31c829SZhenyu Wang 	 * type.
1211f31c829SZhenyu Wang 	 *
1221f31c829SZhenyu Wang 	 */
1232d6ceb8eSZhenyu Wang 	low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
1242d6ceb8eSZhenyu Wang 	high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
125191020b6SZhenyu Wang 	num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
1261f31c829SZhenyu Wang 
1271f31c829SZhenyu Wang 	gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
1281f31c829SZhenyu Wang 			     GFP_KERNEL);
1291f31c829SZhenyu Wang 	if (!gvt->types)
1301f31c829SZhenyu Wang 		return -ENOMEM;
1311f31c829SZhenyu Wang 
1321f31c829SZhenyu Wang 	min_low = MB_TO_BYTES(32);
1331f31c829SZhenyu Wang 	for (i = 0; i < num_types; ++i) {
134191020b6SZhenyu Wang 		if (low_avail / vgpu_types[i].low_mm == 0)
1351f31c829SZhenyu Wang 			break;
136191020b6SZhenyu Wang 
137191020b6SZhenyu Wang 		gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
138191020b6SZhenyu Wang 		gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
139191020b6SZhenyu Wang 		gvt->types[i].fence = vgpu_types[i].fence;
140bc90d097SPing Gao 
141bc90d097SPing Gao 		if (vgpu_types[i].weight < 1 ||
142bc90d097SPing Gao 					vgpu_types[i].weight > VGPU_MAX_WEIGHT)
143bc90d097SPing Gao 			return -EINVAL;
144bc90d097SPing Gao 
145bc90d097SPing Gao 		gvt->types[i].weight = vgpu_types[i].weight;
146d1a513beSZhenyu Wang 		gvt->types[i].resolution = vgpu_types[i].edid;
147191020b6SZhenyu Wang 		gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
148191020b6SZhenyu Wang 						   high_avail / vgpu_types[i].high_mm);
1491f31c829SZhenyu Wang 
1501f31c829SZhenyu Wang 		if (IS_GEN8(gvt->dev_priv))
151191020b6SZhenyu Wang 			sprintf(gvt->types[i].name, "GVTg_V4_%s",
152191020b6SZhenyu Wang 						vgpu_types[i].name);
1531f31c829SZhenyu Wang 		else if (IS_GEN9(gvt->dev_priv))
154191020b6SZhenyu Wang 			sprintf(gvt->types[i].name, "GVTg_V5_%s",
155191020b6SZhenyu Wang 						vgpu_types[i].name);
1561f31c829SZhenyu Wang 
157bc90d097SPing Gao 		gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
158191020b6SZhenyu Wang 			     i, gvt->types[i].name,
1591f31c829SZhenyu Wang 			     gvt->types[i].avail_instance,
1601f31c829SZhenyu Wang 			     gvt->types[i].low_gm_size,
161d1a513beSZhenyu Wang 			     gvt->types[i].high_gm_size, gvt->types[i].fence,
162bc90d097SPing Gao 			     gvt->types[i].weight,
163d1a513beSZhenyu Wang 			     vgpu_edid_str(gvt->types[i].resolution));
1641f31c829SZhenyu Wang 	}
1651f31c829SZhenyu Wang 
1661f31c829SZhenyu Wang 	gvt->num_types = i;
1671f31c829SZhenyu Wang 	return 0;
1681f31c829SZhenyu Wang }
1691f31c829SZhenyu Wang 
1701f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
1711f31c829SZhenyu Wang {
1721f31c829SZhenyu Wang 	kfree(gvt->types);
1731f31c829SZhenyu Wang }
1741f31c829SZhenyu Wang 
1751f31c829SZhenyu Wang static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
1761f31c829SZhenyu Wang {
1771f31c829SZhenyu Wang 	int i;
1781f31c829SZhenyu Wang 	unsigned int low_gm_avail, high_gm_avail, fence_avail;
179191020b6SZhenyu Wang 	unsigned int low_gm_min, high_gm_min, fence_min;
1801f31c829SZhenyu Wang 
1811f31c829SZhenyu Wang 	/* Need to depend on maxium hw resource size but keep on
1821f31c829SZhenyu Wang 	 * static config for now.
1831f31c829SZhenyu Wang 	 */
1842d6ceb8eSZhenyu Wang 	low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
1851f31c829SZhenyu Wang 		gvt->gm.vgpu_allocated_low_gm_size;
1862d6ceb8eSZhenyu Wang 	high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
1871f31c829SZhenyu Wang 		gvt->gm.vgpu_allocated_high_gm_size;
1881f31c829SZhenyu Wang 	fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
1891f31c829SZhenyu Wang 		gvt->fence.vgpu_allocated_fence_num;
1901f31c829SZhenyu Wang 
1911f31c829SZhenyu Wang 	for (i = 0; i < gvt->num_types; i++) {
1921f31c829SZhenyu Wang 		low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
1931f31c829SZhenyu Wang 		high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
1941f31c829SZhenyu Wang 		fence_min = fence_avail / gvt->types[i].fence;
195191020b6SZhenyu Wang 		gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
196191020b6SZhenyu Wang 						   fence_min);
1971f31c829SZhenyu Wang 
198191020b6SZhenyu Wang 		gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
199191020b6SZhenyu Wang 		       i, gvt->types[i].name,
2001f31c829SZhenyu Wang 		       gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
2011f31c829SZhenyu Wang 		       gvt->types[i].high_gm_size, gvt->types[i].fence);
2021f31c829SZhenyu Wang 	}
2031f31c829SZhenyu Wang }
2041f31c829SZhenyu Wang 
2051f31c829SZhenyu Wang /**
206b79c52aeSZhi Wang  * intel_gvt_active_vgpu - activate a virtual GPU
207b79c52aeSZhi Wang  * @vgpu: virtual GPU
208b79c52aeSZhi Wang  *
209b79c52aeSZhi Wang  * This function is called when user wants to activate a virtual GPU.
210b79c52aeSZhi Wang  *
211b79c52aeSZhi Wang  */
212b79c52aeSZhi Wang void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
213b79c52aeSZhi Wang {
214b79c52aeSZhi Wang 	mutex_lock(&vgpu->gvt->lock);
215b79c52aeSZhi Wang 	vgpu->active = true;
216b79c52aeSZhi Wang 	mutex_unlock(&vgpu->gvt->lock);
217b79c52aeSZhi Wang }
218b79c52aeSZhi Wang 
219b79c52aeSZhi Wang /**
220b79c52aeSZhi Wang  * intel_gvt_deactive_vgpu - deactivate a virtual GPU
221b79c52aeSZhi Wang  * @vgpu: virtual GPU
222b79c52aeSZhi Wang  *
223b79c52aeSZhi Wang  * This function is called when user wants to deactivate a virtual GPU.
224b79c52aeSZhi Wang  * All virtual GPU runtime information will be destroyed.
225b79c52aeSZhi Wang  *
226b79c52aeSZhi Wang  */
227b79c52aeSZhi Wang void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
228b79c52aeSZhi Wang {
229f25a49abSColin Xu 	mutex_lock(&vgpu->vgpu_lock);
230b79c52aeSZhi Wang 
231b79c52aeSZhi Wang 	vgpu->active = false;
232b79c52aeSZhi Wang 
2331406a14bSZhi Wang 	if (atomic_read(&vgpu->submission.running_workload_num)) {
234f25a49abSColin Xu 		mutex_unlock(&vgpu->vgpu_lock);
235b79c52aeSZhi Wang 		intel_gvt_wait_vgpu_idle(vgpu);
236f25a49abSColin Xu 		mutex_lock(&vgpu->vgpu_lock);
237b79c52aeSZhi Wang 	}
238b79c52aeSZhi Wang 
239b79c52aeSZhi Wang 	intel_vgpu_stop_schedule(vgpu);
240e546e281STina Zhang 	intel_vgpu_dmabuf_cleanup(vgpu);
241b79c52aeSZhi Wang 
242f25a49abSColin Xu 	mutex_unlock(&vgpu->vgpu_lock);
243b79c52aeSZhi Wang }
244b79c52aeSZhi Wang 
245b79c52aeSZhi Wang /**
24682d375d1SZhi Wang  * intel_gvt_destroy_vgpu - destroy a virtual GPU
24782d375d1SZhi Wang  * @vgpu: virtual GPU
24882d375d1SZhi Wang  *
24982d375d1SZhi Wang  * This function is called when user wants to destroy a virtual GPU.
25082d375d1SZhi Wang  *
25182d375d1SZhi Wang  */
25282d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
25382d375d1SZhi Wang {
25482d375d1SZhi Wang 	struct intel_gvt *gvt = vgpu->gvt;
25582d375d1SZhi Wang 
256f25a49abSColin Xu 	mutex_lock(&vgpu->vgpu_lock);
25782d375d1SZhi Wang 
258b79c52aeSZhi Wang 	WARN(vgpu->active, "vGPU is still active!\n");
259b79c52aeSZhi Wang 
260bc7b0be3SChangbin Du 	intel_gvt_debugfs_remove_vgpu(vgpu);
2614b63960eSZhi Wang 	intel_vgpu_clean_sched_policy(vgpu);
262874b6a91SZhi Wang 	intel_vgpu_clean_submission(vgpu);
26304d348aeSZhi Wang 	intel_vgpu_clean_display(vgpu);
2644d60c5fdSZhi Wang 	intel_vgpu_clean_opregion(vgpu);
2652707e444SZhi Wang 	intel_vgpu_clean_gtt(vgpu);
26682d375d1SZhi Wang 	intel_gvt_hypervisor_detach_vgpu(vgpu);
26782d375d1SZhi Wang 	intel_vgpu_free_resource(vgpu);
268cdcc4347SChangbin Du 	intel_vgpu_clean_mmio(vgpu);
269e546e281STina Zhang 	intel_vgpu_dmabuf_cleanup(vgpu);
270f25a49abSColin Xu 	mutex_unlock(&vgpu->vgpu_lock);
27182d375d1SZhi Wang 
272f25a49abSColin Xu 	mutex_lock(&gvt->lock);
273f25a49abSColin Xu 	idr_remove(&gvt->vgpu_idr, vgpu->id);
274f25a49abSColin Xu 	if (idr_is_empty(&gvt->vgpu_idr))
275f25a49abSColin Xu 		intel_gvt_clean_irq(gvt);
2761f31c829SZhenyu Wang 	intel_gvt_update_vgpu_types(gvt);
27782d375d1SZhi Wang 	mutex_unlock(&gvt->lock);
278f25a49abSColin Xu 
279f25a49abSColin Xu 	vfree(vgpu);
28082d375d1SZhi Wang }
28182d375d1SZhi Wang 
282afe04fbeSPing Gao #define IDLE_VGPU_IDR 0
283afe04fbeSPing Gao 
284afe04fbeSPing Gao /**
285afe04fbeSPing Gao  * intel_gvt_create_idle_vgpu - create an idle virtual GPU
286afe04fbeSPing Gao  * @gvt: GVT device
287afe04fbeSPing Gao  *
288afe04fbeSPing Gao  * This function is called when user wants to create an idle virtual GPU.
289afe04fbeSPing Gao  *
290afe04fbeSPing Gao  * Returns:
291afe04fbeSPing Gao  * pointer to intel_vgpu, error pointer if failed.
292afe04fbeSPing Gao  */
293afe04fbeSPing Gao struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
294afe04fbeSPing Gao {
295afe04fbeSPing Gao 	struct intel_vgpu *vgpu;
296afe04fbeSPing Gao 	enum intel_engine_id i;
297afe04fbeSPing Gao 	int ret;
298afe04fbeSPing Gao 
299afe04fbeSPing Gao 	vgpu = vzalloc(sizeof(*vgpu));
300afe04fbeSPing Gao 	if (!vgpu)
301afe04fbeSPing Gao 		return ERR_PTR(-ENOMEM);
302afe04fbeSPing Gao 
303afe04fbeSPing Gao 	vgpu->id = IDLE_VGPU_IDR;
304afe04fbeSPing Gao 	vgpu->gvt = gvt;
305f25a49abSColin Xu 	mutex_init(&vgpu->vgpu_lock);
306afe04fbeSPing Gao 
307afe04fbeSPing Gao 	for (i = 0; i < I915_NUM_ENGINES; i++)
3081406a14bSZhi Wang 		INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
309afe04fbeSPing Gao 
310afe04fbeSPing Gao 	ret = intel_vgpu_init_sched_policy(vgpu);
311afe04fbeSPing Gao 	if (ret)
312afe04fbeSPing Gao 		goto out_free_vgpu;
313afe04fbeSPing Gao 
314afe04fbeSPing Gao 	vgpu->active = false;
315afe04fbeSPing Gao 
316afe04fbeSPing Gao 	return vgpu;
317afe04fbeSPing Gao 
318afe04fbeSPing Gao out_free_vgpu:
319afe04fbeSPing Gao 	vfree(vgpu);
320afe04fbeSPing Gao 	return ERR_PTR(ret);
321afe04fbeSPing Gao }
322afe04fbeSPing Gao 
323afe04fbeSPing Gao /**
324afe04fbeSPing Gao  * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
325afe04fbeSPing Gao  * @vgpu: virtual GPU
326afe04fbeSPing Gao  *
327afe04fbeSPing Gao  * This function is called when user wants to destroy an idle virtual GPU.
328afe04fbeSPing Gao  *
329afe04fbeSPing Gao  */
330afe04fbeSPing Gao void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
331afe04fbeSPing Gao {
332f25a49abSColin Xu 	mutex_lock(&vgpu->vgpu_lock);
333afe04fbeSPing Gao 	intel_vgpu_clean_sched_policy(vgpu);
334f25a49abSColin Xu 	mutex_unlock(&vgpu->vgpu_lock);
335f25a49abSColin Xu 
336afe04fbeSPing Gao 	vfree(vgpu);
337afe04fbeSPing Gao }
338afe04fbeSPing Gao 
3391f31c829SZhenyu Wang static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
34082d375d1SZhi Wang 		struct intel_vgpu_creation_params *param)
34182d375d1SZhi Wang {
34282d375d1SZhi Wang 	struct intel_vgpu *vgpu;
34382d375d1SZhi Wang 	int ret;
34482d375d1SZhi Wang 
34582d375d1SZhi Wang 	gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
34682d375d1SZhi Wang 			param->handle, param->low_gm_sz, param->high_gm_sz,
34782d375d1SZhi Wang 			param->fence_sz);
34882d375d1SZhi Wang 
34982d375d1SZhi Wang 	vgpu = vzalloc(sizeof(*vgpu));
35082d375d1SZhi Wang 	if (!vgpu)
35182d375d1SZhi Wang 		return ERR_PTR(-ENOMEM);
35282d375d1SZhi Wang 
353afe04fbeSPing Gao 	ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
354afe04fbeSPing Gao 		GFP_KERNEL);
35582d375d1SZhi Wang 	if (ret < 0)
35682d375d1SZhi Wang 		goto out_free_vgpu;
35782d375d1SZhi Wang 
35882d375d1SZhi Wang 	vgpu->id = ret;
35982d375d1SZhi Wang 	vgpu->handle = param->handle;
36082d375d1SZhi Wang 	vgpu->gvt = gvt;
361bc90d097SPing Gao 	vgpu->sched_ctl.weight = param->weight;
362f25a49abSColin Xu 	mutex_init(&vgpu->vgpu_lock);
363e546e281STina Zhang 	INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
364e502a2afSChangbin Du 	INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
365e546e281STina Zhang 	idr_init(&vgpu->object_idr);
366536fc234SChangbin Du 	intel_vgpu_init_cfg_space(vgpu, param->primary);
36782d375d1SZhi Wang 
368cdcc4347SChangbin Du 	ret = intel_vgpu_init_mmio(vgpu);
36982d375d1SZhi Wang 	if (ret)
3704e537891SJike Song 		goto out_clean_idr;
37182d375d1SZhi Wang 
37282d375d1SZhi Wang 	ret = intel_vgpu_alloc_resource(vgpu, param);
37382d375d1SZhi Wang 	if (ret)
37482d375d1SZhi Wang 		goto out_clean_vgpu_mmio;
37582d375d1SZhi Wang 
37682d375d1SZhi Wang 	populate_pvinfo_page(vgpu);
37782d375d1SZhi Wang 
37882d375d1SZhi Wang 	ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
37982d375d1SZhi Wang 	if (ret)
38082d375d1SZhi Wang 		goto out_clean_vgpu_resource;
38182d375d1SZhi Wang 
3822707e444SZhi Wang 	ret = intel_vgpu_init_gtt(vgpu);
3832707e444SZhi Wang 	if (ret)
3842707e444SZhi Wang 		goto out_detach_hypervisor_vgpu;
3852707e444SZhi Wang 
3864dff110bSXiong Zhang 	ret = intel_vgpu_init_opregion(vgpu);
38704d348aeSZhi Wang 	if (ret)
3888f89743bSJike Song 		goto out_clean_gtt;
38904d348aeSZhi Wang 
3904dff110bSXiong Zhang 	ret = intel_vgpu_init_display(vgpu, param->resolution);
3914dff110bSXiong Zhang 	if (ret)
3924dff110bSXiong Zhang 		goto out_clean_opregion;
3934dff110bSXiong Zhang 
394ad1d3636SZhi Wang 	ret = intel_vgpu_setup_submission(vgpu);
3958453d674SZhi Wang 	if (ret)
3968453d674SZhi Wang 		goto out_clean_display;
3978453d674SZhi Wang 
3984b63960eSZhi Wang 	ret = intel_vgpu_init_sched_policy(vgpu);
3994b63960eSZhi Wang 	if (ret)
400ad1d3636SZhi Wang 		goto out_clean_submission;
4014b63960eSZhi Wang 
402bc7b0be3SChangbin Du 	ret = intel_gvt_debugfs_add_vgpu(vgpu);
403bc7b0be3SChangbin Du 	if (ret)
404bc7b0be3SChangbin Du 		goto out_clean_sched_policy;
405bc7b0be3SChangbin Du 
406b851adeaSTina Zhang 	ret = intel_gvt_hypervisor_set_opregion(vgpu);
407b851adeaSTina Zhang 	if (ret)
408b851adeaSTina Zhang 		goto out_clean_sched_policy;
409b851adeaSTina Zhang 
41082d375d1SZhi Wang 	return vgpu;
41182d375d1SZhi Wang 
412bc7b0be3SChangbin Du out_clean_sched_policy:
413bc7b0be3SChangbin Du 	intel_vgpu_clean_sched_policy(vgpu);
414ad1d3636SZhi Wang out_clean_submission:
415874b6a91SZhi Wang 	intel_vgpu_clean_submission(vgpu);
4168453d674SZhi Wang out_clean_display:
4178453d674SZhi Wang 	intel_vgpu_clean_display(vgpu);
4184dff110bSXiong Zhang out_clean_opregion:
4194dff110bSXiong Zhang 	intel_vgpu_clean_opregion(vgpu);
4204d60c5fdSZhi Wang out_clean_gtt:
4214d60c5fdSZhi Wang 	intel_vgpu_clean_gtt(vgpu);
4222707e444SZhi Wang out_detach_hypervisor_vgpu:
4232707e444SZhi Wang 	intel_gvt_hypervisor_detach_vgpu(vgpu);
42482d375d1SZhi Wang out_clean_vgpu_resource:
42582d375d1SZhi Wang 	intel_vgpu_free_resource(vgpu);
42682d375d1SZhi Wang out_clean_vgpu_mmio:
427cdcc4347SChangbin Du 	intel_vgpu_clean_mmio(vgpu);
4284e537891SJike Song out_clean_idr:
4294e537891SJike Song 	idr_remove(&gvt->vgpu_idr, vgpu->id);
43082d375d1SZhi Wang out_free_vgpu:
43182d375d1SZhi Wang 	vfree(vgpu);
43282d375d1SZhi Wang 	return ERR_PTR(ret);
43382d375d1SZhi Wang }
4341f31c829SZhenyu Wang 
4351f31c829SZhenyu Wang /**
4361f31c829SZhenyu Wang  * intel_gvt_create_vgpu - create a virtual GPU
4371f31c829SZhenyu Wang  * @gvt: GVT device
4381f31c829SZhenyu Wang  * @type: type of the vGPU to create
4391f31c829SZhenyu Wang  *
4401f31c829SZhenyu Wang  * This function is called when user wants to create a virtual GPU.
4411f31c829SZhenyu Wang  *
4421f31c829SZhenyu Wang  * Returns:
4431f31c829SZhenyu Wang  * pointer to intel_vgpu, error pointer if failed.
4441f31c829SZhenyu Wang  */
4451f31c829SZhenyu Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
4461f31c829SZhenyu Wang 				struct intel_vgpu_type *type)
4471f31c829SZhenyu Wang {
4481f31c829SZhenyu Wang 	struct intel_vgpu_creation_params param;
4491f31c829SZhenyu Wang 	struct intel_vgpu *vgpu;
4501f31c829SZhenyu Wang 
4511f31c829SZhenyu Wang 	param.handle = 0;
452e992faeeSDu, Changbin 	param.primary = 1;
4531f31c829SZhenyu Wang 	param.low_gm_sz = type->low_gm_size;
4541f31c829SZhenyu Wang 	param.high_gm_sz = type->high_gm_size;
4551f31c829SZhenyu Wang 	param.fence_sz = type->fence;
456bc90d097SPing Gao 	param.weight = type->weight;
457d1a513beSZhenyu Wang 	param.resolution = type->resolution;
4581f31c829SZhenyu Wang 
4591f31c829SZhenyu Wang 	/* XXX current param based on MB */
4601f31c829SZhenyu Wang 	param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
4611f31c829SZhenyu Wang 	param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
4621f31c829SZhenyu Wang 
463f25a49abSColin Xu 	mutex_lock(&gvt->lock);
4641f31c829SZhenyu Wang 	vgpu = __intel_gvt_create_vgpu(gvt, &param);
465f25a49abSColin Xu 	if (!IS_ERR(vgpu))
4661f31c829SZhenyu Wang 		/* calculate left instance change for types */
4671f31c829SZhenyu Wang 		intel_gvt_update_vgpu_types(gvt);
468f25a49abSColin Xu 	mutex_unlock(&gvt->lock);
4691f31c829SZhenyu Wang 
4701f31c829SZhenyu Wang 	return vgpu;
4711f31c829SZhenyu Wang }
4729ec1e66bSJike Song 
4739ec1e66bSJike Song /**
474cfe65f40SChangbin Du  * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
475cfe65f40SChangbin Du  * @vgpu: virtual GPU
476cfe65f40SChangbin Du  * @dmlr: vGPU Device Model Level Reset or GT Reset
477cfe65f40SChangbin Du  * @engine_mask: engines to reset for GT reset
478cfe65f40SChangbin Du  *
479cfe65f40SChangbin Du  * This function is called when user wants to reset a virtual GPU through
480f25a49abSColin Xu  * device model reset or GT reset. The caller should hold the vgpu lock.
481cfe65f40SChangbin Du  *
482cfe65f40SChangbin Du  * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
483cfe65f40SChangbin Du  * the whole vGPU to default state as when it is created. This vGPU function
484cfe65f40SChangbin Du  * is required both for functionary and security concerns.The ultimate goal
485cfe65f40SChangbin Du  * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
486cfe65f40SChangbin Du  * assign a vGPU to a virtual machine we must isse such reset first.
487cfe65f40SChangbin Du  *
488cfe65f40SChangbin Du  * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
489cfe65f40SChangbin Du  * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
490cfe65f40SChangbin Du  * Unlike the FLR, GT reset only reset particular resource of a vGPU per
491cfe65f40SChangbin Du  * the reset request. Guest driver can issue a GT reset by programming the
492cfe65f40SChangbin Du  * virtual GDRST register to reset specific virtual GPU engine or all
493cfe65f40SChangbin Du  * engines.
494cfe65f40SChangbin Du  *
495cfe65f40SChangbin Du  * The parameter dev_level is to identify if we will do DMLR or GT reset.
496cfe65f40SChangbin Du  * The parameter engine_mask is to specific the engines that need to be
497cfe65f40SChangbin Du  * resetted. If value ALL_ENGINES is given for engine_mask, it means
498cfe65f40SChangbin Du  * the caller requests a full GT reset that we will reset all virtual
499cfe65f40SChangbin Du  * GPU engines. For FLR, engine_mask is ignored.
500cfe65f40SChangbin Du  */
501cfe65f40SChangbin Du void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
502cfe65f40SChangbin Du 				 unsigned int engine_mask)
503cfe65f40SChangbin Du {
504cfe65f40SChangbin Du 	struct intel_gvt *gvt = vgpu->gvt;
505cfe65f40SChangbin Du 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
5066184cc8dSChuanxiao Dong 	unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
507cfe65f40SChangbin Du 
508cfe65f40SChangbin Du 	gvt_dbg_core("------------------------------------------\n");
509cfe65f40SChangbin Du 	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
510cfe65f40SChangbin Du 		     vgpu->id, dmlr, engine_mask);
5116184cc8dSChuanxiao Dong 
5126184cc8dSChuanxiao Dong 	vgpu->resetting_eng = resetting_eng;
513cfe65f40SChangbin Du 
514cfe65f40SChangbin Du 	intel_vgpu_stop_schedule(vgpu);
515cfe65f40SChangbin Du 	/*
516cfe65f40SChangbin Du 	 * The current_vgpu will set to NULL after stopping the
517cfe65f40SChangbin Du 	 * scheduler when the reset is triggered by current vgpu.
518cfe65f40SChangbin Du 	 */
519cfe65f40SChangbin Du 	if (scheduler->current_vgpu == NULL) {
520f25a49abSColin Xu 		mutex_unlock(&vgpu->vgpu_lock);
521cfe65f40SChangbin Du 		intel_gvt_wait_vgpu_idle(vgpu);
522f25a49abSColin Xu 		mutex_lock(&vgpu->vgpu_lock);
523cfe65f40SChangbin Du 	}
524cfe65f40SChangbin Du 
52506bb372fSZhi Wang 	intel_vgpu_reset_submission(vgpu, resetting_eng);
526cfe65f40SChangbin Du 	/* full GPU reset or device model level reset */
527cfe65f40SChangbin Du 	if (engine_mask == ALL_ENGINES || dmlr) {
5287569a06dSWeinan Li 		intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
529730c8eadSZhi Wang 		intel_vgpu_invalidate_ppgtt(vgpu);
530615c16a9Sfred gao 		/*fence will not be reset during virtual reset */
5314d3e67bbSChuanxiao Dong 		if (dmlr) {
5324d3e67bbSChuanxiao Dong 			intel_vgpu_reset_gtt(vgpu);
533cfe65f40SChangbin Du 			intel_vgpu_reset_resource(vgpu);
5344d3e67bbSChuanxiao Dong 		}
535615c16a9Sfred gao 
536615c16a9Sfred gao 		intel_vgpu_reset_mmio(vgpu, dmlr);
537cfe65f40SChangbin Du 		populate_pvinfo_page(vgpu);
5386294b61bSChangbin Du 		intel_vgpu_reset_display(vgpu);
539cfe65f40SChangbin Du 
540fd64be63SMin He 		if (dmlr) {
541cfe65f40SChangbin Du 			intel_vgpu_reset_cfg_space(vgpu);
542fd64be63SMin He 			/* only reset the failsafe mode when dmlr reset */
543fd64be63SMin He 			vgpu->failsafe = false;
544fd64be63SMin He 			vgpu->pv_notified = false;
545fd64be63SMin He 		}
546cfe65f40SChangbin Du 	}
547cfe65f40SChangbin Du 
5486184cc8dSChuanxiao Dong 	vgpu->resetting_eng = 0;
549cfe65f40SChangbin Du 	gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
550cfe65f40SChangbin Du 	gvt_dbg_core("------------------------------------------\n");
551cfe65f40SChangbin Du }
552cfe65f40SChangbin Du 
553cfe65f40SChangbin Du /**
554cfe65f40SChangbin Du  * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
5559ec1e66bSJike Song  * @vgpu: virtual GPU
5569ec1e66bSJike Song  *
5579ec1e66bSJike Song  * This function is called when user wants to reset a virtual GPU.
5589ec1e66bSJike Song  *
5599ec1e66bSJike Song  */
5609ec1e66bSJike Song void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
5619ec1e66bSJike Song {
562f25a49abSColin Xu 	mutex_lock(&vgpu->vgpu_lock);
563cfe65f40SChangbin Du 	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
564f25a49abSColin Xu 	mutex_unlock(&vgpu->vgpu_lock);
5659ec1e66bSJike Song }
566