xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/vgpu.c (revision bc7b0be3)
182d375d1SZhi Wang /*
282d375d1SZhi Wang  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
382d375d1SZhi Wang  *
482d375d1SZhi Wang  * Permission is hereby granted, free of charge, to any person obtaining a
582d375d1SZhi Wang  * copy of this software and associated documentation files (the "Software"),
682d375d1SZhi Wang  * to deal in the Software without restriction, including without limitation
782d375d1SZhi Wang  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
882d375d1SZhi Wang  * and/or sell copies of the Software, and to permit persons to whom the
982d375d1SZhi Wang  * Software is furnished to do so, subject to the following conditions:
1082d375d1SZhi Wang  *
1182d375d1SZhi Wang  * The above copyright notice and this permission notice (including the next
1282d375d1SZhi Wang  * paragraph) shall be included in all copies or substantial portions of the
1382d375d1SZhi Wang  * Software.
1482d375d1SZhi Wang  *
1582d375d1SZhi Wang  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1682d375d1SZhi Wang  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1782d375d1SZhi Wang  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1882d375d1SZhi Wang  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1982d375d1SZhi Wang  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
2082d375d1SZhi Wang  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2182d375d1SZhi Wang  * SOFTWARE.
2282d375d1SZhi Wang  *
2382d375d1SZhi Wang  * Authors:
2482d375d1SZhi Wang  *    Eddie Dong <eddie.dong@intel.com>
2582d375d1SZhi Wang  *    Kevin Tian <kevin.tian@intel.com>
2682d375d1SZhi Wang  *
2782d375d1SZhi Wang  * Contributors:
2882d375d1SZhi Wang  *    Ping Gao <ping.a.gao@intel.com>
2982d375d1SZhi Wang  *    Zhi Wang <zhi.a.wang@intel.com>
3082d375d1SZhi Wang  *    Bing Niu <bing.niu@intel.com>
3182d375d1SZhi Wang  *
3282d375d1SZhi Wang  */
3382d375d1SZhi Wang 
3482d375d1SZhi Wang #include "i915_drv.h"
35feddf6e8SZhenyu Wang #include "gvt.h"
36feddf6e8SZhenyu Wang #include "i915_pvinfo.h"
3782d375d1SZhi Wang 
3823736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu)
3982d375d1SZhi Wang {
4082d375d1SZhi Wang 	/* setup the ballooning information */
4182d375d1SZhi Wang 	vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
4282d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
4382d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
4482d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
4582d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
466b3816d6STina Zhang 	vgpu_vreg(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_48BIT_PPGTT;
4782d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
4882d375d1SZhi Wang 		vgpu_aperture_gmadr_base(vgpu);
4982d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
5082d375d1SZhi Wang 		vgpu_aperture_sz(vgpu);
5182d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
5282d375d1SZhi Wang 		vgpu_hidden_gmadr_base(vgpu);
5382d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
5482d375d1SZhi Wang 		vgpu_hidden_sz(vgpu);
5582d375d1SZhi Wang 
5682d375d1SZhi Wang 	vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
5782d375d1SZhi Wang 
5882d375d1SZhi Wang 	gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
5982d375d1SZhi Wang 	gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
6082d375d1SZhi Wang 		vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
6182d375d1SZhi Wang 	gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
6282d375d1SZhi Wang 		vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
6382d375d1SZhi Wang 	gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
6482d375d1SZhi Wang 
6582d375d1SZhi Wang 	WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
6682d375d1SZhi Wang }
6782d375d1SZhi Wang 
68bc90d097SPing Gao #define VGPU_MAX_WEIGHT 16
69bc90d097SPing Gao #define VGPU_WEIGHT(vgpu_num)	\
70bc90d097SPing Gao 	(VGPU_MAX_WEIGHT / (vgpu_num))
71bc90d097SPing Gao 
72191020b6SZhenyu Wang static struct {
73191020b6SZhenyu Wang 	unsigned int low_mm;
74191020b6SZhenyu Wang 	unsigned int high_mm;
75191020b6SZhenyu Wang 	unsigned int fence;
76bc90d097SPing Gao 
77bc90d097SPing Gao 	/* A vGPU with a weight of 8 will get twice as much GPU as a vGPU
78bc90d097SPing Gao 	 * with a weight of 4 on a contended host, different vGPU type has
79bc90d097SPing Gao 	 * different weight set. Legal weights range from 1 to 16.
80bc90d097SPing Gao 	 */
81bc90d097SPing Gao 	unsigned int weight;
82d1a513beSZhenyu Wang 	enum intel_vgpu_edid edid;
83191020b6SZhenyu Wang 	char *name;
84191020b6SZhenyu Wang } vgpu_types[] = {
85191020b6SZhenyu Wang /* Fixed vGPU type table */
86bc90d097SPing Gao 	{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
87bc90d097SPing Gao 	{ MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" },
88bc90d097SPing Gao 	{ MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" },
89bc90d097SPing Gao 	{ MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" },
90191020b6SZhenyu Wang };
91191020b6SZhenyu Wang 
9282d375d1SZhi Wang /**
931f31c829SZhenyu Wang  * intel_gvt_init_vgpu_types - initialize vGPU type list
941f31c829SZhenyu Wang  * @gvt : GVT device
951f31c829SZhenyu Wang  *
961f31c829SZhenyu Wang  * Initialize vGPU type list based on available resource.
971f31c829SZhenyu Wang  *
981f31c829SZhenyu Wang  */
991f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
1001f31c829SZhenyu Wang {
1011f31c829SZhenyu Wang 	unsigned int num_types;
1022d6ceb8eSZhenyu Wang 	unsigned int i, low_avail, high_avail;
1031f31c829SZhenyu Wang 	unsigned int min_low;
1041f31c829SZhenyu Wang 
1051f31c829SZhenyu Wang 	/* vGPU type name is defined as GVTg_Vx_y which contains
106191020b6SZhenyu Wang 	 * physical GPU generation type (e.g V4 as BDW server, V5 as
107191020b6SZhenyu Wang 	 * SKL server).
1081f31c829SZhenyu Wang 	 *
1091f31c829SZhenyu Wang 	 * Depend on physical SKU resource, might see vGPU types like
1101f31c829SZhenyu Wang 	 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
1111f31c829SZhenyu Wang 	 * different types of vGPU on same physical GPU depending on
1121f31c829SZhenyu Wang 	 * available resource. Each vGPU type will have "avail_instance"
1131f31c829SZhenyu Wang 	 * to indicate how many vGPU instance can be created for this
1141f31c829SZhenyu Wang 	 * type.
1151f31c829SZhenyu Wang 	 *
1161f31c829SZhenyu Wang 	 */
1172d6ceb8eSZhenyu Wang 	low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
1182d6ceb8eSZhenyu Wang 	high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
119191020b6SZhenyu Wang 	num_types = sizeof(vgpu_types) / sizeof(vgpu_types[0]);
1201f31c829SZhenyu Wang 
1211f31c829SZhenyu Wang 	gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
1221f31c829SZhenyu Wang 			     GFP_KERNEL);
1231f31c829SZhenyu Wang 	if (!gvt->types)
1241f31c829SZhenyu Wang 		return -ENOMEM;
1251f31c829SZhenyu Wang 
1261f31c829SZhenyu Wang 	min_low = MB_TO_BYTES(32);
1271f31c829SZhenyu Wang 	for (i = 0; i < num_types; ++i) {
128191020b6SZhenyu Wang 		if (low_avail / vgpu_types[i].low_mm == 0)
1291f31c829SZhenyu Wang 			break;
130191020b6SZhenyu Wang 
131191020b6SZhenyu Wang 		gvt->types[i].low_gm_size = vgpu_types[i].low_mm;
132191020b6SZhenyu Wang 		gvt->types[i].high_gm_size = vgpu_types[i].high_mm;
133191020b6SZhenyu Wang 		gvt->types[i].fence = vgpu_types[i].fence;
134bc90d097SPing Gao 
135bc90d097SPing Gao 		if (vgpu_types[i].weight < 1 ||
136bc90d097SPing Gao 					vgpu_types[i].weight > VGPU_MAX_WEIGHT)
137bc90d097SPing Gao 			return -EINVAL;
138bc90d097SPing Gao 
139bc90d097SPing Gao 		gvt->types[i].weight = vgpu_types[i].weight;
140d1a513beSZhenyu Wang 		gvt->types[i].resolution = vgpu_types[i].edid;
141191020b6SZhenyu Wang 		gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm,
142191020b6SZhenyu Wang 						   high_avail / vgpu_types[i].high_mm);
1431f31c829SZhenyu Wang 
1441f31c829SZhenyu Wang 		if (IS_GEN8(gvt->dev_priv))
145191020b6SZhenyu Wang 			sprintf(gvt->types[i].name, "GVTg_V4_%s",
146191020b6SZhenyu Wang 						vgpu_types[i].name);
1471f31c829SZhenyu Wang 		else if (IS_GEN9(gvt->dev_priv))
148191020b6SZhenyu Wang 			sprintf(gvt->types[i].name, "GVTg_V5_%s",
149191020b6SZhenyu Wang 						vgpu_types[i].name);
1501f31c829SZhenyu Wang 
151bc90d097SPing Gao 		gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n",
152191020b6SZhenyu Wang 			     i, gvt->types[i].name,
1531f31c829SZhenyu Wang 			     gvt->types[i].avail_instance,
1541f31c829SZhenyu Wang 			     gvt->types[i].low_gm_size,
155d1a513beSZhenyu Wang 			     gvt->types[i].high_gm_size, gvt->types[i].fence,
156bc90d097SPing Gao 			     gvt->types[i].weight,
157d1a513beSZhenyu Wang 			     vgpu_edid_str(gvt->types[i].resolution));
1581f31c829SZhenyu Wang 	}
1591f31c829SZhenyu Wang 
1601f31c829SZhenyu Wang 	gvt->num_types = i;
1611f31c829SZhenyu Wang 	return 0;
1621f31c829SZhenyu Wang }
1631f31c829SZhenyu Wang 
1641f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
1651f31c829SZhenyu Wang {
1661f31c829SZhenyu Wang 	kfree(gvt->types);
1671f31c829SZhenyu Wang }
1681f31c829SZhenyu Wang 
1691f31c829SZhenyu Wang static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
1701f31c829SZhenyu Wang {
1711f31c829SZhenyu Wang 	int i;
1721f31c829SZhenyu Wang 	unsigned int low_gm_avail, high_gm_avail, fence_avail;
173191020b6SZhenyu Wang 	unsigned int low_gm_min, high_gm_min, fence_min;
1741f31c829SZhenyu Wang 
1751f31c829SZhenyu Wang 	/* Need to depend on maxium hw resource size but keep on
1761f31c829SZhenyu Wang 	 * static config for now.
1771f31c829SZhenyu Wang 	 */
1782d6ceb8eSZhenyu Wang 	low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
1791f31c829SZhenyu Wang 		gvt->gm.vgpu_allocated_low_gm_size;
1802d6ceb8eSZhenyu Wang 	high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
1811f31c829SZhenyu Wang 		gvt->gm.vgpu_allocated_high_gm_size;
1821f31c829SZhenyu Wang 	fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
1831f31c829SZhenyu Wang 		gvt->fence.vgpu_allocated_fence_num;
1841f31c829SZhenyu Wang 
1851f31c829SZhenyu Wang 	for (i = 0; i < gvt->num_types; i++) {
1861f31c829SZhenyu Wang 		low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
1871f31c829SZhenyu Wang 		high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
1881f31c829SZhenyu Wang 		fence_min = fence_avail / gvt->types[i].fence;
189191020b6SZhenyu Wang 		gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min),
190191020b6SZhenyu Wang 						   fence_min);
1911f31c829SZhenyu Wang 
192191020b6SZhenyu Wang 		gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n",
193191020b6SZhenyu Wang 		       i, gvt->types[i].name,
1941f31c829SZhenyu Wang 		       gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
1951f31c829SZhenyu Wang 		       gvt->types[i].high_gm_size, gvt->types[i].fence);
1961f31c829SZhenyu Wang 	}
1971f31c829SZhenyu Wang }
1981f31c829SZhenyu Wang 
1991f31c829SZhenyu Wang /**
200b79c52aeSZhi Wang  * intel_gvt_active_vgpu - activate a virtual GPU
201b79c52aeSZhi Wang  * @vgpu: virtual GPU
202b79c52aeSZhi Wang  *
203b79c52aeSZhi Wang  * This function is called when user wants to activate a virtual GPU.
204b79c52aeSZhi Wang  *
205b79c52aeSZhi Wang  */
206b79c52aeSZhi Wang void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
207b79c52aeSZhi Wang {
208b79c52aeSZhi Wang 	mutex_lock(&vgpu->gvt->lock);
209b79c52aeSZhi Wang 	vgpu->active = true;
210b79c52aeSZhi Wang 	mutex_unlock(&vgpu->gvt->lock);
211b79c52aeSZhi Wang }
212b79c52aeSZhi Wang 
213b79c52aeSZhi Wang /**
214b79c52aeSZhi Wang  * intel_gvt_deactive_vgpu - deactivate a virtual GPU
215b79c52aeSZhi Wang  * @vgpu: virtual GPU
216b79c52aeSZhi Wang  *
217b79c52aeSZhi Wang  * This function is called when user wants to deactivate a virtual GPU.
218b79c52aeSZhi Wang  * All virtual GPU runtime information will be destroyed.
219b79c52aeSZhi Wang  *
220b79c52aeSZhi Wang  */
221b79c52aeSZhi Wang void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
222b79c52aeSZhi Wang {
223b79c52aeSZhi Wang 	struct intel_gvt *gvt = vgpu->gvt;
224b79c52aeSZhi Wang 
225b79c52aeSZhi Wang 	mutex_lock(&gvt->lock);
226b79c52aeSZhi Wang 
227b79c52aeSZhi Wang 	vgpu->active = false;
228b79c52aeSZhi Wang 
2291406a14bSZhi Wang 	if (atomic_read(&vgpu->submission.running_workload_num)) {
230b79c52aeSZhi Wang 		mutex_unlock(&gvt->lock);
231b79c52aeSZhi Wang 		intel_gvt_wait_vgpu_idle(vgpu);
232b79c52aeSZhi Wang 		mutex_lock(&gvt->lock);
233b79c52aeSZhi Wang 	}
234b79c52aeSZhi Wang 
235b79c52aeSZhi Wang 	intel_vgpu_stop_schedule(vgpu);
236b79c52aeSZhi Wang 
237b79c52aeSZhi Wang 	mutex_unlock(&gvt->lock);
238b79c52aeSZhi Wang }
239b79c52aeSZhi Wang 
240b79c52aeSZhi Wang /**
24182d375d1SZhi Wang  * intel_gvt_destroy_vgpu - destroy a virtual GPU
24282d375d1SZhi Wang  * @vgpu: virtual GPU
24382d375d1SZhi Wang  *
24482d375d1SZhi Wang  * This function is called when user wants to destroy a virtual GPU.
24582d375d1SZhi Wang  *
24682d375d1SZhi Wang  */
24782d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
24882d375d1SZhi Wang {
24982d375d1SZhi Wang 	struct intel_gvt *gvt = vgpu->gvt;
25082d375d1SZhi Wang 
25182d375d1SZhi Wang 	mutex_lock(&gvt->lock);
25282d375d1SZhi Wang 
253b79c52aeSZhi Wang 	WARN(vgpu->active, "vGPU is still active!\n");
254b79c52aeSZhi Wang 
255bc7b0be3SChangbin Du 	intel_gvt_debugfs_remove_vgpu(vgpu);
25682d375d1SZhi Wang 	idr_remove(&gvt->vgpu_idr, vgpu->id);
2574b63960eSZhi Wang 	intel_vgpu_clean_sched_policy(vgpu);
258874b6a91SZhi Wang 	intel_vgpu_clean_submission(vgpu);
25904d348aeSZhi Wang 	intel_vgpu_clean_display(vgpu);
2604d60c5fdSZhi Wang 	intel_vgpu_clean_opregion(vgpu);
2612707e444SZhi Wang 	intel_vgpu_clean_gtt(vgpu);
26282d375d1SZhi Wang 	intel_gvt_hypervisor_detach_vgpu(vgpu);
26382d375d1SZhi Wang 	intel_vgpu_free_resource(vgpu);
264cdcc4347SChangbin Du 	intel_vgpu_clean_mmio(vgpu);
26582d375d1SZhi Wang 	vfree(vgpu);
26682d375d1SZhi Wang 
2671f31c829SZhenyu Wang 	intel_gvt_update_vgpu_types(gvt);
26882d375d1SZhi Wang 	mutex_unlock(&gvt->lock);
26982d375d1SZhi Wang }
27082d375d1SZhi Wang 
271afe04fbeSPing Gao #define IDLE_VGPU_IDR 0
272afe04fbeSPing Gao 
273afe04fbeSPing Gao /**
274afe04fbeSPing Gao  * intel_gvt_create_idle_vgpu - create an idle virtual GPU
275afe04fbeSPing Gao  * @gvt: GVT device
276afe04fbeSPing Gao  *
277afe04fbeSPing Gao  * This function is called when user wants to create an idle virtual GPU.
278afe04fbeSPing Gao  *
279afe04fbeSPing Gao  * Returns:
280afe04fbeSPing Gao  * pointer to intel_vgpu, error pointer if failed.
281afe04fbeSPing Gao  */
282afe04fbeSPing Gao struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt)
283afe04fbeSPing Gao {
284afe04fbeSPing Gao 	struct intel_vgpu *vgpu;
285afe04fbeSPing Gao 	enum intel_engine_id i;
286afe04fbeSPing Gao 	int ret;
287afe04fbeSPing Gao 
288afe04fbeSPing Gao 	vgpu = vzalloc(sizeof(*vgpu));
289afe04fbeSPing Gao 	if (!vgpu)
290afe04fbeSPing Gao 		return ERR_PTR(-ENOMEM);
291afe04fbeSPing Gao 
292afe04fbeSPing Gao 	vgpu->id = IDLE_VGPU_IDR;
293afe04fbeSPing Gao 	vgpu->gvt = gvt;
294afe04fbeSPing Gao 
295afe04fbeSPing Gao 	for (i = 0; i < I915_NUM_ENGINES; i++)
2961406a14bSZhi Wang 		INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
297afe04fbeSPing Gao 
298afe04fbeSPing Gao 	ret = intel_vgpu_init_sched_policy(vgpu);
299afe04fbeSPing Gao 	if (ret)
300afe04fbeSPing Gao 		goto out_free_vgpu;
301afe04fbeSPing Gao 
302afe04fbeSPing Gao 	vgpu->active = false;
303afe04fbeSPing Gao 
304afe04fbeSPing Gao 	return vgpu;
305afe04fbeSPing Gao 
306afe04fbeSPing Gao out_free_vgpu:
307afe04fbeSPing Gao 	vfree(vgpu);
308afe04fbeSPing Gao 	return ERR_PTR(ret);
309afe04fbeSPing Gao }
310afe04fbeSPing Gao 
311afe04fbeSPing Gao /**
312afe04fbeSPing Gao  * intel_gvt_destroy_vgpu - destroy an idle virtual GPU
313afe04fbeSPing Gao  * @vgpu: virtual GPU
314afe04fbeSPing Gao  *
315afe04fbeSPing Gao  * This function is called when user wants to destroy an idle virtual GPU.
316afe04fbeSPing Gao  *
317afe04fbeSPing Gao  */
318afe04fbeSPing Gao void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
319afe04fbeSPing Gao {
320afe04fbeSPing Gao 	intel_vgpu_clean_sched_policy(vgpu);
321afe04fbeSPing Gao 	vfree(vgpu);
322afe04fbeSPing Gao }
323afe04fbeSPing Gao 
3241f31c829SZhenyu Wang static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
32582d375d1SZhi Wang 		struct intel_vgpu_creation_params *param)
32682d375d1SZhi Wang {
32782d375d1SZhi Wang 	struct intel_vgpu *vgpu;
32882d375d1SZhi Wang 	int ret;
32982d375d1SZhi Wang 
33082d375d1SZhi Wang 	gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
33182d375d1SZhi Wang 			param->handle, param->low_gm_sz, param->high_gm_sz,
33282d375d1SZhi Wang 			param->fence_sz);
33382d375d1SZhi Wang 
33482d375d1SZhi Wang 	vgpu = vzalloc(sizeof(*vgpu));
33582d375d1SZhi Wang 	if (!vgpu)
33682d375d1SZhi Wang 		return ERR_PTR(-ENOMEM);
33782d375d1SZhi Wang 
33882d375d1SZhi Wang 	mutex_lock(&gvt->lock);
33982d375d1SZhi Wang 
340afe04fbeSPing Gao 	ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
341afe04fbeSPing Gao 		GFP_KERNEL);
34282d375d1SZhi Wang 	if (ret < 0)
34382d375d1SZhi Wang 		goto out_free_vgpu;
34482d375d1SZhi Wang 
34582d375d1SZhi Wang 	vgpu->id = ret;
34682d375d1SZhi Wang 	vgpu->handle = param->handle;
34782d375d1SZhi Wang 	vgpu->gvt = gvt;
348bc90d097SPing Gao 	vgpu->sched_ctl.weight = param->weight;
34982d375d1SZhi Wang 
350536fc234SChangbin Du 	intel_vgpu_init_cfg_space(vgpu, param->primary);
35182d375d1SZhi Wang 
352cdcc4347SChangbin Du 	ret = intel_vgpu_init_mmio(vgpu);
35382d375d1SZhi Wang 	if (ret)
3544e537891SJike Song 		goto out_clean_idr;
35582d375d1SZhi Wang 
35682d375d1SZhi Wang 	ret = intel_vgpu_alloc_resource(vgpu, param);
35782d375d1SZhi Wang 	if (ret)
35882d375d1SZhi Wang 		goto out_clean_vgpu_mmio;
35982d375d1SZhi Wang 
36082d375d1SZhi Wang 	populate_pvinfo_page(vgpu);
36182d375d1SZhi Wang 
36282d375d1SZhi Wang 	ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
36382d375d1SZhi Wang 	if (ret)
36482d375d1SZhi Wang 		goto out_clean_vgpu_resource;
36582d375d1SZhi Wang 
3662707e444SZhi Wang 	ret = intel_vgpu_init_gtt(vgpu);
3672707e444SZhi Wang 	if (ret)
3682707e444SZhi Wang 		goto out_detach_hypervisor_vgpu;
3692707e444SZhi Wang 
370d1a513beSZhenyu Wang 	ret = intel_vgpu_init_display(vgpu, param->resolution);
37104d348aeSZhi Wang 	if (ret)
3728f89743bSJike Song 		goto out_clean_gtt;
37304d348aeSZhi Wang 
374ad1d3636SZhi Wang 	ret = intel_vgpu_setup_submission(vgpu);
3758453d674SZhi Wang 	if (ret)
3768453d674SZhi Wang 		goto out_clean_display;
3778453d674SZhi Wang 
3784b63960eSZhi Wang 	ret = intel_vgpu_init_sched_policy(vgpu);
3794b63960eSZhi Wang 	if (ret)
380ad1d3636SZhi Wang 		goto out_clean_submission;
3814b63960eSZhi Wang 
382bc7b0be3SChangbin Du 	ret = intel_gvt_debugfs_add_vgpu(vgpu);
383bc7b0be3SChangbin Du 	if (ret)
384bc7b0be3SChangbin Du 		goto out_clean_sched_policy;
385bc7b0be3SChangbin Du 
38682d375d1SZhi Wang 	mutex_unlock(&gvt->lock);
38782d375d1SZhi Wang 
38882d375d1SZhi Wang 	return vgpu;
38982d375d1SZhi Wang 
390bc7b0be3SChangbin Du out_clean_sched_policy:
391bc7b0be3SChangbin Du 	intel_vgpu_clean_sched_policy(vgpu);
392ad1d3636SZhi Wang out_clean_submission:
393874b6a91SZhi Wang 	intel_vgpu_clean_submission(vgpu);
3948453d674SZhi Wang out_clean_display:
3958453d674SZhi Wang 	intel_vgpu_clean_display(vgpu);
3964d60c5fdSZhi Wang out_clean_gtt:
3974d60c5fdSZhi Wang 	intel_vgpu_clean_gtt(vgpu);
3982707e444SZhi Wang out_detach_hypervisor_vgpu:
3992707e444SZhi Wang 	intel_gvt_hypervisor_detach_vgpu(vgpu);
40082d375d1SZhi Wang out_clean_vgpu_resource:
40182d375d1SZhi Wang 	intel_vgpu_free_resource(vgpu);
40282d375d1SZhi Wang out_clean_vgpu_mmio:
403cdcc4347SChangbin Du 	intel_vgpu_clean_mmio(vgpu);
4044e537891SJike Song out_clean_idr:
4054e537891SJike Song 	idr_remove(&gvt->vgpu_idr, vgpu->id);
40682d375d1SZhi Wang out_free_vgpu:
40782d375d1SZhi Wang 	vfree(vgpu);
40882d375d1SZhi Wang 	mutex_unlock(&gvt->lock);
40982d375d1SZhi Wang 	return ERR_PTR(ret);
41082d375d1SZhi Wang }
4111f31c829SZhenyu Wang 
4121f31c829SZhenyu Wang /**
4131f31c829SZhenyu Wang  * intel_gvt_create_vgpu - create a virtual GPU
4141f31c829SZhenyu Wang  * @gvt: GVT device
4151f31c829SZhenyu Wang  * @type: type of the vGPU to create
4161f31c829SZhenyu Wang  *
4171f31c829SZhenyu Wang  * This function is called when user wants to create a virtual GPU.
4181f31c829SZhenyu Wang  *
4191f31c829SZhenyu Wang  * Returns:
4201f31c829SZhenyu Wang  * pointer to intel_vgpu, error pointer if failed.
4211f31c829SZhenyu Wang  */
4221f31c829SZhenyu Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
4231f31c829SZhenyu Wang 				struct intel_vgpu_type *type)
4241f31c829SZhenyu Wang {
4251f31c829SZhenyu Wang 	struct intel_vgpu_creation_params param;
4261f31c829SZhenyu Wang 	struct intel_vgpu *vgpu;
4271f31c829SZhenyu Wang 
4281f31c829SZhenyu Wang 	param.handle = 0;
429e992faeeSDu, Changbin 	param.primary = 1;
4301f31c829SZhenyu Wang 	param.low_gm_sz = type->low_gm_size;
4311f31c829SZhenyu Wang 	param.high_gm_sz = type->high_gm_size;
4321f31c829SZhenyu Wang 	param.fence_sz = type->fence;
433bc90d097SPing Gao 	param.weight = type->weight;
434d1a513beSZhenyu Wang 	param.resolution = type->resolution;
4351f31c829SZhenyu Wang 
4361f31c829SZhenyu Wang 	/* XXX current param based on MB */
4371f31c829SZhenyu Wang 	param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
4381f31c829SZhenyu Wang 	param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
4391f31c829SZhenyu Wang 
4401f31c829SZhenyu Wang 	vgpu = __intel_gvt_create_vgpu(gvt, &param);
4411f31c829SZhenyu Wang 	if (IS_ERR(vgpu))
4421f31c829SZhenyu Wang 		return vgpu;
4431f31c829SZhenyu Wang 
4441f31c829SZhenyu Wang 	/* calculate left instance change for types */
4451f31c829SZhenyu Wang 	intel_gvt_update_vgpu_types(gvt);
4461f31c829SZhenyu Wang 
4471f31c829SZhenyu Wang 	return vgpu;
4481f31c829SZhenyu Wang }
4499ec1e66bSJike Song 
4509ec1e66bSJike Song /**
451cfe65f40SChangbin Du  * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
452cfe65f40SChangbin Du  * @vgpu: virtual GPU
453cfe65f40SChangbin Du  * @dmlr: vGPU Device Model Level Reset or GT Reset
454cfe65f40SChangbin Du  * @engine_mask: engines to reset for GT reset
455cfe65f40SChangbin Du  *
456cfe65f40SChangbin Du  * This function is called when user wants to reset a virtual GPU through
457cfe65f40SChangbin Du  * device model reset or GT reset. The caller should hold the gvt lock.
458cfe65f40SChangbin Du  *
459cfe65f40SChangbin Du  * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
460cfe65f40SChangbin Du  * the whole vGPU to default state as when it is created. This vGPU function
461cfe65f40SChangbin Du  * is required both for functionary and security concerns.The ultimate goal
462cfe65f40SChangbin Du  * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
463cfe65f40SChangbin Du  * assign a vGPU to a virtual machine we must isse such reset first.
464cfe65f40SChangbin Du  *
465cfe65f40SChangbin Du  * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
466cfe65f40SChangbin Du  * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
467cfe65f40SChangbin Du  * Unlike the FLR, GT reset only reset particular resource of a vGPU per
468cfe65f40SChangbin Du  * the reset request. Guest driver can issue a GT reset by programming the
469cfe65f40SChangbin Du  * virtual GDRST register to reset specific virtual GPU engine or all
470cfe65f40SChangbin Du  * engines.
471cfe65f40SChangbin Du  *
472cfe65f40SChangbin Du  * The parameter dev_level is to identify if we will do DMLR or GT reset.
473cfe65f40SChangbin Du  * The parameter engine_mask is to specific the engines that need to be
474cfe65f40SChangbin Du  * resetted. If value ALL_ENGINES is given for engine_mask, it means
475cfe65f40SChangbin Du  * the caller requests a full GT reset that we will reset all virtual
476cfe65f40SChangbin Du  * GPU engines. For FLR, engine_mask is ignored.
477cfe65f40SChangbin Du  */
478cfe65f40SChangbin Du void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
479cfe65f40SChangbin Du 				 unsigned int engine_mask)
480cfe65f40SChangbin Du {
481cfe65f40SChangbin Du 	struct intel_gvt *gvt = vgpu->gvt;
482cfe65f40SChangbin Du 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
4836184cc8dSChuanxiao Dong 	unsigned int resetting_eng = dmlr ? ALL_ENGINES : engine_mask;
484cfe65f40SChangbin Du 
485cfe65f40SChangbin Du 	gvt_dbg_core("------------------------------------------\n");
486cfe65f40SChangbin Du 	gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
487cfe65f40SChangbin Du 		     vgpu->id, dmlr, engine_mask);
4886184cc8dSChuanxiao Dong 
4896184cc8dSChuanxiao Dong 	vgpu->resetting_eng = resetting_eng;
490cfe65f40SChangbin Du 
491cfe65f40SChangbin Du 	intel_vgpu_stop_schedule(vgpu);
492cfe65f40SChangbin Du 	/*
493cfe65f40SChangbin Du 	 * The current_vgpu will set to NULL after stopping the
494cfe65f40SChangbin Du 	 * scheduler when the reset is triggered by current vgpu.
495cfe65f40SChangbin Du 	 */
496cfe65f40SChangbin Du 	if (scheduler->current_vgpu == NULL) {
497cfe65f40SChangbin Du 		mutex_unlock(&gvt->lock);
498cfe65f40SChangbin Du 		intel_gvt_wait_vgpu_idle(vgpu);
499cfe65f40SChangbin Du 		mutex_lock(&gvt->lock);
500cfe65f40SChangbin Du 	}
501cfe65f40SChangbin Du 
50206bb372fSZhi Wang 	intel_vgpu_reset_submission(vgpu, resetting_eng);
503cfe65f40SChangbin Du 	/* full GPU reset or device model level reset */
504cfe65f40SChangbin Du 	if (engine_mask == ALL_ENGINES || dmlr) {
50506bb372fSZhi Wang 		intel_vgpu_select_submission_ops(vgpu, 0);
506615c16a9Sfred gao 
507615c16a9Sfred gao 		/*fence will not be reset during virtual reset */
5084d3e67bbSChuanxiao Dong 		if (dmlr) {
5094d3e67bbSChuanxiao Dong 			intel_vgpu_reset_gtt(vgpu);
510cfe65f40SChangbin Du 			intel_vgpu_reset_resource(vgpu);
5114d3e67bbSChuanxiao Dong 		}
512615c16a9Sfred gao 
513615c16a9Sfred gao 		intel_vgpu_reset_mmio(vgpu, dmlr);
514cfe65f40SChangbin Du 		populate_pvinfo_page(vgpu);
5156294b61bSChangbin Du 		intel_vgpu_reset_display(vgpu);
516cfe65f40SChangbin Du 
517fd64be63SMin He 		if (dmlr) {
518cfe65f40SChangbin Du 			intel_vgpu_reset_cfg_space(vgpu);
519fd64be63SMin He 			/* only reset the failsafe mode when dmlr reset */
520fd64be63SMin He 			vgpu->failsafe = false;
521fd64be63SMin He 			vgpu->pv_notified = false;
522fd64be63SMin He 		}
523cfe65f40SChangbin Du 	}
524cfe65f40SChangbin Du 
5256184cc8dSChuanxiao Dong 	vgpu->resetting_eng = 0;
526cfe65f40SChangbin Du 	gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
527cfe65f40SChangbin Du 	gvt_dbg_core("------------------------------------------\n");
528cfe65f40SChangbin Du }
529cfe65f40SChangbin Du 
530cfe65f40SChangbin Du /**
531cfe65f40SChangbin Du  * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
5329ec1e66bSJike Song  * @vgpu: virtual GPU
5339ec1e66bSJike Song  *
5349ec1e66bSJike Song  * This function is called when user wants to reset a virtual GPU.
5359ec1e66bSJike Song  *
5369ec1e66bSJike Song  */
5379ec1e66bSJike Song void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
5389ec1e66bSJike Song {
539cfe65f40SChangbin Du 	mutex_lock(&vgpu->gvt->lock);
540cfe65f40SChangbin Du 	intel_gvt_reset_vgpu_locked(vgpu, true, 0);
541cfe65f40SChangbin Du 	mutex_unlock(&vgpu->gvt->lock);
5429ec1e66bSJike Song }
543