182d375d1SZhi Wang /* 282d375d1SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 382d375d1SZhi Wang * 482d375d1SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 582d375d1SZhi Wang * copy of this software and associated documentation files (the "Software"), 682d375d1SZhi Wang * to deal in the Software without restriction, including without limitation 782d375d1SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 882d375d1SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 982d375d1SZhi Wang * Software is furnished to do so, subject to the following conditions: 1082d375d1SZhi Wang * 1182d375d1SZhi Wang * The above copyright notice and this permission notice (including the next 1282d375d1SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 1382d375d1SZhi Wang * Software. 1482d375d1SZhi Wang * 1582d375d1SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1682d375d1SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1782d375d1SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1882d375d1SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1982d375d1SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2082d375d1SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 2182d375d1SZhi Wang * SOFTWARE. 2282d375d1SZhi Wang * 2382d375d1SZhi Wang * Authors: 2482d375d1SZhi Wang * Eddie Dong <eddie.dong@intel.com> 2582d375d1SZhi Wang * Kevin Tian <kevin.tian@intel.com> 2682d375d1SZhi Wang * 2782d375d1SZhi Wang * Contributors: 2882d375d1SZhi Wang * Ping Gao <ping.a.gao@intel.com> 2982d375d1SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 3082d375d1SZhi Wang * Bing Niu <bing.niu@intel.com> 3182d375d1SZhi Wang * 3282d375d1SZhi Wang */ 3382d375d1SZhi Wang 3482d375d1SZhi Wang #include "i915_drv.h" 35feddf6e8SZhenyu Wang #include "gvt.h" 36feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 3782d375d1SZhi Wang 3823736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu) 3982d375d1SZhi Wang { 40a61ac1e7SChris Wilson struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 4182d375d1SZhi Wang /* setup the ballooning information */ 4290551a12SZhenyu Wang vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 4390551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; 4490551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; 4590551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; 4690551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 47a2ae95afSWeinan Li 48ca6ac684SChris Wilson vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; 4990551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION; 50aa36ed6dSChangbin Du vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; 51a2ae95afSWeinan Li 5290551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 5382d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu); 5490551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 5582d375d1SZhi Wang vgpu_aperture_sz(vgpu); 5690551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 5782d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu); 5890551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 5982d375d1SZhi Wang vgpu_hidden_sz(vgpu); 6082d375d1SZhi Wang 6190551a12SZhenyu Wang vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 6282d375d1SZhi Wang 631c6ccad8STina Zhang vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX; 641c6ccad8STina Zhang vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX; 651c6ccad8STina Zhang 6682d375d1SZhi Wang gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 6782d375d1SZhi Wang gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 6882d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); 6982d375d1SZhi Wang gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", 7082d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); 7182d375d1SZhi Wang gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); 7282d375d1SZhi Wang 7312d58619SPankaj Bharadiya drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 7482d375d1SZhi Wang } 7582d375d1SZhi Wang 76bc90d097SPing Gao #define VGPU_MAX_WEIGHT 16 77bc90d097SPing Gao #define VGPU_WEIGHT(vgpu_num) \ 78bc90d097SPing Gao (VGPU_MAX_WEIGHT / (vgpu_num)) 79bc90d097SPing Gao 80191020b6SZhenyu Wang static struct { 81191020b6SZhenyu Wang unsigned int low_mm; 82191020b6SZhenyu Wang unsigned int high_mm; 83191020b6SZhenyu Wang unsigned int fence; 84bc90d097SPing Gao 85bc90d097SPing Gao /* A vGPU with a weight of 8 will get twice as much GPU as a vGPU 86bc90d097SPing Gao * with a weight of 4 on a contended host, different vGPU type has 87bc90d097SPing Gao * different weight set. Legal weights range from 1 to 16. 88bc90d097SPing Gao */ 89bc90d097SPing Gao unsigned int weight; 90d1a513beSZhenyu Wang enum intel_vgpu_edid edid; 91191020b6SZhenyu Wang char *name; 92191020b6SZhenyu Wang } vgpu_types[] = { 93191020b6SZhenyu Wang /* Fixed vGPU type table */ 94bc90d097SPing Gao { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" }, 95bc90d097SPing Gao { MB_TO_BYTES(128), MB_TO_BYTES(512), 4, VGPU_WEIGHT(4), GVT_EDID_1920_1200, "4" }, 96bc90d097SPing Gao { MB_TO_BYTES(256), MB_TO_BYTES(1024), 4, VGPU_WEIGHT(2), GVT_EDID_1920_1200, "2" }, 97bc90d097SPing Gao { MB_TO_BYTES(512), MB_TO_BYTES(2048), 4, VGPU_WEIGHT(1), GVT_EDID_1920_1200, "1" }, 98191020b6SZhenyu Wang }; 99191020b6SZhenyu Wang 10082d375d1SZhi Wang /** 1011f31c829SZhenyu Wang * intel_gvt_init_vgpu_types - initialize vGPU type list 1021f31c829SZhenyu Wang * @gvt : GVT device 1031f31c829SZhenyu Wang * 1041f31c829SZhenyu Wang * Initialize vGPU type list based on available resource. 1051f31c829SZhenyu Wang * 1061f31c829SZhenyu Wang */ 1071f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) 1081f31c829SZhenyu Wang { 1091f31c829SZhenyu Wang unsigned int num_types; 1102d6ceb8eSZhenyu Wang unsigned int i, low_avail, high_avail; 1111f31c829SZhenyu Wang unsigned int min_low; 1121f31c829SZhenyu Wang 1131f31c829SZhenyu Wang /* vGPU type name is defined as GVTg_Vx_y which contains 114191020b6SZhenyu Wang * physical GPU generation type (e.g V4 as BDW server, V5 as 115191020b6SZhenyu Wang * SKL server). 1161f31c829SZhenyu Wang * 1171f31c829SZhenyu Wang * Depend on physical SKU resource, might see vGPU types like 1181f31c829SZhenyu Wang * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create 1191f31c829SZhenyu Wang * different types of vGPU on same physical GPU depending on 1201f31c829SZhenyu Wang * available resource. Each vGPU type will have "avail_instance" 1211f31c829SZhenyu Wang * to indicate how many vGPU instance can be created for this 1221f31c829SZhenyu Wang * type. 1231f31c829SZhenyu Wang * 1241f31c829SZhenyu Wang */ 1252d6ceb8eSZhenyu Wang low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; 1262d6ceb8eSZhenyu Wang high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; 127cb7ee522SAishwarya Ramakrishnan num_types = ARRAY_SIZE(vgpu_types); 1281f31c829SZhenyu Wang 1296396bb22SKees Cook gvt->types = kcalloc(num_types, sizeof(struct intel_vgpu_type), 1301f31c829SZhenyu Wang GFP_KERNEL); 1311f31c829SZhenyu Wang if (!gvt->types) 1321f31c829SZhenyu Wang return -ENOMEM; 1331f31c829SZhenyu Wang 1341f31c829SZhenyu Wang min_low = MB_TO_BYTES(32); 1351f31c829SZhenyu Wang for (i = 0; i < num_types; ++i) { 136191020b6SZhenyu Wang if (low_avail / vgpu_types[i].low_mm == 0) 1371f31c829SZhenyu Wang break; 138191020b6SZhenyu Wang 139191020b6SZhenyu Wang gvt->types[i].low_gm_size = vgpu_types[i].low_mm; 140191020b6SZhenyu Wang gvt->types[i].high_gm_size = vgpu_types[i].high_mm; 141191020b6SZhenyu Wang gvt->types[i].fence = vgpu_types[i].fence; 142bc90d097SPing Gao 143bc90d097SPing Gao if (vgpu_types[i].weight < 1 || 144bc90d097SPing Gao vgpu_types[i].weight > VGPU_MAX_WEIGHT) 145bc90d097SPing Gao return -EINVAL; 146bc90d097SPing Gao 147bc90d097SPing Gao gvt->types[i].weight = vgpu_types[i].weight; 148d1a513beSZhenyu Wang gvt->types[i].resolution = vgpu_types[i].edid; 149191020b6SZhenyu Wang gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, 150191020b6SZhenyu Wang high_avail / vgpu_types[i].high_mm); 1511f31c829SZhenyu Wang 152a61ac1e7SChris Wilson if (IS_GEN(gvt->gt->i915, 8)) 153191020b6SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V4_%s", 154191020b6SZhenyu Wang vgpu_types[i].name); 155a61ac1e7SChris Wilson else if (IS_GEN(gvt->gt->i915, 9)) 156191020b6SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V5_%s", 157191020b6SZhenyu Wang vgpu_types[i].name); 1581f31c829SZhenyu Wang 159bc90d097SPing Gao gvt_dbg_core("type[%d]: %s avail %u low %u high %u fence %u weight %u res %s\n", 160191020b6SZhenyu Wang i, gvt->types[i].name, 1611f31c829SZhenyu Wang gvt->types[i].avail_instance, 1621f31c829SZhenyu Wang gvt->types[i].low_gm_size, 163d1a513beSZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence, 164bc90d097SPing Gao gvt->types[i].weight, 165d1a513beSZhenyu Wang vgpu_edid_str(gvt->types[i].resolution)); 1661f31c829SZhenyu Wang } 1671f31c829SZhenyu Wang 1681f31c829SZhenyu Wang gvt->num_types = i; 1691f31c829SZhenyu Wang return 0; 1701f31c829SZhenyu Wang } 1711f31c829SZhenyu Wang 1721f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) 1731f31c829SZhenyu Wang { 1741f31c829SZhenyu Wang kfree(gvt->types); 1751f31c829SZhenyu Wang } 1761f31c829SZhenyu Wang 1771f31c829SZhenyu Wang static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt) 1781f31c829SZhenyu Wang { 1791f31c829SZhenyu Wang int i; 1801f31c829SZhenyu Wang unsigned int low_gm_avail, high_gm_avail, fence_avail; 181191020b6SZhenyu Wang unsigned int low_gm_min, high_gm_min, fence_min; 1821f31c829SZhenyu Wang 1831f31c829SZhenyu Wang /* Need to depend on maxium hw resource size but keep on 1841f31c829SZhenyu Wang * static config for now. 1851f31c829SZhenyu Wang */ 1862d6ceb8eSZhenyu Wang low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE - 1871f31c829SZhenyu Wang gvt->gm.vgpu_allocated_low_gm_size; 1882d6ceb8eSZhenyu Wang high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE - 1891f31c829SZhenyu Wang gvt->gm.vgpu_allocated_high_gm_size; 1901f31c829SZhenyu Wang fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 1911f31c829SZhenyu Wang gvt->fence.vgpu_allocated_fence_num; 1921f31c829SZhenyu Wang 1931f31c829SZhenyu Wang for (i = 0; i < gvt->num_types; i++) { 1941f31c829SZhenyu Wang low_gm_min = low_gm_avail / gvt->types[i].low_gm_size; 1951f31c829SZhenyu Wang high_gm_min = high_gm_avail / gvt->types[i].high_gm_size; 1961f31c829SZhenyu Wang fence_min = fence_avail / gvt->types[i].fence; 197191020b6SZhenyu Wang gvt->types[i].avail_instance = min(min(low_gm_min, high_gm_min), 198191020b6SZhenyu Wang fence_min); 1991f31c829SZhenyu Wang 200191020b6SZhenyu Wang gvt_dbg_core("update type[%d]: %s avail %u low %u high %u fence %u\n", 201191020b6SZhenyu Wang i, gvt->types[i].name, 2021f31c829SZhenyu Wang gvt->types[i].avail_instance, gvt->types[i].low_gm_size, 2031f31c829SZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence); 2041f31c829SZhenyu Wang } 2051f31c829SZhenyu Wang } 2061f31c829SZhenyu Wang 2071f31c829SZhenyu Wang /** 208b79c52aeSZhi Wang * intel_gvt_active_vgpu - activate a virtual GPU 209b79c52aeSZhi Wang * @vgpu: virtual GPU 210b79c52aeSZhi Wang * 211b79c52aeSZhi Wang * This function is called when user wants to activate a virtual GPU. 212b79c52aeSZhi Wang * 213b79c52aeSZhi Wang */ 214b79c52aeSZhi Wang void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu) 215b79c52aeSZhi Wang { 2166d44694dSZhenyu Wang mutex_lock(&vgpu->vgpu_lock); 217b79c52aeSZhi Wang vgpu->active = true; 2186d44694dSZhenyu Wang mutex_unlock(&vgpu->vgpu_lock); 219b79c52aeSZhi Wang } 220b79c52aeSZhi Wang 221b79c52aeSZhi Wang /** 222b79c52aeSZhi Wang * intel_gvt_deactive_vgpu - deactivate a virtual GPU 223b79c52aeSZhi Wang * @vgpu: virtual GPU 224b79c52aeSZhi Wang * 225b79c52aeSZhi Wang * This function is called when user wants to deactivate a virtual GPU. 226f9090d4cSHang Yuan * The virtual GPU will be stopped. 227b79c52aeSZhi Wang * 228b79c52aeSZhi Wang */ 229b79c52aeSZhi Wang void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu) 230b79c52aeSZhi Wang { 231f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock); 232b79c52aeSZhi Wang 233b79c52aeSZhi Wang vgpu->active = false; 234b79c52aeSZhi Wang 2351406a14bSZhi Wang if (atomic_read(&vgpu->submission.running_workload_num)) { 236f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 237b79c52aeSZhi Wang intel_gvt_wait_vgpu_idle(vgpu); 238f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock); 239b79c52aeSZhi Wang } 240b79c52aeSZhi Wang 241b79c52aeSZhi Wang intel_vgpu_stop_schedule(vgpu); 242b79c52aeSZhi Wang 243f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 244b79c52aeSZhi Wang } 245b79c52aeSZhi Wang 246b79c52aeSZhi Wang /** 247f9090d4cSHang Yuan * intel_gvt_release_vgpu - release a virtual GPU 248f9090d4cSHang Yuan * @vgpu: virtual GPU 249f9090d4cSHang Yuan * 250f9090d4cSHang Yuan * This function is called when user wants to release a virtual GPU. 251f9090d4cSHang Yuan * The virtual GPU will be stopped and all runtime information will be 252f9090d4cSHang Yuan * destroyed. 253f9090d4cSHang Yuan * 254f9090d4cSHang Yuan */ 255f9090d4cSHang Yuan void intel_gvt_release_vgpu(struct intel_vgpu *vgpu) 256f9090d4cSHang Yuan { 257f9090d4cSHang Yuan intel_gvt_deactivate_vgpu(vgpu); 258f9090d4cSHang Yuan 259f9090d4cSHang Yuan mutex_lock(&vgpu->vgpu_lock); 260ba25d977SColin Xu vgpu->d3_entered = false; 261f9090d4cSHang Yuan intel_vgpu_clean_workloads(vgpu, ALL_ENGINES); 262f9090d4cSHang Yuan intel_vgpu_dmabuf_cleanup(vgpu); 263f9090d4cSHang Yuan mutex_unlock(&vgpu->vgpu_lock); 264f9090d4cSHang Yuan } 265f9090d4cSHang Yuan 266f9090d4cSHang Yuan /** 26782d375d1SZhi Wang * intel_gvt_destroy_vgpu - destroy a virtual GPU 26882d375d1SZhi Wang * @vgpu: virtual GPU 26982d375d1SZhi Wang * 27082d375d1SZhi Wang * This function is called when user wants to destroy a virtual GPU. 27182d375d1SZhi Wang * 27282d375d1SZhi Wang */ 27382d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 27482d375d1SZhi Wang { 27582d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 276a61ac1e7SChris Wilson struct drm_i915_private *i915 = gvt->gt->i915; 27782d375d1SZhi Wang 27812d58619SPankaj Bharadiya drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n"); 279b79c52aeSZhi Wang 28004d6067fSZhenyu Wang /* 28104d6067fSZhenyu Wang * remove idr first so later clean can judge if need to stop 28204d6067fSZhenyu Wang * service if no active vgpu. 28304d6067fSZhenyu Wang */ 28404d6067fSZhenyu Wang mutex_lock(&gvt->lock); 28504d6067fSZhenyu Wang idr_remove(&gvt->vgpu_idr, vgpu->id); 28604d6067fSZhenyu Wang mutex_unlock(&gvt->lock); 28704d6067fSZhenyu Wang 28804d6067fSZhenyu Wang mutex_lock(&vgpu->vgpu_lock); 289bc7b0be3SChangbin Du intel_gvt_debugfs_remove_vgpu(vgpu); 2904b63960eSZhi Wang intel_vgpu_clean_sched_policy(vgpu); 291874b6a91SZhi Wang intel_vgpu_clean_submission(vgpu); 29204d348aeSZhi Wang intel_vgpu_clean_display(vgpu); 2934d60c5fdSZhi Wang intel_vgpu_clean_opregion(vgpu); 2947759ca3aSZhipeng Gong intel_vgpu_reset_ggtt(vgpu, true); 2952707e444SZhi Wang intel_vgpu_clean_gtt(vgpu); 29682d375d1SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 29782d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 298cdcc4347SChangbin Du intel_vgpu_clean_mmio(vgpu); 299e546e281STina Zhang intel_vgpu_dmabuf_cleanup(vgpu); 300f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 30182d375d1SZhi Wang 302f25a49abSColin Xu mutex_lock(&gvt->lock); 303f25a49abSColin Xu if (idr_is_empty(&gvt->vgpu_idr)) 304f25a49abSColin Xu intel_gvt_clean_irq(gvt); 3051f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 30682d375d1SZhi Wang mutex_unlock(&gvt->lock); 307f25a49abSColin Xu 308f25a49abSColin Xu vfree(vgpu); 30982d375d1SZhi Wang } 31082d375d1SZhi Wang 311afe04fbeSPing Gao #define IDLE_VGPU_IDR 0 312afe04fbeSPing Gao 313afe04fbeSPing Gao /** 314afe04fbeSPing Gao * intel_gvt_create_idle_vgpu - create an idle virtual GPU 315afe04fbeSPing Gao * @gvt: GVT device 316afe04fbeSPing Gao * 317afe04fbeSPing Gao * This function is called when user wants to create an idle virtual GPU. 318afe04fbeSPing Gao * 319afe04fbeSPing Gao * Returns: 320afe04fbeSPing Gao * pointer to intel_vgpu, error pointer if failed. 321afe04fbeSPing Gao */ 322afe04fbeSPing Gao struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt) 323afe04fbeSPing Gao { 324afe04fbeSPing Gao struct intel_vgpu *vgpu; 325afe04fbeSPing Gao enum intel_engine_id i; 326afe04fbeSPing Gao int ret; 327afe04fbeSPing Gao 328afe04fbeSPing Gao vgpu = vzalloc(sizeof(*vgpu)); 329afe04fbeSPing Gao if (!vgpu) 330afe04fbeSPing Gao return ERR_PTR(-ENOMEM); 331afe04fbeSPing Gao 332afe04fbeSPing Gao vgpu->id = IDLE_VGPU_IDR; 333afe04fbeSPing Gao vgpu->gvt = gvt; 334f25a49abSColin Xu mutex_init(&vgpu->vgpu_lock); 335afe04fbeSPing Gao 336afe04fbeSPing Gao for (i = 0; i < I915_NUM_ENGINES; i++) 3371406a14bSZhi Wang INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]); 338afe04fbeSPing Gao 339afe04fbeSPing Gao ret = intel_vgpu_init_sched_policy(vgpu); 340afe04fbeSPing Gao if (ret) 341afe04fbeSPing Gao goto out_free_vgpu; 342afe04fbeSPing Gao 343afe04fbeSPing Gao vgpu->active = false; 344afe04fbeSPing Gao 345afe04fbeSPing Gao return vgpu; 346afe04fbeSPing Gao 347afe04fbeSPing Gao out_free_vgpu: 348afe04fbeSPing Gao vfree(vgpu); 349afe04fbeSPing Gao return ERR_PTR(ret); 350afe04fbeSPing Gao } 351afe04fbeSPing Gao 352afe04fbeSPing Gao /** 353afe04fbeSPing Gao * intel_gvt_destroy_vgpu - destroy an idle virtual GPU 354afe04fbeSPing Gao * @vgpu: virtual GPU 355afe04fbeSPing Gao * 356afe04fbeSPing Gao * This function is called when user wants to destroy an idle virtual GPU. 357afe04fbeSPing Gao * 358afe04fbeSPing Gao */ 359afe04fbeSPing Gao void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu) 360afe04fbeSPing Gao { 361f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock); 362afe04fbeSPing Gao intel_vgpu_clean_sched_policy(vgpu); 363f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 364f25a49abSColin Xu 365afe04fbeSPing Gao vfree(vgpu); 366afe04fbeSPing Gao } 367afe04fbeSPing Gao 3681f31c829SZhenyu Wang static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 36982d375d1SZhi Wang struct intel_vgpu_creation_params *param) 37082d375d1SZhi Wang { 37182d375d1SZhi Wang struct intel_vgpu *vgpu; 37282d375d1SZhi Wang int ret; 37382d375d1SZhi Wang 37482d375d1SZhi Wang gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n", 37582d375d1SZhi Wang param->handle, param->low_gm_sz, param->high_gm_sz, 37682d375d1SZhi Wang param->fence_sz); 37782d375d1SZhi Wang 37882d375d1SZhi Wang vgpu = vzalloc(sizeof(*vgpu)); 37982d375d1SZhi Wang if (!vgpu) 38082d375d1SZhi Wang return ERR_PTR(-ENOMEM); 38182d375d1SZhi Wang 382afe04fbeSPing Gao ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU, 383afe04fbeSPing Gao GFP_KERNEL); 38482d375d1SZhi Wang if (ret < 0) 38582d375d1SZhi Wang goto out_free_vgpu; 38682d375d1SZhi Wang 38782d375d1SZhi Wang vgpu->id = ret; 38882d375d1SZhi Wang vgpu->handle = param->handle; 38982d375d1SZhi Wang vgpu->gvt = gvt; 390bc90d097SPing Gao vgpu->sched_ctl.weight = param->weight; 391f25a49abSColin Xu mutex_init(&vgpu->vgpu_lock); 392d6c6113bSHang Yuan mutex_init(&vgpu->dmabuf_lock); 393e546e281STina Zhang INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head); 394e502a2afSChangbin Du INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL); 395e546e281STina Zhang idr_init(&vgpu->object_idr); 396536fc234SChangbin Du intel_vgpu_init_cfg_space(vgpu, param->primary); 397ba25d977SColin Xu vgpu->d3_entered = false; 39882d375d1SZhi Wang 399cdcc4347SChangbin Du ret = intel_vgpu_init_mmio(vgpu); 40082d375d1SZhi Wang if (ret) 4014e537891SJike Song goto out_clean_idr; 40282d375d1SZhi Wang 40382d375d1SZhi Wang ret = intel_vgpu_alloc_resource(vgpu, param); 40482d375d1SZhi Wang if (ret) 40582d375d1SZhi Wang goto out_clean_vgpu_mmio; 40682d375d1SZhi Wang 40782d375d1SZhi Wang populate_pvinfo_page(vgpu); 40882d375d1SZhi Wang 40982d375d1SZhi Wang ret = intel_gvt_hypervisor_attach_vgpu(vgpu); 41082d375d1SZhi Wang if (ret) 41182d375d1SZhi Wang goto out_clean_vgpu_resource; 41282d375d1SZhi Wang 4132707e444SZhi Wang ret = intel_vgpu_init_gtt(vgpu); 4142707e444SZhi Wang if (ret) 4152707e444SZhi Wang goto out_detach_hypervisor_vgpu; 4162707e444SZhi Wang 4174dff110bSXiong Zhang ret = intel_vgpu_init_opregion(vgpu); 41804d348aeSZhi Wang if (ret) 4198f89743bSJike Song goto out_clean_gtt; 42004d348aeSZhi Wang 4214dff110bSXiong Zhang ret = intel_vgpu_init_display(vgpu, param->resolution); 4224dff110bSXiong Zhang if (ret) 4234dff110bSXiong Zhang goto out_clean_opregion; 4244dff110bSXiong Zhang 425ad1d3636SZhi Wang ret = intel_vgpu_setup_submission(vgpu); 4268453d674SZhi Wang if (ret) 4278453d674SZhi Wang goto out_clean_display; 4288453d674SZhi Wang 4294b63960eSZhi Wang ret = intel_vgpu_init_sched_policy(vgpu); 4304b63960eSZhi Wang if (ret) 431ad1d3636SZhi Wang goto out_clean_submission; 4324b63960eSZhi Wang 433f8871ec8SGreg Kroah-Hartman intel_gvt_debugfs_add_vgpu(vgpu); 434bc7b0be3SChangbin Du 435b851adeaSTina Zhang ret = intel_gvt_hypervisor_set_opregion(vgpu); 436b851adeaSTina Zhang if (ret) 437b851adeaSTina Zhang goto out_clean_sched_policy; 438b851adeaSTina Zhang 43939c68e87SHang Yuan ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D); 44039c68e87SHang Yuan if (ret) 44139c68e87SHang Yuan goto out_clean_sched_policy; 44239c68e87SHang Yuan 44382d375d1SZhi Wang return vgpu; 44482d375d1SZhi Wang 445bc7b0be3SChangbin Du out_clean_sched_policy: 446bc7b0be3SChangbin Du intel_vgpu_clean_sched_policy(vgpu); 447ad1d3636SZhi Wang out_clean_submission: 448874b6a91SZhi Wang intel_vgpu_clean_submission(vgpu); 4498453d674SZhi Wang out_clean_display: 4508453d674SZhi Wang intel_vgpu_clean_display(vgpu); 4514dff110bSXiong Zhang out_clean_opregion: 4524dff110bSXiong Zhang intel_vgpu_clean_opregion(vgpu); 4534d60c5fdSZhi Wang out_clean_gtt: 4544d60c5fdSZhi Wang intel_vgpu_clean_gtt(vgpu); 4552707e444SZhi Wang out_detach_hypervisor_vgpu: 4562707e444SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 45782d375d1SZhi Wang out_clean_vgpu_resource: 45882d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 45982d375d1SZhi Wang out_clean_vgpu_mmio: 460cdcc4347SChangbin Du intel_vgpu_clean_mmio(vgpu); 4614e537891SJike Song out_clean_idr: 4624e537891SJike Song idr_remove(&gvt->vgpu_idr, vgpu->id); 46382d375d1SZhi Wang out_free_vgpu: 46482d375d1SZhi Wang vfree(vgpu); 46582d375d1SZhi Wang return ERR_PTR(ret); 46682d375d1SZhi Wang } 4671f31c829SZhenyu Wang 4681f31c829SZhenyu Wang /** 4691f31c829SZhenyu Wang * intel_gvt_create_vgpu - create a virtual GPU 4701f31c829SZhenyu Wang * @gvt: GVT device 4711f31c829SZhenyu Wang * @type: type of the vGPU to create 4721f31c829SZhenyu Wang * 4731f31c829SZhenyu Wang * This function is called when user wants to create a virtual GPU. 4741f31c829SZhenyu Wang * 4751f31c829SZhenyu Wang * Returns: 4761f31c829SZhenyu Wang * pointer to intel_vgpu, error pointer if failed. 4771f31c829SZhenyu Wang */ 4781f31c829SZhenyu Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 4791f31c829SZhenyu Wang struct intel_vgpu_type *type) 4801f31c829SZhenyu Wang { 4811f31c829SZhenyu Wang struct intel_vgpu_creation_params param; 4821f31c829SZhenyu Wang struct intel_vgpu *vgpu; 4831f31c829SZhenyu Wang 4841f31c829SZhenyu Wang param.handle = 0; 485e992faeeSDu, Changbin param.primary = 1; 4861f31c829SZhenyu Wang param.low_gm_sz = type->low_gm_size; 4871f31c829SZhenyu Wang param.high_gm_sz = type->high_gm_size; 4881f31c829SZhenyu Wang param.fence_sz = type->fence; 489bc90d097SPing Gao param.weight = type->weight; 490d1a513beSZhenyu Wang param.resolution = type->resolution; 4911f31c829SZhenyu Wang 4921f31c829SZhenyu Wang /* XXX current param based on MB */ 4931f31c829SZhenyu Wang param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz); 4941f31c829SZhenyu Wang param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz); 4951f31c829SZhenyu Wang 496f25a49abSColin Xu mutex_lock(&gvt->lock); 4971f31c829SZhenyu Wang vgpu = __intel_gvt_create_vgpu(gvt, ¶m); 498f25a49abSColin Xu if (!IS_ERR(vgpu)) 4991f31c829SZhenyu Wang /* calculate left instance change for types */ 5001f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 501f25a49abSColin Xu mutex_unlock(&gvt->lock); 5021f31c829SZhenyu Wang 5031f31c829SZhenyu Wang return vgpu; 5041f31c829SZhenyu Wang } 5059ec1e66bSJike Song 5069ec1e66bSJike Song /** 507cfe65f40SChangbin Du * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset 508cfe65f40SChangbin Du * @vgpu: virtual GPU 509cfe65f40SChangbin Du * @dmlr: vGPU Device Model Level Reset or GT Reset 510cfe65f40SChangbin Du * @engine_mask: engines to reset for GT reset 511cfe65f40SChangbin Du * 512cfe65f40SChangbin Du * This function is called when user wants to reset a virtual GPU through 513f25a49abSColin Xu * device model reset or GT reset. The caller should hold the vgpu lock. 514cfe65f40SChangbin Du * 515cfe65f40SChangbin Du * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset 516cfe65f40SChangbin Du * the whole vGPU to default state as when it is created. This vGPU function 517cfe65f40SChangbin Du * is required both for functionary and security concerns.The ultimate goal 518cfe65f40SChangbin Du * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we 519cfe65f40SChangbin Du * assign a vGPU to a virtual machine we must isse such reset first. 520cfe65f40SChangbin Du * 521cfe65f40SChangbin Du * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines 522cfe65f40SChangbin Du * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec. 523cfe65f40SChangbin Du * Unlike the FLR, GT reset only reset particular resource of a vGPU per 524cfe65f40SChangbin Du * the reset request. Guest driver can issue a GT reset by programming the 525cfe65f40SChangbin Du * virtual GDRST register to reset specific virtual GPU engine or all 526cfe65f40SChangbin Du * engines. 527cfe65f40SChangbin Du * 528cfe65f40SChangbin Du * The parameter dev_level is to identify if we will do DMLR or GT reset. 529cfe65f40SChangbin Du * The parameter engine_mask is to specific the engines that need to be 530cfe65f40SChangbin Du * resetted. If value ALL_ENGINES is given for engine_mask, it means 531cfe65f40SChangbin Du * the caller requests a full GT reset that we will reset all virtual 532cfe65f40SChangbin Du * GPU engines. For FLR, engine_mask is ignored. 533cfe65f40SChangbin Du */ 534cfe65f40SChangbin Du void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 5353a891a62SChris Wilson intel_engine_mask_t engine_mask) 536cfe65f40SChangbin Du { 537cfe65f40SChangbin Du struct intel_gvt *gvt = vgpu->gvt; 538cfe65f40SChangbin Du struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 5393a891a62SChris Wilson intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; 540cfe65f40SChangbin Du 541cfe65f40SChangbin Du gvt_dbg_core("------------------------------------------\n"); 542cfe65f40SChangbin Du gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n", 543cfe65f40SChangbin Du vgpu->id, dmlr, engine_mask); 5446184cc8dSChuanxiao Dong 5456184cc8dSChuanxiao Dong vgpu->resetting_eng = resetting_eng; 546cfe65f40SChangbin Du 547cfe65f40SChangbin Du intel_vgpu_stop_schedule(vgpu); 548cfe65f40SChangbin Du /* 549cfe65f40SChangbin Du * The current_vgpu will set to NULL after stopping the 550cfe65f40SChangbin Du * scheduler when the reset is triggered by current vgpu. 551cfe65f40SChangbin Du */ 552cfe65f40SChangbin Du if (scheduler->current_vgpu == NULL) { 553f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 554cfe65f40SChangbin Du intel_gvt_wait_vgpu_idle(vgpu); 555f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock); 556cfe65f40SChangbin Du } 557cfe65f40SChangbin Du 55806bb372fSZhi Wang intel_vgpu_reset_submission(vgpu, resetting_eng); 559cfe65f40SChangbin Du /* full GPU reset or device model level reset */ 560cfe65f40SChangbin Du if (engine_mask == ALL_ENGINES || dmlr) { 5617569a06dSWeinan Li intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 562ba25d977SColin Xu if (engine_mask == ALL_ENGINES) 563730c8eadSZhi Wang intel_vgpu_invalidate_ppgtt(vgpu); 564615c16a9Sfred gao /*fence will not be reset during virtual reset */ 5654d3e67bbSChuanxiao Dong if (dmlr) { 566ba25d977SColin Xu if(!vgpu->d3_entered) { 567ba25d977SColin Xu intel_vgpu_invalidate_ppgtt(vgpu); 568ba25d977SColin Xu intel_vgpu_destroy_all_ppgtt_mm(vgpu); 569ba25d977SColin Xu } 570ba25d977SColin Xu intel_vgpu_reset_ggtt(vgpu, true); 571cfe65f40SChangbin Du intel_vgpu_reset_resource(vgpu); 5724d3e67bbSChuanxiao Dong } 573615c16a9Sfred gao 574615c16a9Sfred gao intel_vgpu_reset_mmio(vgpu, dmlr); 575cfe65f40SChangbin Du populate_pvinfo_page(vgpu); 576cfe65f40SChangbin Du 577fd64be63SMin He if (dmlr) { 5783eb55e6fSTina Zhang intel_vgpu_reset_display(vgpu); 579cfe65f40SChangbin Du intel_vgpu_reset_cfg_space(vgpu); 580fd64be63SMin He /* only reset the failsafe mode when dmlr reset */ 581fd64be63SMin He vgpu->failsafe = false; 582fd64be63SMin He vgpu->pv_notified = false; 583ba25d977SColin Xu /* 584ba25d977SColin Xu * PCI_D0 is set before dmlr, so reset d3_entered here 585ba25d977SColin Xu * after done using. 586ba25d977SColin Xu */ 587ba25d977SColin Xu if(vgpu->d3_entered) 588ba25d977SColin Xu vgpu->d3_entered = false; 589fd64be63SMin He } 590cfe65f40SChangbin Du } 591cfe65f40SChangbin Du 5926184cc8dSChuanxiao Dong vgpu->resetting_eng = 0; 593cfe65f40SChangbin Du gvt_dbg_core("reset vgpu%d done\n", vgpu->id); 594cfe65f40SChangbin Du gvt_dbg_core("------------------------------------------\n"); 595cfe65f40SChangbin Du } 596cfe65f40SChangbin Du 597cfe65f40SChangbin Du /** 598cfe65f40SChangbin Du * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level) 5999ec1e66bSJike Song * @vgpu: virtual GPU 6009ec1e66bSJike Song * 6019ec1e66bSJike Song * This function is called when user wants to reset a virtual GPU. 6029ec1e66bSJike Song * 6039ec1e66bSJike Song */ 6049ec1e66bSJike Song void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu) 6059ec1e66bSJike Song { 606f25a49abSColin Xu mutex_lock(&vgpu->vgpu_lock); 607cfe65f40SChangbin Du intel_gvt_reset_vgpu_locked(vgpu, true, 0); 608f25a49abSColin Xu mutex_unlock(&vgpu->vgpu_lock); 6099ec1e66bSJike Song } 610