182d375d1SZhi Wang /* 282d375d1SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 382d375d1SZhi Wang * 482d375d1SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 582d375d1SZhi Wang * copy of this software and associated documentation files (the "Software"), 682d375d1SZhi Wang * to deal in the Software without restriction, including without limitation 782d375d1SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 882d375d1SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 982d375d1SZhi Wang * Software is furnished to do so, subject to the following conditions: 1082d375d1SZhi Wang * 1182d375d1SZhi Wang * The above copyright notice and this permission notice (including the next 1282d375d1SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 1382d375d1SZhi Wang * Software. 1482d375d1SZhi Wang * 1582d375d1SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1682d375d1SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1782d375d1SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1882d375d1SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1982d375d1SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2082d375d1SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 2182d375d1SZhi Wang * SOFTWARE. 2282d375d1SZhi Wang * 2382d375d1SZhi Wang * Authors: 2482d375d1SZhi Wang * Eddie Dong <eddie.dong@intel.com> 2582d375d1SZhi Wang * Kevin Tian <kevin.tian@intel.com> 2682d375d1SZhi Wang * 2782d375d1SZhi Wang * Contributors: 2882d375d1SZhi Wang * Ping Gao <ping.a.gao@intel.com> 2982d375d1SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 3082d375d1SZhi Wang * Bing Niu <bing.niu@intel.com> 3182d375d1SZhi Wang * 3282d375d1SZhi Wang */ 3382d375d1SZhi Wang 3482d375d1SZhi Wang #include "i915_drv.h" 35feddf6e8SZhenyu Wang #include "gvt.h" 36feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 3782d375d1SZhi Wang 3882d375d1SZhi Wang static void clean_vgpu_mmio(struct intel_vgpu *vgpu) 3982d375d1SZhi Wang { 4082d375d1SZhi Wang vfree(vgpu->mmio.vreg); 4182d375d1SZhi Wang vgpu->mmio.vreg = vgpu->mmio.sreg = NULL; 4282d375d1SZhi Wang } 4382d375d1SZhi Wang 4423736d1bSPing Gao int setup_vgpu_mmio(struct intel_vgpu *vgpu) 4582d375d1SZhi Wang { 4682d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 4782d375d1SZhi Wang const struct intel_gvt_device_info *info = &gvt->device_info; 4882d375d1SZhi Wang 49f4b0c286SDu, Changbin if (vgpu->mmio.vreg) 50f4b0c286SDu, Changbin memset(vgpu->mmio.vreg, 0, info->mmio_size * 2); 51f4b0c286SDu, Changbin else { 5282d375d1SZhi Wang vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); 5382d375d1SZhi Wang if (!vgpu->mmio.vreg) 5482d375d1SZhi Wang return -ENOMEM; 55f4b0c286SDu, Changbin } 5682d375d1SZhi Wang 5782d375d1SZhi Wang vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size; 5882d375d1SZhi Wang 5982d375d1SZhi Wang memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size); 6082d375d1SZhi Wang memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size); 61e39c5addSZhi Wang 62e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 63e39c5addSZhi Wang 64e39c5addSZhi Wang /* set the bit 0:2(Core C-State ) to C0 */ 65e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0; 6682d375d1SZhi Wang return 0; 6782d375d1SZhi Wang } 6882d375d1SZhi Wang 6923736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu) 7082d375d1SZhi Wang { 7182d375d1SZhi Wang /* setup the ballooning information */ 7282d375d1SZhi Wang vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 7382d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1; 7482d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; 7582d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; 7682d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 7782d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 7882d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu); 7982d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 8082d375d1SZhi Wang vgpu_aperture_sz(vgpu); 8182d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 8282d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu); 8382d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 8482d375d1SZhi Wang vgpu_hidden_sz(vgpu); 8582d375d1SZhi Wang 8682d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 8782d375d1SZhi Wang 8882d375d1SZhi Wang gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 8982d375d1SZhi Wang gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 9082d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); 9182d375d1SZhi Wang gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", 9282d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); 9382d375d1SZhi Wang gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); 9482d375d1SZhi Wang 9582d375d1SZhi Wang WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 9682d375d1SZhi Wang } 9782d375d1SZhi Wang 9882d375d1SZhi Wang /** 991f31c829SZhenyu Wang * intel_gvt_init_vgpu_types - initialize vGPU type list 1001f31c829SZhenyu Wang * @gvt : GVT device 1011f31c829SZhenyu Wang * 1021f31c829SZhenyu Wang * Initialize vGPU type list based on available resource. 1031f31c829SZhenyu Wang * 1041f31c829SZhenyu Wang */ 1051f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) 1061f31c829SZhenyu Wang { 1071f31c829SZhenyu Wang unsigned int num_types; 1081f31c829SZhenyu Wang unsigned int i, low_avail; 1091f31c829SZhenyu Wang unsigned int min_low; 1101f31c829SZhenyu Wang 1111f31c829SZhenyu Wang /* vGPU type name is defined as GVTg_Vx_y which contains 1121f31c829SZhenyu Wang * physical GPU generation type and 'y' means maximum vGPU 1131f31c829SZhenyu Wang * instances user can create on one physical GPU for this 1141f31c829SZhenyu Wang * type. 1151f31c829SZhenyu Wang * 1161f31c829SZhenyu Wang * Depend on physical SKU resource, might see vGPU types like 1171f31c829SZhenyu Wang * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create 1181f31c829SZhenyu Wang * different types of vGPU on same physical GPU depending on 1191f31c829SZhenyu Wang * available resource. Each vGPU type will have "avail_instance" 1201f31c829SZhenyu Wang * to indicate how many vGPU instance can be created for this 1211f31c829SZhenyu Wang * type. 1221f31c829SZhenyu Wang * 1231f31c829SZhenyu Wang * Currently use static size here as we init type earlier.. 1241f31c829SZhenyu Wang */ 1251f31c829SZhenyu Wang low_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE; 1261f31c829SZhenyu Wang num_types = 4; 1271f31c829SZhenyu Wang 1281f31c829SZhenyu Wang gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type), 1291f31c829SZhenyu Wang GFP_KERNEL); 1301f31c829SZhenyu Wang if (!gvt->types) 1311f31c829SZhenyu Wang return -ENOMEM; 1321f31c829SZhenyu Wang 1331f31c829SZhenyu Wang min_low = MB_TO_BYTES(32); 1341f31c829SZhenyu Wang for (i = 0; i < num_types; ++i) { 1351f31c829SZhenyu Wang if (low_avail / min_low == 0) 1361f31c829SZhenyu Wang break; 1371f31c829SZhenyu Wang gvt->types[i].low_gm_size = min_low; 138888530b5SZhenyu Wang gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U)); 1391f31c829SZhenyu Wang gvt->types[i].fence = 4; 1401f31c829SZhenyu Wang gvt->types[i].max_instance = low_avail / min_low; 1411f31c829SZhenyu Wang gvt->types[i].avail_instance = gvt->types[i].max_instance; 1421f31c829SZhenyu Wang 1431f31c829SZhenyu Wang if (IS_GEN8(gvt->dev_priv)) 1441f31c829SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V4_%u", 1451f31c829SZhenyu Wang gvt->types[i].max_instance); 1461f31c829SZhenyu Wang else if (IS_GEN9(gvt->dev_priv)) 1471f31c829SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V5_%u", 1481f31c829SZhenyu Wang gvt->types[i].max_instance); 1491f31c829SZhenyu Wang 1501f31c829SZhenyu Wang min_low <<= 1; 1511f31c829SZhenyu Wang gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n", 1521f31c829SZhenyu Wang i, gvt->types[i].name, gvt->types[i].max_instance, 1531f31c829SZhenyu Wang gvt->types[i].avail_instance, 1541f31c829SZhenyu Wang gvt->types[i].low_gm_size, 1551f31c829SZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence); 1561f31c829SZhenyu Wang } 1571f31c829SZhenyu Wang 1581f31c829SZhenyu Wang gvt->num_types = i; 1591f31c829SZhenyu Wang return 0; 1601f31c829SZhenyu Wang } 1611f31c829SZhenyu Wang 1621f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) 1631f31c829SZhenyu Wang { 1641f31c829SZhenyu Wang kfree(gvt->types); 1651f31c829SZhenyu Wang } 1661f31c829SZhenyu Wang 1671f31c829SZhenyu Wang static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt) 1681f31c829SZhenyu Wang { 1691f31c829SZhenyu Wang int i; 1701f31c829SZhenyu Wang unsigned int low_gm_avail, high_gm_avail, fence_avail; 1711f31c829SZhenyu Wang unsigned int low_gm_min, high_gm_min, fence_min, total_min; 1721f31c829SZhenyu Wang 1731f31c829SZhenyu Wang /* Need to depend on maxium hw resource size but keep on 1741f31c829SZhenyu Wang * static config for now. 1751f31c829SZhenyu Wang */ 1761f31c829SZhenyu Wang low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE - 1771f31c829SZhenyu Wang gvt->gm.vgpu_allocated_low_gm_size; 178888530b5SZhenyu Wang high_gm_avail = MB_TO_BYTES(256) * 8UL - HOST_HIGH_GM_SIZE - 1791f31c829SZhenyu Wang gvt->gm.vgpu_allocated_high_gm_size; 1801f31c829SZhenyu Wang fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 1811f31c829SZhenyu Wang gvt->fence.vgpu_allocated_fence_num; 1821f31c829SZhenyu Wang 1831f31c829SZhenyu Wang for (i = 0; i < gvt->num_types; i++) { 1841f31c829SZhenyu Wang low_gm_min = low_gm_avail / gvt->types[i].low_gm_size; 1851f31c829SZhenyu Wang high_gm_min = high_gm_avail / gvt->types[i].high_gm_size; 1861f31c829SZhenyu Wang fence_min = fence_avail / gvt->types[i].fence; 1871f31c829SZhenyu Wang total_min = min(min(low_gm_min, high_gm_min), fence_min); 1881f31c829SZhenyu Wang gvt->types[i].avail_instance = min(gvt->types[i].max_instance, 1891f31c829SZhenyu Wang total_min); 1901f31c829SZhenyu Wang 1911f31c829SZhenyu Wang gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n", 1921f31c829SZhenyu Wang i, gvt->types[i].name, gvt->types[i].max_instance, 1931f31c829SZhenyu Wang gvt->types[i].avail_instance, gvt->types[i].low_gm_size, 1941f31c829SZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence); 1951f31c829SZhenyu Wang } 1961f31c829SZhenyu Wang } 1971f31c829SZhenyu Wang 1981f31c829SZhenyu Wang /** 19982d375d1SZhi Wang * intel_gvt_destroy_vgpu - destroy a virtual GPU 20082d375d1SZhi Wang * @vgpu: virtual GPU 20182d375d1SZhi Wang * 20282d375d1SZhi Wang * This function is called when user wants to destroy a virtual GPU. 20382d375d1SZhi Wang * 20482d375d1SZhi Wang */ 20582d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 20682d375d1SZhi Wang { 20782d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 20882d375d1SZhi Wang 20982d375d1SZhi Wang mutex_lock(&gvt->lock); 21082d375d1SZhi Wang 21182d375d1SZhi Wang vgpu->active = false; 21282d375d1SZhi Wang idr_remove(&gvt->vgpu_idr, vgpu->id); 21382d375d1SZhi Wang 2144b63960eSZhi Wang if (atomic_read(&vgpu->running_workload_num)) { 2154b63960eSZhi Wang mutex_unlock(&gvt->lock); 2164b63960eSZhi Wang intel_gvt_wait_vgpu_idle(vgpu); 2174b63960eSZhi Wang mutex_lock(&gvt->lock); 2184b63960eSZhi Wang } 2194b63960eSZhi Wang 2204b63960eSZhi Wang intel_vgpu_stop_schedule(vgpu); 2214b63960eSZhi Wang intel_vgpu_clean_sched_policy(vgpu); 222e4734057SZhi Wang intel_vgpu_clean_gvt_context(vgpu); 22328c4c6caSZhi Wang intel_vgpu_clean_execlist(vgpu); 22404d348aeSZhi Wang intel_vgpu_clean_display(vgpu); 2254d60c5fdSZhi Wang intel_vgpu_clean_opregion(vgpu); 2262707e444SZhi Wang intel_vgpu_clean_gtt(vgpu); 22782d375d1SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 22882d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 22982d375d1SZhi Wang clean_vgpu_mmio(vgpu); 23082d375d1SZhi Wang vfree(vgpu); 23182d375d1SZhi Wang 2321f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 23382d375d1SZhi Wang mutex_unlock(&gvt->lock); 23482d375d1SZhi Wang } 23582d375d1SZhi Wang 2361f31c829SZhenyu Wang static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 23782d375d1SZhi Wang struct intel_vgpu_creation_params *param) 23882d375d1SZhi Wang { 23982d375d1SZhi Wang struct intel_vgpu *vgpu; 24082d375d1SZhi Wang int ret; 24182d375d1SZhi Wang 24282d375d1SZhi Wang gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n", 24382d375d1SZhi Wang param->handle, param->low_gm_sz, param->high_gm_sz, 24482d375d1SZhi Wang param->fence_sz); 24582d375d1SZhi Wang 24682d375d1SZhi Wang vgpu = vzalloc(sizeof(*vgpu)); 24782d375d1SZhi Wang if (!vgpu) 24882d375d1SZhi Wang return ERR_PTR(-ENOMEM); 24982d375d1SZhi Wang 25082d375d1SZhi Wang mutex_lock(&gvt->lock); 25182d375d1SZhi Wang 25282d375d1SZhi Wang ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL); 25382d375d1SZhi Wang if (ret < 0) 25482d375d1SZhi Wang goto out_free_vgpu; 25582d375d1SZhi Wang 25682d375d1SZhi Wang vgpu->id = ret; 25782d375d1SZhi Wang vgpu->handle = param->handle; 25882d375d1SZhi Wang vgpu->gvt = gvt; 25917865713SZhi Wang bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES); 26082d375d1SZhi Wang 261536fc234SChangbin Du intel_vgpu_init_cfg_space(vgpu, param->primary); 26282d375d1SZhi Wang 26382d375d1SZhi Wang ret = setup_vgpu_mmio(vgpu); 26482d375d1SZhi Wang if (ret) 2654e537891SJike Song goto out_clean_idr; 26682d375d1SZhi Wang 26782d375d1SZhi Wang ret = intel_vgpu_alloc_resource(vgpu, param); 26882d375d1SZhi Wang if (ret) 26982d375d1SZhi Wang goto out_clean_vgpu_mmio; 27082d375d1SZhi Wang 27182d375d1SZhi Wang populate_pvinfo_page(vgpu); 27282d375d1SZhi Wang 27382d375d1SZhi Wang ret = intel_gvt_hypervisor_attach_vgpu(vgpu); 27482d375d1SZhi Wang if (ret) 27582d375d1SZhi Wang goto out_clean_vgpu_resource; 27682d375d1SZhi Wang 2772707e444SZhi Wang ret = intel_vgpu_init_gtt(vgpu); 2782707e444SZhi Wang if (ret) 2792707e444SZhi Wang goto out_detach_hypervisor_vgpu; 2802707e444SZhi Wang 28104d348aeSZhi Wang ret = intel_vgpu_init_display(vgpu); 28204d348aeSZhi Wang if (ret) 2838f89743bSJike Song goto out_clean_gtt; 28404d348aeSZhi Wang 2858453d674SZhi Wang ret = intel_vgpu_init_execlist(vgpu); 2868453d674SZhi Wang if (ret) 2878453d674SZhi Wang goto out_clean_display; 2888453d674SZhi Wang 289e4734057SZhi Wang ret = intel_vgpu_init_gvt_context(vgpu); 290e4734057SZhi Wang if (ret) 291e4734057SZhi Wang goto out_clean_execlist; 292e4734057SZhi Wang 2934b63960eSZhi Wang ret = intel_vgpu_init_sched_policy(vgpu); 2944b63960eSZhi Wang if (ret) 2954b63960eSZhi Wang goto out_clean_shadow_ctx; 2964b63960eSZhi Wang 29782d375d1SZhi Wang vgpu->active = true; 29882d375d1SZhi Wang mutex_unlock(&gvt->lock); 29982d375d1SZhi Wang 30082d375d1SZhi Wang return vgpu; 30182d375d1SZhi Wang 3024b63960eSZhi Wang out_clean_shadow_ctx: 3034b63960eSZhi Wang intel_vgpu_clean_gvt_context(vgpu); 304e4734057SZhi Wang out_clean_execlist: 305e4734057SZhi Wang intel_vgpu_clean_execlist(vgpu); 3068453d674SZhi Wang out_clean_display: 3078453d674SZhi Wang intel_vgpu_clean_display(vgpu); 3084d60c5fdSZhi Wang out_clean_gtt: 3094d60c5fdSZhi Wang intel_vgpu_clean_gtt(vgpu); 3102707e444SZhi Wang out_detach_hypervisor_vgpu: 3112707e444SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 31282d375d1SZhi Wang out_clean_vgpu_resource: 31382d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 31482d375d1SZhi Wang out_clean_vgpu_mmio: 31582d375d1SZhi Wang clean_vgpu_mmio(vgpu); 3164e537891SJike Song out_clean_idr: 3174e537891SJike Song idr_remove(&gvt->vgpu_idr, vgpu->id); 31882d375d1SZhi Wang out_free_vgpu: 31982d375d1SZhi Wang vfree(vgpu); 32082d375d1SZhi Wang mutex_unlock(&gvt->lock); 32182d375d1SZhi Wang return ERR_PTR(ret); 32282d375d1SZhi Wang } 3231f31c829SZhenyu Wang 3241f31c829SZhenyu Wang /** 3251f31c829SZhenyu Wang * intel_gvt_create_vgpu - create a virtual GPU 3261f31c829SZhenyu Wang * @gvt: GVT device 3271f31c829SZhenyu Wang * @type: type of the vGPU to create 3281f31c829SZhenyu Wang * 3291f31c829SZhenyu Wang * This function is called when user wants to create a virtual GPU. 3301f31c829SZhenyu Wang * 3311f31c829SZhenyu Wang * Returns: 3321f31c829SZhenyu Wang * pointer to intel_vgpu, error pointer if failed. 3331f31c829SZhenyu Wang */ 3341f31c829SZhenyu Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 3351f31c829SZhenyu Wang struct intel_vgpu_type *type) 3361f31c829SZhenyu Wang { 3371f31c829SZhenyu Wang struct intel_vgpu_creation_params param; 3381f31c829SZhenyu Wang struct intel_vgpu *vgpu; 3391f31c829SZhenyu Wang 3401f31c829SZhenyu Wang param.handle = 0; 341e992faeeSDu, Changbin param.primary = 1; 3421f31c829SZhenyu Wang param.low_gm_sz = type->low_gm_size; 3431f31c829SZhenyu Wang param.high_gm_sz = type->high_gm_size; 3441f31c829SZhenyu Wang param.fence_sz = type->fence; 3451f31c829SZhenyu Wang 3461f31c829SZhenyu Wang /* XXX current param based on MB */ 3471f31c829SZhenyu Wang param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz); 3481f31c829SZhenyu Wang param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz); 3491f31c829SZhenyu Wang 3501f31c829SZhenyu Wang vgpu = __intel_gvt_create_vgpu(gvt, ¶m); 3511f31c829SZhenyu Wang if (IS_ERR(vgpu)) 3521f31c829SZhenyu Wang return vgpu; 3531f31c829SZhenyu Wang 3541f31c829SZhenyu Wang /* calculate left instance change for types */ 3551f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 3561f31c829SZhenyu Wang 3571f31c829SZhenyu Wang return vgpu; 3581f31c829SZhenyu Wang } 3599ec1e66bSJike Song 3609ec1e66bSJike Song /** 3619ec1e66bSJike Song * intel_gvt_reset_vgpu - reset a virtual GPU 3629ec1e66bSJike Song * @vgpu: virtual GPU 3639ec1e66bSJike Song * 3649ec1e66bSJike Song * This function is called when user wants to reset a virtual GPU. 3659ec1e66bSJike Song * 3669ec1e66bSJike Song */ 3679ec1e66bSJike Song void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu) 3689ec1e66bSJike Song { 3699ec1e66bSJike Song } 370