182d375d1SZhi Wang /* 282d375d1SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 382d375d1SZhi Wang * 482d375d1SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 582d375d1SZhi Wang * copy of this software and associated documentation files (the "Software"), 682d375d1SZhi Wang * to deal in the Software without restriction, including without limitation 782d375d1SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 882d375d1SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 982d375d1SZhi Wang * Software is furnished to do so, subject to the following conditions: 1082d375d1SZhi Wang * 1182d375d1SZhi Wang * The above copyright notice and this permission notice (including the next 1282d375d1SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 1382d375d1SZhi Wang * Software. 1482d375d1SZhi Wang * 1582d375d1SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1682d375d1SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1782d375d1SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1882d375d1SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1982d375d1SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2082d375d1SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 2182d375d1SZhi Wang * SOFTWARE. 2282d375d1SZhi Wang * 2382d375d1SZhi Wang * Authors: 2482d375d1SZhi Wang * Eddie Dong <eddie.dong@intel.com> 2582d375d1SZhi Wang * Kevin Tian <kevin.tian@intel.com> 2682d375d1SZhi Wang * 2782d375d1SZhi Wang * Contributors: 2882d375d1SZhi Wang * Ping Gao <ping.a.gao@intel.com> 2982d375d1SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 3082d375d1SZhi Wang * Bing Niu <bing.niu@intel.com> 3182d375d1SZhi Wang * 3282d375d1SZhi Wang */ 3382d375d1SZhi Wang 3482d375d1SZhi Wang #include "i915_drv.h" 3582d375d1SZhi Wang 3682d375d1SZhi Wang static void clean_vgpu_mmio(struct intel_vgpu *vgpu) 3782d375d1SZhi Wang { 3882d375d1SZhi Wang vfree(vgpu->mmio.vreg); 3982d375d1SZhi Wang vgpu->mmio.vreg = vgpu->mmio.sreg = NULL; 4082d375d1SZhi Wang } 4182d375d1SZhi Wang 4282d375d1SZhi Wang static int setup_vgpu_mmio(struct intel_vgpu *vgpu) 4382d375d1SZhi Wang { 4482d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 4582d375d1SZhi Wang const struct intel_gvt_device_info *info = &gvt->device_info; 4682d375d1SZhi Wang 4782d375d1SZhi Wang vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); 4882d375d1SZhi Wang if (!vgpu->mmio.vreg) 4982d375d1SZhi Wang return -ENOMEM; 5082d375d1SZhi Wang 5182d375d1SZhi Wang vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size; 5282d375d1SZhi Wang 5382d375d1SZhi Wang memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size); 5482d375d1SZhi Wang memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size); 55e39c5addSZhi Wang 56e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 57e39c5addSZhi Wang 58e39c5addSZhi Wang /* set the bit 0:2(Core C-State ) to C0 */ 59e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0; 6082d375d1SZhi Wang return 0; 6182d375d1SZhi Wang } 6282d375d1SZhi Wang 6382d375d1SZhi Wang static void setup_vgpu_cfg_space(struct intel_vgpu *vgpu, 6482d375d1SZhi Wang struct intel_vgpu_creation_params *param) 6582d375d1SZhi Wang { 6682d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 6782d375d1SZhi Wang const struct intel_gvt_device_info *info = &gvt->device_info; 6882d375d1SZhi Wang u16 *gmch_ctl; 6982d375d1SZhi Wang int i; 7082d375d1SZhi Wang 7182d375d1SZhi Wang memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 7282d375d1SZhi Wang info->cfg_space_size); 7382d375d1SZhi Wang 7482d375d1SZhi Wang if (!param->primary) { 7582d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 7682d375d1SZhi Wang INTEL_GVT_PCI_CLASS_VGA_OTHER; 7782d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 7882d375d1SZhi Wang INTEL_GVT_PCI_CLASS_VGA_OTHER; 7982d375d1SZhi Wang } 8082d375d1SZhi Wang 8182d375d1SZhi Wang /* Show guest that there isn't any stolen memory.*/ 8282d375d1SZhi Wang gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 8382d375d1SZhi Wang *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 8482d375d1SZhi Wang 8582d375d1SZhi Wang intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 8682d375d1SZhi Wang gvt_aperture_pa_base(gvt), true); 8782d375d1SZhi Wang 8882d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 8982d375d1SZhi Wang | PCI_COMMAND_MEMORY 9082d375d1SZhi Wang | PCI_COMMAND_MASTER); 9182d375d1SZhi Wang /* 9282d375d1SZhi Wang * Clear the bar upper 32bit and let guest to assign the new value 9382d375d1SZhi Wang */ 9482d375d1SZhi Wang memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 9582d375d1SZhi Wang memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 9682d375d1SZhi Wang 9782d375d1SZhi Wang for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) { 9882d375d1SZhi Wang vgpu->cfg_space.bar[i].size = pci_resource_len( 9982d375d1SZhi Wang gvt->dev_priv->drm.pdev, i * 2); 10082d375d1SZhi Wang vgpu->cfg_space.bar[i].tracked = false; 10182d375d1SZhi Wang } 10282d375d1SZhi Wang } 10382d375d1SZhi Wang 10482d375d1SZhi Wang static void populate_pvinfo_page(struct intel_vgpu *vgpu) 10582d375d1SZhi Wang { 10682d375d1SZhi Wang /* setup the ballooning information */ 10782d375d1SZhi Wang vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 10882d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1; 10982d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; 11082d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; 11182d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 11282d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 11382d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu); 11482d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 11582d375d1SZhi Wang vgpu_aperture_sz(vgpu); 11682d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 11782d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu); 11882d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 11982d375d1SZhi Wang vgpu_hidden_sz(vgpu); 12082d375d1SZhi Wang 12182d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 12282d375d1SZhi Wang 12382d375d1SZhi Wang gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 12482d375d1SZhi Wang gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 12582d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); 12682d375d1SZhi Wang gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", 12782d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); 12882d375d1SZhi Wang gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); 12982d375d1SZhi Wang 13082d375d1SZhi Wang WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 13182d375d1SZhi Wang } 13282d375d1SZhi Wang 13382d375d1SZhi Wang /** 13482d375d1SZhi Wang * intel_gvt_destroy_vgpu - destroy a virtual GPU 13582d375d1SZhi Wang * @vgpu: virtual GPU 13682d375d1SZhi Wang * 13782d375d1SZhi Wang * This function is called when user wants to destroy a virtual GPU. 13882d375d1SZhi Wang * 13982d375d1SZhi Wang */ 14082d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 14182d375d1SZhi Wang { 14282d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 14382d375d1SZhi Wang 14482d375d1SZhi Wang mutex_lock(&gvt->lock); 14582d375d1SZhi Wang 14682d375d1SZhi Wang vgpu->active = false; 14782d375d1SZhi Wang idr_remove(&gvt->vgpu_idr, vgpu->id); 14882d375d1SZhi Wang 1494b63960eSZhi Wang if (atomic_read(&vgpu->running_workload_num)) { 1504b63960eSZhi Wang mutex_unlock(&gvt->lock); 1514b63960eSZhi Wang intel_gvt_wait_vgpu_idle(vgpu); 1524b63960eSZhi Wang mutex_lock(&gvt->lock); 1534b63960eSZhi Wang } 1544b63960eSZhi Wang 1554b63960eSZhi Wang intel_vgpu_stop_schedule(vgpu); 1564b63960eSZhi Wang intel_vgpu_clean_sched_policy(vgpu); 157e4734057SZhi Wang intel_vgpu_clean_gvt_context(vgpu); 15828c4c6caSZhi Wang intel_vgpu_clean_execlist(vgpu); 15904d348aeSZhi Wang intel_vgpu_clean_display(vgpu); 1604d60c5fdSZhi Wang intel_vgpu_clean_opregion(vgpu); 1612707e444SZhi Wang intel_vgpu_clean_gtt(vgpu); 16282d375d1SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 16382d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 16482d375d1SZhi Wang clean_vgpu_mmio(vgpu); 16582d375d1SZhi Wang vfree(vgpu); 16682d375d1SZhi Wang 16782d375d1SZhi Wang mutex_unlock(&gvt->lock); 16882d375d1SZhi Wang } 16982d375d1SZhi Wang 17082d375d1SZhi Wang /** 17182d375d1SZhi Wang * intel_gvt_create_vgpu - create a virtual GPU 17282d375d1SZhi Wang * @gvt: GVT device 17382d375d1SZhi Wang * @param: vGPU creation parameters 17482d375d1SZhi Wang * 17582d375d1SZhi Wang * This function is called when user wants to create a virtual GPU. 17682d375d1SZhi Wang * 17782d375d1SZhi Wang * Returns: 17882d375d1SZhi Wang * pointer to intel_vgpu, error pointer if failed. 17982d375d1SZhi Wang */ 18082d375d1SZhi Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 18182d375d1SZhi Wang struct intel_vgpu_creation_params *param) 18282d375d1SZhi Wang { 18382d375d1SZhi Wang struct intel_vgpu *vgpu; 18482d375d1SZhi Wang int ret; 18582d375d1SZhi Wang 18682d375d1SZhi Wang gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n", 18782d375d1SZhi Wang param->handle, param->low_gm_sz, param->high_gm_sz, 18882d375d1SZhi Wang param->fence_sz); 18982d375d1SZhi Wang 19082d375d1SZhi Wang vgpu = vzalloc(sizeof(*vgpu)); 19182d375d1SZhi Wang if (!vgpu) 19282d375d1SZhi Wang return ERR_PTR(-ENOMEM); 19382d375d1SZhi Wang 19482d375d1SZhi Wang mutex_lock(&gvt->lock); 19582d375d1SZhi Wang 19682d375d1SZhi Wang ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL); 19782d375d1SZhi Wang if (ret < 0) 19882d375d1SZhi Wang goto out_free_vgpu; 19982d375d1SZhi Wang 20082d375d1SZhi Wang vgpu->id = ret; 20182d375d1SZhi Wang vgpu->handle = param->handle; 20282d375d1SZhi Wang vgpu->gvt = gvt; 20382d375d1SZhi Wang 20482d375d1SZhi Wang setup_vgpu_cfg_space(vgpu, param); 20582d375d1SZhi Wang 20682d375d1SZhi Wang ret = setup_vgpu_mmio(vgpu); 20782d375d1SZhi Wang if (ret) 20882d375d1SZhi Wang goto out_free_vgpu; 20982d375d1SZhi Wang 21082d375d1SZhi Wang ret = intel_vgpu_alloc_resource(vgpu, param); 21182d375d1SZhi Wang if (ret) 21282d375d1SZhi Wang goto out_clean_vgpu_mmio; 21382d375d1SZhi Wang 21482d375d1SZhi Wang populate_pvinfo_page(vgpu); 21582d375d1SZhi Wang 21682d375d1SZhi Wang ret = intel_gvt_hypervisor_attach_vgpu(vgpu); 21782d375d1SZhi Wang if (ret) 21882d375d1SZhi Wang goto out_clean_vgpu_resource; 21982d375d1SZhi Wang 2202707e444SZhi Wang ret = intel_vgpu_init_gtt(vgpu); 2212707e444SZhi Wang if (ret) 2222707e444SZhi Wang goto out_detach_hypervisor_vgpu; 2232707e444SZhi Wang 2244d60c5fdSZhi Wang if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { 2254d60c5fdSZhi Wang ret = intel_vgpu_init_opregion(vgpu, 0); 2264d60c5fdSZhi Wang if (ret) 2274d60c5fdSZhi Wang goto out_clean_gtt; 2284d60c5fdSZhi Wang } 2294d60c5fdSZhi Wang 23004d348aeSZhi Wang ret = intel_vgpu_init_display(vgpu); 23104d348aeSZhi Wang if (ret) 23204d348aeSZhi Wang goto out_clean_opregion; 23304d348aeSZhi Wang 2348453d674SZhi Wang ret = intel_vgpu_init_execlist(vgpu); 2358453d674SZhi Wang if (ret) 2368453d674SZhi Wang goto out_clean_display; 2378453d674SZhi Wang 238e4734057SZhi Wang ret = intel_vgpu_init_gvt_context(vgpu); 239e4734057SZhi Wang if (ret) 240e4734057SZhi Wang goto out_clean_execlist; 241e4734057SZhi Wang 2424b63960eSZhi Wang ret = intel_vgpu_init_sched_policy(vgpu); 2434b63960eSZhi Wang if (ret) 2444b63960eSZhi Wang goto out_clean_shadow_ctx; 2454b63960eSZhi Wang 24682d375d1SZhi Wang vgpu->active = true; 24782d375d1SZhi Wang mutex_unlock(&gvt->lock); 24882d375d1SZhi Wang 24982d375d1SZhi Wang return vgpu; 25082d375d1SZhi Wang 2514b63960eSZhi Wang out_clean_shadow_ctx: 2524b63960eSZhi Wang intel_vgpu_clean_gvt_context(vgpu); 253e4734057SZhi Wang out_clean_execlist: 254e4734057SZhi Wang intel_vgpu_clean_execlist(vgpu); 2558453d674SZhi Wang out_clean_display: 2568453d674SZhi Wang intel_vgpu_clean_display(vgpu); 25704d348aeSZhi Wang out_clean_opregion: 25804d348aeSZhi Wang intel_vgpu_clean_opregion(vgpu); 2594d60c5fdSZhi Wang out_clean_gtt: 2604d60c5fdSZhi Wang intel_vgpu_clean_gtt(vgpu); 2612707e444SZhi Wang out_detach_hypervisor_vgpu: 2622707e444SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 26382d375d1SZhi Wang out_clean_vgpu_resource: 26482d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 26582d375d1SZhi Wang out_clean_vgpu_mmio: 26682d375d1SZhi Wang clean_vgpu_mmio(vgpu); 26782d375d1SZhi Wang out_free_vgpu: 26882d375d1SZhi Wang vfree(vgpu); 26982d375d1SZhi Wang mutex_unlock(&gvt->lock); 27082d375d1SZhi Wang return ERR_PTR(ret); 27182d375d1SZhi Wang } 272