182d375d1SZhi Wang /* 282d375d1SZhi Wang * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 382d375d1SZhi Wang * 482d375d1SZhi Wang * Permission is hereby granted, free of charge, to any person obtaining a 582d375d1SZhi Wang * copy of this software and associated documentation files (the "Software"), 682d375d1SZhi Wang * to deal in the Software without restriction, including without limitation 782d375d1SZhi Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense, 882d375d1SZhi Wang * and/or sell copies of the Software, and to permit persons to whom the 982d375d1SZhi Wang * Software is furnished to do so, subject to the following conditions: 1082d375d1SZhi Wang * 1182d375d1SZhi Wang * The above copyright notice and this permission notice (including the next 1282d375d1SZhi Wang * paragraph) shall be included in all copies or substantial portions of the 1382d375d1SZhi Wang * Software. 1482d375d1SZhi Wang * 1582d375d1SZhi Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1682d375d1SZhi Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1782d375d1SZhi Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1882d375d1SZhi Wang * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1982d375d1SZhi Wang * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 2082d375d1SZhi Wang * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 2182d375d1SZhi Wang * SOFTWARE. 2282d375d1SZhi Wang * 2382d375d1SZhi Wang * Authors: 2482d375d1SZhi Wang * Eddie Dong <eddie.dong@intel.com> 2582d375d1SZhi Wang * Kevin Tian <kevin.tian@intel.com> 2682d375d1SZhi Wang * 2782d375d1SZhi Wang * Contributors: 2882d375d1SZhi Wang * Ping Gao <ping.a.gao@intel.com> 2982d375d1SZhi Wang * Zhi Wang <zhi.a.wang@intel.com> 3082d375d1SZhi Wang * Bing Niu <bing.niu@intel.com> 3182d375d1SZhi Wang * 3282d375d1SZhi Wang */ 3382d375d1SZhi Wang 3482d375d1SZhi Wang #include "i915_drv.h" 35feddf6e8SZhenyu Wang #include "gvt.h" 36feddf6e8SZhenyu Wang #include "i915_pvinfo.h" 3782d375d1SZhi Wang 3882d375d1SZhi Wang static void clean_vgpu_mmio(struct intel_vgpu *vgpu) 3982d375d1SZhi Wang { 4082d375d1SZhi Wang vfree(vgpu->mmio.vreg); 4182d375d1SZhi Wang vgpu->mmio.vreg = vgpu->mmio.sreg = NULL; 4282d375d1SZhi Wang } 4382d375d1SZhi Wang 4423736d1bSPing Gao int setup_vgpu_mmio(struct intel_vgpu *vgpu) 4582d375d1SZhi Wang { 4682d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 4782d375d1SZhi Wang const struct intel_gvt_device_info *info = &gvt->device_info; 4882d375d1SZhi Wang 4982d375d1SZhi Wang vgpu->mmio.vreg = vzalloc(info->mmio_size * 2); 5082d375d1SZhi Wang if (!vgpu->mmio.vreg) 5182d375d1SZhi Wang return -ENOMEM; 5282d375d1SZhi Wang 5382d375d1SZhi Wang vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size; 5482d375d1SZhi Wang 5582d375d1SZhi Wang memcpy(vgpu->mmio.vreg, gvt->firmware.mmio, info->mmio_size); 5682d375d1SZhi Wang memcpy(vgpu->mmio.sreg, gvt->firmware.mmio, info->mmio_size); 57e39c5addSZhi Wang 58e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; 59e39c5addSZhi Wang 60e39c5addSZhi Wang /* set the bit 0:2(Core C-State ) to C0 */ 61e39c5addSZhi Wang vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0; 6282d375d1SZhi Wang return 0; 6382d375d1SZhi Wang } 6482d375d1SZhi Wang 6582d375d1SZhi Wang static void setup_vgpu_cfg_space(struct intel_vgpu *vgpu, 6682d375d1SZhi Wang struct intel_vgpu_creation_params *param) 6782d375d1SZhi Wang { 6882d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 6982d375d1SZhi Wang const struct intel_gvt_device_info *info = &gvt->device_info; 7082d375d1SZhi Wang u16 *gmch_ctl; 7182d375d1SZhi Wang int i; 7282d375d1SZhi Wang 7382d375d1SZhi Wang memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space, 7482d375d1SZhi Wang info->cfg_space_size); 7582d375d1SZhi Wang 7682d375d1SZhi Wang if (!param->primary) { 7782d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] = 7882d375d1SZhi Wang INTEL_GVT_PCI_CLASS_VGA_OTHER; 7982d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] = 8082d375d1SZhi Wang INTEL_GVT_PCI_CLASS_VGA_OTHER; 8182d375d1SZhi Wang } 8282d375d1SZhi Wang 8382d375d1SZhi Wang /* Show guest that there isn't any stolen memory.*/ 8482d375d1SZhi Wang gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL); 8582d375d1SZhi Wang *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT); 8682d375d1SZhi Wang 8782d375d1SZhi Wang intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2, 8882d375d1SZhi Wang gvt_aperture_pa_base(gvt), true); 8982d375d1SZhi Wang 9082d375d1SZhi Wang vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO 9182d375d1SZhi Wang | PCI_COMMAND_MEMORY 9282d375d1SZhi Wang | PCI_COMMAND_MASTER); 9382d375d1SZhi Wang /* 9482d375d1SZhi Wang * Clear the bar upper 32bit and let guest to assign the new value 9582d375d1SZhi Wang */ 9682d375d1SZhi Wang memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4); 9782d375d1SZhi Wang memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4); 9882d375d1SZhi Wang 9982d375d1SZhi Wang for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) { 10082d375d1SZhi Wang vgpu->cfg_space.bar[i].size = pci_resource_len( 10182d375d1SZhi Wang gvt->dev_priv->drm.pdev, i * 2); 10282d375d1SZhi Wang vgpu->cfg_space.bar[i].tracked = false; 10382d375d1SZhi Wang } 10482d375d1SZhi Wang } 10582d375d1SZhi Wang 10623736d1bSPing Gao void populate_pvinfo_page(struct intel_vgpu *vgpu) 10782d375d1SZhi Wang { 10882d375d1SZhi Wang /* setup the ballooning information */ 10982d375d1SZhi Wang vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC; 11082d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1; 11182d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0; 11282d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0; 11382d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id; 11482d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = 11582d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu); 11682d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = 11782d375d1SZhi Wang vgpu_aperture_sz(vgpu); 11882d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = 11982d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu); 12082d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) = 12182d375d1SZhi Wang vgpu_hidden_sz(vgpu); 12282d375d1SZhi Wang 12382d375d1SZhi Wang vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu); 12482d375d1SZhi Wang 12582d375d1SZhi Wang gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); 12682d375d1SZhi Wang gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n", 12782d375d1SZhi Wang vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu)); 12882d375d1SZhi Wang gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n", 12982d375d1SZhi Wang vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu)); 13082d375d1SZhi Wang gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu)); 13182d375d1SZhi Wang 13282d375d1SZhi Wang WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE); 13382d375d1SZhi Wang } 13482d375d1SZhi Wang 13582d375d1SZhi Wang /** 1361f31c829SZhenyu Wang * intel_gvt_init_vgpu_types - initialize vGPU type list 1371f31c829SZhenyu Wang * @gvt : GVT device 1381f31c829SZhenyu Wang * 1391f31c829SZhenyu Wang * Initialize vGPU type list based on available resource. 1401f31c829SZhenyu Wang * 1411f31c829SZhenyu Wang */ 1421f31c829SZhenyu Wang int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) 1431f31c829SZhenyu Wang { 1441f31c829SZhenyu Wang unsigned int num_types; 1451f31c829SZhenyu Wang unsigned int i, low_avail; 1461f31c829SZhenyu Wang unsigned int min_low; 1471f31c829SZhenyu Wang 1481f31c829SZhenyu Wang /* vGPU type name is defined as GVTg_Vx_y which contains 1491f31c829SZhenyu Wang * physical GPU generation type and 'y' means maximum vGPU 1501f31c829SZhenyu Wang * instances user can create on one physical GPU for this 1511f31c829SZhenyu Wang * type. 1521f31c829SZhenyu Wang * 1531f31c829SZhenyu Wang * Depend on physical SKU resource, might see vGPU types like 1541f31c829SZhenyu Wang * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create 1551f31c829SZhenyu Wang * different types of vGPU on same physical GPU depending on 1561f31c829SZhenyu Wang * available resource. Each vGPU type will have "avail_instance" 1571f31c829SZhenyu Wang * to indicate how many vGPU instance can be created for this 1581f31c829SZhenyu Wang * type. 1591f31c829SZhenyu Wang * 1601f31c829SZhenyu Wang * Currently use static size here as we init type earlier.. 1611f31c829SZhenyu Wang */ 1621f31c829SZhenyu Wang low_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE; 1631f31c829SZhenyu Wang num_types = 4; 1641f31c829SZhenyu Wang 1651f31c829SZhenyu Wang gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type), 1661f31c829SZhenyu Wang GFP_KERNEL); 1671f31c829SZhenyu Wang if (!gvt->types) 1681f31c829SZhenyu Wang return -ENOMEM; 1691f31c829SZhenyu Wang 1701f31c829SZhenyu Wang min_low = MB_TO_BYTES(32); 1711f31c829SZhenyu Wang for (i = 0; i < num_types; ++i) { 1721f31c829SZhenyu Wang if (low_avail / min_low == 0) 1731f31c829SZhenyu Wang break; 1741f31c829SZhenyu Wang gvt->types[i].low_gm_size = min_low; 1751f31c829SZhenyu Wang gvt->types[i].high_gm_size = 3 * gvt->types[i].low_gm_size; 1761f31c829SZhenyu Wang gvt->types[i].fence = 4; 1771f31c829SZhenyu Wang gvt->types[i].max_instance = low_avail / min_low; 1781f31c829SZhenyu Wang gvt->types[i].avail_instance = gvt->types[i].max_instance; 1791f31c829SZhenyu Wang 1801f31c829SZhenyu Wang if (IS_GEN8(gvt->dev_priv)) 1811f31c829SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V4_%u", 1821f31c829SZhenyu Wang gvt->types[i].max_instance); 1831f31c829SZhenyu Wang else if (IS_GEN9(gvt->dev_priv)) 1841f31c829SZhenyu Wang sprintf(gvt->types[i].name, "GVTg_V5_%u", 1851f31c829SZhenyu Wang gvt->types[i].max_instance); 1861f31c829SZhenyu Wang 1871f31c829SZhenyu Wang min_low <<= 1; 1881f31c829SZhenyu Wang gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n", 1891f31c829SZhenyu Wang i, gvt->types[i].name, gvt->types[i].max_instance, 1901f31c829SZhenyu Wang gvt->types[i].avail_instance, 1911f31c829SZhenyu Wang gvt->types[i].low_gm_size, 1921f31c829SZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence); 1931f31c829SZhenyu Wang } 1941f31c829SZhenyu Wang 1951f31c829SZhenyu Wang gvt->num_types = i; 1961f31c829SZhenyu Wang return 0; 1971f31c829SZhenyu Wang } 1981f31c829SZhenyu Wang 1991f31c829SZhenyu Wang void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt) 2001f31c829SZhenyu Wang { 2011f31c829SZhenyu Wang kfree(gvt->types); 2021f31c829SZhenyu Wang } 2031f31c829SZhenyu Wang 2041f31c829SZhenyu Wang static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt) 2051f31c829SZhenyu Wang { 2061f31c829SZhenyu Wang int i; 2071f31c829SZhenyu Wang unsigned int low_gm_avail, high_gm_avail, fence_avail; 2081f31c829SZhenyu Wang unsigned int low_gm_min, high_gm_min, fence_min, total_min; 2091f31c829SZhenyu Wang 2101f31c829SZhenyu Wang /* Need to depend on maxium hw resource size but keep on 2111f31c829SZhenyu Wang * static config for now. 2121f31c829SZhenyu Wang */ 2131f31c829SZhenyu Wang low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE - 2141f31c829SZhenyu Wang gvt->gm.vgpu_allocated_low_gm_size; 2151f31c829SZhenyu Wang high_gm_avail = MB_TO_BYTES(256) * 3 - HOST_HIGH_GM_SIZE - 2161f31c829SZhenyu Wang gvt->gm.vgpu_allocated_high_gm_size; 2171f31c829SZhenyu Wang fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 2181f31c829SZhenyu Wang gvt->fence.vgpu_allocated_fence_num; 2191f31c829SZhenyu Wang 2201f31c829SZhenyu Wang for (i = 0; i < gvt->num_types; i++) { 2211f31c829SZhenyu Wang low_gm_min = low_gm_avail / gvt->types[i].low_gm_size; 2221f31c829SZhenyu Wang high_gm_min = high_gm_avail / gvt->types[i].high_gm_size; 2231f31c829SZhenyu Wang fence_min = fence_avail / gvt->types[i].fence; 2241f31c829SZhenyu Wang total_min = min(min(low_gm_min, high_gm_min), fence_min); 2251f31c829SZhenyu Wang gvt->types[i].avail_instance = min(gvt->types[i].max_instance, 2261f31c829SZhenyu Wang total_min); 2271f31c829SZhenyu Wang 2281f31c829SZhenyu Wang gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n", 2291f31c829SZhenyu Wang i, gvt->types[i].name, gvt->types[i].max_instance, 2301f31c829SZhenyu Wang gvt->types[i].avail_instance, gvt->types[i].low_gm_size, 2311f31c829SZhenyu Wang gvt->types[i].high_gm_size, gvt->types[i].fence); 2321f31c829SZhenyu Wang } 2331f31c829SZhenyu Wang } 2341f31c829SZhenyu Wang 2351f31c829SZhenyu Wang /** 23682d375d1SZhi Wang * intel_gvt_destroy_vgpu - destroy a virtual GPU 23782d375d1SZhi Wang * @vgpu: virtual GPU 23882d375d1SZhi Wang * 23982d375d1SZhi Wang * This function is called when user wants to destroy a virtual GPU. 24082d375d1SZhi Wang * 24182d375d1SZhi Wang */ 24282d375d1SZhi Wang void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu) 24382d375d1SZhi Wang { 24482d375d1SZhi Wang struct intel_gvt *gvt = vgpu->gvt; 24582d375d1SZhi Wang 24682d375d1SZhi Wang mutex_lock(&gvt->lock); 24782d375d1SZhi Wang 24882d375d1SZhi Wang vgpu->active = false; 24982d375d1SZhi Wang idr_remove(&gvt->vgpu_idr, vgpu->id); 25082d375d1SZhi Wang 2514b63960eSZhi Wang if (atomic_read(&vgpu->running_workload_num)) { 2524b63960eSZhi Wang mutex_unlock(&gvt->lock); 2534b63960eSZhi Wang intel_gvt_wait_vgpu_idle(vgpu); 2544b63960eSZhi Wang mutex_lock(&gvt->lock); 2554b63960eSZhi Wang } 2564b63960eSZhi Wang 2574b63960eSZhi Wang intel_vgpu_stop_schedule(vgpu); 2584b63960eSZhi Wang intel_vgpu_clean_sched_policy(vgpu); 259e4734057SZhi Wang intel_vgpu_clean_gvt_context(vgpu); 26028c4c6caSZhi Wang intel_vgpu_clean_execlist(vgpu); 26104d348aeSZhi Wang intel_vgpu_clean_display(vgpu); 2624d60c5fdSZhi Wang intel_vgpu_clean_opregion(vgpu); 2632707e444SZhi Wang intel_vgpu_clean_gtt(vgpu); 26482d375d1SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 26582d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 26682d375d1SZhi Wang clean_vgpu_mmio(vgpu); 26782d375d1SZhi Wang vfree(vgpu); 26882d375d1SZhi Wang 2691f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 27082d375d1SZhi Wang mutex_unlock(&gvt->lock); 27182d375d1SZhi Wang } 27282d375d1SZhi Wang 2731f31c829SZhenyu Wang static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 27482d375d1SZhi Wang struct intel_vgpu_creation_params *param) 27582d375d1SZhi Wang { 27682d375d1SZhi Wang struct intel_vgpu *vgpu; 27782d375d1SZhi Wang int ret; 27882d375d1SZhi Wang 27982d375d1SZhi Wang gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n", 28082d375d1SZhi Wang param->handle, param->low_gm_sz, param->high_gm_sz, 28182d375d1SZhi Wang param->fence_sz); 28282d375d1SZhi Wang 28382d375d1SZhi Wang vgpu = vzalloc(sizeof(*vgpu)); 28482d375d1SZhi Wang if (!vgpu) 28582d375d1SZhi Wang return ERR_PTR(-ENOMEM); 28682d375d1SZhi Wang 28782d375d1SZhi Wang mutex_lock(&gvt->lock); 28882d375d1SZhi Wang 28982d375d1SZhi Wang ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL); 29082d375d1SZhi Wang if (ret < 0) 29182d375d1SZhi Wang goto out_free_vgpu; 29282d375d1SZhi Wang 29382d375d1SZhi Wang vgpu->id = ret; 29482d375d1SZhi Wang vgpu->handle = param->handle; 29582d375d1SZhi Wang vgpu->gvt = gvt; 29617865713SZhi Wang bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES); 29782d375d1SZhi Wang 29882d375d1SZhi Wang setup_vgpu_cfg_space(vgpu, param); 29982d375d1SZhi Wang 30082d375d1SZhi Wang ret = setup_vgpu_mmio(vgpu); 30182d375d1SZhi Wang if (ret) 30282d375d1SZhi Wang goto out_free_vgpu; 30382d375d1SZhi Wang 30482d375d1SZhi Wang ret = intel_vgpu_alloc_resource(vgpu, param); 30582d375d1SZhi Wang if (ret) 30682d375d1SZhi Wang goto out_clean_vgpu_mmio; 30782d375d1SZhi Wang 30882d375d1SZhi Wang populate_pvinfo_page(vgpu); 30982d375d1SZhi Wang 31082d375d1SZhi Wang ret = intel_gvt_hypervisor_attach_vgpu(vgpu); 31182d375d1SZhi Wang if (ret) 31282d375d1SZhi Wang goto out_clean_vgpu_resource; 31382d375d1SZhi Wang 3142707e444SZhi Wang ret = intel_vgpu_init_gtt(vgpu); 3152707e444SZhi Wang if (ret) 3162707e444SZhi Wang goto out_detach_hypervisor_vgpu; 3172707e444SZhi Wang 3184d60c5fdSZhi Wang if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_KVM) { 3194d60c5fdSZhi Wang ret = intel_vgpu_init_opregion(vgpu, 0); 3204d60c5fdSZhi Wang if (ret) 3214d60c5fdSZhi Wang goto out_clean_gtt; 3224d60c5fdSZhi Wang } 3234d60c5fdSZhi Wang 32404d348aeSZhi Wang ret = intel_vgpu_init_display(vgpu); 32504d348aeSZhi Wang if (ret) 32604d348aeSZhi Wang goto out_clean_opregion; 32704d348aeSZhi Wang 3288453d674SZhi Wang ret = intel_vgpu_init_execlist(vgpu); 3298453d674SZhi Wang if (ret) 3308453d674SZhi Wang goto out_clean_display; 3318453d674SZhi Wang 332e4734057SZhi Wang ret = intel_vgpu_init_gvt_context(vgpu); 333e4734057SZhi Wang if (ret) 334e4734057SZhi Wang goto out_clean_execlist; 335e4734057SZhi Wang 3364b63960eSZhi Wang ret = intel_vgpu_init_sched_policy(vgpu); 3374b63960eSZhi Wang if (ret) 3384b63960eSZhi Wang goto out_clean_shadow_ctx; 3394b63960eSZhi Wang 34082d375d1SZhi Wang vgpu->active = true; 34182d375d1SZhi Wang mutex_unlock(&gvt->lock); 34282d375d1SZhi Wang 34382d375d1SZhi Wang return vgpu; 34482d375d1SZhi Wang 3454b63960eSZhi Wang out_clean_shadow_ctx: 3464b63960eSZhi Wang intel_vgpu_clean_gvt_context(vgpu); 347e4734057SZhi Wang out_clean_execlist: 348e4734057SZhi Wang intel_vgpu_clean_execlist(vgpu); 3498453d674SZhi Wang out_clean_display: 3508453d674SZhi Wang intel_vgpu_clean_display(vgpu); 35104d348aeSZhi Wang out_clean_opregion: 35204d348aeSZhi Wang intel_vgpu_clean_opregion(vgpu); 3534d60c5fdSZhi Wang out_clean_gtt: 3544d60c5fdSZhi Wang intel_vgpu_clean_gtt(vgpu); 3552707e444SZhi Wang out_detach_hypervisor_vgpu: 3562707e444SZhi Wang intel_gvt_hypervisor_detach_vgpu(vgpu); 35782d375d1SZhi Wang out_clean_vgpu_resource: 35882d375d1SZhi Wang intel_vgpu_free_resource(vgpu); 35982d375d1SZhi Wang out_clean_vgpu_mmio: 36082d375d1SZhi Wang clean_vgpu_mmio(vgpu); 36182d375d1SZhi Wang out_free_vgpu: 36282d375d1SZhi Wang vfree(vgpu); 36382d375d1SZhi Wang mutex_unlock(&gvt->lock); 36482d375d1SZhi Wang return ERR_PTR(ret); 36582d375d1SZhi Wang } 3661f31c829SZhenyu Wang 3671f31c829SZhenyu Wang /** 3681f31c829SZhenyu Wang * intel_gvt_create_vgpu - create a virtual GPU 3691f31c829SZhenyu Wang * @gvt: GVT device 3701f31c829SZhenyu Wang * @type: type of the vGPU to create 3711f31c829SZhenyu Wang * 3721f31c829SZhenyu Wang * This function is called when user wants to create a virtual GPU. 3731f31c829SZhenyu Wang * 3741f31c829SZhenyu Wang * Returns: 3751f31c829SZhenyu Wang * pointer to intel_vgpu, error pointer if failed. 3761f31c829SZhenyu Wang */ 3771f31c829SZhenyu Wang struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 3781f31c829SZhenyu Wang struct intel_vgpu_type *type) 3791f31c829SZhenyu Wang { 3801f31c829SZhenyu Wang struct intel_vgpu_creation_params param; 3811f31c829SZhenyu Wang struct intel_vgpu *vgpu; 3821f31c829SZhenyu Wang 3831f31c829SZhenyu Wang param.handle = 0; 3841f31c829SZhenyu Wang param.low_gm_sz = type->low_gm_size; 3851f31c829SZhenyu Wang param.high_gm_sz = type->high_gm_size; 3861f31c829SZhenyu Wang param.fence_sz = type->fence; 3871f31c829SZhenyu Wang 3881f31c829SZhenyu Wang /* XXX current param based on MB */ 3891f31c829SZhenyu Wang param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz); 3901f31c829SZhenyu Wang param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz); 3911f31c829SZhenyu Wang 3921f31c829SZhenyu Wang vgpu = __intel_gvt_create_vgpu(gvt, ¶m); 3931f31c829SZhenyu Wang if (IS_ERR(vgpu)) 3941f31c829SZhenyu Wang return vgpu; 3951f31c829SZhenyu Wang 3961f31c829SZhenyu Wang /* calculate left instance change for types */ 3971f31c829SZhenyu Wang intel_gvt_update_vgpu_types(gvt); 3981f31c829SZhenyu Wang 3991f31c829SZhenyu Wang return vgpu; 4001f31c829SZhenyu Wang } 401