1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36 #include <linux/kthread.h> 37 38 #include "i915_drv.h" 39 #include "gvt.h" 40 41 #define RING_CTX_OFF(x) \ 42 offsetof(struct execlist_ring_context, x) 43 44 static void set_context_pdp_root_pointer( 45 struct execlist_ring_context *ring_context, 46 u32 pdp[8]) 47 { 48 int i; 49 50 for (i = 0; i < 8; i++) 51 ring_context->pdps[i].val = pdp[7 - i]; 52 } 53 54 static void update_shadow_pdps(struct intel_vgpu_workload *workload) 55 { 56 struct drm_i915_gem_object *ctx_obj = 57 workload->req->hw_context->state->obj; 58 struct execlist_ring_context *shadow_ring_context; 59 struct page *page; 60 61 if (WARN_ON(!workload->shadow_mm)) 62 return; 63 64 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount))) 65 return; 66 67 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 68 shadow_ring_context = kmap(page); 69 set_context_pdp_root_pointer(shadow_ring_context, 70 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); 71 kunmap(page); 72 } 73 74 /* 75 * when populating shadow ctx from guest, we should not overrride oa related 76 * registers, so that they will not be overlapped by guest oa configs. Thus 77 * made it possible to capture oa data from host for both host and guests. 78 */ 79 static void sr_oa_regs(struct intel_vgpu_workload *workload, 80 u32 *reg_state, bool save) 81 { 82 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 83 u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; 84 u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; 85 int i = 0; 86 u32 flex_mmio[] = { 87 i915_mmio_reg_offset(EU_PERF_CNTL0), 88 i915_mmio_reg_offset(EU_PERF_CNTL1), 89 i915_mmio_reg_offset(EU_PERF_CNTL2), 90 i915_mmio_reg_offset(EU_PERF_CNTL3), 91 i915_mmio_reg_offset(EU_PERF_CNTL4), 92 i915_mmio_reg_offset(EU_PERF_CNTL5), 93 i915_mmio_reg_offset(EU_PERF_CNTL6), 94 }; 95 96 if (workload->ring_id != RCS) 97 return; 98 99 if (save) { 100 workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; 101 102 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 103 u32 state_offset = ctx_flexeu0 + i * 2; 104 105 workload->flex_mmio[i] = reg_state[state_offset + 1]; 106 } 107 } else { 108 reg_state[ctx_oactxctrl] = 109 i915_mmio_reg_offset(GEN8_OACTXCONTROL); 110 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; 111 112 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 113 u32 state_offset = ctx_flexeu0 + i * 2; 114 u32 mmio = flex_mmio[i]; 115 116 reg_state[state_offset] = mmio; 117 reg_state[state_offset + 1] = workload->flex_mmio[i]; 118 } 119 } 120 } 121 122 static int populate_shadow_context(struct intel_vgpu_workload *workload) 123 { 124 struct intel_vgpu *vgpu = workload->vgpu; 125 struct intel_gvt *gvt = vgpu->gvt; 126 int ring_id = workload->ring_id; 127 struct drm_i915_gem_object *ctx_obj = 128 workload->req->hw_context->state->obj; 129 struct execlist_ring_context *shadow_ring_context; 130 struct page *page; 131 void *dst; 132 unsigned long context_gpa, context_page_num; 133 int i; 134 135 gvt_dbg_sched("ring id %d workload lrca %x", ring_id, 136 workload->ctx_desc.lrca); 137 138 context_page_num = gvt->dev_priv->engine[ring_id]->context_size; 139 140 context_page_num = context_page_num >> PAGE_SHIFT; 141 142 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) 143 context_page_num = 19; 144 145 i = 2; 146 147 while (i < context_page_num) { 148 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 149 (u32)((workload->ctx_desc.lrca + i) << 150 I915_GTT_PAGE_SHIFT)); 151 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 152 gvt_vgpu_err("Invalid guest context descriptor\n"); 153 return -EFAULT; 154 } 155 156 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 157 dst = kmap(page); 158 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, 159 I915_GTT_PAGE_SIZE); 160 kunmap(page); 161 i++; 162 } 163 164 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 165 shadow_ring_context = kmap(page); 166 167 sr_oa_regs(workload, (u32 *)shadow_ring_context, true); 168 #define COPY_REG(name) \ 169 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 170 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 171 #define COPY_REG_MASKED(name) {\ 172 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 173 + RING_CTX_OFF(name.val),\ 174 &shadow_ring_context->name.val, 4);\ 175 shadow_ring_context->name.val |= 0xffff << 16;\ 176 } 177 178 COPY_REG_MASKED(ctx_ctrl); 179 COPY_REG(ctx_timestamp); 180 181 if (ring_id == RCS) { 182 COPY_REG(bb_per_ctx_ptr); 183 COPY_REG(rcs_indirect_ctx); 184 COPY_REG(rcs_indirect_ctx_offset); 185 } 186 #undef COPY_REG 187 #undef COPY_REG_MASKED 188 189 intel_gvt_hypervisor_read_gpa(vgpu, 190 workload->ring_context_gpa + 191 sizeof(*shadow_ring_context), 192 (void *)shadow_ring_context + 193 sizeof(*shadow_ring_context), 194 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 195 196 sr_oa_regs(workload, (u32 *)shadow_ring_context, false); 197 kunmap(page); 198 return 0; 199 } 200 201 static inline bool is_gvt_request(struct i915_request *req) 202 { 203 return i915_gem_context_force_single_submission(req->gem_context); 204 } 205 206 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) 207 { 208 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 209 u32 ring_base = dev_priv->engine[ring_id]->mmio_base; 210 i915_reg_t reg; 211 212 reg = RING_INSTDONE(ring_base); 213 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 214 reg = RING_ACTHD(ring_base); 215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 216 reg = RING_ACTHD_UDW(ring_base); 217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 218 } 219 220 static int shadow_context_status_change(struct notifier_block *nb, 221 unsigned long action, void *data) 222 { 223 struct i915_request *req = data; 224 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, 225 shadow_ctx_notifier_block[req->engine->id]); 226 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 227 enum intel_engine_id ring_id = req->engine->id; 228 struct intel_vgpu_workload *workload; 229 unsigned long flags; 230 231 if (!is_gvt_request(req)) { 232 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 233 if (action == INTEL_CONTEXT_SCHEDULE_IN && 234 scheduler->engine_owner[ring_id]) { 235 /* Switch ring from vGPU to host. */ 236 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 237 NULL, ring_id); 238 scheduler->engine_owner[ring_id] = NULL; 239 } 240 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 241 242 return NOTIFY_OK; 243 } 244 245 workload = scheduler->current_workload[ring_id]; 246 if (unlikely(!workload)) 247 return NOTIFY_OK; 248 249 switch (action) { 250 case INTEL_CONTEXT_SCHEDULE_IN: 251 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 252 if (workload->vgpu != scheduler->engine_owner[ring_id]) { 253 /* Switch ring from host to vGPU or vGPU to vGPU. */ 254 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 255 workload->vgpu, ring_id); 256 scheduler->engine_owner[ring_id] = workload->vgpu; 257 } else 258 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n", 259 ring_id, workload->vgpu->id); 260 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 261 atomic_set(&workload->shadow_ctx_active, 1); 262 break; 263 case INTEL_CONTEXT_SCHEDULE_OUT: 264 save_ring_hw_state(workload->vgpu, ring_id); 265 atomic_set(&workload->shadow_ctx_active, 0); 266 break; 267 case INTEL_CONTEXT_SCHEDULE_PREEMPTED: 268 save_ring_hw_state(workload->vgpu, ring_id); 269 break; 270 default: 271 WARN_ON(1); 272 return NOTIFY_OK; 273 } 274 wake_up(&workload->shadow_ctx_status_wq); 275 return NOTIFY_OK; 276 } 277 278 static void shadow_context_descriptor_update(struct intel_context *ce) 279 { 280 u64 desc = 0; 281 282 desc = ce->lrc_desc; 283 284 /* Update bits 0-11 of the context descriptor which includes flags 285 * like GEN8_CTX_* cached in desc_template 286 */ 287 desc &= U64_MAX << 12; 288 desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1); 289 290 ce->lrc_desc = desc; 291 } 292 293 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) 294 { 295 struct intel_vgpu *vgpu = workload->vgpu; 296 struct i915_request *req = workload->req; 297 void *shadow_ring_buffer_va; 298 u32 *cs; 299 300 if ((IS_KABYLAKE(req->i915) || IS_BROXTON(req->i915)) 301 && is_inhibit_context(req->hw_context)) 302 intel_vgpu_restore_inhibit_context(vgpu, req); 303 304 /* allocate shadow ring buffer */ 305 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32)); 306 if (IS_ERR(cs)) { 307 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", 308 workload->rb_len); 309 return PTR_ERR(cs); 310 } 311 312 shadow_ring_buffer_va = workload->shadow_ring_buffer_va; 313 314 /* get shadow ring buffer va */ 315 workload->shadow_ring_buffer_va = cs; 316 317 memcpy(cs, shadow_ring_buffer_va, 318 workload->rb_len); 319 320 cs += workload->rb_len / sizeof(u32); 321 intel_ring_advance(workload->req, cs); 322 323 return 0; 324 } 325 326 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 327 { 328 if (!wa_ctx->indirect_ctx.obj) 329 return; 330 331 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj); 332 i915_gem_object_put(wa_ctx->indirect_ctx.obj); 333 } 334 335 /** 336 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and 337 * shadow it as well, include ringbuffer,wa_ctx and ctx. 338 * @workload: an abstract entity for each execlist submission. 339 * 340 * This function is called before the workload submitting to i915, to make 341 * sure the content of the workload is valid. 342 */ 343 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) 344 { 345 struct intel_vgpu *vgpu = workload->vgpu; 346 struct intel_vgpu_submission *s = &vgpu->submission; 347 struct i915_gem_context *shadow_ctx = s->shadow_ctx; 348 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 349 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id]; 350 struct intel_context *ce; 351 struct i915_request *rq; 352 int ret; 353 354 lockdep_assert_held(&dev_priv->drm.struct_mutex); 355 356 if (workload->req) 357 return 0; 358 359 /* pin shadow context by gvt even the shadow context will be pinned 360 * when i915 alloc request. That is because gvt will update the guest 361 * context from shadow context when workload is completed, and at that 362 * moment, i915 may already unpined the shadow context to make the 363 * shadow_ctx pages invalid. So gvt need to pin itself. After update 364 * the guest context, gvt can unpin the shadow_ctx safely. 365 */ 366 ce = intel_context_pin(shadow_ctx, engine); 367 if (IS_ERR(ce)) { 368 gvt_vgpu_err("fail to pin shadow context\n"); 369 return PTR_ERR(ce); 370 } 371 372 shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); 373 shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << 374 GEN8_CTX_ADDRESSING_MODE_SHIFT; 375 376 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated)) 377 shadow_context_descriptor_update(ce); 378 379 ret = intel_gvt_scan_and_shadow_ringbuffer(workload); 380 if (ret) 381 goto err_unpin; 382 383 if ((workload->ring_id == RCS) && 384 (workload->wa_ctx.indirect_ctx.size != 0)) { 385 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 386 if (ret) 387 goto err_shadow; 388 } 389 390 rq = i915_request_alloc(engine, shadow_ctx); 391 if (IS_ERR(rq)) { 392 gvt_vgpu_err("fail to allocate gem request\n"); 393 ret = PTR_ERR(rq); 394 goto err_shadow; 395 } 396 workload->req = i915_request_get(rq); 397 398 ret = populate_shadow_context(workload); 399 if (ret) 400 goto err_req; 401 402 return 0; 403 err_req: 404 rq = fetch_and_zero(&workload->req); 405 i915_request_put(rq); 406 err_shadow: 407 release_shadow_wa_ctx(&workload->wa_ctx); 408 err_unpin: 409 intel_context_unpin(ce); 410 return ret; 411 } 412 413 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload); 414 415 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 416 { 417 struct intel_gvt *gvt = workload->vgpu->gvt; 418 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 419 struct intel_vgpu_shadow_bb *bb; 420 int ret; 421 422 list_for_each_entry(bb, &workload->shadow_bb, list) { 423 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va 424 * is only updated into ring_scan_buffer, not real ring address 425 * allocated in later copy_workload_to_ring_buffer. pls be noted 426 * shadow_ring_buffer_va is now pointed to real ring buffer va 427 * in copy_workload_to_ring_buffer. 428 */ 429 430 if (bb->bb_offset) 431 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va 432 + bb->bb_offset; 433 434 if (bb->ppgtt) { 435 /* for non-priv bb, scan&shadow is only for 436 * debugging purpose, so the content of shadow bb 437 * is the same as original bb. Therefore, 438 * here, rather than switch to shadow bb's gma 439 * address, we directly use original batch buffer's 440 * gma address, and send original bb to hardware 441 * directly 442 */ 443 if (bb->clflush & CLFLUSH_AFTER) { 444 drm_clflush_virt_range(bb->va, 445 bb->obj->base.size); 446 bb->clflush &= ~CLFLUSH_AFTER; 447 } 448 i915_gem_obj_finish_shmem_access(bb->obj); 449 bb->accessing = false; 450 451 } else { 452 bb->vma = i915_gem_object_ggtt_pin(bb->obj, 453 NULL, 0, 0, 0); 454 if (IS_ERR(bb->vma)) { 455 ret = PTR_ERR(bb->vma); 456 goto err; 457 } 458 459 /* relocate shadow batch buffer */ 460 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); 461 if (gmadr_bytes == 8) 462 bb->bb_start_cmd_va[2] = 0; 463 464 /* No one is going to touch shadow bb from now on. */ 465 if (bb->clflush & CLFLUSH_AFTER) { 466 drm_clflush_virt_range(bb->va, 467 bb->obj->base.size); 468 bb->clflush &= ~CLFLUSH_AFTER; 469 } 470 471 ret = i915_gem_object_set_to_gtt_domain(bb->obj, 472 false); 473 if (ret) 474 goto err; 475 476 i915_gem_obj_finish_shmem_access(bb->obj); 477 bb->accessing = false; 478 479 i915_vma_move_to_active(bb->vma, workload->req, 0); 480 } 481 } 482 return 0; 483 err: 484 release_shadow_batch_buffer(workload); 485 return ret; 486 } 487 488 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx) 489 { 490 struct intel_vgpu_workload *workload = 491 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx); 492 struct i915_request *rq = workload->req; 493 struct execlist_ring_context *shadow_ring_context = 494 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state; 495 496 shadow_ring_context->bb_per_ctx_ptr.val = 497 (shadow_ring_context->bb_per_ctx_ptr.val & 498 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma; 499 shadow_ring_context->rcs_indirect_ctx.val = 500 (shadow_ring_context->rcs_indirect_ctx.val & 501 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma; 502 } 503 504 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 505 { 506 struct i915_vma *vma; 507 unsigned char *per_ctx_va = 508 (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 509 wa_ctx->indirect_ctx.size; 510 511 if (wa_ctx->indirect_ctx.size == 0) 512 return 0; 513 514 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL, 515 0, CACHELINE_BYTES, 0); 516 if (IS_ERR(vma)) 517 return PTR_ERR(vma); 518 519 /* FIXME: we are not tracking our pinned VMA leaving it 520 * up to the core to fix up the stray pin_count upon 521 * free. 522 */ 523 524 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); 525 526 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1); 527 memset(per_ctx_va, 0, CACHELINE_BYTES); 528 529 update_wa_ctx_2_shadow_ctx(wa_ctx); 530 return 0; 531 } 532 533 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 534 { 535 struct intel_vgpu *vgpu = workload->vgpu; 536 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 537 struct intel_vgpu_shadow_bb *bb, *pos; 538 539 if (list_empty(&workload->shadow_bb)) 540 return; 541 542 bb = list_first_entry(&workload->shadow_bb, 543 struct intel_vgpu_shadow_bb, list); 544 545 mutex_lock(&dev_priv->drm.struct_mutex); 546 547 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { 548 if (bb->obj) { 549 if (bb->accessing) 550 i915_gem_obj_finish_shmem_access(bb->obj); 551 552 if (bb->va && !IS_ERR(bb->va)) 553 i915_gem_object_unpin_map(bb->obj); 554 555 if (bb->vma && !IS_ERR(bb->vma)) { 556 i915_vma_unpin(bb->vma); 557 i915_vma_close(bb->vma); 558 } 559 __i915_gem_object_release_unless_active(bb->obj); 560 } 561 list_del(&bb->list); 562 kfree(bb); 563 } 564 565 mutex_unlock(&dev_priv->drm.struct_mutex); 566 } 567 568 static int prepare_workload(struct intel_vgpu_workload *workload) 569 { 570 struct intel_vgpu *vgpu = workload->vgpu; 571 int ret = 0; 572 573 ret = intel_vgpu_pin_mm(workload->shadow_mm); 574 if (ret) { 575 gvt_vgpu_err("fail to vgpu pin mm\n"); 576 return ret; 577 } 578 579 update_shadow_pdps(workload); 580 581 ret = intel_vgpu_sync_oos_pages(workload->vgpu); 582 if (ret) { 583 gvt_vgpu_err("fail to vgpu sync oos pages\n"); 584 goto err_unpin_mm; 585 } 586 587 ret = intel_vgpu_flush_post_shadow(workload->vgpu); 588 if (ret) { 589 gvt_vgpu_err("fail to flush post shadow\n"); 590 goto err_unpin_mm; 591 } 592 593 ret = copy_workload_to_ring_buffer(workload); 594 if (ret) { 595 gvt_vgpu_err("fail to generate request\n"); 596 goto err_unpin_mm; 597 } 598 599 ret = prepare_shadow_batch_buffer(workload); 600 if (ret) { 601 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n"); 602 goto err_unpin_mm; 603 } 604 605 ret = prepare_shadow_wa_ctx(&workload->wa_ctx); 606 if (ret) { 607 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n"); 608 goto err_shadow_batch; 609 } 610 611 if (workload->prepare) { 612 ret = workload->prepare(workload); 613 if (ret) 614 goto err_shadow_wa_ctx; 615 } 616 617 return 0; 618 err_shadow_wa_ctx: 619 release_shadow_wa_ctx(&workload->wa_ctx); 620 err_shadow_batch: 621 release_shadow_batch_buffer(workload); 622 err_unpin_mm: 623 intel_vgpu_unpin_mm(workload->shadow_mm); 624 return ret; 625 } 626 627 static int dispatch_workload(struct intel_vgpu_workload *workload) 628 { 629 struct intel_vgpu *vgpu = workload->vgpu; 630 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 631 int ring_id = workload->ring_id; 632 int ret; 633 634 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", 635 ring_id, workload); 636 637 mutex_lock(&vgpu->vgpu_lock); 638 mutex_lock(&dev_priv->drm.struct_mutex); 639 640 ret = intel_gvt_scan_and_shadow_workload(workload); 641 if (ret) 642 goto out; 643 644 ret = prepare_workload(workload); 645 646 out: 647 if (ret) 648 workload->status = ret; 649 650 if (!IS_ERR_OR_NULL(workload->req)) { 651 gvt_dbg_sched("ring id %d submit workload to i915 %p\n", 652 ring_id, workload->req); 653 i915_request_add(workload->req); 654 workload->dispatched = true; 655 } 656 657 mutex_unlock(&dev_priv->drm.struct_mutex); 658 mutex_unlock(&vgpu->vgpu_lock); 659 return ret; 660 } 661 662 static struct intel_vgpu_workload *pick_next_workload( 663 struct intel_gvt *gvt, int ring_id) 664 { 665 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 666 struct intel_vgpu_workload *workload = NULL; 667 668 mutex_lock(&gvt->sched_lock); 669 670 /* 671 * no current vgpu / will be scheduled out / no workload 672 * bail out 673 */ 674 if (!scheduler->current_vgpu) { 675 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id); 676 goto out; 677 } 678 679 if (scheduler->need_reschedule) { 680 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id); 681 goto out; 682 } 683 684 if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) 685 goto out; 686 687 /* 688 * still have current workload, maybe the workload disptacher 689 * fail to submit it for some reason, resubmit it. 690 */ 691 if (scheduler->current_workload[ring_id]) { 692 workload = scheduler->current_workload[ring_id]; 693 gvt_dbg_sched("ring id %d still have current workload %p\n", 694 ring_id, workload); 695 goto out; 696 } 697 698 /* 699 * pick a workload as current workload 700 * once current workload is set, schedule policy routines 701 * will wait the current workload is finished when trying to 702 * schedule out a vgpu. 703 */ 704 scheduler->current_workload[ring_id] = container_of( 705 workload_q_head(scheduler->current_vgpu, ring_id)->next, 706 struct intel_vgpu_workload, list); 707 708 workload = scheduler->current_workload[ring_id]; 709 710 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); 711 712 atomic_inc(&workload->vgpu->submission.running_workload_num); 713 out: 714 mutex_unlock(&gvt->sched_lock); 715 return workload; 716 } 717 718 static void update_guest_context(struct intel_vgpu_workload *workload) 719 { 720 struct i915_request *rq = workload->req; 721 struct intel_vgpu *vgpu = workload->vgpu; 722 struct intel_gvt *gvt = vgpu->gvt; 723 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj; 724 struct execlist_ring_context *shadow_ring_context; 725 struct page *page; 726 void *src; 727 unsigned long context_gpa, context_page_num; 728 int i; 729 730 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id, 731 workload->ctx_desc.lrca); 732 733 context_page_num = rq->engine->context_size; 734 context_page_num = context_page_num >> PAGE_SHIFT; 735 736 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS) 737 context_page_num = 19; 738 739 i = 2; 740 741 while (i < context_page_num) { 742 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 743 (u32)((workload->ctx_desc.lrca + i) << 744 I915_GTT_PAGE_SHIFT)); 745 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 746 gvt_vgpu_err("invalid guest context descriptor\n"); 747 return; 748 } 749 750 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 751 src = kmap(page); 752 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, 753 I915_GTT_PAGE_SIZE); 754 kunmap(page); 755 i++; 756 } 757 758 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 759 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 760 761 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 762 shadow_ring_context = kmap(page); 763 764 #define COPY_REG(name) \ 765 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 766 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 767 768 COPY_REG(ctx_ctrl); 769 COPY_REG(ctx_timestamp); 770 771 #undef COPY_REG 772 773 intel_gvt_hypervisor_write_gpa(vgpu, 774 workload->ring_context_gpa + 775 sizeof(*shadow_ring_context), 776 (void *)shadow_ring_context + 777 sizeof(*shadow_ring_context), 778 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 779 780 kunmap(page); 781 } 782 783 static void clean_workloads(struct intel_vgpu *vgpu, unsigned long engine_mask) 784 { 785 struct intel_vgpu_submission *s = &vgpu->submission; 786 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 787 struct intel_engine_cs *engine; 788 struct intel_vgpu_workload *pos, *n; 789 unsigned int tmp; 790 791 /* free the unsubmited workloads in the queues. */ 792 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { 793 list_for_each_entry_safe(pos, n, 794 &s->workload_q_head[engine->id], list) { 795 list_del_init(&pos->list); 796 intel_vgpu_destroy_workload(pos); 797 } 798 clear_bit(engine->id, s->shadow_ctx_desc_updated); 799 } 800 } 801 802 static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 803 { 804 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 805 struct intel_vgpu_workload *workload = 806 scheduler->current_workload[ring_id]; 807 struct intel_vgpu *vgpu = workload->vgpu; 808 struct intel_vgpu_submission *s = &vgpu->submission; 809 struct i915_request *rq = workload->req; 810 int event; 811 812 mutex_lock(&vgpu->vgpu_lock); 813 mutex_lock(&gvt->sched_lock); 814 815 /* For the workload w/ request, needs to wait for the context 816 * switch to make sure request is completed. 817 * For the workload w/o request, directly complete the workload. 818 */ 819 if (rq) { 820 wait_event(workload->shadow_ctx_status_wq, 821 !atomic_read(&workload->shadow_ctx_active)); 822 823 /* If this request caused GPU hang, req->fence.error will 824 * be set to -EIO. Use -EIO to set workload status so 825 * that when this request caused GPU hang, didn't trigger 826 * context switch interrupt to guest. 827 */ 828 if (likely(workload->status == -EINPROGRESS)) { 829 if (workload->req->fence.error == -EIO) 830 workload->status = -EIO; 831 else 832 workload->status = 0; 833 } 834 835 if (!workload->status && !(vgpu->resetting_eng & 836 ENGINE_MASK(ring_id))) { 837 update_guest_context(workload); 838 839 for_each_set_bit(event, workload->pending_events, 840 INTEL_GVT_EVENT_MAX) 841 intel_vgpu_trigger_virtual_event(vgpu, event); 842 } 843 844 /* unpin shadow ctx as the shadow_ctx update is done */ 845 mutex_lock(&rq->i915->drm.struct_mutex); 846 intel_context_unpin(rq->hw_context); 847 mutex_unlock(&rq->i915->drm.struct_mutex); 848 849 i915_request_put(fetch_and_zero(&workload->req)); 850 } 851 852 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 853 ring_id, workload, workload->status); 854 855 scheduler->current_workload[ring_id] = NULL; 856 857 list_del_init(&workload->list); 858 859 if (!workload->status) { 860 release_shadow_batch_buffer(workload); 861 release_shadow_wa_ctx(&workload->wa_ctx); 862 } 863 864 if (workload->status || (vgpu->resetting_eng & ENGINE_MASK(ring_id))) { 865 /* if workload->status is not successful means HW GPU 866 * has occurred GPU hang or something wrong with i915/GVT, 867 * and GVT won't inject context switch interrupt to guest. 868 * So this error is a vGPU hang actually to the guest. 869 * According to this we should emunlate a vGPU hang. If 870 * there are pending workloads which are already submitted 871 * from guest, we should clean them up like HW GPU does. 872 * 873 * if it is in middle of engine resetting, the pending 874 * workloads won't be submitted to HW GPU and will be 875 * cleaned up during the resetting process later, so doing 876 * the workload clean up here doesn't have any impact. 877 **/ 878 clean_workloads(vgpu, ENGINE_MASK(ring_id)); 879 } 880 881 workload->complete(workload); 882 883 atomic_dec(&s->running_workload_num); 884 wake_up(&scheduler->workload_complete_wq); 885 886 if (gvt->scheduler.need_reschedule) 887 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED); 888 889 mutex_unlock(&gvt->sched_lock); 890 mutex_unlock(&vgpu->vgpu_lock); 891 } 892 893 struct workload_thread_param { 894 struct intel_gvt *gvt; 895 int ring_id; 896 }; 897 898 static int workload_thread(void *priv) 899 { 900 struct workload_thread_param *p = (struct workload_thread_param *)priv; 901 struct intel_gvt *gvt = p->gvt; 902 int ring_id = p->ring_id; 903 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 904 struct intel_vgpu_workload *workload = NULL; 905 struct intel_vgpu *vgpu = NULL; 906 int ret; 907 bool need_force_wake = IS_SKYLAKE(gvt->dev_priv) 908 || IS_KABYLAKE(gvt->dev_priv) 909 || IS_BROXTON(gvt->dev_priv); 910 DEFINE_WAIT_FUNC(wait, woken_wake_function); 911 912 kfree(p); 913 914 gvt_dbg_core("workload thread for ring %d started\n", ring_id); 915 916 while (!kthread_should_stop()) { 917 add_wait_queue(&scheduler->waitq[ring_id], &wait); 918 do { 919 workload = pick_next_workload(gvt, ring_id); 920 if (workload) 921 break; 922 wait_woken(&wait, TASK_INTERRUPTIBLE, 923 MAX_SCHEDULE_TIMEOUT); 924 } while (!kthread_should_stop()); 925 remove_wait_queue(&scheduler->waitq[ring_id], &wait); 926 927 if (!workload) 928 break; 929 930 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n", 931 workload->ring_id, workload, 932 workload->vgpu->id); 933 934 intel_runtime_pm_get(gvt->dev_priv); 935 936 gvt_dbg_sched("ring id %d will dispatch workload %p\n", 937 workload->ring_id, workload); 938 939 if (need_force_wake) 940 intel_uncore_forcewake_get(gvt->dev_priv, 941 FORCEWAKE_ALL); 942 943 ret = dispatch_workload(workload); 944 945 if (ret) { 946 vgpu = workload->vgpu; 947 gvt_vgpu_err("fail to dispatch workload, skip\n"); 948 goto complete; 949 } 950 951 gvt_dbg_sched("ring id %d wait workload %p\n", 952 workload->ring_id, workload); 953 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT); 954 955 complete: 956 gvt_dbg_sched("will complete workload %p, status: %d\n", 957 workload, workload->status); 958 959 complete_current_workload(gvt, ring_id); 960 961 if (need_force_wake) 962 intel_uncore_forcewake_put(gvt->dev_priv, 963 FORCEWAKE_ALL); 964 965 intel_runtime_pm_put(gvt->dev_priv); 966 if (ret && (vgpu_is_vm_unhealthy(ret))) 967 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 968 } 969 return 0; 970 } 971 972 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 973 { 974 struct intel_vgpu_submission *s = &vgpu->submission; 975 struct intel_gvt *gvt = vgpu->gvt; 976 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 977 978 if (atomic_read(&s->running_workload_num)) { 979 gvt_dbg_sched("wait vgpu idle\n"); 980 981 wait_event(scheduler->workload_complete_wq, 982 !atomic_read(&s->running_workload_num)); 983 } 984 } 985 986 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 987 { 988 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 989 struct intel_engine_cs *engine; 990 enum intel_engine_id i; 991 992 gvt_dbg_core("clean workload scheduler\n"); 993 994 for_each_engine(engine, gvt->dev_priv, i) { 995 atomic_notifier_chain_unregister( 996 &engine->context_status_notifier, 997 &gvt->shadow_ctx_notifier_block[i]); 998 kthread_stop(scheduler->thread[i]); 999 } 1000 } 1001 1002 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 1003 { 1004 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1005 struct workload_thread_param *param = NULL; 1006 struct intel_engine_cs *engine; 1007 enum intel_engine_id i; 1008 int ret; 1009 1010 gvt_dbg_core("init workload scheduler\n"); 1011 1012 init_waitqueue_head(&scheduler->workload_complete_wq); 1013 1014 for_each_engine(engine, gvt->dev_priv, i) { 1015 init_waitqueue_head(&scheduler->waitq[i]); 1016 1017 param = kzalloc(sizeof(*param), GFP_KERNEL); 1018 if (!param) { 1019 ret = -ENOMEM; 1020 goto err; 1021 } 1022 1023 param->gvt = gvt; 1024 param->ring_id = i; 1025 1026 scheduler->thread[i] = kthread_run(workload_thread, param, 1027 "gvt workload %d", i); 1028 if (IS_ERR(scheduler->thread[i])) { 1029 gvt_err("fail to create workload thread\n"); 1030 ret = PTR_ERR(scheduler->thread[i]); 1031 goto err; 1032 } 1033 1034 gvt->shadow_ctx_notifier_block[i].notifier_call = 1035 shadow_context_status_change; 1036 atomic_notifier_chain_register(&engine->context_status_notifier, 1037 &gvt->shadow_ctx_notifier_block[i]); 1038 } 1039 return 0; 1040 err: 1041 intel_gvt_clean_workload_scheduler(gvt); 1042 kfree(param); 1043 param = NULL; 1044 return ret; 1045 } 1046 1047 /** 1048 * intel_vgpu_clean_submission - free submission-related resource for vGPU 1049 * @vgpu: a vGPU 1050 * 1051 * This function is called when a vGPU is being destroyed. 1052 * 1053 */ 1054 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) 1055 { 1056 struct intel_vgpu_submission *s = &vgpu->submission; 1057 1058 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 1059 i915_gem_context_put(s->shadow_ctx); 1060 kmem_cache_destroy(s->workloads); 1061 } 1062 1063 1064 /** 1065 * intel_vgpu_reset_submission - reset submission-related resource for vGPU 1066 * @vgpu: a vGPU 1067 * @engine_mask: engines expected to be reset 1068 * 1069 * This function is called when a vGPU is being destroyed. 1070 * 1071 */ 1072 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, 1073 unsigned long engine_mask) 1074 { 1075 struct intel_vgpu_submission *s = &vgpu->submission; 1076 1077 if (!s->active) 1078 return; 1079 1080 clean_workloads(vgpu, engine_mask); 1081 s->ops->reset(vgpu, engine_mask); 1082 } 1083 1084 /** 1085 * intel_vgpu_setup_submission - setup submission-related resource for vGPU 1086 * @vgpu: a vGPU 1087 * 1088 * This function is called when a vGPU is being created. 1089 * 1090 * Returns: 1091 * Zero on success, negative error code if failed. 1092 * 1093 */ 1094 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 1095 { 1096 struct intel_vgpu_submission *s = &vgpu->submission; 1097 enum intel_engine_id i; 1098 struct intel_engine_cs *engine; 1099 int ret; 1100 1101 s->shadow_ctx = i915_gem_context_create_gvt( 1102 &vgpu->gvt->dev_priv->drm); 1103 if (IS_ERR(s->shadow_ctx)) 1104 return PTR_ERR(s->shadow_ctx); 1105 1106 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); 1107 1108 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", 1109 sizeof(struct intel_vgpu_workload), 0, 1110 SLAB_HWCACHE_ALIGN, 1111 offsetof(struct intel_vgpu_workload, rb_tail), 1112 sizeof_field(struct intel_vgpu_workload, rb_tail), 1113 NULL); 1114 1115 if (!s->workloads) { 1116 ret = -ENOMEM; 1117 goto out_shadow_ctx; 1118 } 1119 1120 for_each_engine(engine, vgpu->gvt->dev_priv, i) 1121 INIT_LIST_HEAD(&s->workload_q_head[i]); 1122 1123 atomic_set(&s->running_workload_num, 0); 1124 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES); 1125 1126 return 0; 1127 1128 out_shadow_ctx: 1129 i915_gem_context_put(s->shadow_ctx); 1130 return ret; 1131 } 1132 1133 /** 1134 * intel_vgpu_select_submission_ops - select virtual submission interface 1135 * @vgpu: a vGPU 1136 * @interface: expected vGPU virtual submission interface 1137 * 1138 * This function is called when guest configures submission interface. 1139 * 1140 * Returns: 1141 * Zero on success, negative error code if failed. 1142 * 1143 */ 1144 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, 1145 unsigned long engine_mask, 1146 unsigned int interface) 1147 { 1148 struct intel_vgpu_submission *s = &vgpu->submission; 1149 const struct intel_vgpu_submission_ops *ops[] = { 1150 [INTEL_VGPU_EXECLIST_SUBMISSION] = 1151 &intel_vgpu_execlist_submission_ops, 1152 }; 1153 int ret; 1154 1155 if (WARN_ON(interface >= ARRAY_SIZE(ops))) 1156 return -EINVAL; 1157 1158 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES)) 1159 return -EINVAL; 1160 1161 if (s->active) 1162 s->ops->clean(vgpu, engine_mask); 1163 1164 if (interface == 0) { 1165 s->ops = NULL; 1166 s->virtual_submission_interface = 0; 1167 s->active = false; 1168 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); 1169 return 0; 1170 } 1171 1172 ret = ops[interface]->init(vgpu, engine_mask); 1173 if (ret) 1174 return ret; 1175 1176 s->ops = ops[interface]; 1177 s->virtual_submission_interface = interface; 1178 s->active = true; 1179 1180 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", 1181 vgpu->id, s->ops->name); 1182 1183 return 0; 1184 } 1185 1186 /** 1187 * intel_vgpu_destroy_workload - destroy a vGPU workload 1188 * @vgpu: a vGPU 1189 * 1190 * This function is called when destroy a vGPU workload. 1191 * 1192 */ 1193 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload) 1194 { 1195 struct intel_vgpu_submission *s = &workload->vgpu->submission; 1196 1197 if (workload->shadow_mm) 1198 intel_vgpu_mm_put(workload->shadow_mm); 1199 1200 kmem_cache_free(s->workloads, workload); 1201 } 1202 1203 static struct intel_vgpu_workload * 1204 alloc_workload(struct intel_vgpu *vgpu) 1205 { 1206 struct intel_vgpu_submission *s = &vgpu->submission; 1207 struct intel_vgpu_workload *workload; 1208 1209 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL); 1210 if (!workload) 1211 return ERR_PTR(-ENOMEM); 1212 1213 INIT_LIST_HEAD(&workload->list); 1214 INIT_LIST_HEAD(&workload->shadow_bb); 1215 1216 init_waitqueue_head(&workload->shadow_ctx_status_wq); 1217 atomic_set(&workload->shadow_ctx_active, 0); 1218 1219 workload->status = -EINPROGRESS; 1220 workload->vgpu = vgpu; 1221 1222 return workload; 1223 } 1224 1225 #define RING_CTX_OFF(x) \ 1226 offsetof(struct execlist_ring_context, x) 1227 1228 static void read_guest_pdps(struct intel_vgpu *vgpu, 1229 u64 ring_context_gpa, u32 pdp[8]) 1230 { 1231 u64 gpa; 1232 int i; 1233 1234 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); 1235 1236 for (i = 0; i < 8; i++) 1237 intel_gvt_hypervisor_read_gpa(vgpu, 1238 gpa + i * 8, &pdp[7 - i], 4); 1239 } 1240 1241 static int prepare_mm(struct intel_vgpu_workload *workload) 1242 { 1243 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc; 1244 struct intel_vgpu_mm *mm; 1245 struct intel_vgpu *vgpu = workload->vgpu; 1246 intel_gvt_gtt_type_t root_entry_type; 1247 u64 pdps[GVT_RING_CTX_NR_PDPS]; 1248 1249 switch (desc->addressing_mode) { 1250 case 1: /* legacy 32-bit */ 1251 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1252 break; 1253 case 3: /* legacy 64-bit */ 1254 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1255 break; 1256 default: 1257 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n"); 1258 return -EINVAL; 1259 } 1260 1261 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps); 1262 1263 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps); 1264 if (IS_ERR(mm)) 1265 return PTR_ERR(mm); 1266 1267 workload->shadow_mm = mm; 1268 return 0; 1269 } 1270 1271 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \ 1272 ((a)->lrca == (b)->lrca)) 1273 1274 #define get_last_workload(q) \ 1275 (list_empty(q) ? NULL : container_of(q->prev, \ 1276 struct intel_vgpu_workload, list)) 1277 /** 1278 * intel_vgpu_create_workload - create a vGPU workload 1279 * @vgpu: a vGPU 1280 * @desc: a guest context descriptor 1281 * 1282 * This function is called when creating a vGPU workload. 1283 * 1284 * Returns: 1285 * struct intel_vgpu_workload * on success, negative error code in 1286 * pointer if failed. 1287 * 1288 */ 1289 struct intel_vgpu_workload * 1290 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, 1291 struct execlist_ctx_descriptor_format *desc) 1292 { 1293 struct intel_vgpu_submission *s = &vgpu->submission; 1294 struct list_head *q = workload_q_head(vgpu, ring_id); 1295 struct intel_vgpu_workload *last_workload = get_last_workload(q); 1296 struct intel_vgpu_workload *workload = NULL; 1297 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1298 u64 ring_context_gpa; 1299 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; 1300 int ret; 1301 1302 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 1303 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT)); 1304 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) { 1305 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca); 1306 return ERR_PTR(-EINVAL); 1307 } 1308 1309 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1310 RING_CTX_OFF(ring_header.val), &head, 4); 1311 1312 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1313 RING_CTX_OFF(ring_tail.val), &tail, 4); 1314 1315 head &= RB_HEAD_OFF_MASK; 1316 tail &= RB_TAIL_OFF_MASK; 1317 1318 if (last_workload && same_context(&last_workload->ctx_desc, desc)) { 1319 gvt_dbg_el("ring id %d cur workload == last\n", ring_id); 1320 gvt_dbg_el("ctx head %x real head %lx\n", head, 1321 last_workload->rb_tail); 1322 /* 1323 * cannot use guest context head pointer here, 1324 * as it might not be updated at this time 1325 */ 1326 head = last_workload->rb_tail; 1327 } 1328 1329 gvt_dbg_el("ring id %d begin a new workload\n", ring_id); 1330 1331 /* record some ring buffer register values for scan and shadow */ 1332 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1333 RING_CTX_OFF(rb_start.val), &start, 4); 1334 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1335 RING_CTX_OFF(rb_ctrl.val), &ctl, 4); 1336 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1337 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); 1338 1339 workload = alloc_workload(vgpu); 1340 if (IS_ERR(workload)) 1341 return workload; 1342 1343 workload->ring_id = ring_id; 1344 workload->ctx_desc = *desc; 1345 workload->ring_context_gpa = ring_context_gpa; 1346 workload->rb_head = head; 1347 workload->rb_tail = tail; 1348 workload->rb_start = start; 1349 workload->rb_ctl = ctl; 1350 1351 if (ring_id == RCS) { 1352 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1353 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); 1354 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1355 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4); 1356 1357 workload->wa_ctx.indirect_ctx.guest_gma = 1358 indirect_ctx & INDIRECT_CTX_ADDR_MASK; 1359 workload->wa_ctx.indirect_ctx.size = 1360 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * 1361 CACHELINE_BYTES; 1362 workload->wa_ctx.per_ctx.guest_gma = 1363 per_ctx & PER_CTX_ADDR_MASK; 1364 workload->wa_ctx.per_ctx.valid = per_ctx & 1; 1365 } 1366 1367 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", 1368 workload, ring_id, head, tail, start, ctl); 1369 1370 ret = prepare_mm(workload); 1371 if (ret) { 1372 kmem_cache_free(s->workloads, workload); 1373 return ERR_PTR(ret); 1374 } 1375 1376 /* Only scan and shadow the first workload in the queue 1377 * as there is only one pre-allocated buf-obj for shadow. 1378 */ 1379 if (list_empty(workload_q_head(vgpu, ring_id))) { 1380 intel_runtime_pm_get(dev_priv); 1381 mutex_lock(&dev_priv->drm.struct_mutex); 1382 ret = intel_gvt_scan_and_shadow_workload(workload); 1383 mutex_unlock(&dev_priv->drm.struct_mutex); 1384 intel_runtime_pm_put(dev_priv); 1385 } 1386 1387 if (ret && (vgpu_is_vm_unhealthy(ret))) { 1388 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1389 intel_vgpu_destroy_workload(workload); 1390 return ERR_PTR(ret); 1391 } 1392 1393 return workload; 1394 } 1395 1396 /** 1397 * intel_vgpu_queue_workload - Qeue a vGPU workload 1398 * @workload: the workload to queue in 1399 */ 1400 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) 1401 { 1402 list_add_tail(&workload->list, 1403 workload_q_head(workload->vgpu, workload->ring_id)); 1404 intel_gvt_kick_schedule(workload->vgpu->gvt); 1405 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]); 1406 } 1407