1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36 #include <linux/kthread.h> 37 38 #include "gem/i915_gem_context.h" 39 #include "gem/i915_gem_pm.h" 40 #include "gt/intel_context.h" 41 42 #include "i915_drv.h" 43 #include "gvt.h" 44 45 #define RING_CTX_OFF(x) \ 46 offsetof(struct execlist_ring_context, x) 47 48 static void set_context_pdp_root_pointer( 49 struct execlist_ring_context *ring_context, 50 u32 pdp[8]) 51 { 52 int i; 53 54 for (i = 0; i < 8; i++) 55 ring_context->pdps[i].val = pdp[7 - i]; 56 } 57 58 static void update_shadow_pdps(struct intel_vgpu_workload *workload) 59 { 60 struct drm_i915_gem_object *ctx_obj = 61 workload->req->hw_context->state->obj; 62 struct execlist_ring_context *shadow_ring_context; 63 struct page *page; 64 65 if (WARN_ON(!workload->shadow_mm)) 66 return; 67 68 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount))) 69 return; 70 71 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 72 shadow_ring_context = kmap(page); 73 set_context_pdp_root_pointer(shadow_ring_context, 74 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); 75 kunmap(page); 76 } 77 78 /* 79 * when populating shadow ctx from guest, we should not overrride oa related 80 * registers, so that they will not be overlapped by guest oa configs. Thus 81 * made it possible to capture oa data from host for both host and guests. 82 */ 83 static void sr_oa_regs(struct intel_vgpu_workload *workload, 84 u32 *reg_state, bool save) 85 { 86 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 87 u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset; 88 u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset; 89 int i = 0; 90 u32 flex_mmio[] = { 91 i915_mmio_reg_offset(EU_PERF_CNTL0), 92 i915_mmio_reg_offset(EU_PERF_CNTL1), 93 i915_mmio_reg_offset(EU_PERF_CNTL2), 94 i915_mmio_reg_offset(EU_PERF_CNTL3), 95 i915_mmio_reg_offset(EU_PERF_CNTL4), 96 i915_mmio_reg_offset(EU_PERF_CNTL5), 97 i915_mmio_reg_offset(EU_PERF_CNTL6), 98 }; 99 100 if (workload->ring_id != RCS0) 101 return; 102 103 if (save) { 104 workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; 105 106 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 107 u32 state_offset = ctx_flexeu0 + i * 2; 108 109 workload->flex_mmio[i] = reg_state[state_offset + 1]; 110 } 111 } else { 112 reg_state[ctx_oactxctrl] = 113 i915_mmio_reg_offset(GEN8_OACTXCONTROL); 114 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; 115 116 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 117 u32 state_offset = ctx_flexeu0 + i * 2; 118 u32 mmio = flex_mmio[i]; 119 120 reg_state[state_offset] = mmio; 121 reg_state[state_offset + 1] = workload->flex_mmio[i]; 122 } 123 } 124 } 125 126 static int populate_shadow_context(struct intel_vgpu_workload *workload) 127 { 128 struct intel_vgpu *vgpu = workload->vgpu; 129 struct intel_gvt *gvt = vgpu->gvt; 130 int ring_id = workload->ring_id; 131 struct drm_i915_gem_object *ctx_obj = 132 workload->req->hw_context->state->obj; 133 struct execlist_ring_context *shadow_ring_context; 134 struct page *page; 135 void *dst; 136 unsigned long context_gpa, context_page_num; 137 int i; 138 139 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 140 shadow_ring_context = kmap(page); 141 142 sr_oa_regs(workload, (u32 *)shadow_ring_context, true); 143 #define COPY_REG(name) \ 144 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 145 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 146 #define COPY_REG_MASKED(name) {\ 147 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 148 + RING_CTX_OFF(name.val),\ 149 &shadow_ring_context->name.val, 4);\ 150 shadow_ring_context->name.val |= 0xffff << 16;\ 151 } 152 153 COPY_REG_MASKED(ctx_ctrl); 154 COPY_REG(ctx_timestamp); 155 156 if (ring_id == RCS0) { 157 COPY_REG(bb_per_ctx_ptr); 158 COPY_REG(rcs_indirect_ctx); 159 COPY_REG(rcs_indirect_ctx_offset); 160 } 161 #undef COPY_REG 162 #undef COPY_REG_MASKED 163 164 intel_gvt_hypervisor_read_gpa(vgpu, 165 workload->ring_context_gpa + 166 sizeof(*shadow_ring_context), 167 (void *)shadow_ring_context + 168 sizeof(*shadow_ring_context), 169 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 170 171 sr_oa_regs(workload, (u32 *)shadow_ring_context, false); 172 kunmap(page); 173 174 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val)) 175 return 0; 176 177 gvt_dbg_sched("ring id %d workload lrca %x", ring_id, 178 workload->ctx_desc.lrca); 179 180 context_page_num = gvt->dev_priv->engine[ring_id]->context_size; 181 182 context_page_num = context_page_num >> PAGE_SHIFT; 183 184 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0) 185 context_page_num = 19; 186 187 i = 2; 188 while (i < context_page_num) { 189 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 190 (u32)((workload->ctx_desc.lrca + i) << 191 I915_GTT_PAGE_SHIFT)); 192 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 193 gvt_vgpu_err("Invalid guest context descriptor\n"); 194 return -EFAULT; 195 } 196 197 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 198 dst = kmap(page); 199 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, 200 I915_GTT_PAGE_SIZE); 201 kunmap(page); 202 i++; 203 } 204 return 0; 205 } 206 207 static inline bool is_gvt_request(struct i915_request *req) 208 { 209 return i915_gem_context_force_single_submission(req->gem_context); 210 } 211 212 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) 213 { 214 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 215 u32 ring_base = dev_priv->engine[ring_id]->mmio_base; 216 i915_reg_t reg; 217 218 reg = RING_INSTDONE(ring_base); 219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 220 reg = RING_ACTHD(ring_base); 221 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 222 reg = RING_ACTHD_UDW(ring_base); 223 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 224 } 225 226 static int shadow_context_status_change(struct notifier_block *nb, 227 unsigned long action, void *data) 228 { 229 struct i915_request *req = data; 230 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, 231 shadow_ctx_notifier_block[req->engine->id]); 232 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 233 enum intel_engine_id ring_id = req->engine->id; 234 struct intel_vgpu_workload *workload; 235 unsigned long flags; 236 237 if (!is_gvt_request(req)) { 238 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 239 if (action == INTEL_CONTEXT_SCHEDULE_IN && 240 scheduler->engine_owner[ring_id]) { 241 /* Switch ring from vGPU to host. */ 242 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 243 NULL, ring_id); 244 scheduler->engine_owner[ring_id] = NULL; 245 } 246 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 247 248 return NOTIFY_OK; 249 } 250 251 workload = scheduler->current_workload[ring_id]; 252 if (unlikely(!workload)) 253 return NOTIFY_OK; 254 255 switch (action) { 256 case INTEL_CONTEXT_SCHEDULE_IN: 257 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 258 if (workload->vgpu != scheduler->engine_owner[ring_id]) { 259 /* Switch ring from host to vGPU or vGPU to vGPU. */ 260 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 261 workload->vgpu, ring_id); 262 scheduler->engine_owner[ring_id] = workload->vgpu; 263 } else 264 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n", 265 ring_id, workload->vgpu->id); 266 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 267 atomic_set(&workload->shadow_ctx_active, 1); 268 break; 269 case INTEL_CONTEXT_SCHEDULE_OUT: 270 save_ring_hw_state(workload->vgpu, ring_id); 271 atomic_set(&workload->shadow_ctx_active, 0); 272 break; 273 case INTEL_CONTEXT_SCHEDULE_PREEMPTED: 274 save_ring_hw_state(workload->vgpu, ring_id); 275 break; 276 default: 277 WARN_ON(1); 278 return NOTIFY_OK; 279 } 280 wake_up(&workload->shadow_ctx_status_wq); 281 return NOTIFY_OK; 282 } 283 284 static void 285 shadow_context_descriptor_update(struct intel_context *ce, 286 struct intel_vgpu_workload *workload) 287 { 288 u64 desc = ce->lrc_desc; 289 290 /* 291 * Update bits 0-11 of the context descriptor which includes flags 292 * like GEN8_CTX_* cached in desc_template 293 */ 294 desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); 295 desc |= workload->ctx_desc.addressing_mode << 296 GEN8_CTX_ADDRESSING_MODE_SHIFT; 297 298 ce->lrc_desc = desc; 299 } 300 301 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) 302 { 303 struct intel_vgpu *vgpu = workload->vgpu; 304 struct i915_request *req = workload->req; 305 void *shadow_ring_buffer_va; 306 u32 *cs; 307 int err; 308 309 if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context)) 310 intel_vgpu_restore_inhibit_context(vgpu, req); 311 312 /* 313 * To track whether a request has started on HW, we can emit a 314 * breadcrumb at the beginning of the request and check its 315 * timeline's HWSP to see if the breadcrumb has advanced past the 316 * start of this request. Actually, the request must have the 317 * init_breadcrumb if its timeline set has_init_bread_crumb, or the 318 * scheduler might get a wrong state of it during reset. Since the 319 * requests from gvt always set the has_init_breadcrumb flag, here 320 * need to do the emit_init_breadcrumb for all the requests. 321 */ 322 if (req->engine->emit_init_breadcrumb) { 323 err = req->engine->emit_init_breadcrumb(req); 324 if (err) { 325 gvt_vgpu_err("fail to emit init breadcrumb\n"); 326 return err; 327 } 328 } 329 330 /* allocate shadow ring buffer */ 331 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32)); 332 if (IS_ERR(cs)) { 333 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", 334 workload->rb_len); 335 return PTR_ERR(cs); 336 } 337 338 shadow_ring_buffer_va = workload->shadow_ring_buffer_va; 339 340 /* get shadow ring buffer va */ 341 workload->shadow_ring_buffer_va = cs; 342 343 memcpy(cs, shadow_ring_buffer_va, 344 workload->rb_len); 345 346 cs += workload->rb_len / sizeof(u32); 347 intel_ring_advance(workload->req, cs); 348 349 return 0; 350 } 351 352 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 353 { 354 if (!wa_ctx->indirect_ctx.obj) 355 return; 356 357 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj); 358 i915_gem_object_put(wa_ctx->indirect_ctx.obj); 359 360 wa_ctx->indirect_ctx.obj = NULL; 361 wa_ctx->indirect_ctx.shadow_va = NULL; 362 } 363 364 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, 365 struct i915_gem_context *ctx) 366 { 367 struct intel_vgpu_mm *mm = workload->shadow_mm; 368 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm); 369 int i = 0; 370 371 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { 372 px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0]; 373 } else { 374 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) { 375 struct i915_page_directory * const pd = 376 i915_pd_entry(ppgtt->pd, i); 377 378 px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i]; 379 } 380 } 381 } 382 383 static int 384 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload) 385 { 386 struct intel_vgpu *vgpu = workload->vgpu; 387 struct intel_vgpu_submission *s = &vgpu->submission; 388 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 389 struct i915_request *rq; 390 391 lockdep_assert_held(&dev_priv->drm.struct_mutex); 392 393 if (workload->req) 394 return 0; 395 396 rq = i915_request_create(s->shadow[workload->ring_id]); 397 if (IS_ERR(rq)) { 398 gvt_vgpu_err("fail to allocate gem request\n"); 399 return PTR_ERR(rq); 400 } 401 402 workload->req = i915_request_get(rq); 403 return 0; 404 } 405 406 /** 407 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and 408 * shadow it as well, include ringbuffer,wa_ctx and ctx. 409 * @workload: an abstract entity for each execlist submission. 410 * 411 * This function is called before the workload submitting to i915, to make 412 * sure the content of the workload is valid. 413 */ 414 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) 415 { 416 struct intel_vgpu *vgpu = workload->vgpu; 417 struct intel_vgpu_submission *s = &vgpu->submission; 418 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 419 int ret; 420 421 lockdep_assert_held(&dev_priv->drm.struct_mutex); 422 423 if (workload->shadow) 424 return 0; 425 426 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated)) 427 shadow_context_descriptor_update(s->shadow[workload->ring_id], 428 workload); 429 430 ret = intel_gvt_scan_and_shadow_ringbuffer(workload); 431 if (ret) 432 return ret; 433 434 if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) { 435 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 436 if (ret) 437 goto err_shadow; 438 } 439 440 workload->shadow = true; 441 return 0; 442 err_shadow: 443 release_shadow_wa_ctx(&workload->wa_ctx); 444 return ret; 445 } 446 447 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload); 448 449 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 450 { 451 struct intel_gvt *gvt = workload->vgpu->gvt; 452 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 453 struct intel_vgpu_shadow_bb *bb; 454 int ret; 455 456 list_for_each_entry(bb, &workload->shadow_bb, list) { 457 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va 458 * is only updated into ring_scan_buffer, not real ring address 459 * allocated in later copy_workload_to_ring_buffer. pls be noted 460 * shadow_ring_buffer_va is now pointed to real ring buffer va 461 * in copy_workload_to_ring_buffer. 462 */ 463 464 if (bb->bb_offset) 465 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va 466 + bb->bb_offset; 467 468 if (bb->ppgtt) { 469 /* for non-priv bb, scan&shadow is only for 470 * debugging purpose, so the content of shadow bb 471 * is the same as original bb. Therefore, 472 * here, rather than switch to shadow bb's gma 473 * address, we directly use original batch buffer's 474 * gma address, and send original bb to hardware 475 * directly 476 */ 477 if (bb->clflush & CLFLUSH_AFTER) { 478 drm_clflush_virt_range(bb->va, 479 bb->obj->base.size); 480 bb->clflush &= ~CLFLUSH_AFTER; 481 } 482 i915_gem_object_finish_access(bb->obj); 483 bb->accessing = false; 484 485 } else { 486 bb->vma = i915_gem_object_ggtt_pin(bb->obj, 487 NULL, 0, 0, 0); 488 if (IS_ERR(bb->vma)) { 489 ret = PTR_ERR(bb->vma); 490 goto err; 491 } 492 493 /* relocate shadow batch buffer */ 494 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); 495 if (gmadr_bytes == 8) 496 bb->bb_start_cmd_va[2] = 0; 497 498 /* No one is going to touch shadow bb from now on. */ 499 if (bb->clflush & CLFLUSH_AFTER) { 500 drm_clflush_virt_range(bb->va, 501 bb->obj->base.size); 502 bb->clflush &= ~CLFLUSH_AFTER; 503 } 504 505 ret = i915_gem_object_set_to_gtt_domain(bb->obj, 506 false); 507 if (ret) 508 goto err; 509 510 ret = i915_vma_move_to_active(bb->vma, 511 workload->req, 512 0); 513 if (ret) 514 goto err; 515 516 i915_gem_object_finish_access(bb->obj); 517 bb->accessing = false; 518 } 519 } 520 return 0; 521 err: 522 release_shadow_batch_buffer(workload); 523 return ret; 524 } 525 526 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx) 527 { 528 struct intel_vgpu_workload *workload = 529 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx); 530 struct i915_request *rq = workload->req; 531 struct execlist_ring_context *shadow_ring_context = 532 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state; 533 534 shadow_ring_context->bb_per_ctx_ptr.val = 535 (shadow_ring_context->bb_per_ctx_ptr.val & 536 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma; 537 shadow_ring_context->rcs_indirect_ctx.val = 538 (shadow_ring_context->rcs_indirect_ctx.val & 539 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma; 540 } 541 542 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 543 { 544 struct i915_vma *vma; 545 unsigned char *per_ctx_va = 546 (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 547 wa_ctx->indirect_ctx.size; 548 549 if (wa_ctx->indirect_ctx.size == 0) 550 return 0; 551 552 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL, 553 0, CACHELINE_BYTES, 0); 554 if (IS_ERR(vma)) 555 return PTR_ERR(vma); 556 557 /* FIXME: we are not tracking our pinned VMA leaving it 558 * up to the core to fix up the stray pin_count upon 559 * free. 560 */ 561 562 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); 563 564 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1); 565 memset(per_ctx_va, 0, CACHELINE_BYTES); 566 567 update_wa_ctx_2_shadow_ctx(wa_ctx); 568 return 0; 569 } 570 571 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 572 { 573 struct intel_vgpu *vgpu = workload->vgpu; 574 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 575 struct intel_vgpu_shadow_bb *bb, *pos; 576 577 if (list_empty(&workload->shadow_bb)) 578 return; 579 580 bb = list_first_entry(&workload->shadow_bb, 581 struct intel_vgpu_shadow_bb, list); 582 583 mutex_lock(&dev_priv->drm.struct_mutex); 584 585 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { 586 if (bb->obj) { 587 if (bb->accessing) 588 i915_gem_object_finish_access(bb->obj); 589 590 if (bb->va && !IS_ERR(bb->va)) 591 i915_gem_object_unpin_map(bb->obj); 592 593 if (bb->vma && !IS_ERR(bb->vma)) { 594 i915_vma_unpin(bb->vma); 595 i915_vma_close(bb->vma); 596 } 597 i915_gem_object_put(bb->obj); 598 } 599 list_del(&bb->list); 600 kfree(bb); 601 } 602 603 mutex_unlock(&dev_priv->drm.struct_mutex); 604 } 605 606 static int prepare_workload(struct intel_vgpu_workload *workload) 607 { 608 struct intel_vgpu *vgpu = workload->vgpu; 609 struct intel_vgpu_submission *s = &vgpu->submission; 610 int ring = workload->ring_id; 611 int ret = 0; 612 613 ret = intel_vgpu_pin_mm(workload->shadow_mm); 614 if (ret) { 615 gvt_vgpu_err("fail to vgpu pin mm\n"); 616 return ret; 617 } 618 619 if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT || 620 !workload->shadow_mm->ppgtt_mm.shadowed) { 621 gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); 622 return -EINVAL; 623 } 624 625 update_shadow_pdps(workload); 626 627 set_context_ppgtt_from_shadow(workload, s->shadow[ring]->gem_context); 628 629 ret = intel_vgpu_sync_oos_pages(workload->vgpu); 630 if (ret) { 631 gvt_vgpu_err("fail to vgpu sync oos pages\n"); 632 goto err_unpin_mm; 633 } 634 635 ret = intel_vgpu_flush_post_shadow(workload->vgpu); 636 if (ret) { 637 gvt_vgpu_err("fail to flush post shadow\n"); 638 goto err_unpin_mm; 639 } 640 641 ret = copy_workload_to_ring_buffer(workload); 642 if (ret) { 643 gvt_vgpu_err("fail to generate request\n"); 644 goto err_unpin_mm; 645 } 646 647 ret = prepare_shadow_batch_buffer(workload); 648 if (ret) { 649 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n"); 650 goto err_unpin_mm; 651 } 652 653 ret = prepare_shadow_wa_ctx(&workload->wa_ctx); 654 if (ret) { 655 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n"); 656 goto err_shadow_batch; 657 } 658 659 if (workload->prepare) { 660 ret = workload->prepare(workload); 661 if (ret) 662 goto err_shadow_wa_ctx; 663 } 664 665 return 0; 666 err_shadow_wa_ctx: 667 release_shadow_wa_ctx(&workload->wa_ctx); 668 err_shadow_batch: 669 release_shadow_batch_buffer(workload); 670 err_unpin_mm: 671 intel_vgpu_unpin_mm(workload->shadow_mm); 672 return ret; 673 } 674 675 static int dispatch_workload(struct intel_vgpu_workload *workload) 676 { 677 struct intel_vgpu *vgpu = workload->vgpu; 678 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 679 struct i915_request *rq; 680 int ring_id = workload->ring_id; 681 int ret; 682 683 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", 684 ring_id, workload); 685 686 mutex_lock(&vgpu->vgpu_lock); 687 mutex_lock(&dev_priv->drm.struct_mutex); 688 689 ret = intel_gvt_workload_req_alloc(workload); 690 if (ret) 691 goto err_req; 692 693 ret = intel_gvt_scan_and_shadow_workload(workload); 694 if (ret) 695 goto out; 696 697 ret = populate_shadow_context(workload); 698 if (ret) { 699 release_shadow_wa_ctx(&workload->wa_ctx); 700 goto out; 701 } 702 703 ret = prepare_workload(workload); 704 out: 705 if (ret) { 706 /* We might still need to add request with 707 * clean ctx to retire it properly.. 708 */ 709 rq = fetch_and_zero(&workload->req); 710 i915_request_put(rq); 711 } 712 713 if (!IS_ERR_OR_NULL(workload->req)) { 714 gvt_dbg_sched("ring id %d submit workload to i915 %p\n", 715 ring_id, workload->req); 716 i915_request_add(workload->req); 717 workload->dispatched = true; 718 } 719 err_req: 720 if (ret) 721 workload->status = ret; 722 mutex_unlock(&dev_priv->drm.struct_mutex); 723 mutex_unlock(&vgpu->vgpu_lock); 724 return ret; 725 } 726 727 static struct intel_vgpu_workload *pick_next_workload( 728 struct intel_gvt *gvt, int ring_id) 729 { 730 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 731 struct intel_vgpu_workload *workload = NULL; 732 733 mutex_lock(&gvt->sched_lock); 734 735 /* 736 * no current vgpu / will be scheduled out / no workload 737 * bail out 738 */ 739 if (!scheduler->current_vgpu) { 740 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id); 741 goto out; 742 } 743 744 if (scheduler->need_reschedule) { 745 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id); 746 goto out; 747 } 748 749 if (!scheduler->current_vgpu->active || 750 list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) 751 goto out; 752 753 /* 754 * still have current workload, maybe the workload disptacher 755 * fail to submit it for some reason, resubmit it. 756 */ 757 if (scheduler->current_workload[ring_id]) { 758 workload = scheduler->current_workload[ring_id]; 759 gvt_dbg_sched("ring id %d still have current workload %p\n", 760 ring_id, workload); 761 goto out; 762 } 763 764 /* 765 * pick a workload as current workload 766 * once current workload is set, schedule policy routines 767 * will wait the current workload is finished when trying to 768 * schedule out a vgpu. 769 */ 770 scheduler->current_workload[ring_id] = container_of( 771 workload_q_head(scheduler->current_vgpu, ring_id)->next, 772 struct intel_vgpu_workload, list); 773 774 workload = scheduler->current_workload[ring_id]; 775 776 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); 777 778 atomic_inc(&workload->vgpu->submission.running_workload_num); 779 out: 780 mutex_unlock(&gvt->sched_lock); 781 return workload; 782 } 783 784 static void update_guest_context(struct intel_vgpu_workload *workload) 785 { 786 struct i915_request *rq = workload->req; 787 struct intel_vgpu *vgpu = workload->vgpu; 788 struct intel_gvt *gvt = vgpu->gvt; 789 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj; 790 struct execlist_ring_context *shadow_ring_context; 791 struct page *page; 792 void *src; 793 unsigned long context_gpa, context_page_num; 794 int i; 795 struct drm_i915_private *dev_priv = gvt->dev_priv; 796 u32 ring_base; 797 u32 head, tail; 798 u16 wrap_count; 799 800 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id, 801 workload->ctx_desc.lrca); 802 803 head = workload->rb_head; 804 tail = workload->rb_tail; 805 wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF; 806 807 if (tail < head) { 808 if (wrap_count == RB_HEAD_WRAP_CNT_MAX) 809 wrap_count = 0; 810 else 811 wrap_count += 1; 812 } 813 814 head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail; 815 816 ring_base = dev_priv->engine[workload->ring_id]->mmio_base; 817 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; 818 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; 819 820 context_page_num = rq->engine->context_size; 821 context_page_num = context_page_num >> PAGE_SHIFT; 822 823 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0) 824 context_page_num = 19; 825 826 i = 2; 827 828 while (i < context_page_num) { 829 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 830 (u32)((workload->ctx_desc.lrca + i) << 831 I915_GTT_PAGE_SHIFT)); 832 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 833 gvt_vgpu_err("invalid guest context descriptor\n"); 834 return; 835 } 836 837 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 838 src = kmap(page); 839 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, 840 I915_GTT_PAGE_SIZE); 841 kunmap(page); 842 i++; 843 } 844 845 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 846 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 847 848 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 849 shadow_ring_context = kmap(page); 850 851 #define COPY_REG(name) \ 852 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 853 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 854 855 COPY_REG(ctx_ctrl); 856 COPY_REG(ctx_timestamp); 857 858 #undef COPY_REG 859 860 intel_gvt_hypervisor_write_gpa(vgpu, 861 workload->ring_context_gpa + 862 sizeof(*shadow_ring_context), 863 (void *)shadow_ring_context + 864 sizeof(*shadow_ring_context), 865 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 866 867 kunmap(page); 868 } 869 870 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu, 871 intel_engine_mask_t engine_mask) 872 { 873 struct intel_vgpu_submission *s = &vgpu->submission; 874 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 875 struct intel_engine_cs *engine; 876 struct intel_vgpu_workload *pos, *n; 877 intel_engine_mask_t tmp; 878 879 /* free the unsubmited workloads in the queues. */ 880 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { 881 list_for_each_entry_safe(pos, n, 882 &s->workload_q_head[engine->id], list) { 883 list_del_init(&pos->list); 884 intel_vgpu_destroy_workload(pos); 885 } 886 clear_bit(engine->id, s->shadow_ctx_desc_updated); 887 } 888 } 889 890 static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 891 { 892 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 893 struct intel_vgpu_workload *workload = 894 scheduler->current_workload[ring_id]; 895 struct intel_vgpu *vgpu = workload->vgpu; 896 struct intel_vgpu_submission *s = &vgpu->submission; 897 struct i915_request *rq = workload->req; 898 int event; 899 900 mutex_lock(&vgpu->vgpu_lock); 901 mutex_lock(&gvt->sched_lock); 902 903 /* For the workload w/ request, needs to wait for the context 904 * switch to make sure request is completed. 905 * For the workload w/o request, directly complete the workload. 906 */ 907 if (rq) { 908 wait_event(workload->shadow_ctx_status_wq, 909 !atomic_read(&workload->shadow_ctx_active)); 910 911 /* If this request caused GPU hang, req->fence.error will 912 * be set to -EIO. Use -EIO to set workload status so 913 * that when this request caused GPU hang, didn't trigger 914 * context switch interrupt to guest. 915 */ 916 if (likely(workload->status == -EINPROGRESS)) { 917 if (workload->req->fence.error == -EIO) 918 workload->status = -EIO; 919 else 920 workload->status = 0; 921 } 922 923 if (!workload->status && 924 !(vgpu->resetting_eng & BIT(ring_id))) { 925 update_guest_context(workload); 926 927 for_each_set_bit(event, workload->pending_events, 928 INTEL_GVT_EVENT_MAX) 929 intel_vgpu_trigger_virtual_event(vgpu, event); 930 } 931 932 i915_request_put(fetch_and_zero(&workload->req)); 933 } 934 935 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 936 ring_id, workload, workload->status); 937 938 scheduler->current_workload[ring_id] = NULL; 939 940 list_del_init(&workload->list); 941 942 if (workload->status || vgpu->resetting_eng & BIT(ring_id)) { 943 /* if workload->status is not successful means HW GPU 944 * has occurred GPU hang or something wrong with i915/GVT, 945 * and GVT won't inject context switch interrupt to guest. 946 * So this error is a vGPU hang actually to the guest. 947 * According to this we should emunlate a vGPU hang. If 948 * there are pending workloads which are already submitted 949 * from guest, we should clean them up like HW GPU does. 950 * 951 * if it is in middle of engine resetting, the pending 952 * workloads won't be submitted to HW GPU and will be 953 * cleaned up during the resetting process later, so doing 954 * the workload clean up here doesn't have any impact. 955 **/ 956 intel_vgpu_clean_workloads(vgpu, BIT(ring_id)); 957 } 958 959 workload->complete(workload); 960 961 atomic_dec(&s->running_workload_num); 962 wake_up(&scheduler->workload_complete_wq); 963 964 if (gvt->scheduler.need_reschedule) 965 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED); 966 967 mutex_unlock(&gvt->sched_lock); 968 mutex_unlock(&vgpu->vgpu_lock); 969 } 970 971 struct workload_thread_param { 972 struct intel_gvt *gvt; 973 int ring_id; 974 }; 975 976 static int workload_thread(void *priv) 977 { 978 struct workload_thread_param *p = (struct workload_thread_param *)priv; 979 struct intel_gvt *gvt = p->gvt; 980 int ring_id = p->ring_id; 981 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 982 struct intel_vgpu_workload *workload = NULL; 983 struct intel_vgpu *vgpu = NULL; 984 int ret; 985 bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9); 986 DEFINE_WAIT_FUNC(wait, woken_wake_function); 987 struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm; 988 989 kfree(p); 990 991 gvt_dbg_core("workload thread for ring %d started\n", ring_id); 992 993 while (!kthread_should_stop()) { 994 add_wait_queue(&scheduler->waitq[ring_id], &wait); 995 do { 996 workload = pick_next_workload(gvt, ring_id); 997 if (workload) 998 break; 999 wait_woken(&wait, TASK_INTERRUPTIBLE, 1000 MAX_SCHEDULE_TIMEOUT); 1001 } while (!kthread_should_stop()); 1002 remove_wait_queue(&scheduler->waitq[ring_id], &wait); 1003 1004 if (!workload) 1005 break; 1006 1007 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n", 1008 workload->ring_id, workload, 1009 workload->vgpu->id); 1010 1011 intel_runtime_pm_get(rpm); 1012 1013 gvt_dbg_sched("ring id %d will dispatch workload %p\n", 1014 workload->ring_id, workload); 1015 1016 if (need_force_wake) 1017 intel_uncore_forcewake_get(&gvt->dev_priv->uncore, 1018 FORCEWAKE_ALL); 1019 1020 ret = dispatch_workload(workload); 1021 1022 if (ret) { 1023 vgpu = workload->vgpu; 1024 gvt_vgpu_err("fail to dispatch workload, skip\n"); 1025 goto complete; 1026 } 1027 1028 gvt_dbg_sched("ring id %d wait workload %p\n", 1029 workload->ring_id, workload); 1030 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT); 1031 1032 complete: 1033 gvt_dbg_sched("will complete workload %p, status: %d\n", 1034 workload, workload->status); 1035 1036 complete_current_workload(gvt, ring_id); 1037 1038 if (need_force_wake) 1039 intel_uncore_forcewake_put(&gvt->dev_priv->uncore, 1040 FORCEWAKE_ALL); 1041 1042 intel_runtime_pm_put_unchecked(rpm); 1043 if (ret && (vgpu_is_vm_unhealthy(ret))) 1044 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1045 } 1046 return 0; 1047 } 1048 1049 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 1050 { 1051 struct intel_vgpu_submission *s = &vgpu->submission; 1052 struct intel_gvt *gvt = vgpu->gvt; 1053 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1054 1055 if (atomic_read(&s->running_workload_num)) { 1056 gvt_dbg_sched("wait vgpu idle\n"); 1057 1058 wait_event(scheduler->workload_complete_wq, 1059 !atomic_read(&s->running_workload_num)); 1060 } 1061 } 1062 1063 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 1064 { 1065 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1066 struct intel_engine_cs *engine; 1067 enum intel_engine_id i; 1068 1069 gvt_dbg_core("clean workload scheduler\n"); 1070 1071 for_each_engine(engine, gvt->dev_priv, i) { 1072 atomic_notifier_chain_unregister( 1073 &engine->context_status_notifier, 1074 &gvt->shadow_ctx_notifier_block[i]); 1075 kthread_stop(scheduler->thread[i]); 1076 } 1077 } 1078 1079 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 1080 { 1081 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1082 struct workload_thread_param *param = NULL; 1083 struct intel_engine_cs *engine; 1084 enum intel_engine_id i; 1085 int ret; 1086 1087 gvt_dbg_core("init workload scheduler\n"); 1088 1089 init_waitqueue_head(&scheduler->workload_complete_wq); 1090 1091 for_each_engine(engine, gvt->dev_priv, i) { 1092 init_waitqueue_head(&scheduler->waitq[i]); 1093 1094 param = kzalloc(sizeof(*param), GFP_KERNEL); 1095 if (!param) { 1096 ret = -ENOMEM; 1097 goto err; 1098 } 1099 1100 param->gvt = gvt; 1101 param->ring_id = i; 1102 1103 scheduler->thread[i] = kthread_run(workload_thread, param, 1104 "gvt workload %d", i); 1105 if (IS_ERR(scheduler->thread[i])) { 1106 gvt_err("fail to create workload thread\n"); 1107 ret = PTR_ERR(scheduler->thread[i]); 1108 goto err; 1109 } 1110 1111 gvt->shadow_ctx_notifier_block[i].notifier_call = 1112 shadow_context_status_change; 1113 atomic_notifier_chain_register(&engine->context_status_notifier, 1114 &gvt->shadow_ctx_notifier_block[i]); 1115 } 1116 return 0; 1117 err: 1118 intel_gvt_clean_workload_scheduler(gvt); 1119 kfree(param); 1120 param = NULL; 1121 return ret; 1122 } 1123 1124 static void 1125 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s, 1126 struct i915_ppgtt *ppgtt) 1127 { 1128 int i; 1129 1130 if (i915_vm_is_4lvl(&ppgtt->vm)) { 1131 px_dma(ppgtt->pd) = s->i915_context_pml4; 1132 } else { 1133 for (i = 0; i < GEN8_3LVL_PDPES; i++) { 1134 struct i915_page_directory * const pd = 1135 i915_pd_entry(ppgtt->pd, i); 1136 1137 px_dma(pd) = s->i915_context_pdps[i]; 1138 } 1139 } 1140 } 1141 1142 /** 1143 * intel_vgpu_clean_submission - free submission-related resource for vGPU 1144 * @vgpu: a vGPU 1145 * 1146 * This function is called when a vGPU is being destroyed. 1147 * 1148 */ 1149 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) 1150 { 1151 struct intel_vgpu_submission *s = &vgpu->submission; 1152 struct intel_engine_cs *engine; 1153 enum intel_engine_id id; 1154 1155 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 1156 1157 i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm)); 1158 for_each_engine(engine, vgpu->gvt->dev_priv, id) 1159 intel_context_unpin(s->shadow[id]); 1160 1161 kmem_cache_destroy(s->workloads); 1162 } 1163 1164 1165 /** 1166 * intel_vgpu_reset_submission - reset submission-related resource for vGPU 1167 * @vgpu: a vGPU 1168 * @engine_mask: engines expected to be reset 1169 * 1170 * This function is called when a vGPU is being destroyed. 1171 * 1172 */ 1173 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, 1174 intel_engine_mask_t engine_mask) 1175 { 1176 struct intel_vgpu_submission *s = &vgpu->submission; 1177 1178 if (!s->active) 1179 return; 1180 1181 intel_vgpu_clean_workloads(vgpu, engine_mask); 1182 s->ops->reset(vgpu, engine_mask); 1183 } 1184 1185 static void 1186 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s, 1187 struct i915_ppgtt *ppgtt) 1188 { 1189 int i; 1190 1191 if (i915_vm_is_4lvl(&ppgtt->vm)) { 1192 s->i915_context_pml4 = px_dma(ppgtt->pd); 1193 } else { 1194 for (i = 0; i < GEN8_3LVL_PDPES; i++) { 1195 struct i915_page_directory * const pd = 1196 i915_pd_entry(ppgtt->pd, i); 1197 1198 s->i915_context_pdps[i] = px_dma(pd); 1199 } 1200 } 1201 } 1202 1203 /** 1204 * intel_vgpu_setup_submission - setup submission-related resource for vGPU 1205 * @vgpu: a vGPU 1206 * 1207 * This function is called when a vGPU is being created. 1208 * 1209 * Returns: 1210 * Zero on success, negative error code if failed. 1211 * 1212 */ 1213 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 1214 { 1215 struct drm_i915_private *i915 = vgpu->gvt->dev_priv; 1216 struct intel_vgpu_submission *s = &vgpu->submission; 1217 struct intel_engine_cs *engine; 1218 struct i915_gem_context *ctx; 1219 enum intel_engine_id i; 1220 int ret; 1221 1222 mutex_lock(&i915->drm.struct_mutex); 1223 1224 ctx = i915_gem_context_create_kernel(i915, I915_PRIORITY_MAX); 1225 if (IS_ERR(ctx)) { 1226 ret = PTR_ERR(ctx); 1227 goto out_unlock; 1228 } 1229 1230 i915_gem_context_set_force_single_submission(ctx); 1231 1232 i915_context_ppgtt_root_save(s, i915_vm_to_ppgtt(ctx->vm)); 1233 1234 for_each_engine(engine, i915, i) { 1235 struct intel_context *ce; 1236 1237 INIT_LIST_HEAD(&s->workload_q_head[i]); 1238 s->shadow[i] = ERR_PTR(-EINVAL); 1239 1240 ce = intel_context_create(ctx, engine); 1241 if (IS_ERR(ce)) { 1242 ret = PTR_ERR(ce); 1243 goto out_shadow_ctx; 1244 } 1245 1246 if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */ 1247 const unsigned int ring_size = 512 * SZ_4K; 1248 1249 ce->ring = __intel_context_ring_size(ring_size); 1250 } 1251 1252 ret = intel_context_pin(ce); 1253 intel_context_put(ce); 1254 if (ret) 1255 goto out_shadow_ctx; 1256 1257 s->shadow[i] = ce; 1258 } 1259 1260 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); 1261 1262 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", 1263 sizeof(struct intel_vgpu_workload), 0, 1264 SLAB_HWCACHE_ALIGN, 1265 offsetof(struct intel_vgpu_workload, rb_tail), 1266 sizeof_field(struct intel_vgpu_workload, rb_tail), 1267 NULL); 1268 1269 if (!s->workloads) { 1270 ret = -ENOMEM; 1271 goto out_shadow_ctx; 1272 } 1273 1274 atomic_set(&s->running_workload_num, 0); 1275 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES); 1276 1277 i915_gem_context_put(ctx); 1278 mutex_unlock(&i915->drm.struct_mutex); 1279 return 0; 1280 1281 out_shadow_ctx: 1282 i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(ctx->vm)); 1283 for_each_engine(engine, i915, i) { 1284 if (IS_ERR(s->shadow[i])) 1285 break; 1286 1287 intel_context_unpin(s->shadow[i]); 1288 intel_context_put(s->shadow[i]); 1289 } 1290 i915_gem_context_put(ctx); 1291 out_unlock: 1292 mutex_unlock(&i915->drm.struct_mutex); 1293 return ret; 1294 } 1295 1296 /** 1297 * intel_vgpu_select_submission_ops - select virtual submission interface 1298 * @vgpu: a vGPU 1299 * @engine_mask: either ALL_ENGINES or target engine mask 1300 * @interface: expected vGPU virtual submission interface 1301 * 1302 * This function is called when guest configures submission interface. 1303 * 1304 * Returns: 1305 * Zero on success, negative error code if failed. 1306 * 1307 */ 1308 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, 1309 intel_engine_mask_t engine_mask, 1310 unsigned int interface) 1311 { 1312 struct intel_vgpu_submission *s = &vgpu->submission; 1313 const struct intel_vgpu_submission_ops *ops[] = { 1314 [INTEL_VGPU_EXECLIST_SUBMISSION] = 1315 &intel_vgpu_execlist_submission_ops, 1316 }; 1317 int ret; 1318 1319 if (WARN_ON(interface >= ARRAY_SIZE(ops))) 1320 return -EINVAL; 1321 1322 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES)) 1323 return -EINVAL; 1324 1325 if (s->active) 1326 s->ops->clean(vgpu, engine_mask); 1327 1328 if (interface == 0) { 1329 s->ops = NULL; 1330 s->virtual_submission_interface = 0; 1331 s->active = false; 1332 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); 1333 return 0; 1334 } 1335 1336 ret = ops[interface]->init(vgpu, engine_mask); 1337 if (ret) 1338 return ret; 1339 1340 s->ops = ops[interface]; 1341 s->virtual_submission_interface = interface; 1342 s->active = true; 1343 1344 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", 1345 vgpu->id, s->ops->name); 1346 1347 return 0; 1348 } 1349 1350 /** 1351 * intel_vgpu_destroy_workload - destroy a vGPU workload 1352 * @workload: workload to destroy 1353 * 1354 * This function is called when destroy a vGPU workload. 1355 * 1356 */ 1357 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload) 1358 { 1359 struct intel_vgpu_submission *s = &workload->vgpu->submission; 1360 1361 release_shadow_batch_buffer(workload); 1362 release_shadow_wa_ctx(&workload->wa_ctx); 1363 1364 if (workload->shadow_mm) 1365 intel_vgpu_mm_put(workload->shadow_mm); 1366 1367 kmem_cache_free(s->workloads, workload); 1368 } 1369 1370 static struct intel_vgpu_workload * 1371 alloc_workload(struct intel_vgpu *vgpu) 1372 { 1373 struct intel_vgpu_submission *s = &vgpu->submission; 1374 struct intel_vgpu_workload *workload; 1375 1376 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL); 1377 if (!workload) 1378 return ERR_PTR(-ENOMEM); 1379 1380 INIT_LIST_HEAD(&workload->list); 1381 INIT_LIST_HEAD(&workload->shadow_bb); 1382 1383 init_waitqueue_head(&workload->shadow_ctx_status_wq); 1384 atomic_set(&workload->shadow_ctx_active, 0); 1385 1386 workload->status = -EINPROGRESS; 1387 workload->vgpu = vgpu; 1388 1389 return workload; 1390 } 1391 1392 #define RING_CTX_OFF(x) \ 1393 offsetof(struct execlist_ring_context, x) 1394 1395 static void read_guest_pdps(struct intel_vgpu *vgpu, 1396 u64 ring_context_gpa, u32 pdp[8]) 1397 { 1398 u64 gpa; 1399 int i; 1400 1401 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); 1402 1403 for (i = 0; i < 8; i++) 1404 intel_gvt_hypervisor_read_gpa(vgpu, 1405 gpa + i * 8, &pdp[7 - i], 4); 1406 } 1407 1408 static int prepare_mm(struct intel_vgpu_workload *workload) 1409 { 1410 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc; 1411 struct intel_vgpu_mm *mm; 1412 struct intel_vgpu *vgpu = workload->vgpu; 1413 enum intel_gvt_gtt_type root_entry_type; 1414 u64 pdps[GVT_RING_CTX_NR_PDPS]; 1415 1416 switch (desc->addressing_mode) { 1417 case 1: /* legacy 32-bit */ 1418 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1419 break; 1420 case 3: /* legacy 64-bit */ 1421 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1422 break; 1423 default: 1424 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n"); 1425 return -EINVAL; 1426 } 1427 1428 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps); 1429 1430 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps); 1431 if (IS_ERR(mm)) 1432 return PTR_ERR(mm); 1433 1434 workload->shadow_mm = mm; 1435 return 0; 1436 } 1437 1438 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \ 1439 ((a)->lrca == (b)->lrca)) 1440 1441 #define get_last_workload(q) \ 1442 (list_empty(q) ? NULL : container_of(q->prev, \ 1443 struct intel_vgpu_workload, list)) 1444 /** 1445 * intel_vgpu_create_workload - create a vGPU workload 1446 * @vgpu: a vGPU 1447 * @ring_id: ring index 1448 * @desc: a guest context descriptor 1449 * 1450 * This function is called when creating a vGPU workload. 1451 * 1452 * Returns: 1453 * struct intel_vgpu_workload * on success, negative error code in 1454 * pointer if failed. 1455 * 1456 */ 1457 struct intel_vgpu_workload * 1458 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, 1459 struct execlist_ctx_descriptor_format *desc) 1460 { 1461 struct intel_vgpu_submission *s = &vgpu->submission; 1462 struct list_head *q = workload_q_head(vgpu, ring_id); 1463 struct intel_vgpu_workload *last_workload = get_last_workload(q); 1464 struct intel_vgpu_workload *workload = NULL; 1465 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1466 u64 ring_context_gpa; 1467 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; 1468 u32 guest_head; 1469 int ret; 1470 1471 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 1472 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT)); 1473 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) { 1474 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca); 1475 return ERR_PTR(-EINVAL); 1476 } 1477 1478 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1479 RING_CTX_OFF(ring_header.val), &head, 4); 1480 1481 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1482 RING_CTX_OFF(ring_tail.val), &tail, 4); 1483 1484 guest_head = head; 1485 1486 head &= RB_HEAD_OFF_MASK; 1487 tail &= RB_TAIL_OFF_MASK; 1488 1489 if (last_workload && same_context(&last_workload->ctx_desc, desc)) { 1490 gvt_dbg_el("ring id %d cur workload == last\n", ring_id); 1491 gvt_dbg_el("ctx head %x real head %lx\n", head, 1492 last_workload->rb_tail); 1493 /* 1494 * cannot use guest context head pointer here, 1495 * as it might not be updated at this time 1496 */ 1497 head = last_workload->rb_tail; 1498 } 1499 1500 gvt_dbg_el("ring id %d begin a new workload\n", ring_id); 1501 1502 /* record some ring buffer register values for scan and shadow */ 1503 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1504 RING_CTX_OFF(rb_start.val), &start, 4); 1505 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1506 RING_CTX_OFF(rb_ctrl.val), &ctl, 4); 1507 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1508 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); 1509 1510 if (!intel_gvt_ggtt_validate_range(vgpu, start, 1511 _RING_CTL_BUF_SIZE(ctl))) { 1512 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start); 1513 return ERR_PTR(-EINVAL); 1514 } 1515 1516 workload = alloc_workload(vgpu); 1517 if (IS_ERR(workload)) 1518 return workload; 1519 1520 workload->ring_id = ring_id; 1521 workload->ctx_desc = *desc; 1522 workload->ring_context_gpa = ring_context_gpa; 1523 workload->rb_head = head; 1524 workload->guest_rb_head = guest_head; 1525 workload->rb_tail = tail; 1526 workload->rb_start = start; 1527 workload->rb_ctl = ctl; 1528 1529 if (ring_id == RCS0) { 1530 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1531 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); 1532 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1533 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4); 1534 1535 workload->wa_ctx.indirect_ctx.guest_gma = 1536 indirect_ctx & INDIRECT_CTX_ADDR_MASK; 1537 workload->wa_ctx.indirect_ctx.size = 1538 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * 1539 CACHELINE_BYTES; 1540 1541 if (workload->wa_ctx.indirect_ctx.size != 0) { 1542 if (!intel_gvt_ggtt_validate_range(vgpu, 1543 workload->wa_ctx.indirect_ctx.guest_gma, 1544 workload->wa_ctx.indirect_ctx.size)) { 1545 kmem_cache_free(s->workloads, workload); 1546 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n", 1547 workload->wa_ctx.indirect_ctx.guest_gma); 1548 return ERR_PTR(-EINVAL); 1549 } 1550 } 1551 1552 workload->wa_ctx.per_ctx.guest_gma = 1553 per_ctx & PER_CTX_ADDR_MASK; 1554 workload->wa_ctx.per_ctx.valid = per_ctx & 1; 1555 if (workload->wa_ctx.per_ctx.valid) { 1556 if (!intel_gvt_ggtt_validate_range(vgpu, 1557 workload->wa_ctx.per_ctx.guest_gma, 1558 CACHELINE_BYTES)) { 1559 kmem_cache_free(s->workloads, workload); 1560 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n", 1561 workload->wa_ctx.per_ctx.guest_gma); 1562 return ERR_PTR(-EINVAL); 1563 } 1564 } 1565 } 1566 1567 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", 1568 workload, ring_id, head, tail, start, ctl); 1569 1570 ret = prepare_mm(workload); 1571 if (ret) { 1572 kmem_cache_free(s->workloads, workload); 1573 return ERR_PTR(ret); 1574 } 1575 1576 /* Only scan and shadow the first workload in the queue 1577 * as there is only one pre-allocated buf-obj for shadow. 1578 */ 1579 if (list_empty(workload_q_head(vgpu, ring_id))) { 1580 intel_runtime_pm_get(&dev_priv->runtime_pm); 1581 mutex_lock(&dev_priv->drm.struct_mutex); 1582 ret = intel_gvt_scan_and_shadow_workload(workload); 1583 mutex_unlock(&dev_priv->drm.struct_mutex); 1584 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 1585 } 1586 1587 if (ret) { 1588 if (vgpu_is_vm_unhealthy(ret)) 1589 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1590 intel_vgpu_destroy_workload(workload); 1591 return ERR_PTR(ret); 1592 } 1593 1594 return workload; 1595 } 1596 1597 /** 1598 * intel_vgpu_queue_workload - Qeue a vGPU workload 1599 * @workload: the workload to queue in 1600 */ 1601 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) 1602 { 1603 list_add_tail(&workload->list, 1604 workload_q_head(workload->vgpu, workload->ring_id)); 1605 intel_gvt_kick_schedule(workload->vgpu->gvt); 1606 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]); 1607 } 1608