xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/scheduler.c (revision 91db9311)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Zhi Wang <zhi.a.wang@intel.com>
25  *
26  * Contributors:
27  *    Ping Gao <ping.a.gao@intel.com>
28  *    Tina Zhang <tina.zhang@intel.com>
29  *    Chanbin Du <changbin.du@intel.com>
30  *    Min He <min.he@intel.com>
31  *    Bing Niu <bing.niu@intel.com>
32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
33  *
34  */
35 
36 #include <linux/kthread.h>
37 
38 #include "gem/i915_gem_context.h"
39 #include "gem/i915_gem_pm.h"
40 #include "gt/intel_context.h"
41 
42 #include "i915_drv.h"
43 #include "gvt.h"
44 
45 #define RING_CTX_OFF(x) \
46 	offsetof(struct execlist_ring_context, x)
47 
48 static void set_context_pdp_root_pointer(
49 		struct execlist_ring_context *ring_context,
50 		u32 pdp[8])
51 {
52 	int i;
53 
54 	for (i = 0; i < 8; i++)
55 		ring_context->pdps[i].val = pdp[7 - i];
56 }
57 
58 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
59 {
60 	struct drm_i915_gem_object *ctx_obj =
61 		workload->req->hw_context->state->obj;
62 	struct execlist_ring_context *shadow_ring_context;
63 	struct page *page;
64 
65 	if (WARN_ON(!workload->shadow_mm))
66 		return;
67 
68 	if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
69 		return;
70 
71 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
72 	shadow_ring_context = kmap(page);
73 	set_context_pdp_root_pointer(shadow_ring_context,
74 			(void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
75 	kunmap(page);
76 }
77 
78 /*
79  * when populating shadow ctx from guest, we should not overrride oa related
80  * registers, so that they will not be overlapped by guest oa configs. Thus
81  * made it possible to capture oa data from host for both host and guests.
82  */
83 static void sr_oa_regs(struct intel_vgpu_workload *workload,
84 		u32 *reg_state, bool save)
85 {
86 	struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
87 	u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset;
88 	u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset;
89 	int i = 0;
90 	u32 flex_mmio[] = {
91 		i915_mmio_reg_offset(EU_PERF_CNTL0),
92 		i915_mmio_reg_offset(EU_PERF_CNTL1),
93 		i915_mmio_reg_offset(EU_PERF_CNTL2),
94 		i915_mmio_reg_offset(EU_PERF_CNTL3),
95 		i915_mmio_reg_offset(EU_PERF_CNTL4),
96 		i915_mmio_reg_offset(EU_PERF_CNTL5),
97 		i915_mmio_reg_offset(EU_PERF_CNTL6),
98 	};
99 
100 	if (workload->ring_id != RCS0)
101 		return;
102 
103 	if (save) {
104 		workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
105 
106 		for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
107 			u32 state_offset = ctx_flexeu0 + i * 2;
108 
109 			workload->flex_mmio[i] = reg_state[state_offset + 1];
110 		}
111 	} else {
112 		reg_state[ctx_oactxctrl] =
113 			i915_mmio_reg_offset(GEN8_OACTXCONTROL);
114 		reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
115 
116 		for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
117 			u32 state_offset = ctx_flexeu0 + i * 2;
118 			u32 mmio = flex_mmio[i];
119 
120 			reg_state[state_offset] = mmio;
121 			reg_state[state_offset + 1] = workload->flex_mmio[i];
122 		}
123 	}
124 }
125 
126 static int populate_shadow_context(struct intel_vgpu_workload *workload)
127 {
128 	struct intel_vgpu *vgpu = workload->vgpu;
129 	struct intel_gvt *gvt = vgpu->gvt;
130 	int ring_id = workload->ring_id;
131 	struct drm_i915_gem_object *ctx_obj =
132 		workload->req->hw_context->state->obj;
133 	struct execlist_ring_context *shadow_ring_context;
134 	struct page *page;
135 	void *dst;
136 	unsigned long context_gpa, context_page_num;
137 	int i;
138 
139 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
140 	shadow_ring_context = kmap(page);
141 
142 	sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
143 #define COPY_REG(name) \
144 	intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
145 		+ RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
146 #define COPY_REG_MASKED(name) {\
147 		intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
148 					      + RING_CTX_OFF(name.val),\
149 					      &shadow_ring_context->name.val, 4);\
150 		shadow_ring_context->name.val |= 0xffff << 16;\
151 	}
152 
153 	COPY_REG_MASKED(ctx_ctrl);
154 	COPY_REG(ctx_timestamp);
155 
156 	if (ring_id == RCS0) {
157 		COPY_REG(bb_per_ctx_ptr);
158 		COPY_REG(rcs_indirect_ctx);
159 		COPY_REG(rcs_indirect_ctx_offset);
160 	}
161 #undef COPY_REG
162 #undef COPY_REG_MASKED
163 
164 	intel_gvt_hypervisor_read_gpa(vgpu,
165 			workload->ring_context_gpa +
166 			sizeof(*shadow_ring_context),
167 			(void *)shadow_ring_context +
168 			sizeof(*shadow_ring_context),
169 			I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
170 
171 	sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
172 	kunmap(page);
173 
174 	if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val))
175 		return 0;
176 
177 	gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
178 			workload->ctx_desc.lrca);
179 
180 	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
181 
182 	context_page_num = context_page_num >> PAGE_SHIFT;
183 
184 	if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
185 		context_page_num = 19;
186 
187 	i = 2;
188 	while (i < context_page_num) {
189 		context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
190 				(u32)((workload->ctx_desc.lrca + i) <<
191 				I915_GTT_PAGE_SHIFT));
192 		if (context_gpa == INTEL_GVT_INVALID_ADDR) {
193 			gvt_vgpu_err("Invalid guest context descriptor\n");
194 			return -EFAULT;
195 		}
196 
197 		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
198 		dst = kmap(page);
199 		intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
200 				I915_GTT_PAGE_SIZE);
201 		kunmap(page);
202 		i++;
203 	}
204 	return 0;
205 }
206 
207 static inline bool is_gvt_request(struct i915_request *req)
208 {
209 	return i915_gem_context_force_single_submission(req->gem_context);
210 }
211 
212 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id)
213 {
214 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
215 	u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
216 	i915_reg_t reg;
217 
218 	reg = RING_INSTDONE(ring_base);
219 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
220 	reg = RING_ACTHD(ring_base);
221 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
222 	reg = RING_ACTHD_UDW(ring_base);
223 	vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg);
224 }
225 
226 static int shadow_context_status_change(struct notifier_block *nb,
227 		unsigned long action, void *data)
228 {
229 	struct i915_request *req = data;
230 	struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
231 				shadow_ctx_notifier_block[req->engine->id]);
232 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
233 	enum intel_engine_id ring_id = req->engine->id;
234 	struct intel_vgpu_workload *workload;
235 	unsigned long flags;
236 
237 	if (!is_gvt_request(req)) {
238 		spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
239 		if (action == INTEL_CONTEXT_SCHEDULE_IN &&
240 		    scheduler->engine_owner[ring_id]) {
241 			/* Switch ring from vGPU to host. */
242 			intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
243 					      NULL, ring_id);
244 			scheduler->engine_owner[ring_id] = NULL;
245 		}
246 		spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
247 
248 		return NOTIFY_OK;
249 	}
250 
251 	workload = scheduler->current_workload[ring_id];
252 	if (unlikely(!workload))
253 		return NOTIFY_OK;
254 
255 	switch (action) {
256 	case INTEL_CONTEXT_SCHEDULE_IN:
257 		spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
258 		if (workload->vgpu != scheduler->engine_owner[ring_id]) {
259 			/* Switch ring from host to vGPU or vGPU to vGPU. */
260 			intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
261 					      workload->vgpu, ring_id);
262 			scheduler->engine_owner[ring_id] = workload->vgpu;
263 		} else
264 			gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
265 				      ring_id, workload->vgpu->id);
266 		spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
267 		atomic_set(&workload->shadow_ctx_active, 1);
268 		break;
269 	case INTEL_CONTEXT_SCHEDULE_OUT:
270 		save_ring_hw_state(workload->vgpu, ring_id);
271 		atomic_set(&workload->shadow_ctx_active, 0);
272 		break;
273 	case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
274 		save_ring_hw_state(workload->vgpu, ring_id);
275 		break;
276 	default:
277 		WARN_ON(1);
278 		return NOTIFY_OK;
279 	}
280 	wake_up(&workload->shadow_ctx_status_wq);
281 	return NOTIFY_OK;
282 }
283 
284 static void
285 shadow_context_descriptor_update(struct intel_context *ce,
286 				 struct intel_vgpu_workload *workload)
287 {
288 	u64 desc = ce->lrc_desc;
289 
290 	/*
291 	 * Update bits 0-11 of the context descriptor which includes flags
292 	 * like GEN8_CTX_* cached in desc_template
293 	 */
294 	desc &= U64_MAX << 12;
295 	desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
296 
297 	desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
298 	desc |= workload->ctx_desc.addressing_mode <<
299 		GEN8_CTX_ADDRESSING_MODE_SHIFT;
300 
301 	ce->lrc_desc = desc;
302 }
303 
304 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
305 {
306 	struct intel_vgpu *vgpu = workload->vgpu;
307 	struct i915_request *req = workload->req;
308 	void *shadow_ring_buffer_va;
309 	u32 *cs;
310 	int err;
311 
312 	if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context))
313 		intel_vgpu_restore_inhibit_context(vgpu, req);
314 
315 	/*
316 	 * To track whether a request has started on HW, we can emit a
317 	 * breadcrumb at the beginning of the request and check its
318 	 * timeline's HWSP to see if the breadcrumb has advanced past the
319 	 * start of this request. Actually, the request must have the
320 	 * init_breadcrumb if its timeline set has_init_bread_crumb, or the
321 	 * scheduler might get a wrong state of it during reset. Since the
322 	 * requests from gvt always set the has_init_breadcrumb flag, here
323 	 * need to do the emit_init_breadcrumb for all the requests.
324 	 */
325 	if (req->engine->emit_init_breadcrumb) {
326 		err = req->engine->emit_init_breadcrumb(req);
327 		if (err) {
328 			gvt_vgpu_err("fail to emit init breadcrumb\n");
329 			return err;
330 		}
331 	}
332 
333 	/* allocate shadow ring buffer */
334 	cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
335 	if (IS_ERR(cs)) {
336 		gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
337 			workload->rb_len);
338 		return PTR_ERR(cs);
339 	}
340 
341 	shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
342 
343 	/* get shadow ring buffer va */
344 	workload->shadow_ring_buffer_va = cs;
345 
346 	memcpy(cs, shadow_ring_buffer_va,
347 			workload->rb_len);
348 
349 	cs += workload->rb_len / sizeof(u32);
350 	intel_ring_advance(workload->req, cs);
351 
352 	return 0;
353 }
354 
355 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
356 {
357 	if (!wa_ctx->indirect_ctx.obj)
358 		return;
359 
360 	i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
361 	i915_gem_object_put(wa_ctx->indirect_ctx.obj);
362 
363 	wa_ctx->indirect_ctx.obj = NULL;
364 	wa_ctx->indirect_ctx.shadow_va = NULL;
365 }
366 
367 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
368 					  struct i915_gem_context *ctx)
369 {
370 	struct intel_vgpu_mm *mm = workload->shadow_mm;
371 	struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm);
372 	int i = 0;
373 
374 	if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
375 		px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
376 	} else {
377 		for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
378 			struct i915_page_directory * const pd =
379 				i915_pd_entry(ppgtt->pd, i);
380 
381 			px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
382 		}
383 	}
384 }
385 
386 static int
387 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
388 {
389 	struct intel_vgpu *vgpu = workload->vgpu;
390 	struct intel_vgpu_submission *s = &vgpu->submission;
391 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
392 	struct i915_request *rq;
393 
394 	lockdep_assert_held(&dev_priv->drm.struct_mutex);
395 
396 	if (workload->req)
397 		return 0;
398 
399 	rq = i915_request_create(s->shadow[workload->ring_id]);
400 	if (IS_ERR(rq)) {
401 		gvt_vgpu_err("fail to allocate gem request\n");
402 		return PTR_ERR(rq);
403 	}
404 
405 	workload->req = i915_request_get(rq);
406 	return 0;
407 }
408 
409 /**
410  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
411  * shadow it as well, include ringbuffer,wa_ctx and ctx.
412  * @workload: an abstract entity for each execlist submission.
413  *
414  * This function is called before the workload submitting to i915, to make
415  * sure the content of the workload is valid.
416  */
417 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
418 {
419 	struct intel_vgpu *vgpu = workload->vgpu;
420 	struct intel_vgpu_submission *s = &vgpu->submission;
421 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
422 	int ret;
423 
424 	lockdep_assert_held(&dev_priv->drm.struct_mutex);
425 
426 	if (workload->shadow)
427 		return 0;
428 
429 	if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated))
430 		shadow_context_descriptor_update(s->shadow[workload->ring_id],
431 						 workload);
432 
433 	ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
434 	if (ret)
435 		return ret;
436 
437 	if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
438 		ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
439 		if (ret)
440 			goto err_shadow;
441 	}
442 
443 	workload->shadow = true;
444 	return 0;
445 err_shadow:
446 	release_shadow_wa_ctx(&workload->wa_ctx);
447 	return ret;
448 }
449 
450 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
451 
452 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
453 {
454 	struct intel_gvt *gvt = workload->vgpu->gvt;
455 	const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
456 	struct intel_vgpu_shadow_bb *bb;
457 	int ret;
458 
459 	list_for_each_entry(bb, &workload->shadow_bb, list) {
460 		/* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
461 		 * is only updated into ring_scan_buffer, not real ring address
462 		 * allocated in later copy_workload_to_ring_buffer. pls be noted
463 		 * shadow_ring_buffer_va is now pointed to real ring buffer va
464 		 * in copy_workload_to_ring_buffer.
465 		 */
466 
467 		if (bb->bb_offset)
468 			bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
469 				+ bb->bb_offset;
470 
471 		if (bb->ppgtt) {
472 			/* for non-priv bb, scan&shadow is only for
473 			 * debugging purpose, so the content of shadow bb
474 			 * is the same as original bb. Therefore,
475 			 * here, rather than switch to shadow bb's gma
476 			 * address, we directly use original batch buffer's
477 			 * gma address, and send original bb to hardware
478 			 * directly
479 			 */
480 			if (bb->clflush & CLFLUSH_AFTER) {
481 				drm_clflush_virt_range(bb->va,
482 						bb->obj->base.size);
483 				bb->clflush &= ~CLFLUSH_AFTER;
484 			}
485 			i915_gem_object_finish_access(bb->obj);
486 			bb->accessing = false;
487 
488 		} else {
489 			bb->vma = i915_gem_object_ggtt_pin(bb->obj,
490 					NULL, 0, 0, 0);
491 			if (IS_ERR(bb->vma)) {
492 				ret = PTR_ERR(bb->vma);
493 				goto err;
494 			}
495 
496 			/* relocate shadow batch buffer */
497 			bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
498 			if (gmadr_bytes == 8)
499 				bb->bb_start_cmd_va[2] = 0;
500 
501 			/* No one is going to touch shadow bb from now on. */
502 			if (bb->clflush & CLFLUSH_AFTER) {
503 				drm_clflush_virt_range(bb->va,
504 						bb->obj->base.size);
505 				bb->clflush &= ~CLFLUSH_AFTER;
506 			}
507 
508 			ret = i915_gem_object_set_to_gtt_domain(bb->obj,
509 								false);
510 			if (ret)
511 				goto err;
512 
513 			ret = i915_vma_move_to_active(bb->vma,
514 						      workload->req,
515 						      0);
516 			if (ret)
517 				goto err;
518 
519 			i915_gem_object_finish_access(bb->obj);
520 			bb->accessing = false;
521 		}
522 	}
523 	return 0;
524 err:
525 	release_shadow_batch_buffer(workload);
526 	return ret;
527 }
528 
529 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
530 {
531 	struct intel_vgpu_workload *workload =
532 		container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
533 	struct i915_request *rq = workload->req;
534 	struct execlist_ring_context *shadow_ring_context =
535 		(struct execlist_ring_context *)rq->hw_context->lrc_reg_state;
536 
537 	shadow_ring_context->bb_per_ctx_ptr.val =
538 		(shadow_ring_context->bb_per_ctx_ptr.val &
539 		(~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
540 	shadow_ring_context->rcs_indirect_ctx.val =
541 		(shadow_ring_context->rcs_indirect_ctx.val &
542 		(~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
543 }
544 
545 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
546 {
547 	struct i915_vma *vma;
548 	unsigned char *per_ctx_va =
549 		(unsigned char *)wa_ctx->indirect_ctx.shadow_va +
550 		wa_ctx->indirect_ctx.size;
551 
552 	if (wa_ctx->indirect_ctx.size == 0)
553 		return 0;
554 
555 	vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
556 				       0, CACHELINE_BYTES, 0);
557 	if (IS_ERR(vma))
558 		return PTR_ERR(vma);
559 
560 	/* FIXME: we are not tracking our pinned VMA leaving it
561 	 * up to the core to fix up the stray pin_count upon
562 	 * free.
563 	 */
564 
565 	wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
566 
567 	wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
568 	memset(per_ctx_va, 0, CACHELINE_BYTES);
569 
570 	update_wa_ctx_2_shadow_ctx(wa_ctx);
571 	return 0;
572 }
573 
574 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
575 {
576 	struct intel_vgpu *vgpu = workload->vgpu;
577 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
578 	struct intel_vgpu_shadow_bb *bb, *pos;
579 
580 	if (list_empty(&workload->shadow_bb))
581 		return;
582 
583 	bb = list_first_entry(&workload->shadow_bb,
584 			struct intel_vgpu_shadow_bb, list);
585 
586 	mutex_lock(&dev_priv->drm.struct_mutex);
587 
588 	list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
589 		if (bb->obj) {
590 			if (bb->accessing)
591 				i915_gem_object_finish_access(bb->obj);
592 
593 			if (bb->va && !IS_ERR(bb->va))
594 				i915_gem_object_unpin_map(bb->obj);
595 
596 			if (bb->vma && !IS_ERR(bb->vma)) {
597 				i915_vma_unpin(bb->vma);
598 				i915_vma_close(bb->vma);
599 			}
600 			i915_gem_object_put(bb->obj);
601 		}
602 		list_del(&bb->list);
603 		kfree(bb);
604 	}
605 
606 	mutex_unlock(&dev_priv->drm.struct_mutex);
607 }
608 
609 static int prepare_workload(struct intel_vgpu_workload *workload)
610 {
611 	struct intel_vgpu *vgpu = workload->vgpu;
612 	struct intel_vgpu_submission *s = &vgpu->submission;
613 	int ring = workload->ring_id;
614 	int ret = 0;
615 
616 	ret = intel_vgpu_pin_mm(workload->shadow_mm);
617 	if (ret) {
618 		gvt_vgpu_err("fail to vgpu pin mm\n");
619 		return ret;
620 	}
621 
622 	if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
623 	    !workload->shadow_mm->ppgtt_mm.shadowed) {
624 		gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
625 		return -EINVAL;
626 	}
627 
628 	update_shadow_pdps(workload);
629 
630 	set_context_ppgtt_from_shadow(workload, s->shadow[ring]->gem_context);
631 
632 	ret = intel_vgpu_sync_oos_pages(workload->vgpu);
633 	if (ret) {
634 		gvt_vgpu_err("fail to vgpu sync oos pages\n");
635 		goto err_unpin_mm;
636 	}
637 
638 	ret = intel_vgpu_flush_post_shadow(workload->vgpu);
639 	if (ret) {
640 		gvt_vgpu_err("fail to flush post shadow\n");
641 		goto err_unpin_mm;
642 	}
643 
644 	ret = copy_workload_to_ring_buffer(workload);
645 	if (ret) {
646 		gvt_vgpu_err("fail to generate request\n");
647 		goto err_unpin_mm;
648 	}
649 
650 	ret = prepare_shadow_batch_buffer(workload);
651 	if (ret) {
652 		gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
653 		goto err_unpin_mm;
654 	}
655 
656 	ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
657 	if (ret) {
658 		gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
659 		goto err_shadow_batch;
660 	}
661 
662 	if (workload->prepare) {
663 		ret = workload->prepare(workload);
664 		if (ret)
665 			goto err_shadow_wa_ctx;
666 	}
667 
668 	return 0;
669 err_shadow_wa_ctx:
670 	release_shadow_wa_ctx(&workload->wa_ctx);
671 err_shadow_batch:
672 	release_shadow_batch_buffer(workload);
673 err_unpin_mm:
674 	intel_vgpu_unpin_mm(workload->shadow_mm);
675 	return ret;
676 }
677 
678 static int dispatch_workload(struct intel_vgpu_workload *workload)
679 {
680 	struct intel_vgpu *vgpu = workload->vgpu;
681 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
682 	struct i915_request *rq;
683 	int ring_id = workload->ring_id;
684 	int ret;
685 
686 	gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
687 		ring_id, workload);
688 
689 	mutex_lock(&vgpu->vgpu_lock);
690 	mutex_lock(&dev_priv->drm.struct_mutex);
691 
692 	ret = intel_gvt_workload_req_alloc(workload);
693 	if (ret)
694 		goto err_req;
695 
696 	ret = intel_gvt_scan_and_shadow_workload(workload);
697 	if (ret)
698 		goto out;
699 
700 	ret = populate_shadow_context(workload);
701 	if (ret) {
702 		release_shadow_wa_ctx(&workload->wa_ctx);
703 		goto out;
704 	}
705 
706 	ret = prepare_workload(workload);
707 out:
708 	if (ret) {
709 		/* We might still need to add request with
710 		 * clean ctx to retire it properly..
711 		 */
712 		rq = fetch_and_zero(&workload->req);
713 		i915_request_put(rq);
714 	}
715 
716 	if (!IS_ERR_OR_NULL(workload->req)) {
717 		gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
718 				ring_id, workload->req);
719 		i915_request_add(workload->req);
720 		workload->dispatched = true;
721 	}
722 err_req:
723 	if (ret)
724 		workload->status = ret;
725 	mutex_unlock(&dev_priv->drm.struct_mutex);
726 	mutex_unlock(&vgpu->vgpu_lock);
727 	return ret;
728 }
729 
730 static struct intel_vgpu_workload *pick_next_workload(
731 		struct intel_gvt *gvt, int ring_id)
732 {
733 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
734 	struct intel_vgpu_workload *workload = NULL;
735 
736 	mutex_lock(&gvt->sched_lock);
737 
738 	/*
739 	 * no current vgpu / will be scheduled out / no workload
740 	 * bail out
741 	 */
742 	if (!scheduler->current_vgpu) {
743 		gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
744 		goto out;
745 	}
746 
747 	if (scheduler->need_reschedule) {
748 		gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
749 		goto out;
750 	}
751 
752 	if (!scheduler->current_vgpu->active ||
753 	    list_empty(workload_q_head(scheduler->current_vgpu, ring_id)))
754 		goto out;
755 
756 	/*
757 	 * still have current workload, maybe the workload disptacher
758 	 * fail to submit it for some reason, resubmit it.
759 	 */
760 	if (scheduler->current_workload[ring_id]) {
761 		workload = scheduler->current_workload[ring_id];
762 		gvt_dbg_sched("ring id %d still have current workload %p\n",
763 				ring_id, workload);
764 		goto out;
765 	}
766 
767 	/*
768 	 * pick a workload as current workload
769 	 * once current workload is set, schedule policy routines
770 	 * will wait the current workload is finished when trying to
771 	 * schedule out a vgpu.
772 	 */
773 	scheduler->current_workload[ring_id] = container_of(
774 			workload_q_head(scheduler->current_vgpu, ring_id)->next,
775 			struct intel_vgpu_workload, list);
776 
777 	workload = scheduler->current_workload[ring_id];
778 
779 	gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
780 
781 	atomic_inc(&workload->vgpu->submission.running_workload_num);
782 out:
783 	mutex_unlock(&gvt->sched_lock);
784 	return workload;
785 }
786 
787 static void update_guest_context(struct intel_vgpu_workload *workload)
788 {
789 	struct i915_request *rq = workload->req;
790 	struct intel_vgpu *vgpu = workload->vgpu;
791 	struct intel_gvt *gvt = vgpu->gvt;
792 	struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj;
793 	struct execlist_ring_context *shadow_ring_context;
794 	struct page *page;
795 	void *src;
796 	unsigned long context_gpa, context_page_num;
797 	int i;
798 	struct drm_i915_private *dev_priv = gvt->dev_priv;
799 	u32 ring_base;
800 	u32 head, tail;
801 	u16 wrap_count;
802 
803 	gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
804 		      workload->ctx_desc.lrca);
805 
806 	head = workload->rb_head;
807 	tail = workload->rb_tail;
808 	wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
809 
810 	if (tail < head) {
811 		if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
812 			wrap_count = 0;
813 		else
814 			wrap_count += 1;
815 	}
816 
817 	head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
818 
819 	ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
820 	vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
821 	vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
822 
823 	context_page_num = rq->engine->context_size;
824 	context_page_num = context_page_num >> PAGE_SHIFT;
825 
826 	if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
827 		context_page_num = 19;
828 
829 	i = 2;
830 
831 	while (i < context_page_num) {
832 		context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
833 				(u32)((workload->ctx_desc.lrca + i) <<
834 					I915_GTT_PAGE_SHIFT));
835 		if (context_gpa == INTEL_GVT_INVALID_ADDR) {
836 			gvt_vgpu_err("invalid guest context descriptor\n");
837 			return;
838 		}
839 
840 		page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i);
841 		src = kmap(page);
842 		intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
843 				I915_GTT_PAGE_SIZE);
844 		kunmap(page);
845 		i++;
846 	}
847 
848 	intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
849 		RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
850 
851 	page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
852 	shadow_ring_context = kmap(page);
853 
854 #define COPY_REG(name) \
855 	intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
856 		RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
857 
858 	COPY_REG(ctx_ctrl);
859 	COPY_REG(ctx_timestamp);
860 
861 #undef COPY_REG
862 
863 	intel_gvt_hypervisor_write_gpa(vgpu,
864 			workload->ring_context_gpa +
865 			sizeof(*shadow_ring_context),
866 			(void *)shadow_ring_context +
867 			sizeof(*shadow_ring_context),
868 			I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
869 
870 	kunmap(page);
871 }
872 
873 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
874 				intel_engine_mask_t engine_mask)
875 {
876 	struct intel_vgpu_submission *s = &vgpu->submission;
877 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
878 	struct intel_engine_cs *engine;
879 	struct intel_vgpu_workload *pos, *n;
880 	intel_engine_mask_t tmp;
881 
882 	/* free the unsubmited workloads in the queues. */
883 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
884 		list_for_each_entry_safe(pos, n,
885 			&s->workload_q_head[engine->id], list) {
886 			list_del_init(&pos->list);
887 			intel_vgpu_destroy_workload(pos);
888 		}
889 		clear_bit(engine->id, s->shadow_ctx_desc_updated);
890 	}
891 }
892 
893 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
894 {
895 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
896 	struct intel_vgpu_workload *workload =
897 		scheduler->current_workload[ring_id];
898 	struct intel_vgpu *vgpu = workload->vgpu;
899 	struct intel_vgpu_submission *s = &vgpu->submission;
900 	struct i915_request *rq = workload->req;
901 	int event;
902 
903 	mutex_lock(&vgpu->vgpu_lock);
904 	mutex_lock(&gvt->sched_lock);
905 
906 	/* For the workload w/ request, needs to wait for the context
907 	 * switch to make sure request is completed.
908 	 * For the workload w/o request, directly complete the workload.
909 	 */
910 	if (rq) {
911 		wait_event(workload->shadow_ctx_status_wq,
912 			   !atomic_read(&workload->shadow_ctx_active));
913 
914 		/* If this request caused GPU hang, req->fence.error will
915 		 * be set to -EIO. Use -EIO to set workload status so
916 		 * that when this request caused GPU hang, didn't trigger
917 		 * context switch interrupt to guest.
918 		 */
919 		if (likely(workload->status == -EINPROGRESS)) {
920 			if (workload->req->fence.error == -EIO)
921 				workload->status = -EIO;
922 			else
923 				workload->status = 0;
924 		}
925 
926 		if (!workload->status &&
927 		    !(vgpu->resetting_eng & BIT(ring_id))) {
928 			update_guest_context(workload);
929 
930 			for_each_set_bit(event, workload->pending_events,
931 					 INTEL_GVT_EVENT_MAX)
932 				intel_vgpu_trigger_virtual_event(vgpu, event);
933 		}
934 
935 		i915_request_put(fetch_and_zero(&workload->req));
936 	}
937 
938 	gvt_dbg_sched("ring id %d complete workload %p status %d\n",
939 			ring_id, workload, workload->status);
940 
941 	scheduler->current_workload[ring_id] = NULL;
942 
943 	list_del_init(&workload->list);
944 
945 	if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
946 		/* if workload->status is not successful means HW GPU
947 		 * has occurred GPU hang or something wrong with i915/GVT,
948 		 * and GVT won't inject context switch interrupt to guest.
949 		 * So this error is a vGPU hang actually to the guest.
950 		 * According to this we should emunlate a vGPU hang. If
951 		 * there are pending workloads which are already submitted
952 		 * from guest, we should clean them up like HW GPU does.
953 		 *
954 		 * if it is in middle of engine resetting, the pending
955 		 * workloads won't be submitted to HW GPU and will be
956 		 * cleaned up during the resetting process later, so doing
957 		 * the workload clean up here doesn't have any impact.
958 		 **/
959 		intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
960 	}
961 
962 	workload->complete(workload);
963 
964 	atomic_dec(&s->running_workload_num);
965 	wake_up(&scheduler->workload_complete_wq);
966 
967 	if (gvt->scheduler.need_reschedule)
968 		intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
969 
970 	mutex_unlock(&gvt->sched_lock);
971 	mutex_unlock(&vgpu->vgpu_lock);
972 }
973 
974 struct workload_thread_param {
975 	struct intel_gvt *gvt;
976 	int ring_id;
977 };
978 
979 static int workload_thread(void *priv)
980 {
981 	struct workload_thread_param *p = (struct workload_thread_param *)priv;
982 	struct intel_gvt *gvt = p->gvt;
983 	int ring_id = p->ring_id;
984 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
985 	struct intel_vgpu_workload *workload = NULL;
986 	struct intel_vgpu *vgpu = NULL;
987 	int ret;
988 	bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
989 	DEFINE_WAIT_FUNC(wait, woken_wake_function);
990 	struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm;
991 
992 	kfree(p);
993 
994 	gvt_dbg_core("workload thread for ring %d started\n", ring_id);
995 
996 	while (!kthread_should_stop()) {
997 		add_wait_queue(&scheduler->waitq[ring_id], &wait);
998 		do {
999 			workload = pick_next_workload(gvt, ring_id);
1000 			if (workload)
1001 				break;
1002 			wait_woken(&wait, TASK_INTERRUPTIBLE,
1003 				   MAX_SCHEDULE_TIMEOUT);
1004 		} while (!kthread_should_stop());
1005 		remove_wait_queue(&scheduler->waitq[ring_id], &wait);
1006 
1007 		if (!workload)
1008 			break;
1009 
1010 		gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
1011 				workload->ring_id, workload,
1012 				workload->vgpu->id);
1013 
1014 		intel_runtime_pm_get(rpm);
1015 
1016 		gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1017 				workload->ring_id, workload);
1018 
1019 		if (need_force_wake)
1020 			intel_uncore_forcewake_get(&gvt->dev_priv->uncore,
1021 					FORCEWAKE_ALL);
1022 
1023 		ret = dispatch_workload(workload);
1024 
1025 		if (ret) {
1026 			vgpu = workload->vgpu;
1027 			gvt_vgpu_err("fail to dispatch workload, skip\n");
1028 			goto complete;
1029 		}
1030 
1031 		gvt_dbg_sched("ring id %d wait workload %p\n",
1032 				workload->ring_id, workload);
1033 		i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1034 
1035 complete:
1036 		gvt_dbg_sched("will complete workload %p, status: %d\n",
1037 				workload, workload->status);
1038 
1039 		complete_current_workload(gvt, ring_id);
1040 
1041 		if (need_force_wake)
1042 			intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1043 					FORCEWAKE_ALL);
1044 
1045 		intel_runtime_pm_put_unchecked(rpm);
1046 		if (ret && (vgpu_is_vm_unhealthy(ret)))
1047 			enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1048 	}
1049 	return 0;
1050 }
1051 
1052 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1053 {
1054 	struct intel_vgpu_submission *s = &vgpu->submission;
1055 	struct intel_gvt *gvt = vgpu->gvt;
1056 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1057 
1058 	if (atomic_read(&s->running_workload_num)) {
1059 		gvt_dbg_sched("wait vgpu idle\n");
1060 
1061 		wait_event(scheduler->workload_complete_wq,
1062 				!atomic_read(&s->running_workload_num));
1063 	}
1064 }
1065 
1066 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1067 {
1068 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1069 	struct intel_engine_cs *engine;
1070 	enum intel_engine_id i;
1071 
1072 	gvt_dbg_core("clean workload scheduler\n");
1073 
1074 	for_each_engine(engine, gvt->dev_priv, i) {
1075 		atomic_notifier_chain_unregister(
1076 					&engine->context_status_notifier,
1077 					&gvt->shadow_ctx_notifier_block[i]);
1078 		kthread_stop(scheduler->thread[i]);
1079 	}
1080 }
1081 
1082 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1083 {
1084 	struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1085 	struct workload_thread_param *param = NULL;
1086 	struct intel_engine_cs *engine;
1087 	enum intel_engine_id i;
1088 	int ret;
1089 
1090 	gvt_dbg_core("init workload scheduler\n");
1091 
1092 	init_waitqueue_head(&scheduler->workload_complete_wq);
1093 
1094 	for_each_engine(engine, gvt->dev_priv, i) {
1095 		init_waitqueue_head(&scheduler->waitq[i]);
1096 
1097 		param = kzalloc(sizeof(*param), GFP_KERNEL);
1098 		if (!param) {
1099 			ret = -ENOMEM;
1100 			goto err;
1101 		}
1102 
1103 		param->gvt = gvt;
1104 		param->ring_id = i;
1105 
1106 		scheduler->thread[i] = kthread_run(workload_thread, param,
1107 			"gvt workload %d", i);
1108 		if (IS_ERR(scheduler->thread[i])) {
1109 			gvt_err("fail to create workload thread\n");
1110 			ret = PTR_ERR(scheduler->thread[i]);
1111 			goto err;
1112 		}
1113 
1114 		gvt->shadow_ctx_notifier_block[i].notifier_call =
1115 					shadow_context_status_change;
1116 		atomic_notifier_chain_register(&engine->context_status_notifier,
1117 					&gvt->shadow_ctx_notifier_block[i]);
1118 	}
1119 	return 0;
1120 err:
1121 	intel_gvt_clean_workload_scheduler(gvt);
1122 	kfree(param);
1123 	param = NULL;
1124 	return ret;
1125 }
1126 
1127 static void
1128 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1129 				struct i915_ppgtt *ppgtt)
1130 {
1131 	int i;
1132 
1133 	if (i915_vm_is_4lvl(&ppgtt->vm)) {
1134 		px_dma(ppgtt->pd) = s->i915_context_pml4;
1135 	} else {
1136 		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1137 			struct i915_page_directory * const pd =
1138 				i915_pd_entry(ppgtt->pd, i);
1139 
1140 			px_dma(pd) = s->i915_context_pdps[i];
1141 		}
1142 	}
1143 }
1144 
1145 /**
1146  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1147  * @vgpu: a vGPU
1148  *
1149  * This function is called when a vGPU is being destroyed.
1150  *
1151  */
1152 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1153 {
1154 	struct intel_vgpu_submission *s = &vgpu->submission;
1155 	struct intel_engine_cs *engine;
1156 	enum intel_engine_id id;
1157 
1158 	intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1159 
1160 	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1161 	for_each_engine(engine, vgpu->gvt->dev_priv, id)
1162 		intel_context_unpin(s->shadow[id]);
1163 
1164 	kmem_cache_destroy(s->workloads);
1165 }
1166 
1167 
1168 /**
1169  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1170  * @vgpu: a vGPU
1171  * @engine_mask: engines expected to be reset
1172  *
1173  * This function is called when a vGPU is being destroyed.
1174  *
1175  */
1176 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1177 				 intel_engine_mask_t engine_mask)
1178 {
1179 	struct intel_vgpu_submission *s = &vgpu->submission;
1180 
1181 	if (!s->active)
1182 		return;
1183 
1184 	intel_vgpu_clean_workloads(vgpu, engine_mask);
1185 	s->ops->reset(vgpu, engine_mask);
1186 }
1187 
1188 static void
1189 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1190 			     struct i915_ppgtt *ppgtt)
1191 {
1192 	int i;
1193 
1194 	if (i915_vm_is_4lvl(&ppgtt->vm)) {
1195 		s->i915_context_pml4 = px_dma(ppgtt->pd);
1196 	} else {
1197 		for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1198 			struct i915_page_directory * const pd =
1199 				i915_pd_entry(ppgtt->pd, i);
1200 
1201 			s->i915_context_pdps[i] = px_dma(pd);
1202 		}
1203 	}
1204 }
1205 
1206 /**
1207  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1208  * @vgpu: a vGPU
1209  *
1210  * This function is called when a vGPU is being created.
1211  *
1212  * Returns:
1213  * Zero on success, negative error code if failed.
1214  *
1215  */
1216 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1217 {
1218 	struct intel_vgpu_submission *s = &vgpu->submission;
1219 	struct intel_engine_cs *engine;
1220 	struct i915_gem_context *ctx;
1221 	enum intel_engine_id i;
1222 	int ret;
1223 
1224 	ctx = i915_gem_context_create_gvt(&vgpu->gvt->dev_priv->drm);
1225 	if (IS_ERR(ctx))
1226 		return PTR_ERR(ctx);
1227 
1228 	i915_context_ppgtt_root_save(s, i915_vm_to_ppgtt(ctx->vm));
1229 
1230 	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
1231 		struct intel_context *ce;
1232 
1233 		INIT_LIST_HEAD(&s->workload_q_head[i]);
1234 		s->shadow[i] = ERR_PTR(-EINVAL);
1235 
1236 		ce = i915_gem_context_get_engine(ctx, i);
1237 		if (IS_ERR(ce)) {
1238 			ret = PTR_ERR(ce);
1239 			goto out_shadow_ctx;
1240 		}
1241 
1242 		ret = intel_context_pin(ce);
1243 		intel_context_put(ce);
1244 		if (ret)
1245 			goto out_shadow_ctx;
1246 
1247 		s->shadow[i] = ce;
1248 	}
1249 
1250 	bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1251 
1252 	s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1253 						  sizeof(struct intel_vgpu_workload), 0,
1254 						  SLAB_HWCACHE_ALIGN,
1255 						  offsetof(struct intel_vgpu_workload, rb_tail),
1256 						  sizeof_field(struct intel_vgpu_workload, rb_tail),
1257 						  NULL);
1258 
1259 	if (!s->workloads) {
1260 		ret = -ENOMEM;
1261 		goto out_shadow_ctx;
1262 	}
1263 
1264 	atomic_set(&s->running_workload_num, 0);
1265 	bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1266 
1267 	i915_gem_context_put(ctx);
1268 	return 0;
1269 
1270 out_shadow_ctx:
1271 	i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(ctx->vm));
1272 	for_each_engine(engine, vgpu->gvt->dev_priv, i) {
1273 		if (IS_ERR(s->shadow[i]))
1274 			break;
1275 
1276 		intel_context_unpin(s->shadow[i]);
1277 	}
1278 	i915_gem_context_put(ctx);
1279 	return ret;
1280 }
1281 
1282 /**
1283  * intel_vgpu_select_submission_ops - select virtual submission interface
1284  * @vgpu: a vGPU
1285  * @engine_mask: either ALL_ENGINES or target engine mask
1286  * @interface: expected vGPU virtual submission interface
1287  *
1288  * This function is called when guest configures submission interface.
1289  *
1290  * Returns:
1291  * Zero on success, negative error code if failed.
1292  *
1293  */
1294 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1295 				     intel_engine_mask_t engine_mask,
1296 				     unsigned int interface)
1297 {
1298 	struct intel_vgpu_submission *s = &vgpu->submission;
1299 	const struct intel_vgpu_submission_ops *ops[] = {
1300 		[INTEL_VGPU_EXECLIST_SUBMISSION] =
1301 			&intel_vgpu_execlist_submission_ops,
1302 	};
1303 	int ret;
1304 
1305 	if (WARN_ON(interface >= ARRAY_SIZE(ops)))
1306 		return -EINVAL;
1307 
1308 	if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES))
1309 		return -EINVAL;
1310 
1311 	if (s->active)
1312 		s->ops->clean(vgpu, engine_mask);
1313 
1314 	if (interface == 0) {
1315 		s->ops = NULL;
1316 		s->virtual_submission_interface = 0;
1317 		s->active = false;
1318 		gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1319 		return 0;
1320 	}
1321 
1322 	ret = ops[interface]->init(vgpu, engine_mask);
1323 	if (ret)
1324 		return ret;
1325 
1326 	s->ops = ops[interface];
1327 	s->virtual_submission_interface = interface;
1328 	s->active = true;
1329 
1330 	gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1331 			vgpu->id, s->ops->name);
1332 
1333 	return 0;
1334 }
1335 
1336 /**
1337  * intel_vgpu_destroy_workload - destroy a vGPU workload
1338  * @workload: workload to destroy
1339  *
1340  * This function is called when destroy a vGPU workload.
1341  *
1342  */
1343 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1344 {
1345 	struct intel_vgpu_submission *s = &workload->vgpu->submission;
1346 
1347 	release_shadow_batch_buffer(workload);
1348 	release_shadow_wa_ctx(&workload->wa_ctx);
1349 
1350 	if (workload->shadow_mm)
1351 		intel_vgpu_mm_put(workload->shadow_mm);
1352 
1353 	kmem_cache_free(s->workloads, workload);
1354 }
1355 
1356 static struct intel_vgpu_workload *
1357 alloc_workload(struct intel_vgpu *vgpu)
1358 {
1359 	struct intel_vgpu_submission *s = &vgpu->submission;
1360 	struct intel_vgpu_workload *workload;
1361 
1362 	workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1363 	if (!workload)
1364 		return ERR_PTR(-ENOMEM);
1365 
1366 	INIT_LIST_HEAD(&workload->list);
1367 	INIT_LIST_HEAD(&workload->shadow_bb);
1368 
1369 	init_waitqueue_head(&workload->shadow_ctx_status_wq);
1370 	atomic_set(&workload->shadow_ctx_active, 0);
1371 
1372 	workload->status = -EINPROGRESS;
1373 	workload->vgpu = vgpu;
1374 
1375 	return workload;
1376 }
1377 
1378 #define RING_CTX_OFF(x) \
1379 	offsetof(struct execlist_ring_context, x)
1380 
1381 static void read_guest_pdps(struct intel_vgpu *vgpu,
1382 		u64 ring_context_gpa, u32 pdp[8])
1383 {
1384 	u64 gpa;
1385 	int i;
1386 
1387 	gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1388 
1389 	for (i = 0; i < 8; i++)
1390 		intel_gvt_hypervisor_read_gpa(vgpu,
1391 				gpa + i * 8, &pdp[7 - i], 4);
1392 }
1393 
1394 static int prepare_mm(struct intel_vgpu_workload *workload)
1395 {
1396 	struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1397 	struct intel_vgpu_mm *mm;
1398 	struct intel_vgpu *vgpu = workload->vgpu;
1399 	enum intel_gvt_gtt_type root_entry_type;
1400 	u64 pdps[GVT_RING_CTX_NR_PDPS];
1401 
1402 	switch (desc->addressing_mode) {
1403 	case 1: /* legacy 32-bit */
1404 		root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1405 		break;
1406 	case 3: /* legacy 64-bit */
1407 		root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1408 		break;
1409 	default:
1410 		gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1411 		return -EINVAL;
1412 	}
1413 
1414 	read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1415 
1416 	mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1417 	if (IS_ERR(mm))
1418 		return PTR_ERR(mm);
1419 
1420 	workload->shadow_mm = mm;
1421 	return 0;
1422 }
1423 
1424 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1425 		((a)->lrca == (b)->lrca))
1426 
1427 #define get_last_workload(q) \
1428 	(list_empty(q) ? NULL : container_of(q->prev, \
1429 	struct intel_vgpu_workload, list))
1430 /**
1431  * intel_vgpu_create_workload - create a vGPU workload
1432  * @vgpu: a vGPU
1433  * @ring_id: ring index
1434  * @desc: a guest context descriptor
1435  *
1436  * This function is called when creating a vGPU workload.
1437  *
1438  * Returns:
1439  * struct intel_vgpu_workload * on success, negative error code in
1440  * pointer if failed.
1441  *
1442  */
1443 struct intel_vgpu_workload *
1444 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
1445 			   struct execlist_ctx_descriptor_format *desc)
1446 {
1447 	struct intel_vgpu_submission *s = &vgpu->submission;
1448 	struct list_head *q = workload_q_head(vgpu, ring_id);
1449 	struct intel_vgpu_workload *last_workload = get_last_workload(q);
1450 	struct intel_vgpu_workload *workload = NULL;
1451 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1452 	u64 ring_context_gpa;
1453 	u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1454 	u32 guest_head;
1455 	int ret;
1456 
1457 	ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1458 			(u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1459 	if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1460 		gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1461 		return ERR_PTR(-EINVAL);
1462 	}
1463 
1464 	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1465 			RING_CTX_OFF(ring_header.val), &head, 4);
1466 
1467 	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1468 			RING_CTX_OFF(ring_tail.val), &tail, 4);
1469 
1470 	guest_head = head;
1471 
1472 	head &= RB_HEAD_OFF_MASK;
1473 	tail &= RB_TAIL_OFF_MASK;
1474 
1475 	if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
1476 		gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
1477 		gvt_dbg_el("ctx head %x real head %lx\n", head,
1478 				last_workload->rb_tail);
1479 		/*
1480 		 * cannot use guest context head pointer here,
1481 		 * as it might not be updated at this time
1482 		 */
1483 		head = last_workload->rb_tail;
1484 	}
1485 
1486 	gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
1487 
1488 	/* record some ring buffer register values for scan and shadow */
1489 	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1490 			RING_CTX_OFF(rb_start.val), &start, 4);
1491 	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1492 			RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1493 	intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1494 			RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1495 
1496 	if (!intel_gvt_ggtt_validate_range(vgpu, start,
1497 				_RING_CTL_BUF_SIZE(ctl))) {
1498 		gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1499 		return ERR_PTR(-EINVAL);
1500 	}
1501 
1502 	workload = alloc_workload(vgpu);
1503 	if (IS_ERR(workload))
1504 		return workload;
1505 
1506 	workload->ring_id = ring_id;
1507 	workload->ctx_desc = *desc;
1508 	workload->ring_context_gpa = ring_context_gpa;
1509 	workload->rb_head = head;
1510 	workload->guest_rb_head = guest_head;
1511 	workload->rb_tail = tail;
1512 	workload->rb_start = start;
1513 	workload->rb_ctl = ctl;
1514 
1515 	if (ring_id == RCS0) {
1516 		intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1517 			RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1518 		intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1519 			RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1520 
1521 		workload->wa_ctx.indirect_ctx.guest_gma =
1522 			indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1523 		workload->wa_ctx.indirect_ctx.size =
1524 			(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1525 			CACHELINE_BYTES;
1526 
1527 		if (workload->wa_ctx.indirect_ctx.size != 0) {
1528 			if (!intel_gvt_ggtt_validate_range(vgpu,
1529 				workload->wa_ctx.indirect_ctx.guest_gma,
1530 				workload->wa_ctx.indirect_ctx.size)) {
1531 				kmem_cache_free(s->workloads, workload);
1532 				gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1533 				    workload->wa_ctx.indirect_ctx.guest_gma);
1534 				return ERR_PTR(-EINVAL);
1535 			}
1536 		}
1537 
1538 		workload->wa_ctx.per_ctx.guest_gma =
1539 			per_ctx & PER_CTX_ADDR_MASK;
1540 		workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1541 		if (workload->wa_ctx.per_ctx.valid) {
1542 			if (!intel_gvt_ggtt_validate_range(vgpu,
1543 				workload->wa_ctx.per_ctx.guest_gma,
1544 				CACHELINE_BYTES)) {
1545 				kmem_cache_free(s->workloads, workload);
1546 				gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1547 					workload->wa_ctx.per_ctx.guest_gma);
1548 				return ERR_PTR(-EINVAL);
1549 			}
1550 		}
1551 	}
1552 
1553 	gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
1554 			workload, ring_id, head, tail, start, ctl);
1555 
1556 	ret = prepare_mm(workload);
1557 	if (ret) {
1558 		kmem_cache_free(s->workloads, workload);
1559 		return ERR_PTR(ret);
1560 	}
1561 
1562 	/* Only scan and shadow the first workload in the queue
1563 	 * as there is only one pre-allocated buf-obj for shadow.
1564 	 */
1565 	if (list_empty(workload_q_head(vgpu, ring_id))) {
1566 		intel_runtime_pm_get(&dev_priv->runtime_pm);
1567 		mutex_lock(&dev_priv->drm.struct_mutex);
1568 		ret = intel_gvt_scan_and_shadow_workload(workload);
1569 		mutex_unlock(&dev_priv->drm.struct_mutex);
1570 		intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm);
1571 	}
1572 
1573 	if (ret) {
1574 		if (vgpu_is_vm_unhealthy(ret))
1575 			enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1576 		intel_vgpu_destroy_workload(workload);
1577 		return ERR_PTR(ret);
1578 	}
1579 
1580 	return workload;
1581 }
1582 
1583 /**
1584  * intel_vgpu_queue_workload - Qeue a vGPU workload
1585  * @workload: the workload to queue in
1586  */
1587 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1588 {
1589 	list_add_tail(&workload->list,
1590 		workload_q_head(workload->vgpu, workload->ring_id));
1591 	intel_gvt_kick_schedule(workload->vgpu->gvt);
1592 	wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]);
1593 }
1594