1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36 #include <linux/kthread.h> 37 38 #include "i915_drv.h" 39 #include "gvt.h" 40 41 #define RING_CTX_OFF(x) \ 42 offsetof(struct execlist_ring_context, x) 43 44 static void set_context_pdp_root_pointer( 45 struct execlist_ring_context *ring_context, 46 u32 pdp[8]) 47 { 48 int i; 49 50 for (i = 0; i < 8; i++) 51 ring_context->pdps[i].val = pdp[7 - i]; 52 } 53 54 static void update_shadow_pdps(struct intel_vgpu_workload *workload) 55 { 56 struct drm_i915_gem_object *ctx_obj = 57 workload->req->hw_context->state->obj; 58 struct execlist_ring_context *shadow_ring_context; 59 struct page *page; 60 61 if (WARN_ON(!workload->shadow_mm)) 62 return; 63 64 if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount))) 65 return; 66 67 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 68 shadow_ring_context = kmap(page); 69 set_context_pdp_root_pointer(shadow_ring_context, 70 (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps); 71 kunmap(page); 72 } 73 74 /* 75 * when populating shadow ctx from guest, we should not overrride oa related 76 * registers, so that they will not be overlapped by guest oa configs. Thus 77 * made it possible to capture oa data from host for both host and guests. 78 */ 79 static void sr_oa_regs(struct intel_vgpu_workload *workload, 80 u32 *reg_state, bool save) 81 { 82 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 83 u32 ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_offset; 84 u32 ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_offset; 85 int i = 0; 86 u32 flex_mmio[] = { 87 i915_mmio_reg_offset(EU_PERF_CNTL0), 88 i915_mmio_reg_offset(EU_PERF_CNTL1), 89 i915_mmio_reg_offset(EU_PERF_CNTL2), 90 i915_mmio_reg_offset(EU_PERF_CNTL3), 91 i915_mmio_reg_offset(EU_PERF_CNTL4), 92 i915_mmio_reg_offset(EU_PERF_CNTL5), 93 i915_mmio_reg_offset(EU_PERF_CNTL6), 94 }; 95 96 if (workload->ring_id != RCS0) 97 return; 98 99 if (save) { 100 workload->oactxctrl = reg_state[ctx_oactxctrl + 1]; 101 102 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 103 u32 state_offset = ctx_flexeu0 + i * 2; 104 105 workload->flex_mmio[i] = reg_state[state_offset + 1]; 106 } 107 } else { 108 reg_state[ctx_oactxctrl] = 109 i915_mmio_reg_offset(GEN8_OACTXCONTROL); 110 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl; 111 112 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) { 113 u32 state_offset = ctx_flexeu0 + i * 2; 114 u32 mmio = flex_mmio[i]; 115 116 reg_state[state_offset] = mmio; 117 reg_state[state_offset + 1] = workload->flex_mmio[i]; 118 } 119 } 120 } 121 122 static int populate_shadow_context(struct intel_vgpu_workload *workload) 123 { 124 struct intel_vgpu *vgpu = workload->vgpu; 125 struct intel_gvt *gvt = vgpu->gvt; 126 int ring_id = workload->ring_id; 127 struct drm_i915_gem_object *ctx_obj = 128 workload->req->hw_context->state->obj; 129 struct execlist_ring_context *shadow_ring_context; 130 struct page *page; 131 void *dst; 132 unsigned long context_gpa, context_page_num; 133 int i; 134 135 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 136 shadow_ring_context = kmap(page); 137 138 sr_oa_regs(workload, (u32 *)shadow_ring_context, true); 139 #define COPY_REG(name) \ 140 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 141 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 142 #define COPY_REG_MASKED(name) {\ 143 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 144 + RING_CTX_OFF(name.val),\ 145 &shadow_ring_context->name.val, 4);\ 146 shadow_ring_context->name.val |= 0xffff << 16;\ 147 } 148 149 COPY_REG_MASKED(ctx_ctrl); 150 COPY_REG(ctx_timestamp); 151 152 if (ring_id == RCS0) { 153 COPY_REG(bb_per_ctx_ptr); 154 COPY_REG(rcs_indirect_ctx); 155 COPY_REG(rcs_indirect_ctx_offset); 156 } 157 #undef COPY_REG 158 #undef COPY_REG_MASKED 159 160 intel_gvt_hypervisor_read_gpa(vgpu, 161 workload->ring_context_gpa + 162 sizeof(*shadow_ring_context), 163 (void *)shadow_ring_context + 164 sizeof(*shadow_ring_context), 165 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 166 167 sr_oa_regs(workload, (u32 *)shadow_ring_context, false); 168 kunmap(page); 169 170 if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val)) 171 return 0; 172 173 gvt_dbg_sched("ring id %d workload lrca %x", ring_id, 174 workload->ctx_desc.lrca); 175 176 context_page_num = gvt->dev_priv->engine[ring_id]->context_size; 177 178 context_page_num = context_page_num >> PAGE_SHIFT; 179 180 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0) 181 context_page_num = 19; 182 183 i = 2; 184 while (i < context_page_num) { 185 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 186 (u32)((workload->ctx_desc.lrca + i) << 187 I915_GTT_PAGE_SHIFT)); 188 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 189 gvt_vgpu_err("Invalid guest context descriptor\n"); 190 return -EFAULT; 191 } 192 193 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 194 dst = kmap(page); 195 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, 196 I915_GTT_PAGE_SIZE); 197 kunmap(page); 198 i++; 199 } 200 return 0; 201 } 202 203 static inline bool is_gvt_request(struct i915_request *req) 204 { 205 return i915_gem_context_force_single_submission(req->gem_context); 206 } 207 208 static void save_ring_hw_state(struct intel_vgpu *vgpu, int ring_id) 209 { 210 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 211 u32 ring_base = dev_priv->engine[ring_id]->mmio_base; 212 i915_reg_t reg; 213 214 reg = RING_INSTDONE(ring_base); 215 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 216 reg = RING_ACTHD(ring_base); 217 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 218 reg = RING_ACTHD_UDW(ring_base); 219 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = I915_READ_FW(reg); 220 } 221 222 static int shadow_context_status_change(struct notifier_block *nb, 223 unsigned long action, void *data) 224 { 225 struct i915_request *req = data; 226 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, 227 shadow_ctx_notifier_block[req->engine->id]); 228 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 229 enum intel_engine_id ring_id = req->engine->id; 230 struct intel_vgpu_workload *workload; 231 unsigned long flags; 232 233 if (!is_gvt_request(req)) { 234 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 235 if (action == INTEL_CONTEXT_SCHEDULE_IN && 236 scheduler->engine_owner[ring_id]) { 237 /* Switch ring from vGPU to host. */ 238 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 239 NULL, ring_id); 240 scheduler->engine_owner[ring_id] = NULL; 241 } 242 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 243 244 return NOTIFY_OK; 245 } 246 247 workload = scheduler->current_workload[ring_id]; 248 if (unlikely(!workload)) 249 return NOTIFY_OK; 250 251 switch (action) { 252 case INTEL_CONTEXT_SCHEDULE_IN: 253 spin_lock_irqsave(&scheduler->mmio_context_lock, flags); 254 if (workload->vgpu != scheduler->engine_owner[ring_id]) { 255 /* Switch ring from host to vGPU or vGPU to vGPU. */ 256 intel_gvt_switch_mmio(scheduler->engine_owner[ring_id], 257 workload->vgpu, ring_id); 258 scheduler->engine_owner[ring_id] = workload->vgpu; 259 } else 260 gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n", 261 ring_id, workload->vgpu->id); 262 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags); 263 atomic_set(&workload->shadow_ctx_active, 1); 264 break; 265 case INTEL_CONTEXT_SCHEDULE_OUT: 266 save_ring_hw_state(workload->vgpu, ring_id); 267 atomic_set(&workload->shadow_ctx_active, 0); 268 break; 269 case INTEL_CONTEXT_SCHEDULE_PREEMPTED: 270 save_ring_hw_state(workload->vgpu, ring_id); 271 break; 272 default: 273 WARN_ON(1); 274 return NOTIFY_OK; 275 } 276 wake_up(&workload->shadow_ctx_status_wq); 277 return NOTIFY_OK; 278 } 279 280 static void shadow_context_descriptor_update(struct intel_context *ce) 281 { 282 u64 desc = 0; 283 284 desc = ce->lrc_desc; 285 286 /* Update bits 0-11 of the context descriptor which includes flags 287 * like GEN8_CTX_* cached in desc_template 288 */ 289 desc &= U64_MAX << 12; 290 desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1); 291 292 ce->lrc_desc = desc; 293 } 294 295 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload) 296 { 297 struct intel_vgpu *vgpu = workload->vgpu; 298 struct i915_request *req = workload->req; 299 void *shadow_ring_buffer_va; 300 u32 *cs; 301 int err; 302 303 if (IS_GEN(req->i915, 9) && is_inhibit_context(req->hw_context)) 304 intel_vgpu_restore_inhibit_context(vgpu, req); 305 306 /* 307 * To track whether a request has started on HW, we can emit a 308 * breadcrumb at the beginning of the request and check its 309 * timeline's HWSP to see if the breadcrumb has advanced past the 310 * start of this request. Actually, the request must have the 311 * init_breadcrumb if its timeline set has_init_bread_crumb, or the 312 * scheduler might get a wrong state of it during reset. Since the 313 * requests from gvt always set the has_init_breadcrumb flag, here 314 * need to do the emit_init_breadcrumb for all the requests. 315 */ 316 if (req->engine->emit_init_breadcrumb) { 317 err = req->engine->emit_init_breadcrumb(req); 318 if (err) { 319 gvt_vgpu_err("fail to emit init breadcrumb\n"); 320 return err; 321 } 322 } 323 324 /* allocate shadow ring buffer */ 325 cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32)); 326 if (IS_ERR(cs)) { 327 gvt_vgpu_err("fail to alloc size =%ld shadow ring buffer\n", 328 workload->rb_len); 329 return PTR_ERR(cs); 330 } 331 332 shadow_ring_buffer_va = workload->shadow_ring_buffer_va; 333 334 /* get shadow ring buffer va */ 335 workload->shadow_ring_buffer_va = cs; 336 337 memcpy(cs, shadow_ring_buffer_va, 338 workload->rb_len); 339 340 cs += workload->rb_len / sizeof(u32); 341 intel_ring_advance(workload->req, cs); 342 343 return 0; 344 } 345 346 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 347 { 348 if (!wa_ctx->indirect_ctx.obj) 349 return; 350 351 i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj); 352 i915_gem_object_put(wa_ctx->indirect_ctx.obj); 353 354 wa_ctx->indirect_ctx.obj = NULL; 355 wa_ctx->indirect_ctx.shadow_va = NULL; 356 } 357 358 static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload, 359 struct i915_gem_context *ctx) 360 { 361 struct intel_vgpu_mm *mm = workload->shadow_mm; 362 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 363 int i = 0; 364 365 if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed) 366 return -EINVAL; 367 368 if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) { 369 px_dma(&ppgtt->pml4) = mm->ppgtt_mm.shadow_pdps[0]; 370 } else { 371 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) { 372 px_dma(ppgtt->pdp.page_directory[i]) = 373 mm->ppgtt_mm.shadow_pdps[i]; 374 } 375 } 376 377 return 0; 378 } 379 380 static int 381 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload) 382 { 383 struct intel_vgpu *vgpu = workload->vgpu; 384 struct intel_vgpu_submission *s = &vgpu->submission; 385 struct i915_gem_context *shadow_ctx = s->shadow_ctx; 386 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 387 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id]; 388 struct i915_request *rq; 389 int ret = 0; 390 391 lockdep_assert_held(&dev_priv->drm.struct_mutex); 392 393 if (workload->req) 394 goto out; 395 396 rq = i915_request_alloc(engine, shadow_ctx); 397 if (IS_ERR(rq)) { 398 gvt_vgpu_err("fail to allocate gem request\n"); 399 ret = PTR_ERR(rq); 400 goto out; 401 } 402 workload->req = i915_request_get(rq); 403 out: 404 return ret; 405 } 406 407 /** 408 * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and 409 * shadow it as well, include ringbuffer,wa_ctx and ctx. 410 * @workload: an abstract entity for each execlist submission. 411 * 412 * This function is called before the workload submitting to i915, to make 413 * sure the content of the workload is valid. 414 */ 415 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload) 416 { 417 struct intel_vgpu *vgpu = workload->vgpu; 418 struct intel_vgpu_submission *s = &vgpu->submission; 419 struct i915_gem_context *shadow_ctx = s->shadow_ctx; 420 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 421 struct intel_engine_cs *engine = dev_priv->engine[workload->ring_id]; 422 struct intel_context *ce; 423 int ret; 424 425 lockdep_assert_held(&dev_priv->drm.struct_mutex); 426 427 if (workload->shadow) 428 return 0; 429 430 /* pin shadow context by gvt even the shadow context will be pinned 431 * when i915 alloc request. That is because gvt will update the guest 432 * context from shadow context when workload is completed, and at that 433 * moment, i915 may already unpined the shadow context to make the 434 * shadow_ctx pages invalid. So gvt need to pin itself. After update 435 * the guest context, gvt can unpin the shadow_ctx safely. 436 */ 437 ce = intel_context_pin(shadow_ctx, engine); 438 if (IS_ERR(ce)) { 439 gvt_vgpu_err("fail to pin shadow context\n"); 440 return PTR_ERR(ce); 441 } 442 443 shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); 444 shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << 445 GEN8_CTX_ADDRESSING_MODE_SHIFT; 446 447 if (!test_and_set_bit(workload->ring_id, s->shadow_ctx_desc_updated)) 448 shadow_context_descriptor_update(ce); 449 450 ret = intel_gvt_scan_and_shadow_ringbuffer(workload); 451 if (ret) 452 goto err_unpin; 453 454 if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) { 455 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 456 if (ret) 457 goto err_shadow; 458 } 459 460 workload->shadow = true; 461 return 0; 462 err_shadow: 463 release_shadow_wa_ctx(&workload->wa_ctx); 464 err_unpin: 465 intel_context_unpin(ce); 466 return ret; 467 } 468 469 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload); 470 471 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 472 { 473 struct intel_gvt *gvt = workload->vgpu->gvt; 474 const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd; 475 struct intel_vgpu_shadow_bb *bb; 476 int ret; 477 478 list_for_each_entry(bb, &workload->shadow_bb, list) { 479 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va 480 * is only updated into ring_scan_buffer, not real ring address 481 * allocated in later copy_workload_to_ring_buffer. pls be noted 482 * shadow_ring_buffer_va is now pointed to real ring buffer va 483 * in copy_workload_to_ring_buffer. 484 */ 485 486 if (bb->bb_offset) 487 bb->bb_start_cmd_va = workload->shadow_ring_buffer_va 488 + bb->bb_offset; 489 490 if (bb->ppgtt) { 491 /* for non-priv bb, scan&shadow is only for 492 * debugging purpose, so the content of shadow bb 493 * is the same as original bb. Therefore, 494 * here, rather than switch to shadow bb's gma 495 * address, we directly use original batch buffer's 496 * gma address, and send original bb to hardware 497 * directly 498 */ 499 if (bb->clflush & CLFLUSH_AFTER) { 500 drm_clflush_virt_range(bb->va, 501 bb->obj->base.size); 502 bb->clflush &= ~CLFLUSH_AFTER; 503 } 504 i915_gem_obj_finish_shmem_access(bb->obj); 505 bb->accessing = false; 506 507 } else { 508 bb->vma = i915_gem_object_ggtt_pin(bb->obj, 509 NULL, 0, 0, 0); 510 if (IS_ERR(bb->vma)) { 511 ret = PTR_ERR(bb->vma); 512 goto err; 513 } 514 515 /* relocate shadow batch buffer */ 516 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); 517 if (gmadr_bytes == 8) 518 bb->bb_start_cmd_va[2] = 0; 519 520 /* No one is going to touch shadow bb from now on. */ 521 if (bb->clflush & CLFLUSH_AFTER) { 522 drm_clflush_virt_range(bb->va, 523 bb->obj->base.size); 524 bb->clflush &= ~CLFLUSH_AFTER; 525 } 526 527 ret = i915_gem_object_set_to_gtt_domain(bb->obj, 528 false); 529 if (ret) 530 goto err; 531 532 i915_gem_obj_finish_shmem_access(bb->obj); 533 bb->accessing = false; 534 535 ret = i915_vma_move_to_active(bb->vma, 536 workload->req, 537 0); 538 if (ret) 539 goto err; 540 } 541 } 542 return 0; 543 err: 544 release_shadow_batch_buffer(workload); 545 return ret; 546 } 547 548 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx) 549 { 550 struct intel_vgpu_workload *workload = 551 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx); 552 struct i915_request *rq = workload->req; 553 struct execlist_ring_context *shadow_ring_context = 554 (struct execlist_ring_context *)rq->hw_context->lrc_reg_state; 555 556 shadow_ring_context->bb_per_ctx_ptr.val = 557 (shadow_ring_context->bb_per_ctx_ptr.val & 558 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma; 559 shadow_ring_context->rcs_indirect_ctx.val = 560 (shadow_ring_context->rcs_indirect_ctx.val & 561 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma; 562 } 563 564 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 565 { 566 struct i915_vma *vma; 567 unsigned char *per_ctx_va = 568 (unsigned char *)wa_ctx->indirect_ctx.shadow_va + 569 wa_ctx->indirect_ctx.size; 570 571 if (wa_ctx->indirect_ctx.size == 0) 572 return 0; 573 574 vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL, 575 0, CACHELINE_BYTES, 0); 576 if (IS_ERR(vma)) 577 return PTR_ERR(vma); 578 579 /* FIXME: we are not tracking our pinned VMA leaving it 580 * up to the core to fix up the stray pin_count upon 581 * free. 582 */ 583 584 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); 585 586 wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1); 587 memset(per_ctx_va, 0, CACHELINE_BYTES); 588 589 update_wa_ctx_2_shadow_ctx(wa_ctx); 590 return 0; 591 } 592 593 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 594 { 595 struct intel_vgpu *vgpu = workload->vgpu; 596 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 597 struct intel_vgpu_shadow_bb *bb, *pos; 598 599 if (list_empty(&workload->shadow_bb)) 600 return; 601 602 bb = list_first_entry(&workload->shadow_bb, 603 struct intel_vgpu_shadow_bb, list); 604 605 mutex_lock(&dev_priv->drm.struct_mutex); 606 607 list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) { 608 if (bb->obj) { 609 if (bb->accessing) 610 i915_gem_obj_finish_shmem_access(bb->obj); 611 612 if (bb->va && !IS_ERR(bb->va)) 613 i915_gem_object_unpin_map(bb->obj); 614 615 if (bb->vma && !IS_ERR(bb->vma)) { 616 i915_vma_unpin(bb->vma); 617 i915_vma_close(bb->vma); 618 } 619 __i915_gem_object_release_unless_active(bb->obj); 620 } 621 list_del(&bb->list); 622 kfree(bb); 623 } 624 625 mutex_unlock(&dev_priv->drm.struct_mutex); 626 } 627 628 static int prepare_workload(struct intel_vgpu_workload *workload) 629 { 630 struct intel_vgpu *vgpu = workload->vgpu; 631 int ret = 0; 632 633 ret = intel_vgpu_pin_mm(workload->shadow_mm); 634 if (ret) { 635 gvt_vgpu_err("fail to vgpu pin mm\n"); 636 return ret; 637 } 638 639 update_shadow_pdps(workload); 640 641 ret = intel_vgpu_sync_oos_pages(workload->vgpu); 642 if (ret) { 643 gvt_vgpu_err("fail to vgpu sync oos pages\n"); 644 goto err_unpin_mm; 645 } 646 647 ret = intel_vgpu_flush_post_shadow(workload->vgpu); 648 if (ret) { 649 gvt_vgpu_err("fail to flush post shadow\n"); 650 goto err_unpin_mm; 651 } 652 653 ret = copy_workload_to_ring_buffer(workload); 654 if (ret) { 655 gvt_vgpu_err("fail to generate request\n"); 656 goto err_unpin_mm; 657 } 658 659 ret = prepare_shadow_batch_buffer(workload); 660 if (ret) { 661 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n"); 662 goto err_unpin_mm; 663 } 664 665 ret = prepare_shadow_wa_ctx(&workload->wa_ctx); 666 if (ret) { 667 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n"); 668 goto err_shadow_batch; 669 } 670 671 if (workload->prepare) { 672 ret = workload->prepare(workload); 673 if (ret) 674 goto err_shadow_wa_ctx; 675 } 676 677 return 0; 678 err_shadow_wa_ctx: 679 release_shadow_wa_ctx(&workload->wa_ctx); 680 err_shadow_batch: 681 release_shadow_batch_buffer(workload); 682 err_unpin_mm: 683 intel_vgpu_unpin_mm(workload->shadow_mm); 684 return ret; 685 } 686 687 static int dispatch_workload(struct intel_vgpu_workload *workload) 688 { 689 struct intel_vgpu *vgpu = workload->vgpu; 690 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 691 struct intel_vgpu_submission *s = &vgpu->submission; 692 struct i915_gem_context *shadow_ctx = s->shadow_ctx; 693 struct i915_request *rq; 694 int ring_id = workload->ring_id; 695 int ret; 696 697 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", 698 ring_id, workload); 699 700 mutex_lock(&vgpu->vgpu_lock); 701 mutex_lock(&dev_priv->drm.struct_mutex); 702 703 ret = set_context_ppgtt_from_shadow(workload, shadow_ctx); 704 if (ret < 0) { 705 gvt_vgpu_err("workload shadow ppgtt isn't ready\n"); 706 goto err_req; 707 } 708 709 ret = intel_gvt_workload_req_alloc(workload); 710 if (ret) 711 goto err_req; 712 713 ret = intel_gvt_scan_and_shadow_workload(workload); 714 if (ret) 715 goto out; 716 717 ret = populate_shadow_context(workload); 718 if (ret) { 719 release_shadow_wa_ctx(&workload->wa_ctx); 720 goto out; 721 } 722 723 ret = prepare_workload(workload); 724 out: 725 if (ret) { 726 /* We might still need to add request with 727 * clean ctx to retire it properly.. 728 */ 729 rq = fetch_and_zero(&workload->req); 730 i915_request_put(rq); 731 } 732 733 if (!IS_ERR_OR_NULL(workload->req)) { 734 gvt_dbg_sched("ring id %d submit workload to i915 %p\n", 735 ring_id, workload->req); 736 i915_request_add(workload->req); 737 workload->dispatched = true; 738 } 739 err_req: 740 if (ret) 741 workload->status = ret; 742 mutex_unlock(&dev_priv->drm.struct_mutex); 743 mutex_unlock(&vgpu->vgpu_lock); 744 return ret; 745 } 746 747 static struct intel_vgpu_workload *pick_next_workload( 748 struct intel_gvt *gvt, int ring_id) 749 { 750 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 751 struct intel_vgpu_workload *workload = NULL; 752 753 mutex_lock(&gvt->sched_lock); 754 755 /* 756 * no current vgpu / will be scheduled out / no workload 757 * bail out 758 */ 759 if (!scheduler->current_vgpu) { 760 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id); 761 goto out; 762 } 763 764 if (scheduler->need_reschedule) { 765 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id); 766 goto out; 767 } 768 769 if (!scheduler->current_vgpu->active || 770 list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) 771 goto out; 772 773 /* 774 * still have current workload, maybe the workload disptacher 775 * fail to submit it for some reason, resubmit it. 776 */ 777 if (scheduler->current_workload[ring_id]) { 778 workload = scheduler->current_workload[ring_id]; 779 gvt_dbg_sched("ring id %d still have current workload %p\n", 780 ring_id, workload); 781 goto out; 782 } 783 784 /* 785 * pick a workload as current workload 786 * once current workload is set, schedule policy routines 787 * will wait the current workload is finished when trying to 788 * schedule out a vgpu. 789 */ 790 scheduler->current_workload[ring_id] = container_of( 791 workload_q_head(scheduler->current_vgpu, ring_id)->next, 792 struct intel_vgpu_workload, list); 793 794 workload = scheduler->current_workload[ring_id]; 795 796 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); 797 798 atomic_inc(&workload->vgpu->submission.running_workload_num); 799 out: 800 mutex_unlock(&gvt->sched_lock); 801 return workload; 802 } 803 804 static void update_guest_context(struct intel_vgpu_workload *workload) 805 { 806 struct i915_request *rq = workload->req; 807 struct intel_vgpu *vgpu = workload->vgpu; 808 struct intel_gvt *gvt = vgpu->gvt; 809 struct drm_i915_gem_object *ctx_obj = rq->hw_context->state->obj; 810 struct execlist_ring_context *shadow_ring_context; 811 struct page *page; 812 void *src; 813 unsigned long context_gpa, context_page_num; 814 int i; 815 816 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id, 817 workload->ctx_desc.lrca); 818 819 context_page_num = rq->engine->context_size; 820 context_page_num = context_page_num >> PAGE_SHIFT; 821 822 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0) 823 context_page_num = 19; 824 825 i = 2; 826 827 while (i < context_page_num) { 828 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 829 (u32)((workload->ctx_desc.lrca + i) << 830 I915_GTT_PAGE_SHIFT)); 831 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 832 gvt_vgpu_err("invalid guest context descriptor\n"); 833 return; 834 } 835 836 page = i915_gem_object_get_page(ctx_obj, LRC_HEADER_PAGES + i); 837 src = kmap(page); 838 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, 839 I915_GTT_PAGE_SIZE); 840 kunmap(page); 841 i++; 842 } 843 844 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 845 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 846 847 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 848 shadow_ring_context = kmap(page); 849 850 #define COPY_REG(name) \ 851 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 852 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 853 854 COPY_REG(ctx_ctrl); 855 COPY_REG(ctx_timestamp); 856 857 #undef COPY_REG 858 859 intel_gvt_hypervisor_write_gpa(vgpu, 860 workload->ring_context_gpa + 861 sizeof(*shadow_ring_context), 862 (void *)shadow_ring_context + 863 sizeof(*shadow_ring_context), 864 I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 865 866 kunmap(page); 867 } 868 869 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu, 870 intel_engine_mask_t engine_mask) 871 { 872 struct intel_vgpu_submission *s = &vgpu->submission; 873 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 874 struct intel_engine_cs *engine; 875 struct intel_vgpu_workload *pos, *n; 876 intel_engine_mask_t tmp; 877 878 /* free the unsubmited workloads in the queues. */ 879 for_each_engine_masked(engine, dev_priv, engine_mask, tmp) { 880 list_for_each_entry_safe(pos, n, 881 &s->workload_q_head[engine->id], list) { 882 list_del_init(&pos->list); 883 intel_vgpu_destroy_workload(pos); 884 } 885 clear_bit(engine->id, s->shadow_ctx_desc_updated); 886 } 887 } 888 889 static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 890 { 891 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 892 struct intel_vgpu_workload *workload = 893 scheduler->current_workload[ring_id]; 894 struct intel_vgpu *vgpu = workload->vgpu; 895 struct intel_vgpu_submission *s = &vgpu->submission; 896 struct i915_request *rq = workload->req; 897 int event; 898 899 mutex_lock(&vgpu->vgpu_lock); 900 mutex_lock(&gvt->sched_lock); 901 902 /* For the workload w/ request, needs to wait for the context 903 * switch to make sure request is completed. 904 * For the workload w/o request, directly complete the workload. 905 */ 906 if (rq) { 907 wait_event(workload->shadow_ctx_status_wq, 908 !atomic_read(&workload->shadow_ctx_active)); 909 910 /* If this request caused GPU hang, req->fence.error will 911 * be set to -EIO. Use -EIO to set workload status so 912 * that when this request caused GPU hang, didn't trigger 913 * context switch interrupt to guest. 914 */ 915 if (likely(workload->status == -EINPROGRESS)) { 916 if (workload->req->fence.error == -EIO) 917 workload->status = -EIO; 918 else 919 workload->status = 0; 920 } 921 922 if (!workload->status && 923 !(vgpu->resetting_eng & BIT(ring_id))) { 924 update_guest_context(workload); 925 926 for_each_set_bit(event, workload->pending_events, 927 INTEL_GVT_EVENT_MAX) 928 intel_vgpu_trigger_virtual_event(vgpu, event); 929 } 930 931 /* unpin shadow ctx as the shadow_ctx update is done */ 932 mutex_lock(&rq->i915->drm.struct_mutex); 933 intel_context_unpin(rq->hw_context); 934 mutex_unlock(&rq->i915->drm.struct_mutex); 935 936 i915_request_put(fetch_and_zero(&workload->req)); 937 } 938 939 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 940 ring_id, workload, workload->status); 941 942 scheduler->current_workload[ring_id] = NULL; 943 944 list_del_init(&workload->list); 945 946 if (workload->status || vgpu->resetting_eng & BIT(ring_id)) { 947 /* if workload->status is not successful means HW GPU 948 * has occurred GPU hang or something wrong with i915/GVT, 949 * and GVT won't inject context switch interrupt to guest. 950 * So this error is a vGPU hang actually to the guest. 951 * According to this we should emunlate a vGPU hang. If 952 * there are pending workloads which are already submitted 953 * from guest, we should clean them up like HW GPU does. 954 * 955 * if it is in middle of engine resetting, the pending 956 * workloads won't be submitted to HW GPU and will be 957 * cleaned up during the resetting process later, so doing 958 * the workload clean up here doesn't have any impact. 959 **/ 960 intel_vgpu_clean_workloads(vgpu, BIT(ring_id)); 961 } 962 963 workload->complete(workload); 964 965 atomic_dec(&s->running_workload_num); 966 wake_up(&scheduler->workload_complete_wq); 967 968 if (gvt->scheduler.need_reschedule) 969 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED); 970 971 mutex_unlock(&gvt->sched_lock); 972 mutex_unlock(&vgpu->vgpu_lock); 973 } 974 975 struct workload_thread_param { 976 struct intel_gvt *gvt; 977 int ring_id; 978 }; 979 980 static int workload_thread(void *priv) 981 { 982 struct workload_thread_param *p = (struct workload_thread_param *)priv; 983 struct intel_gvt *gvt = p->gvt; 984 int ring_id = p->ring_id; 985 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 986 struct intel_vgpu_workload *workload = NULL; 987 struct intel_vgpu *vgpu = NULL; 988 int ret; 989 bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9); 990 DEFINE_WAIT_FUNC(wait, woken_wake_function); 991 992 kfree(p); 993 994 gvt_dbg_core("workload thread for ring %d started\n", ring_id); 995 996 while (!kthread_should_stop()) { 997 add_wait_queue(&scheduler->waitq[ring_id], &wait); 998 do { 999 workload = pick_next_workload(gvt, ring_id); 1000 if (workload) 1001 break; 1002 wait_woken(&wait, TASK_INTERRUPTIBLE, 1003 MAX_SCHEDULE_TIMEOUT); 1004 } while (!kthread_should_stop()); 1005 remove_wait_queue(&scheduler->waitq[ring_id], &wait); 1006 1007 if (!workload) 1008 break; 1009 1010 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n", 1011 workload->ring_id, workload, 1012 workload->vgpu->id); 1013 1014 intel_runtime_pm_get(gvt->dev_priv); 1015 1016 gvt_dbg_sched("ring id %d will dispatch workload %p\n", 1017 workload->ring_id, workload); 1018 1019 if (need_force_wake) 1020 intel_uncore_forcewake_get(&gvt->dev_priv->uncore, 1021 FORCEWAKE_ALL); 1022 1023 ret = dispatch_workload(workload); 1024 1025 if (ret) { 1026 vgpu = workload->vgpu; 1027 gvt_vgpu_err("fail to dispatch workload, skip\n"); 1028 goto complete; 1029 } 1030 1031 gvt_dbg_sched("ring id %d wait workload %p\n", 1032 workload->ring_id, workload); 1033 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT); 1034 1035 complete: 1036 gvt_dbg_sched("will complete workload %p, status: %d\n", 1037 workload, workload->status); 1038 1039 complete_current_workload(gvt, ring_id); 1040 1041 if (need_force_wake) 1042 intel_uncore_forcewake_put(&gvt->dev_priv->uncore, 1043 FORCEWAKE_ALL); 1044 1045 intel_runtime_pm_put_unchecked(gvt->dev_priv); 1046 if (ret && (vgpu_is_vm_unhealthy(ret))) 1047 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1048 } 1049 return 0; 1050 } 1051 1052 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 1053 { 1054 struct intel_vgpu_submission *s = &vgpu->submission; 1055 struct intel_gvt *gvt = vgpu->gvt; 1056 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1057 1058 if (atomic_read(&s->running_workload_num)) { 1059 gvt_dbg_sched("wait vgpu idle\n"); 1060 1061 wait_event(scheduler->workload_complete_wq, 1062 !atomic_read(&s->running_workload_num)); 1063 } 1064 } 1065 1066 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 1067 { 1068 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1069 struct intel_engine_cs *engine; 1070 enum intel_engine_id i; 1071 1072 gvt_dbg_core("clean workload scheduler\n"); 1073 1074 for_each_engine(engine, gvt->dev_priv, i) { 1075 atomic_notifier_chain_unregister( 1076 &engine->context_status_notifier, 1077 &gvt->shadow_ctx_notifier_block[i]); 1078 kthread_stop(scheduler->thread[i]); 1079 } 1080 } 1081 1082 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 1083 { 1084 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 1085 struct workload_thread_param *param = NULL; 1086 struct intel_engine_cs *engine; 1087 enum intel_engine_id i; 1088 int ret; 1089 1090 gvt_dbg_core("init workload scheduler\n"); 1091 1092 init_waitqueue_head(&scheduler->workload_complete_wq); 1093 1094 for_each_engine(engine, gvt->dev_priv, i) { 1095 init_waitqueue_head(&scheduler->waitq[i]); 1096 1097 param = kzalloc(sizeof(*param), GFP_KERNEL); 1098 if (!param) { 1099 ret = -ENOMEM; 1100 goto err; 1101 } 1102 1103 param->gvt = gvt; 1104 param->ring_id = i; 1105 1106 scheduler->thread[i] = kthread_run(workload_thread, param, 1107 "gvt workload %d", i); 1108 if (IS_ERR(scheduler->thread[i])) { 1109 gvt_err("fail to create workload thread\n"); 1110 ret = PTR_ERR(scheduler->thread[i]); 1111 goto err; 1112 } 1113 1114 gvt->shadow_ctx_notifier_block[i].notifier_call = 1115 shadow_context_status_change; 1116 atomic_notifier_chain_register(&engine->context_status_notifier, 1117 &gvt->shadow_ctx_notifier_block[i]); 1118 } 1119 return 0; 1120 err: 1121 intel_gvt_clean_workload_scheduler(gvt); 1122 kfree(param); 1123 param = NULL; 1124 return ret; 1125 } 1126 1127 static void 1128 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s) 1129 { 1130 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt; 1131 int i; 1132 1133 if (i915_vm_is_4lvl(&i915_ppgtt->vm)) { 1134 px_dma(&i915_ppgtt->pml4) = s->i915_context_pml4; 1135 } else { 1136 for (i = 0; i < GEN8_3LVL_PDPES; i++) 1137 px_dma(i915_ppgtt->pdp.page_directory[i]) = 1138 s->i915_context_pdps[i]; 1139 } 1140 } 1141 1142 /** 1143 * intel_vgpu_clean_submission - free submission-related resource for vGPU 1144 * @vgpu: a vGPU 1145 * 1146 * This function is called when a vGPU is being destroyed. 1147 * 1148 */ 1149 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu) 1150 { 1151 struct intel_vgpu_submission *s = &vgpu->submission; 1152 1153 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0); 1154 i915_context_ppgtt_root_restore(s); 1155 i915_gem_context_put(s->shadow_ctx); 1156 kmem_cache_destroy(s->workloads); 1157 } 1158 1159 1160 /** 1161 * intel_vgpu_reset_submission - reset submission-related resource for vGPU 1162 * @vgpu: a vGPU 1163 * @engine_mask: engines expected to be reset 1164 * 1165 * This function is called when a vGPU is being destroyed. 1166 * 1167 */ 1168 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu, 1169 intel_engine_mask_t engine_mask) 1170 { 1171 struct intel_vgpu_submission *s = &vgpu->submission; 1172 1173 if (!s->active) 1174 return; 1175 1176 intel_vgpu_clean_workloads(vgpu, engine_mask); 1177 s->ops->reset(vgpu, engine_mask); 1178 } 1179 1180 static void 1181 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s) 1182 { 1183 struct i915_hw_ppgtt *i915_ppgtt = s->shadow_ctx->ppgtt; 1184 int i; 1185 1186 if (i915_vm_is_4lvl(&i915_ppgtt->vm)) 1187 s->i915_context_pml4 = px_dma(&i915_ppgtt->pml4); 1188 else { 1189 for (i = 0; i < GEN8_3LVL_PDPES; i++) 1190 s->i915_context_pdps[i] = 1191 px_dma(i915_ppgtt->pdp.page_directory[i]); 1192 } 1193 } 1194 1195 /** 1196 * intel_vgpu_setup_submission - setup submission-related resource for vGPU 1197 * @vgpu: a vGPU 1198 * 1199 * This function is called when a vGPU is being created. 1200 * 1201 * Returns: 1202 * Zero on success, negative error code if failed. 1203 * 1204 */ 1205 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 1206 { 1207 struct intel_vgpu_submission *s = &vgpu->submission; 1208 enum intel_engine_id i; 1209 struct intel_engine_cs *engine; 1210 int ret; 1211 1212 s->shadow_ctx = i915_gem_context_create_gvt( 1213 &vgpu->gvt->dev_priv->drm); 1214 if (IS_ERR(s->shadow_ctx)) 1215 return PTR_ERR(s->shadow_ctx); 1216 1217 i915_context_ppgtt_root_save(s); 1218 1219 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); 1220 1221 s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload", 1222 sizeof(struct intel_vgpu_workload), 0, 1223 SLAB_HWCACHE_ALIGN, 1224 offsetof(struct intel_vgpu_workload, rb_tail), 1225 sizeof_field(struct intel_vgpu_workload, rb_tail), 1226 NULL); 1227 1228 if (!s->workloads) { 1229 ret = -ENOMEM; 1230 goto out_shadow_ctx; 1231 } 1232 1233 for_each_engine(engine, vgpu->gvt->dev_priv, i) 1234 INIT_LIST_HEAD(&s->workload_q_head[i]); 1235 1236 atomic_set(&s->running_workload_num, 0); 1237 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES); 1238 1239 return 0; 1240 1241 out_shadow_ctx: 1242 i915_gem_context_put(s->shadow_ctx); 1243 return ret; 1244 } 1245 1246 /** 1247 * intel_vgpu_select_submission_ops - select virtual submission interface 1248 * @vgpu: a vGPU 1249 * @engine_mask: either ALL_ENGINES or target engine mask 1250 * @interface: expected vGPU virtual submission interface 1251 * 1252 * This function is called when guest configures submission interface. 1253 * 1254 * Returns: 1255 * Zero on success, negative error code if failed. 1256 * 1257 */ 1258 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu, 1259 intel_engine_mask_t engine_mask, 1260 unsigned int interface) 1261 { 1262 struct intel_vgpu_submission *s = &vgpu->submission; 1263 const struct intel_vgpu_submission_ops *ops[] = { 1264 [INTEL_VGPU_EXECLIST_SUBMISSION] = 1265 &intel_vgpu_execlist_submission_ops, 1266 }; 1267 int ret; 1268 1269 if (WARN_ON(interface >= ARRAY_SIZE(ops))) 1270 return -EINVAL; 1271 1272 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES)) 1273 return -EINVAL; 1274 1275 if (s->active) 1276 s->ops->clean(vgpu, engine_mask); 1277 1278 if (interface == 0) { 1279 s->ops = NULL; 1280 s->virtual_submission_interface = 0; 1281 s->active = false; 1282 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id); 1283 return 0; 1284 } 1285 1286 ret = ops[interface]->init(vgpu, engine_mask); 1287 if (ret) 1288 return ret; 1289 1290 s->ops = ops[interface]; 1291 s->virtual_submission_interface = interface; 1292 s->active = true; 1293 1294 gvt_dbg_core("vgpu%d: activate ops [ %s ]\n", 1295 vgpu->id, s->ops->name); 1296 1297 return 0; 1298 } 1299 1300 /** 1301 * intel_vgpu_destroy_workload - destroy a vGPU workload 1302 * @workload: workload to destroy 1303 * 1304 * This function is called when destroy a vGPU workload. 1305 * 1306 */ 1307 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload) 1308 { 1309 struct intel_vgpu_submission *s = &workload->vgpu->submission; 1310 1311 release_shadow_batch_buffer(workload); 1312 release_shadow_wa_ctx(&workload->wa_ctx); 1313 1314 if (workload->shadow_mm) 1315 intel_vgpu_mm_put(workload->shadow_mm); 1316 1317 kmem_cache_free(s->workloads, workload); 1318 } 1319 1320 static struct intel_vgpu_workload * 1321 alloc_workload(struct intel_vgpu *vgpu) 1322 { 1323 struct intel_vgpu_submission *s = &vgpu->submission; 1324 struct intel_vgpu_workload *workload; 1325 1326 workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL); 1327 if (!workload) 1328 return ERR_PTR(-ENOMEM); 1329 1330 INIT_LIST_HEAD(&workload->list); 1331 INIT_LIST_HEAD(&workload->shadow_bb); 1332 1333 init_waitqueue_head(&workload->shadow_ctx_status_wq); 1334 atomic_set(&workload->shadow_ctx_active, 0); 1335 1336 workload->status = -EINPROGRESS; 1337 workload->vgpu = vgpu; 1338 1339 return workload; 1340 } 1341 1342 #define RING_CTX_OFF(x) \ 1343 offsetof(struct execlist_ring_context, x) 1344 1345 static void read_guest_pdps(struct intel_vgpu *vgpu, 1346 u64 ring_context_gpa, u32 pdp[8]) 1347 { 1348 u64 gpa; 1349 int i; 1350 1351 gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val); 1352 1353 for (i = 0; i < 8; i++) 1354 intel_gvt_hypervisor_read_gpa(vgpu, 1355 gpa + i * 8, &pdp[7 - i], 4); 1356 } 1357 1358 static int prepare_mm(struct intel_vgpu_workload *workload) 1359 { 1360 struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc; 1361 struct intel_vgpu_mm *mm; 1362 struct intel_vgpu *vgpu = workload->vgpu; 1363 enum intel_gvt_gtt_type root_entry_type; 1364 u64 pdps[GVT_RING_CTX_NR_PDPS]; 1365 1366 switch (desc->addressing_mode) { 1367 case 1: /* legacy 32-bit */ 1368 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1369 break; 1370 case 3: /* legacy 64-bit */ 1371 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1372 break; 1373 default: 1374 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n"); 1375 return -EINVAL; 1376 } 1377 1378 read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps); 1379 1380 mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps); 1381 if (IS_ERR(mm)) 1382 return PTR_ERR(mm); 1383 1384 workload->shadow_mm = mm; 1385 return 0; 1386 } 1387 1388 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \ 1389 ((a)->lrca == (b)->lrca)) 1390 1391 #define get_last_workload(q) \ 1392 (list_empty(q) ? NULL : container_of(q->prev, \ 1393 struct intel_vgpu_workload, list)) 1394 /** 1395 * intel_vgpu_create_workload - create a vGPU workload 1396 * @vgpu: a vGPU 1397 * @ring_id: ring index 1398 * @desc: a guest context descriptor 1399 * 1400 * This function is called when creating a vGPU workload. 1401 * 1402 * Returns: 1403 * struct intel_vgpu_workload * on success, negative error code in 1404 * pointer if failed. 1405 * 1406 */ 1407 struct intel_vgpu_workload * 1408 intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id, 1409 struct execlist_ctx_descriptor_format *desc) 1410 { 1411 struct intel_vgpu_submission *s = &vgpu->submission; 1412 struct list_head *q = workload_q_head(vgpu, ring_id); 1413 struct intel_vgpu_workload *last_workload = get_last_workload(q); 1414 struct intel_vgpu_workload *workload = NULL; 1415 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1416 u64 ring_context_gpa; 1417 u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx; 1418 int ret; 1419 1420 ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 1421 (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT)); 1422 if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) { 1423 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca); 1424 return ERR_PTR(-EINVAL); 1425 } 1426 1427 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1428 RING_CTX_OFF(ring_header.val), &head, 4); 1429 1430 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1431 RING_CTX_OFF(ring_tail.val), &tail, 4); 1432 1433 head &= RB_HEAD_OFF_MASK; 1434 tail &= RB_TAIL_OFF_MASK; 1435 1436 if (last_workload && same_context(&last_workload->ctx_desc, desc)) { 1437 gvt_dbg_el("ring id %d cur workload == last\n", ring_id); 1438 gvt_dbg_el("ctx head %x real head %lx\n", head, 1439 last_workload->rb_tail); 1440 /* 1441 * cannot use guest context head pointer here, 1442 * as it might not be updated at this time 1443 */ 1444 head = last_workload->rb_tail; 1445 } 1446 1447 gvt_dbg_el("ring id %d begin a new workload\n", ring_id); 1448 1449 /* record some ring buffer register values for scan and shadow */ 1450 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1451 RING_CTX_OFF(rb_start.val), &start, 4); 1452 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1453 RING_CTX_OFF(rb_ctrl.val), &ctl, 4); 1454 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1455 RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4); 1456 1457 workload = alloc_workload(vgpu); 1458 if (IS_ERR(workload)) 1459 return workload; 1460 1461 workload->ring_id = ring_id; 1462 workload->ctx_desc = *desc; 1463 workload->ring_context_gpa = ring_context_gpa; 1464 workload->rb_head = head; 1465 workload->rb_tail = tail; 1466 workload->rb_start = start; 1467 workload->rb_ctl = ctl; 1468 1469 if (ring_id == RCS0) { 1470 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1471 RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4); 1472 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa + 1473 RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4); 1474 1475 workload->wa_ctx.indirect_ctx.guest_gma = 1476 indirect_ctx & INDIRECT_CTX_ADDR_MASK; 1477 workload->wa_ctx.indirect_ctx.size = 1478 (indirect_ctx & INDIRECT_CTX_SIZE_MASK) * 1479 CACHELINE_BYTES; 1480 workload->wa_ctx.per_ctx.guest_gma = 1481 per_ctx & PER_CTX_ADDR_MASK; 1482 workload->wa_ctx.per_ctx.valid = per_ctx & 1; 1483 } 1484 1485 gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n", 1486 workload, ring_id, head, tail, start, ctl); 1487 1488 ret = prepare_mm(workload); 1489 if (ret) { 1490 kmem_cache_free(s->workloads, workload); 1491 return ERR_PTR(ret); 1492 } 1493 1494 /* Only scan and shadow the first workload in the queue 1495 * as there is only one pre-allocated buf-obj for shadow. 1496 */ 1497 if (list_empty(workload_q_head(vgpu, ring_id))) { 1498 intel_runtime_pm_get(dev_priv); 1499 mutex_lock(&dev_priv->drm.struct_mutex); 1500 ret = intel_gvt_scan_and_shadow_workload(workload); 1501 mutex_unlock(&dev_priv->drm.struct_mutex); 1502 intel_runtime_pm_put_unchecked(dev_priv); 1503 } 1504 1505 if (ret) { 1506 if (vgpu_is_vm_unhealthy(ret)) 1507 enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR); 1508 intel_vgpu_destroy_workload(workload); 1509 return ERR_PTR(ret); 1510 } 1511 1512 return workload; 1513 } 1514 1515 /** 1516 * intel_vgpu_queue_workload - Qeue a vGPU workload 1517 * @workload: the workload to queue in 1518 */ 1519 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload) 1520 { 1521 list_add_tail(&workload->list, 1522 workload_q_head(workload->vgpu, workload->ring_id)); 1523 intel_gvt_kick_schedule(workload->vgpu->gvt); 1524 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->ring_id]); 1525 } 1526