1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36 #include <linux/kthread.h> 37 38 #include "i915_drv.h" 39 #include "gvt.h" 40 41 #define RING_CTX_OFF(x) \ 42 offsetof(struct execlist_ring_context, x) 43 44 static void set_context_pdp_root_pointer( 45 struct execlist_ring_context *ring_context, 46 u32 pdp[8]) 47 { 48 struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW; 49 int i; 50 51 for (i = 0; i < 8; i++) 52 pdp_pair[i].val = pdp[7 - i]; 53 } 54 55 static int populate_shadow_context(struct intel_vgpu_workload *workload) 56 { 57 struct intel_vgpu *vgpu = workload->vgpu; 58 struct intel_gvt *gvt = vgpu->gvt; 59 int ring_id = workload->ring_id; 60 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 61 struct drm_i915_gem_object *ctx_obj = 62 shadow_ctx->engine[ring_id].state->obj; 63 struct execlist_ring_context *shadow_ring_context; 64 struct page *page; 65 void *dst; 66 unsigned long context_gpa, context_page_num; 67 int i; 68 69 gvt_dbg_sched("ring id %d workload lrca %x", ring_id, 70 workload->ctx_desc.lrca); 71 72 context_page_num = intel_lr_context_size( 73 gvt->dev_priv->engine[ring_id]); 74 75 context_page_num = context_page_num >> PAGE_SHIFT; 76 77 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) 78 context_page_num = 19; 79 80 i = 2; 81 82 while (i < context_page_num) { 83 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 84 (u32)((workload->ctx_desc.lrca + i) << 85 GTT_PAGE_SHIFT)); 86 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 87 gvt_err("Invalid guest context descriptor\n"); 88 return -EINVAL; 89 } 90 91 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); 92 dst = kmap(page); 93 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, 94 GTT_PAGE_SIZE); 95 kunmap(page); 96 i++; 97 } 98 99 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 100 shadow_ring_context = kmap(page); 101 102 #define COPY_REG(name) \ 103 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 104 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 105 106 COPY_REG(ctx_ctrl); 107 COPY_REG(ctx_timestamp); 108 109 if (ring_id == RCS) { 110 COPY_REG(bb_per_ctx_ptr); 111 COPY_REG(rcs_indirect_ctx); 112 COPY_REG(rcs_indirect_ctx_offset); 113 } 114 #undef COPY_REG 115 116 set_context_pdp_root_pointer(shadow_ring_context, 117 workload->shadow_mm->shadow_page_table); 118 119 intel_gvt_hypervisor_read_gpa(vgpu, 120 workload->ring_context_gpa + 121 sizeof(*shadow_ring_context), 122 (void *)shadow_ring_context + 123 sizeof(*shadow_ring_context), 124 GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 125 126 kunmap(page); 127 return 0; 128 } 129 130 static int shadow_context_status_change(struct notifier_block *nb, 131 unsigned long action, void *data) 132 { 133 struct intel_vgpu *vgpu = container_of(nb, 134 struct intel_vgpu, shadow_ctx_notifier_block); 135 struct drm_i915_gem_request *req = 136 (struct drm_i915_gem_request *)data; 137 struct intel_gvt_workload_scheduler *scheduler = 138 &vgpu->gvt->scheduler; 139 struct intel_vgpu_workload *workload = 140 scheduler->current_workload[req->engine->id]; 141 142 switch (action) { 143 case INTEL_CONTEXT_SCHEDULE_IN: 144 intel_gvt_load_render_mmio(workload->vgpu, 145 workload->ring_id); 146 atomic_set(&workload->shadow_ctx_active, 1); 147 break; 148 case INTEL_CONTEXT_SCHEDULE_OUT: 149 intel_gvt_restore_render_mmio(workload->vgpu, 150 workload->ring_id); 151 atomic_set(&workload->shadow_ctx_active, 0); 152 break; 153 default: 154 WARN_ON(1); 155 return NOTIFY_OK; 156 } 157 wake_up(&workload->shadow_ctx_status_wq); 158 return NOTIFY_OK; 159 } 160 161 static int dispatch_workload(struct intel_vgpu_workload *workload) 162 { 163 int ring_id = workload->ring_id; 164 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 165 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 166 struct drm_i915_gem_request *rq; 167 int ret; 168 169 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", 170 ring_id, workload); 171 172 shadow_ctx->desc_template = workload->ctx_desc.addressing_mode << 173 GEN8_CTX_ADDRESSING_MODE_SHIFT; 174 175 mutex_lock(&dev_priv->drm.struct_mutex); 176 177 rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); 178 if (IS_ERR(rq)) { 179 gvt_err("fail to allocate gem request\n"); 180 ret = PTR_ERR(rq); 181 goto out; 182 } 183 184 gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq); 185 186 workload->req = i915_gem_request_get(rq); 187 188 ret = intel_gvt_scan_and_shadow_workload(workload); 189 if (ret) 190 goto out; 191 192 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 193 if (ret) 194 goto out; 195 196 ret = populate_shadow_context(workload); 197 if (ret) 198 goto out; 199 200 if (workload->prepare) { 201 ret = workload->prepare(workload); 202 if (ret) 203 goto out; 204 } 205 206 gvt_dbg_sched("ring id %d submit workload to i915 %p\n", 207 ring_id, workload->req); 208 209 ret = 0; 210 workload->dispatched = true; 211 out: 212 if (ret) 213 workload->status = ret; 214 215 if (!IS_ERR_OR_NULL(rq)) 216 i915_add_request_no_flush(rq); 217 mutex_unlock(&dev_priv->drm.struct_mutex); 218 return ret; 219 } 220 221 static struct intel_vgpu_workload *pick_next_workload( 222 struct intel_gvt *gvt, int ring_id) 223 { 224 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 225 struct intel_vgpu_workload *workload = NULL; 226 227 mutex_lock(&gvt->lock); 228 229 /* 230 * no current vgpu / will be scheduled out / no workload 231 * bail out 232 */ 233 if (!scheduler->current_vgpu) { 234 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id); 235 goto out; 236 } 237 238 if (scheduler->need_reschedule) { 239 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id); 240 goto out; 241 } 242 243 if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) { 244 gvt_dbg_sched("ring id %d stop - no available workload\n", 245 ring_id); 246 goto out; 247 } 248 249 /* 250 * still have current workload, maybe the workload disptacher 251 * fail to submit it for some reason, resubmit it. 252 */ 253 if (scheduler->current_workload[ring_id]) { 254 workload = scheduler->current_workload[ring_id]; 255 gvt_dbg_sched("ring id %d still have current workload %p\n", 256 ring_id, workload); 257 goto out; 258 } 259 260 /* 261 * pick a workload as current workload 262 * once current workload is set, schedule policy routines 263 * will wait the current workload is finished when trying to 264 * schedule out a vgpu. 265 */ 266 scheduler->current_workload[ring_id] = container_of( 267 workload_q_head(scheduler->current_vgpu, ring_id)->next, 268 struct intel_vgpu_workload, list); 269 270 workload = scheduler->current_workload[ring_id]; 271 272 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); 273 274 atomic_inc(&workload->vgpu->running_workload_num); 275 out: 276 mutex_unlock(&gvt->lock); 277 return workload; 278 } 279 280 static void update_guest_context(struct intel_vgpu_workload *workload) 281 { 282 struct intel_vgpu *vgpu = workload->vgpu; 283 struct intel_gvt *gvt = vgpu->gvt; 284 int ring_id = workload->ring_id; 285 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 286 struct drm_i915_gem_object *ctx_obj = 287 shadow_ctx->engine[ring_id].state->obj; 288 struct execlist_ring_context *shadow_ring_context; 289 struct page *page; 290 void *src; 291 unsigned long context_gpa, context_page_num; 292 int i; 293 294 gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id, 295 workload->ctx_desc.lrca); 296 297 context_page_num = intel_lr_context_size( 298 gvt->dev_priv->engine[ring_id]); 299 300 context_page_num = context_page_num >> PAGE_SHIFT; 301 302 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) 303 context_page_num = 19; 304 305 i = 2; 306 307 while (i < context_page_num) { 308 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 309 (u32)((workload->ctx_desc.lrca + i) << 310 GTT_PAGE_SHIFT)); 311 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 312 gvt_err("invalid guest context descriptor\n"); 313 return; 314 } 315 316 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); 317 src = kmap(page); 318 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, 319 GTT_PAGE_SIZE); 320 kunmap(page); 321 i++; 322 } 323 324 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 325 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 326 327 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 328 shadow_ring_context = kmap(page); 329 330 #define COPY_REG(name) \ 331 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 332 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 333 334 COPY_REG(ctx_ctrl); 335 COPY_REG(ctx_timestamp); 336 337 #undef COPY_REG 338 339 intel_gvt_hypervisor_write_gpa(vgpu, 340 workload->ring_context_gpa + 341 sizeof(*shadow_ring_context), 342 (void *)shadow_ring_context + 343 sizeof(*shadow_ring_context), 344 GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 345 346 kunmap(page); 347 } 348 349 static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 350 { 351 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 352 struct intel_vgpu_workload *workload; 353 int event; 354 355 mutex_lock(&gvt->lock); 356 357 workload = scheduler->current_workload[ring_id]; 358 359 if (!workload->status && !workload->vgpu->resetting) { 360 wait_event(workload->shadow_ctx_status_wq, 361 !atomic_read(&workload->shadow_ctx_active)); 362 363 update_guest_context(workload); 364 365 for_each_set_bit(event, workload->pending_events, 366 INTEL_GVT_EVENT_MAX) 367 intel_vgpu_trigger_virtual_event(workload->vgpu, 368 event); 369 } 370 371 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 372 ring_id, workload, workload->status); 373 374 scheduler->current_workload[ring_id] = NULL; 375 376 atomic_dec(&workload->vgpu->running_workload_num); 377 378 list_del_init(&workload->list); 379 workload->complete(workload); 380 381 wake_up(&scheduler->workload_complete_wq); 382 mutex_unlock(&gvt->lock); 383 } 384 385 struct workload_thread_param { 386 struct intel_gvt *gvt; 387 int ring_id; 388 }; 389 390 static DEFINE_MUTEX(scheduler_mutex); 391 392 static int workload_thread(void *priv) 393 { 394 struct workload_thread_param *p = (struct workload_thread_param *)priv; 395 struct intel_gvt *gvt = p->gvt; 396 int ring_id = p->ring_id; 397 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 398 struct intel_vgpu_workload *workload = NULL; 399 long lret; 400 int ret; 401 bool need_force_wake = IS_SKYLAKE(gvt->dev_priv); 402 DEFINE_WAIT_FUNC(wait, woken_wake_function); 403 404 kfree(p); 405 406 gvt_dbg_core("workload thread for ring %d started\n", ring_id); 407 408 while (!kthread_should_stop()) { 409 add_wait_queue(&scheduler->waitq[ring_id], &wait); 410 do { 411 workload = pick_next_workload(gvt, ring_id); 412 if (workload) 413 break; 414 wait_woken(&wait, TASK_INTERRUPTIBLE, 415 MAX_SCHEDULE_TIMEOUT); 416 } while (!kthread_should_stop()); 417 remove_wait_queue(&scheduler->waitq[ring_id], &wait); 418 419 if (!workload) 420 break; 421 422 mutex_lock(&scheduler_mutex); 423 424 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n", 425 workload->ring_id, workload, 426 workload->vgpu->id); 427 428 intel_runtime_pm_get(gvt->dev_priv); 429 430 gvt_dbg_sched("ring id %d will dispatch workload %p\n", 431 workload->ring_id, workload); 432 433 if (need_force_wake) 434 intel_uncore_forcewake_get(gvt->dev_priv, 435 FORCEWAKE_ALL); 436 437 mutex_lock(&gvt->lock); 438 ret = dispatch_workload(workload); 439 mutex_unlock(&gvt->lock); 440 441 if (ret) { 442 gvt_err("fail to dispatch workload, skip\n"); 443 goto complete; 444 } 445 446 gvt_dbg_sched("ring id %d wait workload %p\n", 447 workload->ring_id, workload); 448 449 lret = i915_wait_request(workload->req, 450 0, MAX_SCHEDULE_TIMEOUT); 451 if (lret < 0) { 452 workload->status = lret; 453 gvt_err("fail to wait workload, skip\n"); 454 } else { 455 workload->status = 0; 456 } 457 458 complete: 459 gvt_dbg_sched("will complete workload %p\n, status: %d\n", 460 workload, workload->status); 461 462 complete_current_workload(gvt, ring_id); 463 464 if (workload->req) 465 i915_gem_request_put(fetch_and_zero(&workload->req)); 466 467 if (need_force_wake) 468 intel_uncore_forcewake_put(gvt->dev_priv, 469 FORCEWAKE_ALL); 470 471 intel_runtime_pm_put(gvt->dev_priv); 472 473 mutex_unlock(&scheduler_mutex); 474 475 } 476 return 0; 477 } 478 479 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 480 { 481 struct intel_gvt *gvt = vgpu->gvt; 482 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 483 484 if (atomic_read(&vgpu->running_workload_num)) { 485 gvt_dbg_sched("wait vgpu idle\n"); 486 487 wait_event(scheduler->workload_complete_wq, 488 !atomic_read(&vgpu->running_workload_num)); 489 } 490 } 491 492 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 493 { 494 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 495 int i; 496 497 gvt_dbg_core("clean workload scheduler\n"); 498 499 for (i = 0; i < I915_NUM_ENGINES; i++) { 500 if (scheduler->thread[i]) { 501 kthread_stop(scheduler->thread[i]); 502 scheduler->thread[i] = NULL; 503 } 504 } 505 } 506 507 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 508 { 509 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 510 struct workload_thread_param *param = NULL; 511 int ret; 512 int i; 513 514 gvt_dbg_core("init workload scheduler\n"); 515 516 init_waitqueue_head(&scheduler->workload_complete_wq); 517 518 for (i = 0; i < I915_NUM_ENGINES; i++) { 519 /* check ring mask at init time */ 520 if (!HAS_ENGINE(gvt->dev_priv, i)) 521 continue; 522 523 init_waitqueue_head(&scheduler->waitq[i]); 524 525 param = kzalloc(sizeof(*param), GFP_KERNEL); 526 if (!param) { 527 ret = -ENOMEM; 528 goto err; 529 } 530 531 param->gvt = gvt; 532 param->ring_id = i; 533 534 scheduler->thread[i] = kthread_run(workload_thread, param, 535 "gvt workload %d", i); 536 if (IS_ERR(scheduler->thread[i])) { 537 gvt_err("fail to create workload thread\n"); 538 ret = PTR_ERR(scheduler->thread[i]); 539 goto err; 540 } 541 } 542 return 0; 543 err: 544 intel_gvt_clean_workload_scheduler(gvt); 545 kfree(param); 546 param = NULL; 547 return ret; 548 } 549 550 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu) 551 { 552 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 553 554 atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier, 555 &vgpu->shadow_ctx_notifier_block); 556 557 mutex_lock(&dev_priv->drm.struct_mutex); 558 559 /* a little hacky to mark as ctx closed */ 560 vgpu->shadow_ctx->closed = true; 561 i915_gem_context_put(vgpu->shadow_ctx); 562 563 mutex_unlock(&dev_priv->drm.struct_mutex); 564 } 565 566 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) 567 { 568 atomic_set(&vgpu->running_workload_num, 0); 569 570 vgpu->shadow_ctx = i915_gem_context_create_gvt( 571 &vgpu->gvt->dev_priv->drm); 572 if (IS_ERR(vgpu->shadow_ctx)) 573 return PTR_ERR(vgpu->shadow_ctx); 574 575 vgpu->shadow_ctx->engine[RCS].initialised = true; 576 577 vgpu->shadow_ctx_notifier_block.notifier_call = 578 shadow_context_status_change; 579 580 atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier, 581 &vgpu->shadow_ctx_notifier_block); 582 return 0; 583 } 584