1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhi Wang <zhi.a.wang@intel.com> 25 * 26 * Contributors: 27 * Ping Gao <ping.a.gao@intel.com> 28 * Tina Zhang <tina.zhang@intel.com> 29 * Chanbin Du <changbin.du@intel.com> 30 * Min He <min.he@intel.com> 31 * Bing Niu <bing.niu@intel.com> 32 * Zhenyu Wang <zhenyuw@linux.intel.com> 33 * 34 */ 35 36 #include <linux/kthread.h> 37 38 #include "i915_drv.h" 39 #include "gvt.h" 40 41 #define RING_CTX_OFF(x) \ 42 offsetof(struct execlist_ring_context, x) 43 44 static void set_context_pdp_root_pointer( 45 struct execlist_ring_context *ring_context, 46 u32 pdp[8]) 47 { 48 struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW; 49 int i; 50 51 for (i = 0; i < 8; i++) 52 pdp_pair[i].val = pdp[7 - i]; 53 } 54 55 static int populate_shadow_context(struct intel_vgpu_workload *workload) 56 { 57 struct intel_vgpu *vgpu = workload->vgpu; 58 struct intel_gvt *gvt = vgpu->gvt; 59 int ring_id = workload->ring_id; 60 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 61 struct drm_i915_gem_object *ctx_obj = 62 shadow_ctx->engine[ring_id].state->obj; 63 struct execlist_ring_context *shadow_ring_context; 64 struct page *page; 65 void *dst; 66 unsigned long context_gpa, context_page_num; 67 int i; 68 69 gvt_dbg_sched("ring id %d workload lrca %x", ring_id, 70 workload->ctx_desc.lrca); 71 72 context_page_num = intel_lr_context_size( 73 gvt->dev_priv->engine[ring_id]); 74 75 context_page_num = context_page_num >> PAGE_SHIFT; 76 77 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) 78 context_page_num = 19; 79 80 i = 2; 81 82 while (i < context_page_num) { 83 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 84 (u32)((workload->ctx_desc.lrca + i) << 85 GTT_PAGE_SHIFT)); 86 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 87 gvt_vgpu_err("Invalid guest context descriptor\n"); 88 return -EINVAL; 89 } 90 91 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); 92 dst = kmap(page); 93 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst, 94 GTT_PAGE_SIZE); 95 kunmap(page); 96 i++; 97 } 98 99 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 100 shadow_ring_context = kmap(page); 101 102 #define COPY_REG(name) \ 103 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \ 104 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 105 106 COPY_REG(ctx_ctrl); 107 COPY_REG(ctx_timestamp); 108 109 if (ring_id == RCS) { 110 COPY_REG(bb_per_ctx_ptr); 111 COPY_REG(rcs_indirect_ctx); 112 COPY_REG(rcs_indirect_ctx_offset); 113 } 114 #undef COPY_REG 115 116 set_context_pdp_root_pointer(shadow_ring_context, 117 workload->shadow_mm->shadow_page_table); 118 119 intel_gvt_hypervisor_read_gpa(vgpu, 120 workload->ring_context_gpa + 121 sizeof(*shadow_ring_context), 122 (void *)shadow_ring_context + 123 sizeof(*shadow_ring_context), 124 GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 125 126 kunmap(page); 127 return 0; 128 } 129 130 static int shadow_context_status_change(struct notifier_block *nb, 131 unsigned long action, void *data) 132 { 133 struct drm_i915_gem_request *req = (struct drm_i915_gem_request *)data; 134 struct intel_gvt *gvt = container_of(nb, struct intel_gvt, 135 shadow_ctx_notifier_block[req->engine->id]); 136 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 137 struct intel_vgpu_workload *workload = 138 scheduler->current_workload[req->engine->id]; 139 140 if (unlikely(!workload)) 141 return NOTIFY_OK; 142 143 switch (action) { 144 case INTEL_CONTEXT_SCHEDULE_IN: 145 intel_gvt_load_render_mmio(workload->vgpu, 146 workload->ring_id); 147 atomic_set(&workload->shadow_ctx_active, 1); 148 break; 149 case INTEL_CONTEXT_SCHEDULE_OUT: 150 intel_gvt_restore_render_mmio(workload->vgpu, 151 workload->ring_id); 152 /* If the status is -EINPROGRESS means this workload 153 * doesn't meet any issue during dispatching so when 154 * get the SCHEDULE_OUT set the status to be zero for 155 * good. If the status is NOT -EINPROGRESS means there 156 * is something wrong happened during dispatching and 157 * the status should not be set to zero 158 */ 159 if (workload->status == -EINPROGRESS) 160 workload->status = 0; 161 atomic_set(&workload->shadow_ctx_active, 0); 162 break; 163 default: 164 WARN_ON(1); 165 return NOTIFY_OK; 166 } 167 wake_up(&workload->shadow_ctx_status_wq); 168 return NOTIFY_OK; 169 } 170 171 static int dispatch_workload(struct intel_vgpu_workload *workload) 172 { 173 int ring_id = workload->ring_id; 174 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 175 struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv; 176 struct intel_engine_cs *engine = dev_priv->engine[ring_id]; 177 struct drm_i915_gem_request *rq; 178 struct intel_vgpu *vgpu = workload->vgpu; 179 int ret; 180 181 gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n", 182 ring_id, workload); 183 184 shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT); 185 shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode << 186 GEN8_CTX_ADDRESSING_MODE_SHIFT; 187 188 mutex_lock(&dev_priv->drm.struct_mutex); 189 190 /* pin shadow context by gvt even the shadow context will be pinned 191 * when i915 alloc request. That is because gvt will update the guest 192 * context from shadow context when workload is completed, and at that 193 * moment, i915 may already unpined the shadow context to make the 194 * shadow_ctx pages invalid. So gvt need to pin itself. After update 195 * the guest context, gvt can unpin the shadow_ctx safely. 196 */ 197 ret = engine->context_pin(engine, shadow_ctx); 198 if (ret) { 199 gvt_vgpu_err("fail to pin shadow context\n"); 200 workload->status = ret; 201 mutex_unlock(&dev_priv->drm.struct_mutex); 202 return ret; 203 } 204 205 rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx); 206 if (IS_ERR(rq)) { 207 gvt_vgpu_err("fail to allocate gem request\n"); 208 ret = PTR_ERR(rq); 209 goto out; 210 } 211 212 gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq); 213 214 workload->req = i915_gem_request_get(rq); 215 216 ret = intel_gvt_scan_and_shadow_workload(workload); 217 if (ret) 218 goto out; 219 220 if ((workload->ring_id == RCS) && 221 (workload->wa_ctx.indirect_ctx.size != 0)) { 222 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx); 223 if (ret) 224 goto out; 225 } 226 227 ret = populate_shadow_context(workload); 228 if (ret) 229 goto out; 230 231 if (workload->prepare) { 232 ret = workload->prepare(workload); 233 if (ret) 234 goto out; 235 } 236 237 gvt_dbg_sched("ring id %d submit workload to i915 %p\n", 238 ring_id, workload->req); 239 240 ret = 0; 241 workload->dispatched = true; 242 out: 243 if (ret) 244 workload->status = ret; 245 246 if (!IS_ERR_OR_NULL(rq)) 247 i915_add_request_no_flush(rq); 248 else 249 engine->context_unpin(engine, shadow_ctx); 250 251 mutex_unlock(&dev_priv->drm.struct_mutex); 252 return ret; 253 } 254 255 static struct intel_vgpu_workload *pick_next_workload( 256 struct intel_gvt *gvt, int ring_id) 257 { 258 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 259 struct intel_vgpu_workload *workload = NULL; 260 261 mutex_lock(&gvt->lock); 262 263 /* 264 * no current vgpu / will be scheduled out / no workload 265 * bail out 266 */ 267 if (!scheduler->current_vgpu) { 268 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id); 269 goto out; 270 } 271 272 if (scheduler->need_reschedule) { 273 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id); 274 goto out; 275 } 276 277 if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) { 278 gvt_dbg_sched("ring id %d stop - no available workload\n", 279 ring_id); 280 goto out; 281 } 282 283 /* 284 * still have current workload, maybe the workload disptacher 285 * fail to submit it for some reason, resubmit it. 286 */ 287 if (scheduler->current_workload[ring_id]) { 288 workload = scheduler->current_workload[ring_id]; 289 gvt_dbg_sched("ring id %d still have current workload %p\n", 290 ring_id, workload); 291 goto out; 292 } 293 294 /* 295 * pick a workload as current workload 296 * once current workload is set, schedule policy routines 297 * will wait the current workload is finished when trying to 298 * schedule out a vgpu. 299 */ 300 scheduler->current_workload[ring_id] = container_of( 301 workload_q_head(scheduler->current_vgpu, ring_id)->next, 302 struct intel_vgpu_workload, list); 303 304 workload = scheduler->current_workload[ring_id]; 305 306 gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload); 307 308 atomic_inc(&workload->vgpu->running_workload_num); 309 out: 310 mutex_unlock(&gvt->lock); 311 return workload; 312 } 313 314 static void update_guest_context(struct intel_vgpu_workload *workload) 315 { 316 struct intel_vgpu *vgpu = workload->vgpu; 317 struct intel_gvt *gvt = vgpu->gvt; 318 int ring_id = workload->ring_id; 319 struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx; 320 struct drm_i915_gem_object *ctx_obj = 321 shadow_ctx->engine[ring_id].state->obj; 322 struct execlist_ring_context *shadow_ring_context; 323 struct page *page; 324 void *src; 325 unsigned long context_gpa, context_page_num; 326 int i; 327 328 gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id, 329 workload->ctx_desc.lrca); 330 331 context_page_num = intel_lr_context_size( 332 gvt->dev_priv->engine[ring_id]); 333 334 context_page_num = context_page_num >> PAGE_SHIFT; 335 336 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS) 337 context_page_num = 19; 338 339 i = 2; 340 341 while (i < context_page_num) { 342 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 343 (u32)((workload->ctx_desc.lrca + i) << 344 GTT_PAGE_SHIFT)); 345 if (context_gpa == INTEL_GVT_INVALID_ADDR) { 346 gvt_vgpu_err("invalid guest context descriptor\n"); 347 return; 348 } 349 350 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i); 351 src = kmap(page); 352 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src, 353 GTT_PAGE_SIZE); 354 kunmap(page); 355 i++; 356 } 357 358 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + 359 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4); 360 361 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); 362 shadow_ring_context = kmap(page); 363 364 #define COPY_REG(name) \ 365 intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \ 366 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) 367 368 COPY_REG(ctx_ctrl); 369 COPY_REG(ctx_timestamp); 370 371 #undef COPY_REG 372 373 intel_gvt_hypervisor_write_gpa(vgpu, 374 workload->ring_context_gpa + 375 sizeof(*shadow_ring_context), 376 (void *)shadow_ring_context + 377 sizeof(*shadow_ring_context), 378 GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); 379 380 kunmap(page); 381 } 382 383 static void complete_current_workload(struct intel_gvt *gvt, int ring_id) 384 { 385 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 386 struct intel_vgpu_workload *workload; 387 struct intel_vgpu *vgpu; 388 int event; 389 390 mutex_lock(&gvt->lock); 391 392 workload = scheduler->current_workload[ring_id]; 393 vgpu = workload->vgpu; 394 395 /* For the workload w/ request, needs to wait for the context 396 * switch to make sure request is completed. 397 * For the workload w/o request, directly complete the workload. 398 */ 399 if (workload->req) { 400 struct drm_i915_private *dev_priv = 401 workload->vgpu->gvt->dev_priv; 402 struct intel_engine_cs *engine = 403 dev_priv->engine[workload->ring_id]; 404 wait_event(workload->shadow_ctx_status_wq, 405 !atomic_read(&workload->shadow_ctx_active)); 406 407 i915_gem_request_put(fetch_and_zero(&workload->req)); 408 409 if (!workload->status && !vgpu->resetting) { 410 update_guest_context(workload); 411 412 for_each_set_bit(event, workload->pending_events, 413 INTEL_GVT_EVENT_MAX) 414 intel_vgpu_trigger_virtual_event(vgpu, event); 415 } 416 mutex_lock(&dev_priv->drm.struct_mutex); 417 /* unpin shadow ctx as the shadow_ctx update is done */ 418 engine->context_unpin(engine, workload->vgpu->shadow_ctx); 419 mutex_unlock(&dev_priv->drm.struct_mutex); 420 } 421 422 gvt_dbg_sched("ring id %d complete workload %p status %d\n", 423 ring_id, workload, workload->status); 424 425 scheduler->current_workload[ring_id] = NULL; 426 427 list_del_init(&workload->list); 428 workload->complete(workload); 429 430 atomic_dec(&vgpu->running_workload_num); 431 wake_up(&scheduler->workload_complete_wq); 432 mutex_unlock(&gvt->lock); 433 } 434 435 struct workload_thread_param { 436 struct intel_gvt *gvt; 437 int ring_id; 438 }; 439 440 static DEFINE_MUTEX(scheduler_mutex); 441 442 static int workload_thread(void *priv) 443 { 444 struct workload_thread_param *p = (struct workload_thread_param *)priv; 445 struct intel_gvt *gvt = p->gvt; 446 int ring_id = p->ring_id; 447 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 448 struct intel_vgpu_workload *workload = NULL; 449 struct intel_vgpu *vgpu = NULL; 450 int ret; 451 bool need_force_wake = IS_SKYLAKE(gvt->dev_priv); 452 DEFINE_WAIT_FUNC(wait, woken_wake_function); 453 454 kfree(p); 455 456 gvt_dbg_core("workload thread for ring %d started\n", ring_id); 457 458 while (!kthread_should_stop()) { 459 add_wait_queue(&scheduler->waitq[ring_id], &wait); 460 do { 461 workload = pick_next_workload(gvt, ring_id); 462 if (workload) 463 break; 464 wait_woken(&wait, TASK_INTERRUPTIBLE, 465 MAX_SCHEDULE_TIMEOUT); 466 } while (!kthread_should_stop()); 467 remove_wait_queue(&scheduler->waitq[ring_id], &wait); 468 469 if (!workload) 470 break; 471 472 mutex_lock(&scheduler_mutex); 473 474 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n", 475 workload->ring_id, workload, 476 workload->vgpu->id); 477 478 intel_runtime_pm_get(gvt->dev_priv); 479 480 gvt_dbg_sched("ring id %d will dispatch workload %p\n", 481 workload->ring_id, workload); 482 483 if (need_force_wake) 484 intel_uncore_forcewake_get(gvt->dev_priv, 485 FORCEWAKE_ALL); 486 487 mutex_lock(&gvt->lock); 488 ret = dispatch_workload(workload); 489 mutex_unlock(&gvt->lock); 490 491 if (ret) { 492 vgpu = workload->vgpu; 493 gvt_vgpu_err("fail to dispatch workload, skip\n"); 494 goto complete; 495 } 496 497 gvt_dbg_sched("ring id %d wait workload %p\n", 498 workload->ring_id, workload); 499 i915_wait_request(workload->req, 0, MAX_SCHEDULE_TIMEOUT); 500 501 complete: 502 gvt_dbg_sched("will complete workload %p, status: %d\n", 503 workload, workload->status); 504 505 complete_current_workload(gvt, ring_id); 506 507 if (need_force_wake) 508 intel_uncore_forcewake_put(gvt->dev_priv, 509 FORCEWAKE_ALL); 510 511 intel_runtime_pm_put(gvt->dev_priv); 512 513 mutex_unlock(&scheduler_mutex); 514 515 } 516 return 0; 517 } 518 519 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu) 520 { 521 struct intel_gvt *gvt = vgpu->gvt; 522 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 523 524 if (atomic_read(&vgpu->running_workload_num)) { 525 gvt_dbg_sched("wait vgpu idle\n"); 526 527 wait_event(scheduler->workload_complete_wq, 528 !atomic_read(&vgpu->running_workload_num)); 529 } 530 } 531 532 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt) 533 { 534 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 535 struct intel_engine_cs *engine; 536 enum intel_engine_id i; 537 538 gvt_dbg_core("clean workload scheduler\n"); 539 540 for_each_engine(engine, gvt->dev_priv, i) { 541 atomic_notifier_chain_unregister( 542 &engine->context_status_notifier, 543 &gvt->shadow_ctx_notifier_block[i]); 544 kthread_stop(scheduler->thread[i]); 545 } 546 } 547 548 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt) 549 { 550 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; 551 struct workload_thread_param *param = NULL; 552 struct intel_engine_cs *engine; 553 enum intel_engine_id i; 554 int ret; 555 556 gvt_dbg_core("init workload scheduler\n"); 557 558 init_waitqueue_head(&scheduler->workload_complete_wq); 559 560 for_each_engine(engine, gvt->dev_priv, i) { 561 init_waitqueue_head(&scheduler->waitq[i]); 562 563 param = kzalloc(sizeof(*param), GFP_KERNEL); 564 if (!param) { 565 ret = -ENOMEM; 566 goto err; 567 } 568 569 param->gvt = gvt; 570 param->ring_id = i; 571 572 scheduler->thread[i] = kthread_run(workload_thread, param, 573 "gvt workload %d", i); 574 if (IS_ERR(scheduler->thread[i])) { 575 gvt_err("fail to create workload thread\n"); 576 ret = PTR_ERR(scheduler->thread[i]); 577 goto err; 578 } 579 580 gvt->shadow_ctx_notifier_block[i].notifier_call = 581 shadow_context_status_change; 582 atomic_notifier_chain_register(&engine->context_status_notifier, 583 &gvt->shadow_ctx_notifier_block[i]); 584 } 585 return 0; 586 err: 587 intel_gvt_clean_workload_scheduler(gvt); 588 kfree(param); 589 param = NULL; 590 return ret; 591 } 592 593 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu) 594 { 595 i915_gem_context_put_unlocked(vgpu->shadow_ctx); 596 } 597 598 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu) 599 { 600 atomic_set(&vgpu->running_workload_num, 0); 601 602 vgpu->shadow_ctx = i915_gem_context_create_gvt( 603 &vgpu->gvt->dev_priv->drm); 604 if (IS_ERR(vgpu->shadow_ctx)) 605 return PTR_ERR(vgpu->shadow_ctx); 606 607 vgpu->shadow_ctx->engine[RCS].initialised = true; 608 609 return 0; 610 } 611