1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Zhenyu Wang <zhenyuw@linux.intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * Bing Niu <bing.niu@intel.com> 33 * 34 */ 35 36 #include "i915_drv.h" 37 #include "i915_reg.h" 38 #include "gt/intel_context.h" 39 #include "gt/intel_engine_regs.h" 40 #include "gt/intel_gpu_commands.h" 41 #include "gt/intel_gt_regs.h" 42 #include "gt/intel_ring.h" 43 #include "gvt.h" 44 #include "trace.h" 45 46 #define GEN9_MOCS_SIZE 64 47 48 /* Raw offset is appened to each line for convenience. */ 49 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 50 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ 51 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 52 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 53 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 61 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 62 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 63 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 64 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 65 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 66 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 67 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 68 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 69 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 70 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 71 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 72 73 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 74 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 75 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 76 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 77 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 78 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 79 }; 80 81 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 82 {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ 83 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 84 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 85 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 86 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 87 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 88 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 89 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 90 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 91 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 92 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 93 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 94 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 95 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 96 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 97 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 98 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 99 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 100 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 101 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 102 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 103 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 104 105 {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 106 {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 107 {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 108 {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 109 {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 110 {RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */ 111 {RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */ 112 {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */ 113 {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 114 {RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */ 115 {RCS0, _MMIO(0xe184), 0xffff, true}, /* GEN8_HALF_SLICE_CHICKEN3 */ 116 {RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */ 117 {RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */ 118 {RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */ 119 {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */ 120 {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */ 121 {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */ 122 {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ 123 {RCS0, TRVADR, 0, true}, /* 0x4df0 */ 124 {RCS0, TRTTE, 0, true}, /* 0x4df4 */ 125 {RCS0, _MMIO(0x4dfc), 0, true}, 126 127 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 128 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 129 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 130 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 131 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 132 133 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 134 135 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 136 137 {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 138 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 139 {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 140 {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 141 142 {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 143 {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */ 144 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ 145 146 {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 147 {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 148 {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 149 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 150 }; 151 152 static struct { 153 bool initialized; 154 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 155 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 156 } gen9_render_mocs; 157 158 static u32 gen9_mocs_mmio_offset_list[] = { 159 [RCS0] = 0xc800, 160 [VCS0] = 0xc900, 161 [VCS1] = 0xca00, 162 [BCS0] = 0xcc00, 163 [VECS0] = 0xcb00, 164 }; 165 166 static void load_render_mocs(const struct intel_engine_cs *engine) 167 { 168 struct intel_gvt *gvt = engine->i915->gvt; 169 struct intel_uncore *uncore = engine->uncore; 170 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; 171 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; 172 i915_reg_t offset; 173 int ring_id, i; 174 175 /* Platform doesn't have mocs mmios. */ 176 if (!regs) 177 return; 178 179 for (ring_id = 0; ring_id < cnt; ring_id++) { 180 if (!HAS_ENGINE(engine->gt, ring_id)) 181 continue; 182 183 offset.reg = regs[ring_id]; 184 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 185 gen9_render_mocs.control_table[ring_id][i] = 186 intel_uncore_read_fw(uncore, offset); 187 offset.reg += 4; 188 } 189 } 190 191 offset.reg = 0xb020; 192 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 193 gen9_render_mocs.l3cc_table[i] = 194 intel_uncore_read_fw(uncore, offset); 195 offset.reg += 4; 196 } 197 gen9_render_mocs.initialized = true; 198 } 199 200 static int 201 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 202 struct i915_request *req) 203 { 204 u32 *cs; 205 int ret; 206 struct engine_mmio *mmio; 207 struct intel_gvt *gvt = vgpu->gvt; 208 int ring_id = req->engine->id; 209 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 210 211 if (count == 0) 212 return 0; 213 214 ret = req->engine->emit_flush(req, EMIT_BARRIER); 215 if (ret) 216 return ret; 217 218 cs = intel_ring_begin(req, count * 2 + 2); 219 if (IS_ERR(cs)) 220 return PTR_ERR(cs); 221 222 *cs++ = MI_LOAD_REGISTER_IMM(count); 223 for (mmio = gvt->engine_mmio_list.mmio; 224 i915_mmio_reg_valid(mmio->reg); mmio++) { 225 if (mmio->id != ring_id || !mmio->in_context) 226 continue; 227 228 *cs++ = i915_mmio_reg_offset(mmio->reg); 229 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); 230 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 231 *(cs-2), *(cs-1), vgpu->id, ring_id); 232 } 233 234 *cs++ = MI_NOOP; 235 intel_ring_advance(req, cs); 236 237 ret = req->engine->emit_flush(req, EMIT_BARRIER); 238 if (ret) 239 return ret; 240 241 return 0; 242 } 243 244 static int 245 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 246 struct i915_request *req) 247 { 248 unsigned int index; 249 u32 *cs; 250 251 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 252 if (IS_ERR(cs)) 253 return PTR_ERR(cs); 254 255 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 256 257 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 258 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 259 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 260 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 261 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 262 263 } 264 265 *cs++ = MI_NOOP; 266 intel_ring_advance(req, cs); 267 268 return 0; 269 } 270 271 static int 272 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 273 struct i915_request *req) 274 { 275 unsigned int index; 276 u32 *cs; 277 278 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 279 if (IS_ERR(cs)) 280 return PTR_ERR(cs); 281 282 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 283 284 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 285 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 286 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 287 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 288 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 289 290 } 291 292 *cs++ = MI_NOOP; 293 intel_ring_advance(req, cs); 294 295 return 0; 296 } 297 298 /* 299 * Use lri command to initialize the mmio which is in context state image for 300 * inhibit context, it contains tracked engine mmio, render_mocs and 301 * render_mocs_l3cc. 302 */ 303 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 304 struct i915_request *req) 305 { 306 int ret; 307 u32 *cs; 308 309 cs = intel_ring_begin(req, 2); 310 if (IS_ERR(cs)) 311 return PTR_ERR(cs); 312 313 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 314 *cs++ = MI_NOOP; 315 intel_ring_advance(req, cs); 316 317 ret = restore_context_mmio_for_inhibit(vgpu, req); 318 if (ret) 319 goto out; 320 321 /* no MOCS register in context except render engine */ 322 if (req->engine->id != RCS0) 323 goto out; 324 325 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 326 if (ret) 327 goto out; 328 329 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 330 if (ret) 331 goto out; 332 333 out: 334 cs = intel_ring_begin(req, 2); 335 if (IS_ERR(cs)) 336 return PTR_ERR(cs); 337 338 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 339 *cs++ = MI_NOOP; 340 intel_ring_advance(req, cs); 341 342 return ret; 343 } 344 345 static u32 gen8_tlb_mmio_offset_list[] = { 346 [RCS0] = 0x4260, 347 [VCS0] = 0x4264, 348 [VCS1] = 0x4268, 349 [BCS0] = 0x426c, 350 [VECS0] = 0x4270, 351 }; 352 353 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, 354 const struct intel_engine_cs *engine) 355 { 356 struct intel_uncore *uncore = engine->uncore; 357 struct intel_vgpu_submission *s = &vgpu->submission; 358 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; 359 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; 360 enum forcewake_domains fw; 361 i915_reg_t reg; 362 363 if (!regs) 364 return; 365 366 if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt)) 367 return; 368 369 if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending)) 370 return; 371 372 reg = _MMIO(regs[engine->id]); 373 374 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 375 * we need to put a forcewake when invalidating RCS TLB caches, 376 * otherwise device can go to RC6 state and interrupt invalidation 377 * process 378 */ 379 fw = intel_uncore_forcewake_for_reg(uncore, reg, 380 FW_REG_READ | FW_REG_WRITE); 381 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9) 382 fw |= FORCEWAKE_RENDER; 383 384 intel_uncore_forcewake_get(uncore, fw); 385 386 intel_uncore_write_fw(uncore, reg, 0x1); 387 388 if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50)) 389 gvt_vgpu_err("timeout in invalidate ring %s tlb\n", 390 engine->name); 391 else 392 vgpu_vreg_t(vgpu, reg) = 0; 393 394 intel_uncore_forcewake_put(uncore, fw); 395 396 gvt_dbg_core("invalidate TLB for ring %s\n", engine->name); 397 } 398 399 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 400 const struct intel_engine_cs *engine) 401 { 402 u32 regs[] = { 403 [RCS0] = 0xc800, 404 [VCS0] = 0xc900, 405 [VCS1] = 0xca00, 406 [BCS0] = 0xcc00, 407 [VECS0] = 0xcb00, 408 }; 409 struct intel_uncore *uncore = engine->uncore; 410 i915_reg_t offset, l3_offset; 411 u32 old_v, new_v; 412 int i; 413 414 if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs))) 415 return; 416 417 if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9) 418 return; 419 420 if (!pre && !gen9_render_mocs.initialized) 421 load_render_mocs(engine); 422 423 offset.reg = regs[engine->id]; 424 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 425 if (pre) 426 old_v = vgpu_vreg_t(pre, offset); 427 else 428 old_v = gen9_render_mocs.control_table[engine->id][i]; 429 if (next) 430 new_v = vgpu_vreg_t(next, offset); 431 else 432 new_v = gen9_render_mocs.control_table[engine->id][i]; 433 434 if (old_v != new_v) 435 intel_uncore_write_fw(uncore, offset, new_v); 436 437 offset.reg += 4; 438 } 439 440 if (engine->id == RCS0) { 441 l3_offset.reg = 0xb020; 442 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 443 if (pre) 444 old_v = vgpu_vreg_t(pre, l3_offset); 445 else 446 old_v = gen9_render_mocs.l3cc_table[i]; 447 if (next) 448 new_v = vgpu_vreg_t(next, l3_offset); 449 else 450 new_v = gen9_render_mocs.l3cc_table[i]; 451 452 if (old_v != new_v) 453 intel_uncore_write_fw(uncore, l3_offset, new_v); 454 455 l3_offset.reg += 4; 456 } 457 } 458 } 459 460 #define CTX_CONTEXT_CONTROL_VAL 0x03 461 462 bool is_inhibit_context(struct intel_context *ce) 463 { 464 const u32 *reg_state = ce->lrc_reg_state; 465 u32 inhibit_mask = 466 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 467 468 return inhibit_mask == 469 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 470 } 471 472 /* Switch ring mmio values (context). */ 473 static void switch_mmio(struct intel_vgpu *pre, 474 struct intel_vgpu *next, 475 const struct intel_engine_cs *engine) 476 { 477 struct intel_uncore *uncore = engine->uncore; 478 struct intel_vgpu_submission *s; 479 struct engine_mmio *mmio; 480 u32 old_v, new_v; 481 482 if (GRAPHICS_VER(engine->i915) >= 9) 483 switch_mocs(pre, next, engine); 484 485 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; 486 i915_mmio_reg_valid(mmio->reg); mmio++) { 487 if (mmio->id != engine->id) 488 continue; 489 /* 490 * No need to do save or restore of the mmio which is in context 491 * state image on gen9, it's initialized by lri command and 492 * save or restore with context together. 493 */ 494 if (GRAPHICS_VER(engine->i915) == 9 && mmio->in_context) 495 continue; 496 497 // save 498 if (pre) { 499 vgpu_vreg_t(pre, mmio->reg) = 500 intel_uncore_read_fw(uncore, mmio->reg); 501 if (mmio->mask) 502 vgpu_vreg_t(pre, mmio->reg) &= 503 ~(mmio->mask << 16); 504 old_v = vgpu_vreg_t(pre, mmio->reg); 505 } else { 506 old_v = mmio->value = 507 intel_uncore_read_fw(uncore, mmio->reg); 508 } 509 510 // restore 511 if (next) { 512 s = &next->submission; 513 /* 514 * No need to restore the mmio which is in context state 515 * image if it's not inhibit context, it will restore 516 * itself. 517 */ 518 if (mmio->in_context && 519 !is_inhibit_context(s->shadow[engine->id])) 520 continue; 521 522 if (mmio->mask) 523 new_v = vgpu_vreg_t(next, mmio->reg) | 524 (mmio->mask << 16); 525 else 526 new_v = vgpu_vreg_t(next, mmio->reg); 527 } else { 528 if (mmio->in_context) 529 continue; 530 if (mmio->mask) 531 new_v = mmio->value | (mmio->mask << 16); 532 else 533 new_v = mmio->value; 534 } 535 536 intel_uncore_write_fw(uncore, mmio->reg, new_v); 537 538 trace_render_mmio(pre ? pre->id : 0, 539 next ? next->id : 0, 540 "switch", 541 i915_mmio_reg_offset(mmio->reg), 542 old_v, new_v); 543 } 544 545 if (next) 546 handle_tlb_pending_event(next, engine); 547 } 548 549 /** 550 * intel_gvt_switch_mmio - switch mmio context of specific engine 551 * @pre: the last vGPU that own the engine 552 * @next: the vGPU to switch to 553 * @engine: the engine 554 * 555 * If pre is null indicates that host own the engine. If next is null 556 * indicates that we are switching to host workload. 557 */ 558 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 559 struct intel_vgpu *next, 560 const struct intel_engine_cs *engine) 561 { 562 if (WARN(!pre && !next, "switch ring %s from host to HOST\n", 563 engine->name)) 564 return; 565 566 gvt_dbg_render("switch ring %s from %s to %s\n", engine->name, 567 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 568 569 /** 570 * We are using raw mmio access wrapper to improve the 571 * performace for batch mmio read/write, so we need 572 * handle forcewake mannually. 573 */ 574 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); 575 switch_mmio(pre, next, engine); 576 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); 577 } 578 579 /** 580 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 581 * @gvt: GVT device 582 * 583 */ 584 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 585 { 586 struct engine_mmio *mmio; 587 588 if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 589 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 590 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 591 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 592 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list; 593 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list); 594 } else { 595 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 596 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 597 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 598 } 599 600 for (mmio = gvt->engine_mmio_list.mmio; 601 i915_mmio_reg_valid(mmio->reg); mmio++) { 602 if (mmio->in_context) { 603 gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++; 604 intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg); 605 } 606 } 607 } 608