1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Eddie Dong <eddie.dong@intel.com>
25  *    Kevin Tian <kevin.tian@intel.com>
26  *
27  * Contributors:
28  *    Zhi Wang <zhi.a.wang@intel.com>
29  *    Changbin Du <changbin.du@intel.com>
30  *    Zhenyu Wang <zhenyuw@linux.intel.com>
31  *    Tina Zhang <tina.zhang@intel.com>
32  *    Bing Niu <bing.niu@intel.com>
33  *
34  */
35 
36 #include "i915_drv.h"
37 #include "gt/intel_context.h"
38 #include "gt/intel_engine_regs.h"
39 #include "gt/intel_gpu_commands.h"
40 #include "gt/intel_gt_regs.h"
41 #include "gt/intel_ring.h"
42 #include "gvt.h"
43 #include "trace.h"
44 
45 #define GEN9_MOCS_SIZE		64
46 
47 /* Raw offset is appened to each line for convenience. */
48 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
49 	{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
50 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
51 	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
52 	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
53 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
54 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
55 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
56 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
57 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
58 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
59 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
60 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
61 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
62 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
63 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
64 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
65 	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
66 	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
67 	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
68 	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
69 	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
70 	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
71 
72 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
73 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
74 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
75 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
76 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
77 	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
78 };
79 
80 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
81 	{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
82 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
83 	{RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
84 	{RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
85 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
86 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
87 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
88 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
89 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
90 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */
91 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */
92 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */
93 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */
94 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */
95 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */
96 	{RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */
97 	{RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */
98 	{RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */
99 	{RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */
100 	{RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */
101 	{RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */
102 	{RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */
103 
104 	{RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */
105 	{RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */
106 	{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
107 	{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
108 	{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
109 	{RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
110 	{RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */
111 	{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
112 	{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
113 	{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
114 	{RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
115 	{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
116 	{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
117 	{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
118 	{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
119 	{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
120 	{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
121 	{RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */
122 	{RCS0, TRVADR, 0, true}, /* 0x4df0 */
123 	{RCS0, TRTTE, 0, true}, /* 0x4df4 */
124 	{RCS0, _MMIO(0x4dfc), 0, true},
125 
126 	{BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */
127 	{BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */
128 	{BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
129 	{BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
130 	{BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */
131 
132 	{VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */
133 
134 	{VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
135 
136 	{RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */
137 	{RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
138 	{RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */
139 	{RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */
140 
141 	{RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */
142 	{RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */
143 	{RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
144 
145 	{RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
146 	{RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
147 	{RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
148 	{RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */
149 };
150 
151 static struct {
152 	bool initialized;
153 	u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
154 	u32 l3cc_table[GEN9_MOCS_SIZE / 2];
155 } gen9_render_mocs;
156 
157 static u32 gen9_mocs_mmio_offset_list[] = {
158 	[RCS0]  = 0xc800,
159 	[VCS0]  = 0xc900,
160 	[VCS1]  = 0xca00,
161 	[BCS0]  = 0xcc00,
162 	[VECS0] = 0xcb00,
163 };
164 
165 static void load_render_mocs(const struct intel_engine_cs *engine)
166 {
167 	struct intel_gvt *gvt = engine->i915->gvt;
168 	struct intel_uncore *uncore = engine->uncore;
169 	u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;
170 	u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;
171 	i915_reg_t offset;
172 	int ring_id, i;
173 
174 	/* Platform doesn't have mocs mmios. */
175 	if (!regs)
176 		return;
177 
178 	for (ring_id = 0; ring_id < cnt; ring_id++) {
179 		if (!HAS_ENGINE(engine->gt, ring_id))
180 			continue;
181 
182 		offset.reg = regs[ring_id];
183 		for (i = 0; i < GEN9_MOCS_SIZE; i++) {
184 			gen9_render_mocs.control_table[ring_id][i] =
185 				intel_uncore_read_fw(uncore, offset);
186 			offset.reg += 4;
187 		}
188 	}
189 
190 	offset.reg = 0xb020;
191 	for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
192 		gen9_render_mocs.l3cc_table[i] =
193 			intel_uncore_read_fw(uncore, offset);
194 		offset.reg += 4;
195 	}
196 	gen9_render_mocs.initialized = true;
197 }
198 
199 static int
200 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu,
201 				 struct i915_request *req)
202 {
203 	u32 *cs;
204 	int ret;
205 	struct engine_mmio *mmio;
206 	struct intel_gvt *gvt = vgpu->gvt;
207 	int ring_id = req->engine->id;
208 	int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];
209 
210 	if (count == 0)
211 		return 0;
212 
213 	ret = req->engine->emit_flush(req, EMIT_BARRIER);
214 	if (ret)
215 		return ret;
216 
217 	cs = intel_ring_begin(req, count * 2 + 2);
218 	if (IS_ERR(cs))
219 		return PTR_ERR(cs);
220 
221 	*cs++ = MI_LOAD_REGISTER_IMM(count);
222 	for (mmio = gvt->engine_mmio_list.mmio;
223 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
224 		if (mmio->id != ring_id || !mmio->in_context)
225 			continue;
226 
227 		*cs++ = i915_mmio_reg_offset(mmio->reg);
228 		*cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16);
229 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
230 			      *(cs-2), *(cs-1), vgpu->id, ring_id);
231 	}
232 
233 	*cs++ = MI_NOOP;
234 	intel_ring_advance(req, cs);
235 
236 	ret = req->engine->emit_flush(req, EMIT_BARRIER);
237 	if (ret)
238 		return ret;
239 
240 	return 0;
241 }
242 
243 static int
244 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu,
245 					struct i915_request *req)
246 {
247 	unsigned int index;
248 	u32 *cs;
249 
250 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2);
251 	if (IS_ERR(cs))
252 		return PTR_ERR(cs);
253 
254 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE);
255 
256 	for (index = 0; index < GEN9_MOCS_SIZE; index++) {
257 		*cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index));
258 		*cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index));
259 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
260 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);
261 
262 	}
263 
264 	*cs++ = MI_NOOP;
265 	intel_ring_advance(req, cs);
266 
267 	return 0;
268 }
269 
270 static int
271 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu,
272 				     struct i915_request *req)
273 {
274 	unsigned int index;
275 	u32 *cs;
276 
277 	cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2);
278 	if (IS_ERR(cs))
279 		return PTR_ERR(cs);
280 
281 	*cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2);
282 
283 	for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) {
284 		*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index));
285 		*cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index));
286 		gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n",
287 			      *(cs-2), *(cs-1), vgpu->id, req->engine->id);
288 
289 	}
290 
291 	*cs++ = MI_NOOP;
292 	intel_ring_advance(req, cs);
293 
294 	return 0;
295 }
296 
297 /*
298  * Use lri command to initialize the mmio which is in context state image for
299  * inhibit context, it contains tracked engine mmio, render_mocs and
300  * render_mocs_l3cc.
301  */
302 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
303 				       struct i915_request *req)
304 {
305 	int ret;
306 	u32 *cs;
307 
308 	cs = intel_ring_begin(req, 2);
309 	if (IS_ERR(cs))
310 		return PTR_ERR(cs);
311 
312 	*cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
313 	*cs++ = MI_NOOP;
314 	intel_ring_advance(req, cs);
315 
316 	ret = restore_context_mmio_for_inhibit(vgpu, req);
317 	if (ret)
318 		goto out;
319 
320 	/* no MOCS register in context except render engine */
321 	if (req->engine->id != RCS0)
322 		goto out;
323 
324 	ret = restore_render_mocs_control_for_inhibit(vgpu, req);
325 	if (ret)
326 		goto out;
327 
328 	ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req);
329 	if (ret)
330 		goto out;
331 
332 out:
333 	cs = intel_ring_begin(req, 2);
334 	if (IS_ERR(cs))
335 		return PTR_ERR(cs);
336 
337 	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
338 	*cs++ = MI_NOOP;
339 	intel_ring_advance(req, cs);
340 
341 	return ret;
342 }
343 
344 static u32 gen8_tlb_mmio_offset_list[] = {
345 	[RCS0]  = 0x4260,
346 	[VCS0]  = 0x4264,
347 	[VCS1]  = 0x4268,
348 	[BCS0]  = 0x426c,
349 	[VECS0] = 0x4270,
350 };
351 
352 static void handle_tlb_pending_event(struct intel_vgpu *vgpu,
353 				     const struct intel_engine_cs *engine)
354 {
355 	struct intel_uncore *uncore = engine->uncore;
356 	struct intel_vgpu_submission *s = &vgpu->submission;
357 	u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;
358 	u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;
359 	enum forcewake_domains fw;
360 	i915_reg_t reg;
361 
362 	if (!regs)
363 		return;
364 
365 	if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt))
366 		return;
367 
368 	if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending))
369 		return;
370 
371 	reg = _MMIO(regs[engine->id]);
372 
373 	/* WaForceWakeRenderDuringMmioTLBInvalidate:skl
374 	 * we need to put a forcewake when invalidating RCS TLB caches,
375 	 * otherwise device can go to RC6 state and interrupt invalidation
376 	 * process
377 	 */
378 	fw = intel_uncore_forcewake_for_reg(uncore, reg,
379 					    FW_REG_READ | FW_REG_WRITE);
380 	if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) >= 9)
381 		fw |= FORCEWAKE_RENDER;
382 
383 	intel_uncore_forcewake_get(uncore, fw);
384 
385 	intel_uncore_write_fw(uncore, reg, 0x1);
386 
387 	if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50))
388 		gvt_vgpu_err("timeout in invalidate ring %s tlb\n",
389 			     engine->name);
390 	else
391 		vgpu_vreg_t(vgpu, reg) = 0;
392 
393 	intel_uncore_forcewake_put(uncore, fw);
394 
395 	gvt_dbg_core("invalidate TLB for ring %s\n", engine->name);
396 }
397 
398 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next,
399 			const struct intel_engine_cs *engine)
400 {
401 	u32 regs[] = {
402 		[RCS0]  = 0xc800,
403 		[VCS0]  = 0xc900,
404 		[VCS1]  = 0xca00,
405 		[BCS0]  = 0xcc00,
406 		[VECS0] = 0xcb00,
407 	};
408 	struct intel_uncore *uncore = engine->uncore;
409 	i915_reg_t offset, l3_offset;
410 	u32 old_v, new_v;
411 	int i;
412 
413 	if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs)))
414 		return;
415 
416 	if (engine->id == RCS0 && GRAPHICS_VER(engine->i915) == 9)
417 		return;
418 
419 	if (!pre && !gen9_render_mocs.initialized)
420 		load_render_mocs(engine);
421 
422 	offset.reg = regs[engine->id];
423 	for (i = 0; i < GEN9_MOCS_SIZE; i++) {
424 		if (pre)
425 			old_v = vgpu_vreg_t(pre, offset);
426 		else
427 			old_v = gen9_render_mocs.control_table[engine->id][i];
428 		if (next)
429 			new_v = vgpu_vreg_t(next, offset);
430 		else
431 			new_v = gen9_render_mocs.control_table[engine->id][i];
432 
433 		if (old_v != new_v)
434 			intel_uncore_write_fw(uncore, offset, new_v);
435 
436 		offset.reg += 4;
437 	}
438 
439 	if (engine->id == RCS0) {
440 		l3_offset.reg = 0xb020;
441 		for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) {
442 			if (pre)
443 				old_v = vgpu_vreg_t(pre, l3_offset);
444 			else
445 				old_v = gen9_render_mocs.l3cc_table[i];
446 			if (next)
447 				new_v = vgpu_vreg_t(next, l3_offset);
448 			else
449 				new_v = gen9_render_mocs.l3cc_table[i];
450 
451 			if (old_v != new_v)
452 				intel_uncore_write_fw(uncore, l3_offset, new_v);
453 
454 			l3_offset.reg += 4;
455 		}
456 	}
457 }
458 
459 #define CTX_CONTEXT_CONTROL_VAL	0x03
460 
461 bool is_inhibit_context(struct intel_context *ce)
462 {
463 	const u32 *reg_state = ce->lrc_reg_state;
464 	u32 inhibit_mask =
465 		_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
466 
467 	return inhibit_mask ==
468 		(reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask);
469 }
470 
471 /* Switch ring mmio values (context). */
472 static void switch_mmio(struct intel_vgpu *pre,
473 			struct intel_vgpu *next,
474 			const struct intel_engine_cs *engine)
475 {
476 	struct intel_uncore *uncore = engine->uncore;
477 	struct intel_vgpu_submission *s;
478 	struct engine_mmio *mmio;
479 	u32 old_v, new_v;
480 
481 	if (GRAPHICS_VER(engine->i915) >= 9)
482 		switch_mocs(pre, next, engine);
483 
484 	for (mmio = engine->i915->gvt->engine_mmio_list.mmio;
485 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
486 		if (mmio->id != engine->id)
487 			continue;
488 		/*
489 		 * No need to do save or restore of the mmio which is in context
490 		 * state image on gen9, it's initialized by lri command and
491 		 * save or restore with context together.
492 		 */
493 		if (GRAPHICS_VER(engine->i915) == 9 && mmio->in_context)
494 			continue;
495 
496 		// save
497 		if (pre) {
498 			vgpu_vreg_t(pre, mmio->reg) =
499 				intel_uncore_read_fw(uncore, mmio->reg);
500 			if (mmio->mask)
501 				vgpu_vreg_t(pre, mmio->reg) &=
502 					~(mmio->mask << 16);
503 			old_v = vgpu_vreg_t(pre, mmio->reg);
504 		} else {
505 			old_v = mmio->value =
506 				intel_uncore_read_fw(uncore, mmio->reg);
507 		}
508 
509 		// restore
510 		if (next) {
511 			s = &next->submission;
512 			/*
513 			 * No need to restore the mmio which is in context state
514 			 * image if it's not inhibit context, it will restore
515 			 * itself.
516 			 */
517 			if (mmio->in_context &&
518 			    !is_inhibit_context(s->shadow[engine->id]))
519 				continue;
520 
521 			if (mmio->mask)
522 				new_v = vgpu_vreg_t(next, mmio->reg) |
523 					(mmio->mask << 16);
524 			else
525 				new_v = vgpu_vreg_t(next, mmio->reg);
526 		} else {
527 			if (mmio->in_context)
528 				continue;
529 			if (mmio->mask)
530 				new_v = mmio->value | (mmio->mask << 16);
531 			else
532 				new_v = mmio->value;
533 		}
534 
535 		intel_uncore_write_fw(uncore, mmio->reg, new_v);
536 
537 		trace_render_mmio(pre ? pre->id : 0,
538 				  next ? next->id : 0,
539 				  "switch",
540 				  i915_mmio_reg_offset(mmio->reg),
541 				  old_v, new_v);
542 	}
543 
544 	if (next)
545 		handle_tlb_pending_event(next, engine);
546 }
547 
548 /**
549  * intel_gvt_switch_render_mmio - switch mmio context of specific engine
550  * @pre: the last vGPU that own the engine
551  * @next: the vGPU to switch to
552  * @engine: the engine
553  *
554  * If pre is null indicates that host own the engine. If next is null
555  * indicates that we are switching to host workload.
556  */
557 void intel_gvt_switch_mmio(struct intel_vgpu *pre,
558 			   struct intel_vgpu *next,
559 			   const struct intel_engine_cs *engine)
560 {
561 	if (WARN(!pre && !next, "switch ring %s from host to HOST\n",
562 		 engine->name))
563 		return;
564 
565 	gvt_dbg_render("switch ring %s from %s to %s\n", engine->name,
566 		       pre ? "vGPU" : "host", next ? "vGPU" : "HOST");
567 
568 	/**
569 	 * We are using raw mmio access wrapper to improve the
570 	 * performace for batch mmio read/write, so we need
571 	 * handle forcewake mannually.
572 	 */
573 	intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
574 	switch_mmio(pre, next, engine);
575 	intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
576 }
577 
578 /**
579  * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list
580  * @gvt: GVT device
581  *
582  */
583 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
584 {
585 	struct engine_mmio *mmio;
586 
587 	if (GRAPHICS_VER(gvt->gt->i915) >= 9) {
588 		gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;
589 		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
590 		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
591 		gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list;
592 		gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list);
593 	} else {
594 		gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;
595 		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;
596 		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);
597 	}
598 
599 	for (mmio = gvt->engine_mmio_list.mmio;
600 	     i915_mmio_reg_valid(mmio->reg); mmio++) {
601 		if (mmio->in_context) {
602 			gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++;
603 			intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg);
604 		}
605 	}
606 }
607