1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Zhenyu Wang <zhenyuw@linux.intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * Bing Niu <bing.niu@intel.com> 33 * 34 */ 35 36 #include "i915_drv.h" 37 #include "gvt.h" 38 #include "trace.h" 39 40 #define GEN9_MOCS_SIZE 64 41 42 /* Raw offset is appened to each line for convenience. */ 43 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 44 {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 45 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 46 {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ 47 {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ 48 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 49 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 50 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 51 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 52 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 53 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 54 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 55 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 56 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 57 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 58 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 59 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 60 {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 61 {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 62 {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 63 {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 64 {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 65 {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 66 67 {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 68 {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 69 {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 70 {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 71 {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ 72 {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */ 73 }; 74 75 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 76 {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 77 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 78 {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ 79 {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ 80 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 81 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 82 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 83 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 84 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 85 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 86 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 87 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 88 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 89 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 90 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 91 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 92 {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 93 {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 94 {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 95 {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 96 {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 97 {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 98 99 {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 100 {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 101 {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 102 {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 103 {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 104 {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ 105 {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 106 {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ 107 {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ 108 {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ 109 {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ 110 {RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */ 111 {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */ 112 {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */ 113 {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */ 114 {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */ 115 {RCS, TRVADR, 0, false}, /* 0x4df0 */ 116 {RCS, TRTTE, 0, false}, /* 0x4df4 */ 117 118 {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 119 {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 120 {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 121 {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 122 {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ 123 124 {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 125 126 {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 127 128 {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 129 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 130 {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 131 {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 132 133 {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 134 {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */ 135 136 {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 137 {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 138 {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 139 {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */ 140 }; 141 142 static struct { 143 bool initialized; 144 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 145 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 146 } gen9_render_mocs; 147 148 static void load_render_mocs(struct drm_i915_private *dev_priv) 149 { 150 i915_reg_t offset; 151 u32 regs[] = { 152 [RCS] = 0xc800, 153 [VCS] = 0xc900, 154 [VCS2] = 0xca00, 155 [BCS] = 0xcc00, 156 [VECS] = 0xcb00, 157 }; 158 int ring_id, i; 159 160 for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) { 161 offset.reg = regs[ring_id]; 162 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 163 gen9_render_mocs.control_table[ring_id][i] = 164 I915_READ_FW(offset); 165 offset.reg += 4; 166 } 167 } 168 169 offset.reg = 0xb020; 170 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 171 gen9_render_mocs.l3cc_table[i] = 172 I915_READ_FW(offset); 173 offset.reg += 4; 174 } 175 gen9_render_mocs.initialized = true; 176 } 177 178 static int 179 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 180 struct i915_request *req) 181 { 182 u32 *cs; 183 int ret; 184 struct engine_mmio *mmio; 185 struct intel_gvt *gvt = vgpu->gvt; 186 int ring_id = req->engine->id; 187 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 188 189 if (count == 0) 190 return 0; 191 192 ret = req->engine->emit_flush(req, EMIT_BARRIER); 193 if (ret) 194 return ret; 195 196 cs = intel_ring_begin(req, count * 2 + 2); 197 if (IS_ERR(cs)) 198 return PTR_ERR(cs); 199 200 *cs++ = MI_LOAD_REGISTER_IMM(count); 201 for (mmio = gvt->engine_mmio_list.mmio; 202 i915_mmio_reg_valid(mmio->reg); mmio++) { 203 if (mmio->ring_id != ring_id || 204 !mmio->in_context) 205 continue; 206 207 *cs++ = i915_mmio_reg_offset(mmio->reg); 208 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | 209 (mmio->mask << 16); 210 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 211 *(cs-2), *(cs-1), vgpu->id, ring_id); 212 } 213 214 *cs++ = MI_NOOP; 215 intel_ring_advance(req, cs); 216 217 ret = req->engine->emit_flush(req, EMIT_BARRIER); 218 if (ret) 219 return ret; 220 221 return 0; 222 } 223 224 static int 225 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 226 struct i915_request *req) 227 { 228 unsigned int index; 229 u32 *cs; 230 231 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 232 if (IS_ERR(cs)) 233 return PTR_ERR(cs); 234 235 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 236 237 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 238 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 239 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 240 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 241 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 242 243 } 244 245 *cs++ = MI_NOOP; 246 intel_ring_advance(req, cs); 247 248 return 0; 249 } 250 251 static int 252 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 253 struct i915_request *req) 254 { 255 unsigned int index; 256 u32 *cs; 257 258 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 259 if (IS_ERR(cs)) 260 return PTR_ERR(cs); 261 262 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 263 264 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 265 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 266 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 267 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 268 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 269 270 } 271 272 *cs++ = MI_NOOP; 273 intel_ring_advance(req, cs); 274 275 return 0; 276 } 277 278 /* 279 * Use lri command to initialize the mmio which is in context state image for 280 * inhibit context, it contains tracked engine mmio, render_mocs and 281 * render_mocs_l3cc. 282 */ 283 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 284 struct i915_request *req) 285 { 286 int ret; 287 u32 *cs; 288 289 cs = intel_ring_begin(req, 2); 290 if (IS_ERR(cs)) 291 return PTR_ERR(cs); 292 293 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 294 *cs++ = MI_NOOP; 295 intel_ring_advance(req, cs); 296 297 ret = restore_context_mmio_for_inhibit(vgpu, req); 298 if (ret) 299 goto out; 300 301 /* no MOCS register in context except render engine */ 302 if (req->engine->id != RCS) 303 goto out; 304 305 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 306 if (ret) 307 goto out; 308 309 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 310 if (ret) 311 goto out; 312 313 out: 314 cs = intel_ring_begin(req, 2); 315 if (IS_ERR(cs)) 316 return PTR_ERR(cs); 317 318 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 319 *cs++ = MI_NOOP; 320 intel_ring_advance(req, cs); 321 322 return ret; 323 } 324 325 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 326 { 327 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 328 struct intel_vgpu_submission *s = &vgpu->submission; 329 enum forcewake_domains fw; 330 i915_reg_t reg; 331 u32 regs[] = { 332 [RCS] = 0x4260, 333 [VCS] = 0x4264, 334 [VCS2] = 0x4268, 335 [BCS] = 0x426c, 336 [VECS] = 0x4270, 337 }; 338 339 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 340 return; 341 342 if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending)) 343 return; 344 345 reg = _MMIO(regs[ring_id]); 346 347 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 348 * we need to put a forcewake when invalidating RCS TLB caches, 349 * otherwise device can go to RC6 state and interrupt invalidation 350 * process 351 */ 352 fw = intel_uncore_forcewake_for_reg(dev_priv, reg, 353 FW_REG_READ | FW_REG_WRITE); 354 if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || 355 IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv))) 356 fw |= FORCEWAKE_RENDER; 357 358 intel_uncore_forcewake_get(dev_priv, fw); 359 360 I915_WRITE_FW(reg, 0x1); 361 362 if (wait_for_atomic((I915_READ_FW(reg) == 0), 50)) 363 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id); 364 else 365 vgpu_vreg_t(vgpu, reg) = 0; 366 367 intel_uncore_forcewake_put(dev_priv, fw); 368 369 gvt_dbg_core("invalidate TLB for ring %d\n", ring_id); 370 } 371 372 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 373 int ring_id) 374 { 375 struct drm_i915_private *dev_priv; 376 i915_reg_t offset, l3_offset; 377 u32 old_v, new_v; 378 379 u32 regs[] = { 380 [RCS] = 0xc800, 381 [VCS] = 0xc900, 382 [VCS2] = 0xca00, 383 [BCS] = 0xcc00, 384 [VECS] = 0xcb00, 385 }; 386 int i; 387 388 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 389 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 390 return; 391 392 if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && ring_id == RCS) 393 return; 394 395 if (!pre && !gen9_render_mocs.initialized) 396 load_render_mocs(dev_priv); 397 398 offset.reg = regs[ring_id]; 399 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 400 if (pre) 401 old_v = vgpu_vreg_t(pre, offset); 402 else 403 old_v = gen9_render_mocs.control_table[ring_id][i]; 404 if (next) 405 new_v = vgpu_vreg_t(next, offset); 406 else 407 new_v = gen9_render_mocs.control_table[ring_id][i]; 408 409 if (old_v != new_v) 410 I915_WRITE_FW(offset, new_v); 411 412 offset.reg += 4; 413 } 414 415 if (ring_id == RCS) { 416 l3_offset.reg = 0xb020; 417 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 418 if (pre) 419 old_v = vgpu_vreg_t(pre, l3_offset); 420 else 421 old_v = gen9_render_mocs.l3cc_table[i]; 422 if (next) 423 new_v = vgpu_vreg_t(next, l3_offset); 424 else 425 new_v = gen9_render_mocs.l3cc_table[i]; 426 427 if (old_v != new_v) 428 I915_WRITE_FW(l3_offset, new_v); 429 430 l3_offset.reg += 4; 431 } 432 } 433 } 434 435 #define CTX_CONTEXT_CONTROL_VAL 0x03 436 437 bool is_inhibit_context(struct intel_context *ce) 438 { 439 const u32 *reg_state = ce->lrc_reg_state; 440 u32 inhibit_mask = 441 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 442 443 return inhibit_mask == 444 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 445 } 446 447 /* Switch ring mmio values (context). */ 448 static void switch_mmio(struct intel_vgpu *pre, 449 struct intel_vgpu *next, 450 int ring_id) 451 { 452 struct drm_i915_private *dev_priv; 453 struct intel_vgpu_submission *s; 454 struct engine_mmio *mmio; 455 u32 old_v, new_v; 456 457 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 458 if (IS_SKYLAKE(dev_priv) 459 || IS_KABYLAKE(dev_priv) 460 || IS_BROXTON(dev_priv)) 461 switch_mocs(pre, next, ring_id); 462 463 for (mmio = dev_priv->gvt->engine_mmio_list.mmio; 464 i915_mmio_reg_valid(mmio->reg); mmio++) { 465 if (mmio->ring_id != ring_id) 466 continue; 467 /* 468 * No need to do save or restore of the mmio which is in context 469 * state image on kabylake, it's initialized by lri command and 470 * save or restore with context together. 471 */ 472 if ((IS_KABYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 473 && mmio->in_context) 474 continue; 475 476 // save 477 if (pre) { 478 vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); 479 if (mmio->mask) 480 vgpu_vreg_t(pre, mmio->reg) &= 481 ~(mmio->mask << 16); 482 old_v = vgpu_vreg_t(pre, mmio->reg); 483 } else 484 old_v = mmio->value = I915_READ_FW(mmio->reg); 485 486 // restore 487 if (next) { 488 s = &next->submission; 489 /* 490 * No need to restore the mmio which is in context state 491 * image if it's not inhibit context, it will restore 492 * itself. 493 */ 494 if (mmio->in_context && 495 !is_inhibit_context(&s->shadow_ctx->__engine[ring_id])) 496 continue; 497 498 if (mmio->mask) 499 new_v = vgpu_vreg_t(next, mmio->reg) | 500 (mmio->mask << 16); 501 else 502 new_v = vgpu_vreg_t(next, mmio->reg); 503 } else { 504 if (mmio->in_context) 505 continue; 506 if (mmio->mask) 507 new_v = mmio->value | (mmio->mask << 16); 508 else 509 new_v = mmio->value; 510 } 511 512 I915_WRITE_FW(mmio->reg, new_v); 513 514 trace_render_mmio(pre ? pre->id : 0, 515 next ? next->id : 0, 516 "switch", 517 i915_mmio_reg_offset(mmio->reg), 518 old_v, new_v); 519 } 520 521 if (next) 522 handle_tlb_pending_event(next, ring_id); 523 } 524 525 /** 526 * intel_gvt_switch_render_mmio - switch mmio context of specific engine 527 * @pre: the last vGPU that own the engine 528 * @next: the vGPU to switch to 529 * @ring_id: specify the engine 530 * 531 * If pre is null indicates that host own the engine. If next is null 532 * indicates that we are switching to host workload. 533 */ 534 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 535 struct intel_vgpu *next, int ring_id) 536 { 537 struct drm_i915_private *dev_priv; 538 539 if (WARN_ON(!pre && !next)) 540 return; 541 542 gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, 543 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 544 545 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 546 547 /** 548 * We are using raw mmio access wrapper to improve the 549 * performace for batch mmio read/write, so we need 550 * handle forcewake mannually. 551 */ 552 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 553 switch_mmio(pre, next, ring_id); 554 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 555 } 556 557 /** 558 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 559 * @gvt: GVT device 560 * 561 */ 562 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 563 { 564 struct engine_mmio *mmio; 565 566 if (IS_SKYLAKE(gvt->dev_priv) || 567 IS_KABYLAKE(gvt->dev_priv) || 568 IS_BROXTON(gvt->dev_priv)) 569 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 570 else 571 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 572 573 for (mmio = gvt->engine_mmio_list.mmio; 574 i915_mmio_reg_valid(mmio->reg); mmio++) { 575 if (mmio->in_context) { 576 gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++; 577 intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg); 578 } 579 } 580 } 581