1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Zhenyu Wang <zhenyuw@linux.intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * Bing Niu <bing.niu@intel.com> 33 * 34 */ 35 36 #include "i915_drv.h" 37 #include "gt/intel_context.h" 38 #include "gt/intel_ring.h" 39 #include "gvt.h" 40 #include "trace.h" 41 42 #define GEN9_MOCS_SIZE 64 43 44 /* Raw offset is appened to each line for convenience. */ 45 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 46 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 47 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 48 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 49 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 50 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 51 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 52 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 53 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 54 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 61 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 62 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 63 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 64 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 65 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 66 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 67 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 68 69 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 70 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 71 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 72 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 73 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 74 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 75 }; 76 77 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 78 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 79 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 80 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */ 81 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */ 82 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 83 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 84 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 85 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 86 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 87 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 88 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 89 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 90 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 91 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 92 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 93 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 94 {RCS0, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 95 {RCS0, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 96 {RCS0, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 97 {RCS0, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 98 {RCS0, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 99 {RCS0, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 100 101 {RCS0, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 102 {RCS0, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 103 {RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 104 {RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 105 {RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 106 {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ 107 {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 108 {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ 109 {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ 110 {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ 111 {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ 112 {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */ 113 {RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */ 114 {RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */ 115 {RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */ 116 {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ 117 {RCS0, TRVADR, 0, true}, /* 0x4df0 */ 118 {RCS0, TRTTE, 0, true}, /* 0x4df4 */ 119 {RCS0, _MMIO(0x4dfc), 0, true}, 120 121 {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 122 {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 123 {BCS0, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 124 {BCS0, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 125 {BCS0, RING_EXCC(BLT_RING_BASE), 0xffff, false}, /* 0x22028 */ 126 127 {VCS1, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 128 129 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 130 131 {RCS0, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 132 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 133 {RCS0, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 134 {RCS0, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 135 136 {RCS0, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 137 {RCS0, GEN9_CSFE_CHICKEN1_RCS, 0xffff, false}, /* 0x20d4 */ 138 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */ 139 140 {RCS0, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 141 {RCS0, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 142 {RCS0, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 143 {RCS0, INVALID_MMIO_REG, 0, false } /* Terminated */ 144 }; 145 146 static struct { 147 bool initialized; 148 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 149 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 150 } gen9_render_mocs; 151 152 static u32 gen9_mocs_mmio_offset_list[] = { 153 [RCS0] = 0xc800, 154 [VCS0] = 0xc900, 155 [VCS1] = 0xca00, 156 [BCS0] = 0xcc00, 157 [VECS0] = 0xcb00, 158 }; 159 160 static void load_render_mocs(const struct intel_engine_cs *engine) 161 { 162 struct intel_gvt *gvt = engine->i915->gvt; 163 struct intel_uncore *uncore = engine->uncore; 164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; 165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; 166 i915_reg_t offset; 167 int ring_id, i; 168 169 /* Platform doesn't have mocs mmios. */ 170 if (!regs) 171 return; 172 173 for (ring_id = 0; ring_id < cnt; ring_id++) { 174 if (!HAS_ENGINE(engine->i915, ring_id)) 175 continue; 176 177 offset.reg = regs[ring_id]; 178 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 179 gen9_render_mocs.control_table[ring_id][i] = 180 intel_uncore_read_fw(uncore, offset); 181 offset.reg += 4; 182 } 183 } 184 185 offset.reg = 0xb020; 186 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 187 gen9_render_mocs.l3cc_table[i] = 188 intel_uncore_read_fw(uncore, offset); 189 offset.reg += 4; 190 } 191 gen9_render_mocs.initialized = true; 192 } 193 194 static int 195 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 196 struct i915_request *req) 197 { 198 u32 *cs; 199 int ret; 200 struct engine_mmio *mmio; 201 struct intel_gvt *gvt = vgpu->gvt; 202 int ring_id = req->engine->id; 203 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 204 205 if (count == 0) 206 return 0; 207 208 ret = req->engine->emit_flush(req, EMIT_BARRIER); 209 if (ret) 210 return ret; 211 212 cs = intel_ring_begin(req, count * 2 + 2); 213 if (IS_ERR(cs)) 214 return PTR_ERR(cs); 215 216 *cs++ = MI_LOAD_REGISTER_IMM(count); 217 for (mmio = gvt->engine_mmio_list.mmio; 218 i915_mmio_reg_valid(mmio->reg); mmio++) { 219 if (mmio->id != ring_id || !mmio->in_context) 220 continue; 221 222 *cs++ = i915_mmio_reg_offset(mmio->reg); 223 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); 224 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 225 *(cs-2), *(cs-1), vgpu->id, ring_id); 226 } 227 228 *cs++ = MI_NOOP; 229 intel_ring_advance(req, cs); 230 231 ret = req->engine->emit_flush(req, EMIT_BARRIER); 232 if (ret) 233 return ret; 234 235 return 0; 236 } 237 238 static int 239 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 240 struct i915_request *req) 241 { 242 unsigned int index; 243 u32 *cs; 244 245 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 246 if (IS_ERR(cs)) 247 return PTR_ERR(cs); 248 249 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 250 251 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 252 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 253 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 254 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 255 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 256 257 } 258 259 *cs++ = MI_NOOP; 260 intel_ring_advance(req, cs); 261 262 return 0; 263 } 264 265 static int 266 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 267 struct i915_request *req) 268 { 269 unsigned int index; 270 u32 *cs; 271 272 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 273 if (IS_ERR(cs)) 274 return PTR_ERR(cs); 275 276 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 277 278 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 279 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 280 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 281 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 282 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 283 284 } 285 286 *cs++ = MI_NOOP; 287 intel_ring_advance(req, cs); 288 289 return 0; 290 } 291 292 /* 293 * Use lri command to initialize the mmio which is in context state image for 294 * inhibit context, it contains tracked engine mmio, render_mocs and 295 * render_mocs_l3cc. 296 */ 297 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 298 struct i915_request *req) 299 { 300 int ret; 301 u32 *cs; 302 303 cs = intel_ring_begin(req, 2); 304 if (IS_ERR(cs)) 305 return PTR_ERR(cs); 306 307 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 308 *cs++ = MI_NOOP; 309 intel_ring_advance(req, cs); 310 311 ret = restore_context_mmio_for_inhibit(vgpu, req); 312 if (ret) 313 goto out; 314 315 /* no MOCS register in context except render engine */ 316 if (req->engine->id != RCS0) 317 goto out; 318 319 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 320 if (ret) 321 goto out; 322 323 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 324 if (ret) 325 goto out; 326 327 out: 328 cs = intel_ring_begin(req, 2); 329 if (IS_ERR(cs)) 330 return PTR_ERR(cs); 331 332 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 333 *cs++ = MI_NOOP; 334 intel_ring_advance(req, cs); 335 336 return ret; 337 } 338 339 static u32 gen8_tlb_mmio_offset_list[] = { 340 [RCS0] = 0x4260, 341 [VCS0] = 0x4264, 342 [VCS1] = 0x4268, 343 [BCS0] = 0x426c, 344 [VECS0] = 0x4270, 345 }; 346 347 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, 348 const struct intel_engine_cs *engine) 349 { 350 struct intel_uncore *uncore = engine->uncore; 351 struct intel_vgpu_submission *s = &vgpu->submission; 352 u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list; 353 u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt; 354 enum forcewake_domains fw; 355 i915_reg_t reg; 356 357 if (!regs) 358 return; 359 360 if (drm_WARN_ON(&engine->i915->drm, engine->id >= cnt)) 361 return; 362 363 if (!test_and_clear_bit(engine->id, (void *)s->tlb_handle_pending)) 364 return; 365 366 reg = _MMIO(regs[engine->id]); 367 368 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 369 * we need to put a forcewake when invalidating RCS TLB caches, 370 * otherwise device can go to RC6 state and interrupt invalidation 371 * process 372 */ 373 fw = intel_uncore_forcewake_for_reg(uncore, reg, 374 FW_REG_READ | FW_REG_WRITE); 375 if (engine->id == RCS0 && INTEL_GEN(engine->i915) >= 9) 376 fw |= FORCEWAKE_RENDER; 377 378 intel_uncore_forcewake_get(uncore, fw); 379 380 intel_uncore_write_fw(uncore, reg, 0x1); 381 382 if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50)) 383 gvt_vgpu_err("timeout in invalidate ring %s tlb\n", 384 engine->name); 385 else 386 vgpu_vreg_t(vgpu, reg) = 0; 387 388 intel_uncore_forcewake_put(uncore, fw); 389 390 gvt_dbg_core("invalidate TLB for ring %s\n", engine->name); 391 } 392 393 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 394 const struct intel_engine_cs *engine) 395 { 396 u32 regs[] = { 397 [RCS0] = 0xc800, 398 [VCS0] = 0xc900, 399 [VCS1] = 0xca00, 400 [BCS0] = 0xcc00, 401 [VECS0] = 0xcb00, 402 }; 403 struct intel_uncore *uncore = engine->uncore; 404 i915_reg_t offset, l3_offset; 405 u32 old_v, new_v; 406 int i; 407 408 if (drm_WARN_ON(&engine->i915->drm, engine->id >= ARRAY_SIZE(regs))) 409 return; 410 411 if (engine->id == RCS0 && IS_GEN(engine->i915, 9)) 412 return; 413 414 if (!pre && !gen9_render_mocs.initialized) 415 load_render_mocs(engine); 416 417 offset.reg = regs[engine->id]; 418 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 419 if (pre) 420 old_v = vgpu_vreg_t(pre, offset); 421 else 422 old_v = gen9_render_mocs.control_table[engine->id][i]; 423 if (next) 424 new_v = vgpu_vreg_t(next, offset); 425 else 426 new_v = gen9_render_mocs.control_table[engine->id][i]; 427 428 if (old_v != new_v) 429 intel_uncore_write_fw(uncore, offset, new_v); 430 431 offset.reg += 4; 432 } 433 434 if (engine->id == RCS0) { 435 l3_offset.reg = 0xb020; 436 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 437 if (pre) 438 old_v = vgpu_vreg_t(pre, l3_offset); 439 else 440 old_v = gen9_render_mocs.l3cc_table[i]; 441 if (next) 442 new_v = vgpu_vreg_t(next, l3_offset); 443 else 444 new_v = gen9_render_mocs.l3cc_table[i]; 445 446 if (old_v != new_v) 447 intel_uncore_write_fw(uncore, l3_offset, new_v); 448 449 l3_offset.reg += 4; 450 } 451 } 452 } 453 454 #define CTX_CONTEXT_CONTROL_VAL 0x03 455 456 bool is_inhibit_context(struct intel_context *ce) 457 { 458 const u32 *reg_state = ce->lrc_reg_state; 459 u32 inhibit_mask = 460 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 461 462 return inhibit_mask == 463 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 464 } 465 466 /* Switch ring mmio values (context). */ 467 static void switch_mmio(struct intel_vgpu *pre, 468 struct intel_vgpu *next, 469 const struct intel_engine_cs *engine) 470 { 471 struct intel_uncore *uncore = engine->uncore; 472 struct intel_vgpu_submission *s; 473 struct engine_mmio *mmio; 474 u32 old_v, new_v; 475 476 if (INTEL_GEN(engine->i915) >= 9) 477 switch_mocs(pre, next, engine); 478 479 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; 480 i915_mmio_reg_valid(mmio->reg); mmio++) { 481 if (mmio->id != engine->id) 482 continue; 483 /* 484 * No need to do save or restore of the mmio which is in context 485 * state image on gen9, it's initialized by lri command and 486 * save or restore with context together. 487 */ 488 if (IS_GEN(engine->i915, 9) && mmio->in_context) 489 continue; 490 491 // save 492 if (pre) { 493 vgpu_vreg_t(pre, mmio->reg) = 494 intel_uncore_read_fw(uncore, mmio->reg); 495 if (mmio->mask) 496 vgpu_vreg_t(pre, mmio->reg) &= 497 ~(mmio->mask << 16); 498 old_v = vgpu_vreg_t(pre, mmio->reg); 499 } else { 500 old_v = mmio->value = 501 intel_uncore_read_fw(uncore, mmio->reg); 502 } 503 504 // restore 505 if (next) { 506 s = &next->submission; 507 /* 508 * No need to restore the mmio which is in context state 509 * image if it's not inhibit context, it will restore 510 * itself. 511 */ 512 if (mmio->in_context && 513 !is_inhibit_context(s->shadow[engine->id])) 514 continue; 515 516 if (mmio->mask) 517 new_v = vgpu_vreg_t(next, mmio->reg) | 518 (mmio->mask << 16); 519 else 520 new_v = vgpu_vreg_t(next, mmio->reg); 521 } else { 522 if (mmio->in_context) 523 continue; 524 if (mmio->mask) 525 new_v = mmio->value | (mmio->mask << 16); 526 else 527 new_v = mmio->value; 528 } 529 530 intel_uncore_write_fw(uncore, mmio->reg, new_v); 531 532 trace_render_mmio(pre ? pre->id : 0, 533 next ? next->id : 0, 534 "switch", 535 i915_mmio_reg_offset(mmio->reg), 536 old_v, new_v); 537 } 538 539 if (next) 540 handle_tlb_pending_event(next, engine); 541 } 542 543 /** 544 * intel_gvt_switch_render_mmio - switch mmio context of specific engine 545 * @pre: the last vGPU that own the engine 546 * @next: the vGPU to switch to 547 * @engine: the engine 548 * 549 * If pre is null indicates that host own the engine. If next is null 550 * indicates that we are switching to host workload. 551 */ 552 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 553 struct intel_vgpu *next, 554 const struct intel_engine_cs *engine) 555 { 556 if (WARN(!pre && !next, "switch ring %s from host to HOST\n", 557 engine->name)) 558 return; 559 560 gvt_dbg_render("switch ring %s from %s to %s\n", engine->name, 561 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 562 563 /** 564 * We are using raw mmio access wrapper to improve the 565 * performace for batch mmio read/write, so we need 566 * handle forcewake mannually. 567 */ 568 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); 569 switch_mmio(pre, next, engine); 570 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); 571 } 572 573 /** 574 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 575 * @gvt: GVT device 576 * 577 */ 578 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 579 { 580 struct engine_mmio *mmio; 581 582 if (INTEL_GEN(gvt->gt->i915) >= 9) { 583 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 584 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 585 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 586 gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list; 587 gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list); 588 } else { 589 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 590 gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list; 591 gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list); 592 } 593 594 for (mmio = gvt->engine_mmio_list.mmio; 595 i915_mmio_reg_valid(mmio->reg); mmio++) { 596 if (mmio->in_context) { 597 gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++; 598 intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg); 599 } 600 } 601 } 602