1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eddie Dong <eddie.dong@intel.com> 25 * Kevin Tian <kevin.tian@intel.com> 26 * 27 * Contributors: 28 * Zhi Wang <zhi.a.wang@intel.com> 29 * Changbin Du <changbin.du@intel.com> 30 * Zhenyu Wang <zhenyuw@linux.intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * Bing Niu <bing.niu@intel.com> 33 * 34 */ 35 36 #include "i915_drv.h" 37 #include "gvt.h" 38 #include "trace.h" 39 40 /** 41 * Defined in Intel Open Source PRM. 42 * Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms 43 */ 44 #define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4) 45 #define TRNULLDETCT _MMIO(0x4de8) 46 #define TRINVTILEDETCT _MMIO(0x4dec) 47 #define TRVADR _MMIO(0x4df0) 48 #define TRTTE _MMIO(0x4df4) 49 #define RING_EXCC(base) _MMIO((base) + 0x28) 50 #define RING_GFX_MODE(base) _MMIO((base) + 0x29c) 51 #define VF_GUARDBAND _MMIO(0x83a4) 52 53 #define GEN9_MOCS_SIZE 64 54 55 /* Raw offset is appened to each line for convenience. */ 56 static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { 57 {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 58 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 59 {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ 60 {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ 61 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 62 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 63 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 64 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 65 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 66 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 67 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 68 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 69 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 70 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 71 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 72 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 73 {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 74 {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 75 {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 76 {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 77 {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 78 {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 79 80 {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 81 {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 82 {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 83 {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 84 {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ 85 {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */ 86 }; 87 88 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 89 {RCS, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */ 90 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 91 {RCS, HWSTAM, 0x0, false}, /* 0x2098 */ 92 {RCS, INSTPM, 0xffff, true}, /* 0x20c0 */ 93 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */ 94 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */ 95 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */ 96 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */ 97 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */ 98 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 */ 99 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 6), 0, false}, /* 0x24e8 */ 100 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 7), 0, false}, /* 0x24ec */ 101 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 8), 0, false}, /* 0x24f0 */ 102 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 9), 0, false}, /* 0x24f4 */ 103 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 10), 0, false}, /* 0x24f8 */ 104 {RCS, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 11), 0, false}, /* 0x24fc */ 105 {RCS, CACHE_MODE_1, 0xffff, true}, /* 0x7004 */ 106 {RCS, GEN7_GT_MODE, 0xffff, true}, /* 0x7008 */ 107 {RCS, CACHE_MODE_0_GEN7, 0xffff, true}, /* 0x7000 */ 108 {RCS, GEN7_COMMON_SLICE_CHICKEN1, 0xffff, true}, /* 0x7010 */ 109 {RCS, HDC_CHICKEN0, 0xffff, true}, /* 0x7300 */ 110 {RCS, VF_GUARDBAND, 0xffff, true}, /* 0x83a4 */ 111 112 {RCS, GEN8_PRIVATE_PAT_LO, 0, false}, /* 0x40e0 */ 113 {RCS, GEN8_PRIVATE_PAT_HI, 0, false}, /* 0x40e4 */ 114 {RCS, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */ 115 {RCS, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */ 116 {RCS, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */ 117 {RCS, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */ 118 {RCS, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */ 119 {RCS, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */ 120 {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */ 121 {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */ 122 {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */ 123 {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */ 124 {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */ 125 {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */ 126 {RCS, TRINVTILEDETCT, 0, false}, /* 0x4dec */ 127 {RCS, TRVADR, 0, false}, /* 0x4df0 */ 128 {RCS, TRTTE, 0, false}, /* 0x4df4 */ 129 130 {BCS, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ 131 {BCS, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ 132 {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */ 133 {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */ 134 {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */ 135 136 {VCS2, RING_EXCC(GEN8_BSD2_RING_BASE), 0xffff, false}, /* 0x1c028 */ 137 138 {VECS, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */ 139 140 {RCS, GEN8_HDC_CHICKEN1, 0xffff, true}, /* 0x7304 */ 141 {RCS, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */ 142 {RCS, GEN7_UCGCTL4, 0x0, false}, /* 0x940c */ 143 {RCS, GAMT_CHKN_BIT_REG, 0x0, false}, /* 0x4ab8 */ 144 145 {RCS, GEN9_GAMT_ECO_REG_RW_IA, 0x0, false}, /* 0x4ab0 */ 146 {RCS, GEN9_CSFE_CHICKEN1_RCS, 0x0, false}, /* 0x20d4 */ 147 148 {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */ 149 {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */ 150 {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */ 151 {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */ 152 }; 153 154 static struct { 155 bool initialized; 156 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE]; 157 u32 l3cc_table[GEN9_MOCS_SIZE / 2]; 158 } gen9_render_mocs; 159 160 static void load_render_mocs(struct drm_i915_private *dev_priv) 161 { 162 i915_reg_t offset; 163 u32 regs[] = { 164 [RCS] = 0xc800, 165 [VCS] = 0xc900, 166 [VCS2] = 0xca00, 167 [BCS] = 0xcc00, 168 [VECS] = 0xcb00, 169 }; 170 int ring_id, i; 171 172 for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) { 173 offset.reg = regs[ring_id]; 174 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 175 gen9_render_mocs.control_table[ring_id][i] = 176 I915_READ_FW(offset); 177 offset.reg += 4; 178 } 179 } 180 181 offset.reg = 0xb020; 182 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 183 gen9_render_mocs.l3cc_table[i] = 184 I915_READ_FW(offset); 185 offset.reg += 4; 186 } 187 gen9_render_mocs.initialized = true; 188 } 189 190 static int 191 restore_context_mmio_for_inhibit(struct intel_vgpu *vgpu, 192 struct i915_request *req) 193 { 194 u32 *cs; 195 int ret; 196 struct engine_mmio *mmio; 197 struct intel_gvt *gvt = vgpu->gvt; 198 int ring_id = req->engine->id; 199 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; 200 201 if (count == 0) 202 return 0; 203 204 ret = req->engine->emit_flush(req, EMIT_BARRIER); 205 if (ret) 206 return ret; 207 208 cs = intel_ring_begin(req, count * 2 + 2); 209 if (IS_ERR(cs)) 210 return PTR_ERR(cs); 211 212 *cs++ = MI_LOAD_REGISTER_IMM(count); 213 for (mmio = gvt->engine_mmio_list.mmio; 214 i915_mmio_reg_valid(mmio->reg); mmio++) { 215 if (mmio->ring_id != ring_id || 216 !mmio->in_context) 217 continue; 218 219 *cs++ = i915_mmio_reg_offset(mmio->reg); 220 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | 221 (mmio->mask << 16); 222 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 223 *(cs-2), *(cs-1), vgpu->id, ring_id); 224 } 225 226 *cs++ = MI_NOOP; 227 intel_ring_advance(req, cs); 228 229 ret = req->engine->emit_flush(req, EMIT_BARRIER); 230 if (ret) 231 return ret; 232 233 return 0; 234 } 235 236 static int 237 restore_render_mocs_control_for_inhibit(struct intel_vgpu *vgpu, 238 struct i915_request *req) 239 { 240 unsigned int index; 241 u32 *cs; 242 243 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE + 2); 244 if (IS_ERR(cs)) 245 return PTR_ERR(cs); 246 247 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); 248 249 for (index = 0; index < GEN9_MOCS_SIZE; index++) { 250 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); 251 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); 252 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 253 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 254 255 } 256 257 *cs++ = MI_NOOP; 258 intel_ring_advance(req, cs); 259 260 return 0; 261 } 262 263 static int 264 restore_render_mocs_l3cc_for_inhibit(struct intel_vgpu *vgpu, 265 struct i915_request *req) 266 { 267 unsigned int index; 268 u32 *cs; 269 270 cs = intel_ring_begin(req, 2 * GEN9_MOCS_SIZE / 2 + 2); 271 if (IS_ERR(cs)) 272 return PTR_ERR(cs); 273 274 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); 275 276 for (index = 0; index < GEN9_MOCS_SIZE / 2; index++) { 277 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); 278 *cs++ = vgpu_vreg_t(vgpu, GEN9_LNCFCMOCS(index)); 279 gvt_dbg_core("add lri reg pair 0x%x:0x%x in inhibit ctx, vgpu:%d, rind_id:%d\n", 280 *(cs-2), *(cs-1), vgpu->id, req->engine->id); 281 282 } 283 284 *cs++ = MI_NOOP; 285 intel_ring_advance(req, cs); 286 287 return 0; 288 } 289 290 /* 291 * Use lri command to initialize the mmio which is in context state image for 292 * inhibit context, it contains tracked engine mmio, render_mocs and 293 * render_mocs_l3cc. 294 */ 295 int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu, 296 struct i915_request *req) 297 { 298 int ret; 299 u32 *cs; 300 301 cs = intel_ring_begin(req, 2); 302 if (IS_ERR(cs)) 303 return PTR_ERR(cs); 304 305 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; 306 *cs++ = MI_NOOP; 307 intel_ring_advance(req, cs); 308 309 ret = restore_context_mmio_for_inhibit(vgpu, req); 310 if (ret) 311 goto out; 312 313 /* no MOCS register in context except render engine */ 314 if (req->engine->id != RCS) 315 goto out; 316 317 ret = restore_render_mocs_control_for_inhibit(vgpu, req); 318 if (ret) 319 goto out; 320 321 ret = restore_render_mocs_l3cc_for_inhibit(vgpu, req); 322 if (ret) 323 goto out; 324 325 out: 326 cs = intel_ring_begin(req, 2); 327 if (IS_ERR(cs)) 328 return PTR_ERR(cs); 329 330 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; 331 *cs++ = MI_NOOP; 332 intel_ring_advance(req, cs); 333 334 return ret; 335 } 336 337 static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 338 { 339 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 340 struct intel_vgpu_submission *s = &vgpu->submission; 341 enum forcewake_domains fw; 342 i915_reg_t reg; 343 u32 regs[] = { 344 [RCS] = 0x4260, 345 [VCS] = 0x4264, 346 [VCS2] = 0x4268, 347 [BCS] = 0x426c, 348 [VECS] = 0x4270, 349 }; 350 351 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 352 return; 353 354 if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending)) 355 return; 356 357 reg = _MMIO(regs[ring_id]); 358 359 /* WaForceWakeRenderDuringMmioTLBInvalidate:skl 360 * we need to put a forcewake when invalidating RCS TLB caches, 361 * otherwise device can go to RC6 state and interrupt invalidation 362 * process 363 */ 364 fw = intel_uncore_forcewake_for_reg(dev_priv, reg, 365 FW_REG_READ | FW_REG_WRITE); 366 if (ring_id == RCS && (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) 367 fw |= FORCEWAKE_RENDER; 368 369 intel_uncore_forcewake_get(dev_priv, fw); 370 371 I915_WRITE_FW(reg, 0x1); 372 373 if (wait_for_atomic((I915_READ_FW(reg) == 0), 50)) 374 gvt_vgpu_err("timeout in invalidate ring (%d) tlb\n", ring_id); 375 else 376 vgpu_vreg_t(vgpu, reg) = 0; 377 378 intel_uncore_forcewake_put(dev_priv, fw); 379 380 gvt_dbg_core("invalidate TLB for ring %d\n", ring_id); 381 } 382 383 static void switch_mocs(struct intel_vgpu *pre, struct intel_vgpu *next, 384 int ring_id) 385 { 386 struct drm_i915_private *dev_priv; 387 i915_reg_t offset, l3_offset; 388 u32 old_v, new_v; 389 390 u32 regs[] = { 391 [RCS] = 0xc800, 392 [VCS] = 0xc900, 393 [VCS2] = 0xca00, 394 [BCS] = 0xcc00, 395 [VECS] = 0xcb00, 396 }; 397 int i; 398 399 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 400 if (WARN_ON(ring_id >= ARRAY_SIZE(regs))) 401 return; 402 403 if (IS_KABYLAKE(dev_priv) && ring_id == RCS) 404 return; 405 406 if (!pre && !gen9_render_mocs.initialized) 407 load_render_mocs(dev_priv); 408 409 offset.reg = regs[ring_id]; 410 for (i = 0; i < GEN9_MOCS_SIZE; i++) { 411 if (pre) 412 old_v = vgpu_vreg_t(pre, offset); 413 else 414 old_v = gen9_render_mocs.control_table[ring_id][i]; 415 if (next) 416 new_v = vgpu_vreg_t(next, offset); 417 else 418 new_v = gen9_render_mocs.control_table[ring_id][i]; 419 420 if (old_v != new_v) 421 I915_WRITE_FW(offset, new_v); 422 423 offset.reg += 4; 424 } 425 426 if (ring_id == RCS) { 427 l3_offset.reg = 0xb020; 428 for (i = 0; i < GEN9_MOCS_SIZE / 2; i++) { 429 if (pre) 430 old_v = vgpu_vreg_t(pre, l3_offset); 431 else 432 old_v = gen9_render_mocs.l3cc_table[i]; 433 if (next) 434 new_v = vgpu_vreg_t(next, l3_offset); 435 else 436 new_v = gen9_render_mocs.l3cc_table[i]; 437 438 if (old_v != new_v) 439 I915_WRITE_FW(l3_offset, new_v); 440 441 l3_offset.reg += 4; 442 } 443 } 444 } 445 446 #define CTX_CONTEXT_CONTROL_VAL 0x03 447 448 bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id) 449 { 450 u32 *reg_state = ctx->engine[ring_id].lrc_reg_state; 451 u32 inhibit_mask = 452 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 453 454 return inhibit_mask == 455 (reg_state[CTX_CONTEXT_CONTROL_VAL] & inhibit_mask); 456 } 457 458 /* Switch ring mmio values (context). */ 459 static void switch_mmio(struct intel_vgpu *pre, 460 struct intel_vgpu *next, 461 int ring_id) 462 { 463 struct drm_i915_private *dev_priv; 464 struct intel_vgpu_submission *s; 465 struct engine_mmio *mmio; 466 u32 old_v, new_v; 467 468 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 469 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 470 switch_mocs(pre, next, ring_id); 471 472 for (mmio = dev_priv->gvt->engine_mmio_list.mmio; 473 i915_mmio_reg_valid(mmio->reg); mmio++) { 474 if (mmio->ring_id != ring_id) 475 continue; 476 /* 477 * No need to do save or restore of the mmio which is in context 478 * state image on kabylake, it's initialized by lri command and 479 * save or restore with context together. 480 */ 481 if (IS_KABYLAKE(dev_priv) && mmio->in_context) 482 continue; 483 484 // save 485 if (pre) { 486 vgpu_vreg_t(pre, mmio->reg) = I915_READ_FW(mmio->reg); 487 if (mmio->mask) 488 vgpu_vreg_t(pre, mmio->reg) &= 489 ~(mmio->mask << 16); 490 old_v = vgpu_vreg_t(pre, mmio->reg); 491 } else 492 old_v = mmio->value = I915_READ_FW(mmio->reg); 493 494 // restore 495 if (next) { 496 s = &next->submission; 497 /* 498 * No need to restore the mmio which is in context state 499 * image if it's not inhibit context, it will restore 500 * itself. 501 */ 502 if (mmio->in_context && 503 !is_inhibit_context(s->shadow_ctx, ring_id)) 504 continue; 505 506 if (mmio->mask) 507 new_v = vgpu_vreg_t(next, mmio->reg) | 508 (mmio->mask << 16); 509 else 510 new_v = vgpu_vreg_t(next, mmio->reg); 511 } else { 512 if (mmio->in_context) 513 continue; 514 if (mmio->mask) 515 new_v = mmio->value | (mmio->mask << 16); 516 else 517 new_v = mmio->value; 518 } 519 520 I915_WRITE_FW(mmio->reg, new_v); 521 522 trace_render_mmio(pre ? pre->id : 0, 523 next ? next->id : 0, 524 "switch", 525 i915_mmio_reg_offset(mmio->reg), 526 old_v, new_v); 527 } 528 529 if (next) 530 handle_tlb_pending_event(next, ring_id); 531 } 532 533 /** 534 * intel_gvt_switch_render_mmio - switch mmio context of specific engine 535 * @pre: the last vGPU that own the engine 536 * @next: the vGPU to switch to 537 * @ring_id: specify the engine 538 * 539 * If pre is null indicates that host own the engine. If next is null 540 * indicates that we are switching to host workload. 541 */ 542 void intel_gvt_switch_mmio(struct intel_vgpu *pre, 543 struct intel_vgpu *next, int ring_id) 544 { 545 struct drm_i915_private *dev_priv; 546 547 if (WARN_ON(!pre && !next)) 548 return; 549 550 gvt_dbg_render("switch ring %d from %s to %s\n", ring_id, 551 pre ? "vGPU" : "host", next ? "vGPU" : "HOST"); 552 553 dev_priv = pre ? pre->gvt->dev_priv : next->gvt->dev_priv; 554 555 /** 556 * We are using raw mmio access wrapper to improve the 557 * performace for batch mmio read/write, so we need 558 * handle forcewake mannually. 559 */ 560 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 561 switch_mmio(pre, next, ring_id); 562 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 563 } 564 565 /** 566 * intel_gvt_init_engine_mmio_context - Initiate the engine mmio list 567 * @gvt: GVT device 568 * 569 */ 570 void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt) 571 { 572 struct engine_mmio *mmio; 573 574 if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) 575 gvt->engine_mmio_list.mmio = gen9_engine_mmio_list; 576 else 577 gvt->engine_mmio_list.mmio = gen8_engine_mmio_list; 578 579 for (mmio = gvt->engine_mmio_list.mmio; 580 i915_mmio_reg_valid(mmio->reg); mmio++) { 581 if (mmio->in_context) 582 gvt->engine_mmio_list.ctx_mmio_count[mmio->ring_id]++; 583 } 584 } 585