1 /* 2 * KVMGT - the implementation of Intel mediated pass-through framework for KVM 3 * 4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Kevin Tian <kevin.tian@intel.com> 27 * Jike Song <jike.song@intel.com> 28 * Xiaoguang Chen <xiaoguang.chen@intel.com> 29 * Eddie Dong <eddie.dong@intel.com> 30 * 31 * Contributors: 32 * Niu Bing <bing.niu@intel.com> 33 * Zhi Wang <zhi.a.wang@intel.com> 34 */ 35 36 #include <linux/init.h> 37 #include <linux/mm.h> 38 #include <linux/kthread.h> 39 #include <linux/sched/mm.h> 40 #include <linux/types.h> 41 #include <linux/list.h> 42 #include <linux/rbtree.h> 43 #include <linux/spinlock.h> 44 #include <linux/eventfd.h> 45 #include <linux/mdev.h> 46 #include <linux/debugfs.h> 47 48 #include <linux/nospec.h> 49 50 #include <drm/drm_edid.h> 51 52 #include "i915_drv.h" 53 #include "intel_gvt.h" 54 #include "gvt.h" 55 56 MODULE_IMPORT_NS(DMA_BUF); 57 MODULE_IMPORT_NS(I915_GVT); 58 59 /* helper macros copied from vfio-pci */ 60 #define VFIO_PCI_OFFSET_SHIFT 40 61 #define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT) 62 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT) 63 #define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1) 64 65 #define EDID_BLOB_OFFSET (PAGE_SIZE/2) 66 67 #define OPREGION_SIGNATURE "IntelGraphicsMem" 68 69 struct vfio_region; 70 struct intel_vgpu_regops { 71 size_t (*rw)(struct intel_vgpu *vgpu, char *buf, 72 size_t count, loff_t *ppos, bool iswrite); 73 void (*release)(struct intel_vgpu *vgpu, 74 struct vfio_region *region); 75 }; 76 77 struct vfio_region { 78 u32 type; 79 u32 subtype; 80 size_t size; 81 u32 flags; 82 const struct intel_vgpu_regops *ops; 83 void *data; 84 }; 85 86 struct vfio_edid_region { 87 struct vfio_region_gfx_edid vfio_edid_regs; 88 void *edid_blob; 89 }; 90 91 struct kvmgt_pgfn { 92 gfn_t gfn; 93 struct hlist_node hnode; 94 }; 95 96 struct gvt_dma { 97 struct intel_vgpu *vgpu; 98 struct rb_node gfn_node; 99 struct rb_node dma_addr_node; 100 gfn_t gfn; 101 dma_addr_t dma_addr; 102 unsigned long size; 103 struct kref ref; 104 }; 105 106 #define vfio_dev_to_vgpu(vfio_dev) \ 107 container_of((vfio_dev), struct intel_vgpu, vfio_device) 108 109 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 110 const u8 *val, int len, 111 struct kvm_page_track_notifier_node *node); 112 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 113 struct kvm_memory_slot *slot, 114 struct kvm_page_track_notifier_node *node); 115 116 static ssize_t intel_vgpu_show_description(struct mdev_type *mtype, char *buf) 117 { 118 struct intel_vgpu_type *type = 119 container_of(mtype, struct intel_vgpu_type, type); 120 121 return sprintf(buf, "low_gm_size: %dMB\nhigh_gm_size: %dMB\n" 122 "fence: %d\nresolution: %s\n" 123 "weight: %d\n", 124 BYTES_TO_MB(type->conf->low_mm), 125 BYTES_TO_MB(type->conf->high_mm), 126 type->conf->fence, vgpu_edid_str(type->conf->edid), 127 type->conf->weight); 128 } 129 130 static void gvt_unpin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 131 unsigned long size) 132 { 133 vfio_unpin_pages(&vgpu->vfio_device, gfn << PAGE_SHIFT, 134 DIV_ROUND_UP(size, PAGE_SIZE)); 135 } 136 137 /* Pin a normal or compound guest page for dma. */ 138 static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 139 unsigned long size, struct page **page) 140 { 141 int total_pages = DIV_ROUND_UP(size, PAGE_SIZE); 142 struct page *base_page = NULL; 143 int npage; 144 int ret; 145 146 /* 147 * We pin the pages one-by-one to avoid allocating a big arrary 148 * on stack to hold pfns. 149 */ 150 for (npage = 0; npage < total_pages; npage++) { 151 dma_addr_t cur_iova = (gfn + npage) << PAGE_SHIFT; 152 struct page *cur_page; 153 154 ret = vfio_pin_pages(&vgpu->vfio_device, cur_iova, 1, 155 IOMMU_READ | IOMMU_WRITE, &cur_page); 156 if (ret != 1) { 157 gvt_vgpu_err("vfio_pin_pages failed for iova %pad, ret %d\n", 158 &cur_iova, ret); 159 goto err; 160 } 161 162 if (npage == 0) 163 base_page = cur_page; 164 else if (base_page + npage != cur_page) { 165 gvt_vgpu_err("The pages are not continuous\n"); 166 ret = -EINVAL; 167 npage++; 168 goto err; 169 } 170 } 171 172 *page = base_page; 173 return 0; 174 err: 175 gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); 176 return ret; 177 } 178 179 static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 180 dma_addr_t *dma_addr, unsigned long size) 181 { 182 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 183 struct page *page = NULL; 184 int ret; 185 186 ret = gvt_pin_guest_page(vgpu, gfn, size, &page); 187 if (ret) 188 return ret; 189 190 /* Setup DMA mapping. */ 191 *dma_addr = dma_map_page(dev, page, 0, size, DMA_BIDIRECTIONAL); 192 if (dma_mapping_error(dev, *dma_addr)) { 193 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n", 194 page_to_pfn(page), ret); 195 gvt_unpin_guest_page(vgpu, gfn, size); 196 return -ENOMEM; 197 } 198 199 return 0; 200 } 201 202 static void gvt_dma_unmap_page(struct intel_vgpu *vgpu, unsigned long gfn, 203 dma_addr_t dma_addr, unsigned long size) 204 { 205 struct device *dev = vgpu->gvt->gt->i915->drm.dev; 206 207 dma_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL); 208 gvt_unpin_guest_page(vgpu, gfn, size); 209 } 210 211 static struct gvt_dma *__gvt_cache_find_dma_addr(struct intel_vgpu *vgpu, 212 dma_addr_t dma_addr) 213 { 214 struct rb_node *node = vgpu->dma_addr_cache.rb_node; 215 struct gvt_dma *itr; 216 217 while (node) { 218 itr = rb_entry(node, struct gvt_dma, dma_addr_node); 219 220 if (dma_addr < itr->dma_addr) 221 node = node->rb_left; 222 else if (dma_addr > itr->dma_addr) 223 node = node->rb_right; 224 else 225 return itr; 226 } 227 return NULL; 228 } 229 230 static struct gvt_dma *__gvt_cache_find_gfn(struct intel_vgpu *vgpu, gfn_t gfn) 231 { 232 struct rb_node *node = vgpu->gfn_cache.rb_node; 233 struct gvt_dma *itr; 234 235 while (node) { 236 itr = rb_entry(node, struct gvt_dma, gfn_node); 237 238 if (gfn < itr->gfn) 239 node = node->rb_left; 240 else if (gfn > itr->gfn) 241 node = node->rb_right; 242 else 243 return itr; 244 } 245 return NULL; 246 } 247 248 static int __gvt_cache_add(struct intel_vgpu *vgpu, gfn_t gfn, 249 dma_addr_t dma_addr, unsigned long size) 250 { 251 struct gvt_dma *new, *itr; 252 struct rb_node **link, *parent = NULL; 253 254 new = kzalloc(sizeof(struct gvt_dma), GFP_KERNEL); 255 if (!new) 256 return -ENOMEM; 257 258 new->vgpu = vgpu; 259 new->gfn = gfn; 260 new->dma_addr = dma_addr; 261 new->size = size; 262 kref_init(&new->ref); 263 264 /* gfn_cache maps gfn to struct gvt_dma. */ 265 link = &vgpu->gfn_cache.rb_node; 266 while (*link) { 267 parent = *link; 268 itr = rb_entry(parent, struct gvt_dma, gfn_node); 269 270 if (gfn < itr->gfn) 271 link = &parent->rb_left; 272 else 273 link = &parent->rb_right; 274 } 275 rb_link_node(&new->gfn_node, parent, link); 276 rb_insert_color(&new->gfn_node, &vgpu->gfn_cache); 277 278 /* dma_addr_cache maps dma addr to struct gvt_dma. */ 279 parent = NULL; 280 link = &vgpu->dma_addr_cache.rb_node; 281 while (*link) { 282 parent = *link; 283 itr = rb_entry(parent, struct gvt_dma, dma_addr_node); 284 285 if (dma_addr < itr->dma_addr) 286 link = &parent->rb_left; 287 else 288 link = &parent->rb_right; 289 } 290 rb_link_node(&new->dma_addr_node, parent, link); 291 rb_insert_color(&new->dma_addr_node, &vgpu->dma_addr_cache); 292 293 vgpu->nr_cache_entries++; 294 return 0; 295 } 296 297 static void __gvt_cache_remove_entry(struct intel_vgpu *vgpu, 298 struct gvt_dma *entry) 299 { 300 rb_erase(&entry->gfn_node, &vgpu->gfn_cache); 301 rb_erase(&entry->dma_addr_node, &vgpu->dma_addr_cache); 302 kfree(entry); 303 vgpu->nr_cache_entries--; 304 } 305 306 static void gvt_cache_destroy(struct intel_vgpu *vgpu) 307 { 308 struct gvt_dma *dma; 309 struct rb_node *node = NULL; 310 311 for (;;) { 312 mutex_lock(&vgpu->cache_lock); 313 node = rb_first(&vgpu->gfn_cache); 314 if (!node) { 315 mutex_unlock(&vgpu->cache_lock); 316 break; 317 } 318 dma = rb_entry(node, struct gvt_dma, gfn_node); 319 gvt_dma_unmap_page(vgpu, dma->gfn, dma->dma_addr, dma->size); 320 __gvt_cache_remove_entry(vgpu, dma); 321 mutex_unlock(&vgpu->cache_lock); 322 } 323 } 324 325 static void gvt_cache_init(struct intel_vgpu *vgpu) 326 { 327 vgpu->gfn_cache = RB_ROOT; 328 vgpu->dma_addr_cache = RB_ROOT; 329 vgpu->nr_cache_entries = 0; 330 mutex_init(&vgpu->cache_lock); 331 } 332 333 static void kvmgt_protect_table_init(struct intel_vgpu *info) 334 { 335 hash_init(info->ptable); 336 } 337 338 static void kvmgt_protect_table_destroy(struct intel_vgpu *info) 339 { 340 struct kvmgt_pgfn *p; 341 struct hlist_node *tmp; 342 int i; 343 344 hash_for_each_safe(info->ptable, i, tmp, p, hnode) { 345 hash_del(&p->hnode); 346 kfree(p); 347 } 348 } 349 350 static struct kvmgt_pgfn * 351 __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) 352 { 353 struct kvmgt_pgfn *p, *res = NULL; 354 355 hash_for_each_possible(info->ptable, p, hnode, gfn) { 356 if (gfn == p->gfn) { 357 res = p; 358 break; 359 } 360 } 361 362 return res; 363 } 364 365 static bool kvmgt_gfn_is_write_protected(struct intel_vgpu *info, gfn_t gfn) 366 { 367 struct kvmgt_pgfn *p; 368 369 p = __kvmgt_protect_table_find(info, gfn); 370 return !!p; 371 } 372 373 static void kvmgt_protect_table_add(struct intel_vgpu *info, gfn_t gfn) 374 { 375 struct kvmgt_pgfn *p; 376 377 if (kvmgt_gfn_is_write_protected(info, gfn)) 378 return; 379 380 p = kzalloc(sizeof(struct kvmgt_pgfn), GFP_ATOMIC); 381 if (WARN(!p, "gfn: 0x%llx\n", gfn)) 382 return; 383 384 p->gfn = gfn; 385 hash_add(info->ptable, &p->hnode, gfn); 386 } 387 388 static void kvmgt_protect_table_del(struct intel_vgpu *info, gfn_t gfn) 389 { 390 struct kvmgt_pgfn *p; 391 392 p = __kvmgt_protect_table_find(info, gfn); 393 if (p) { 394 hash_del(&p->hnode); 395 kfree(p); 396 } 397 } 398 399 static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf, 400 size_t count, loff_t *ppos, bool iswrite) 401 { 402 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 403 VFIO_PCI_NUM_REGIONS; 404 void *base = vgpu->region[i].data; 405 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 406 407 408 if (pos >= vgpu->region[i].size || iswrite) { 409 gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n"); 410 return -EINVAL; 411 } 412 count = min(count, (size_t)(vgpu->region[i].size - pos)); 413 memcpy(buf, base + pos, count); 414 415 return count; 416 } 417 418 static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu, 419 struct vfio_region *region) 420 { 421 } 422 423 static const struct intel_vgpu_regops intel_vgpu_regops_opregion = { 424 .rw = intel_vgpu_reg_rw_opregion, 425 .release = intel_vgpu_reg_release_opregion, 426 }; 427 428 static int handle_edid_regs(struct intel_vgpu *vgpu, 429 struct vfio_edid_region *region, char *buf, 430 size_t count, u16 offset, bool is_write) 431 { 432 struct vfio_region_gfx_edid *regs = ®ion->vfio_edid_regs; 433 unsigned int data; 434 435 if (offset + count > sizeof(*regs)) 436 return -EINVAL; 437 438 if (count != 4) 439 return -EINVAL; 440 441 if (is_write) { 442 data = *((unsigned int *)buf); 443 switch (offset) { 444 case offsetof(struct vfio_region_gfx_edid, link_state): 445 if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) { 446 if (!drm_edid_block_valid( 447 (u8 *)region->edid_blob, 448 0, 449 true, 450 NULL)) { 451 gvt_vgpu_err("invalid EDID blob\n"); 452 return -EINVAL; 453 } 454 intel_vgpu_emulate_hotplug(vgpu, true); 455 } else if (data == VFIO_DEVICE_GFX_LINK_STATE_DOWN) 456 intel_vgpu_emulate_hotplug(vgpu, false); 457 else { 458 gvt_vgpu_err("invalid EDID link state %d\n", 459 regs->link_state); 460 return -EINVAL; 461 } 462 regs->link_state = data; 463 break; 464 case offsetof(struct vfio_region_gfx_edid, edid_size): 465 if (data > regs->edid_max_size) { 466 gvt_vgpu_err("EDID size is bigger than %d!\n", 467 regs->edid_max_size); 468 return -EINVAL; 469 } 470 regs->edid_size = data; 471 break; 472 default: 473 /* read-only regs */ 474 gvt_vgpu_err("write read-only EDID region at offset %d\n", 475 offset); 476 return -EPERM; 477 } 478 } else { 479 memcpy(buf, (char *)regs + offset, count); 480 } 481 482 return count; 483 } 484 485 static int handle_edid_blob(struct vfio_edid_region *region, char *buf, 486 size_t count, u16 offset, bool is_write) 487 { 488 if (offset + count > region->vfio_edid_regs.edid_size) 489 return -EINVAL; 490 491 if (is_write) 492 memcpy(region->edid_blob + offset, buf, count); 493 else 494 memcpy(buf, region->edid_blob + offset, count); 495 496 return count; 497 } 498 499 static size_t intel_vgpu_reg_rw_edid(struct intel_vgpu *vgpu, char *buf, 500 size_t count, loff_t *ppos, bool iswrite) 501 { 502 int ret; 503 unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - 504 VFIO_PCI_NUM_REGIONS; 505 struct vfio_edid_region *region = vgpu->region[i].data; 506 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 507 508 if (pos < region->vfio_edid_regs.edid_offset) { 509 ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite); 510 } else { 511 pos -= EDID_BLOB_OFFSET; 512 ret = handle_edid_blob(region, buf, count, pos, iswrite); 513 } 514 515 if (ret < 0) 516 gvt_vgpu_err("failed to access EDID region\n"); 517 518 return ret; 519 } 520 521 static void intel_vgpu_reg_release_edid(struct intel_vgpu *vgpu, 522 struct vfio_region *region) 523 { 524 kfree(region->data); 525 } 526 527 static const struct intel_vgpu_regops intel_vgpu_regops_edid = { 528 .rw = intel_vgpu_reg_rw_edid, 529 .release = intel_vgpu_reg_release_edid, 530 }; 531 532 static int intel_vgpu_register_reg(struct intel_vgpu *vgpu, 533 unsigned int type, unsigned int subtype, 534 const struct intel_vgpu_regops *ops, 535 size_t size, u32 flags, void *data) 536 { 537 struct vfio_region *region; 538 539 region = krealloc(vgpu->region, 540 (vgpu->num_regions + 1) * sizeof(*region), 541 GFP_KERNEL); 542 if (!region) 543 return -ENOMEM; 544 545 vgpu->region = region; 546 vgpu->region[vgpu->num_regions].type = type; 547 vgpu->region[vgpu->num_regions].subtype = subtype; 548 vgpu->region[vgpu->num_regions].ops = ops; 549 vgpu->region[vgpu->num_regions].size = size; 550 vgpu->region[vgpu->num_regions].flags = flags; 551 vgpu->region[vgpu->num_regions].data = data; 552 vgpu->num_regions++; 553 return 0; 554 } 555 556 int intel_gvt_set_opregion(struct intel_vgpu *vgpu) 557 { 558 void *base; 559 int ret; 560 561 /* Each vgpu has its own opregion, although VFIO would create another 562 * one later. This one is used to expose opregion to VFIO. And the 563 * other one created by VFIO later, is used by guest actually. 564 */ 565 base = vgpu_opregion(vgpu)->va; 566 if (!base) 567 return -ENOMEM; 568 569 if (memcmp(base, OPREGION_SIGNATURE, 16)) { 570 memunmap(base); 571 return -EINVAL; 572 } 573 574 ret = intel_vgpu_register_reg(vgpu, 575 PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE, 576 VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION, 577 &intel_vgpu_regops_opregion, OPREGION_SIZE, 578 VFIO_REGION_INFO_FLAG_READ, base); 579 580 return ret; 581 } 582 583 int intel_gvt_set_edid(struct intel_vgpu *vgpu, int port_num) 584 { 585 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num); 586 struct vfio_edid_region *base; 587 int ret; 588 589 base = kzalloc(sizeof(*base), GFP_KERNEL); 590 if (!base) 591 return -ENOMEM; 592 593 /* TODO: Add multi-port and EDID extension block support */ 594 base->vfio_edid_regs.edid_offset = EDID_BLOB_OFFSET; 595 base->vfio_edid_regs.edid_max_size = EDID_SIZE; 596 base->vfio_edid_regs.edid_size = EDID_SIZE; 597 base->vfio_edid_regs.max_xres = vgpu_edid_xres(port->id); 598 base->vfio_edid_regs.max_yres = vgpu_edid_yres(port->id); 599 base->edid_blob = port->edid->edid_block; 600 601 ret = intel_vgpu_register_reg(vgpu, 602 VFIO_REGION_TYPE_GFX, 603 VFIO_REGION_SUBTYPE_GFX_EDID, 604 &intel_vgpu_regops_edid, EDID_SIZE, 605 VFIO_REGION_INFO_FLAG_READ | 606 VFIO_REGION_INFO_FLAG_WRITE | 607 VFIO_REGION_INFO_FLAG_CAPS, base); 608 609 return ret; 610 } 611 612 static void intel_vgpu_dma_unmap(struct vfio_device *vfio_dev, u64 iova, 613 u64 length) 614 { 615 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 616 struct gvt_dma *entry; 617 u64 iov_pfn = iova >> PAGE_SHIFT; 618 u64 end_iov_pfn = iov_pfn + length / PAGE_SIZE; 619 620 mutex_lock(&vgpu->cache_lock); 621 for (; iov_pfn < end_iov_pfn; iov_pfn++) { 622 entry = __gvt_cache_find_gfn(vgpu, iov_pfn); 623 if (!entry) 624 continue; 625 626 gvt_dma_unmap_page(vgpu, entry->gfn, entry->dma_addr, 627 entry->size); 628 __gvt_cache_remove_entry(vgpu, entry); 629 } 630 mutex_unlock(&vgpu->cache_lock); 631 } 632 633 static bool __kvmgt_vgpu_exist(struct intel_vgpu *vgpu) 634 { 635 struct intel_vgpu *itr; 636 int id; 637 bool ret = false; 638 639 mutex_lock(&vgpu->gvt->lock); 640 for_each_active_vgpu(vgpu->gvt, itr, id) { 641 if (!itr->attached) 642 continue; 643 644 if (vgpu->vfio_device.kvm == itr->vfio_device.kvm) { 645 ret = true; 646 goto out; 647 } 648 } 649 out: 650 mutex_unlock(&vgpu->gvt->lock); 651 return ret; 652 } 653 654 static int intel_vgpu_open_device(struct vfio_device *vfio_dev) 655 { 656 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 657 658 if (vgpu->attached) 659 return -EEXIST; 660 661 if (!vgpu->vfio_device.kvm || 662 vgpu->vfio_device.kvm->mm != current->mm) { 663 gvt_vgpu_err("KVM is required to use Intel vGPU\n"); 664 return -ESRCH; 665 } 666 667 kvm_get_kvm(vgpu->vfio_device.kvm); 668 669 if (__kvmgt_vgpu_exist(vgpu)) 670 return -EEXIST; 671 672 vgpu->attached = true; 673 674 kvmgt_protect_table_init(vgpu); 675 gvt_cache_init(vgpu); 676 677 vgpu->track_node.track_write = kvmgt_page_track_write; 678 vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; 679 kvm_page_track_register_notifier(vgpu->vfio_device.kvm, 680 &vgpu->track_node); 681 682 debugfs_create_ulong(KVMGT_DEBUGFS_FILENAME, 0444, vgpu->debugfs, 683 &vgpu->nr_cache_entries); 684 685 intel_gvt_activate_vgpu(vgpu); 686 687 return 0; 688 } 689 690 static void intel_vgpu_release_msi_eventfd_ctx(struct intel_vgpu *vgpu) 691 { 692 struct eventfd_ctx *trigger; 693 694 trigger = vgpu->msi_trigger; 695 if (trigger) { 696 eventfd_ctx_put(trigger); 697 vgpu->msi_trigger = NULL; 698 } 699 } 700 701 static void intel_vgpu_close_device(struct vfio_device *vfio_dev) 702 { 703 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 704 705 if (!vgpu->attached) 706 return; 707 708 intel_gvt_release_vgpu(vgpu); 709 710 debugfs_remove(debugfs_lookup(KVMGT_DEBUGFS_FILENAME, vgpu->debugfs)); 711 712 kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, 713 &vgpu->track_node); 714 kvmgt_protect_table_destroy(vgpu); 715 gvt_cache_destroy(vgpu); 716 717 intel_vgpu_release_msi_eventfd_ctx(vgpu); 718 719 vgpu->attached = false; 720 721 if (vgpu->vfio_device.kvm) 722 kvm_put_kvm(vgpu->vfio_device.kvm); 723 } 724 725 static u64 intel_vgpu_get_bar_addr(struct intel_vgpu *vgpu, int bar) 726 { 727 u32 start_lo, start_hi; 728 u32 mem_type; 729 730 start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 731 PCI_BASE_ADDRESS_MEM_MASK; 732 mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 733 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 734 735 switch (mem_type) { 736 case PCI_BASE_ADDRESS_MEM_TYPE_64: 737 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space 738 + bar + 4)); 739 break; 740 case PCI_BASE_ADDRESS_MEM_TYPE_32: 741 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 742 /* 1M mem BAR treated as 32-bit BAR */ 743 default: 744 /* mem unknown type treated as 32-bit BAR */ 745 start_hi = 0; 746 break; 747 } 748 749 return ((u64)start_hi << 32) | start_lo; 750 } 751 752 static int intel_vgpu_bar_rw(struct intel_vgpu *vgpu, int bar, u64 off, 753 void *buf, unsigned int count, bool is_write) 754 { 755 u64 bar_start = intel_vgpu_get_bar_addr(vgpu, bar); 756 int ret; 757 758 if (is_write) 759 ret = intel_vgpu_emulate_mmio_write(vgpu, 760 bar_start + off, buf, count); 761 else 762 ret = intel_vgpu_emulate_mmio_read(vgpu, 763 bar_start + off, buf, count); 764 return ret; 765 } 766 767 static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) 768 { 769 return off >= vgpu_aperture_offset(vgpu) && 770 off < vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu); 771 } 772 773 static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, 774 void *buf, unsigned long count, bool is_write) 775 { 776 void __iomem *aperture_va; 777 778 if (!intel_vgpu_in_aperture(vgpu, off) || 779 !intel_vgpu_in_aperture(vgpu, off + count)) { 780 gvt_vgpu_err("Invalid aperture offset %llu\n", off); 781 return -EINVAL; 782 } 783 784 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, 785 ALIGN_DOWN(off, PAGE_SIZE), 786 count + offset_in_page(off)); 787 if (!aperture_va) 788 return -EIO; 789 790 if (is_write) 791 memcpy_toio(aperture_va + offset_in_page(off), buf, count); 792 else 793 memcpy_fromio(buf, aperture_va + offset_in_page(off), count); 794 795 io_mapping_unmap(aperture_va); 796 797 return 0; 798 } 799 800 static ssize_t intel_vgpu_rw(struct intel_vgpu *vgpu, char *buf, 801 size_t count, loff_t *ppos, bool is_write) 802 { 803 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 804 u64 pos = *ppos & VFIO_PCI_OFFSET_MASK; 805 int ret = -EINVAL; 806 807 808 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) { 809 gvt_vgpu_err("invalid index: %u\n", index); 810 return -EINVAL; 811 } 812 813 switch (index) { 814 case VFIO_PCI_CONFIG_REGION_INDEX: 815 if (is_write) 816 ret = intel_vgpu_emulate_cfg_write(vgpu, pos, 817 buf, count); 818 else 819 ret = intel_vgpu_emulate_cfg_read(vgpu, pos, 820 buf, count); 821 break; 822 case VFIO_PCI_BAR0_REGION_INDEX: 823 ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos, 824 buf, count, is_write); 825 break; 826 case VFIO_PCI_BAR2_REGION_INDEX: 827 ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write); 828 break; 829 case VFIO_PCI_BAR1_REGION_INDEX: 830 case VFIO_PCI_BAR3_REGION_INDEX: 831 case VFIO_PCI_BAR4_REGION_INDEX: 832 case VFIO_PCI_BAR5_REGION_INDEX: 833 case VFIO_PCI_VGA_REGION_INDEX: 834 case VFIO_PCI_ROM_REGION_INDEX: 835 break; 836 default: 837 if (index >= VFIO_PCI_NUM_REGIONS + vgpu->num_regions) 838 return -EINVAL; 839 840 index -= VFIO_PCI_NUM_REGIONS; 841 return vgpu->region[index].ops->rw(vgpu, buf, count, 842 ppos, is_write); 843 } 844 845 return ret == 0 ? count : ret; 846 } 847 848 static bool gtt_entry(struct intel_vgpu *vgpu, loff_t *ppos) 849 { 850 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 851 struct intel_gvt *gvt = vgpu->gvt; 852 int offset; 853 854 /* Only allow MMIO GGTT entry access */ 855 if (index != PCI_BASE_ADDRESS_0) 856 return false; 857 858 offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) - 859 intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0); 860 861 return (offset >= gvt->device_info.gtt_start_offset && 862 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? 863 true : false; 864 } 865 866 static ssize_t intel_vgpu_read(struct vfio_device *vfio_dev, char __user *buf, 867 size_t count, loff_t *ppos) 868 { 869 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 870 unsigned int done = 0; 871 int ret; 872 873 while (count) { 874 size_t filled; 875 876 /* Only support GGTT entry 8 bytes read */ 877 if (count >= 8 && !(*ppos % 8) && 878 gtt_entry(vgpu, ppos)) { 879 u64 val; 880 881 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 882 ppos, false); 883 if (ret <= 0) 884 goto read_err; 885 886 if (copy_to_user(buf, &val, sizeof(val))) 887 goto read_err; 888 889 filled = 8; 890 } else if (count >= 4 && !(*ppos % 4)) { 891 u32 val; 892 893 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 894 ppos, false); 895 if (ret <= 0) 896 goto read_err; 897 898 if (copy_to_user(buf, &val, sizeof(val))) 899 goto read_err; 900 901 filled = 4; 902 } else if (count >= 2 && !(*ppos % 2)) { 903 u16 val; 904 905 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 906 ppos, false); 907 if (ret <= 0) 908 goto read_err; 909 910 if (copy_to_user(buf, &val, sizeof(val))) 911 goto read_err; 912 913 filled = 2; 914 } else { 915 u8 val; 916 917 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), ppos, 918 false); 919 if (ret <= 0) 920 goto read_err; 921 922 if (copy_to_user(buf, &val, sizeof(val))) 923 goto read_err; 924 925 filled = 1; 926 } 927 928 count -= filled; 929 done += filled; 930 *ppos += filled; 931 buf += filled; 932 } 933 934 return done; 935 936 read_err: 937 return -EFAULT; 938 } 939 940 static ssize_t intel_vgpu_write(struct vfio_device *vfio_dev, 941 const char __user *buf, 942 size_t count, loff_t *ppos) 943 { 944 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 945 unsigned int done = 0; 946 int ret; 947 948 while (count) { 949 size_t filled; 950 951 /* Only support GGTT entry 8 bytes write */ 952 if (count >= 8 && !(*ppos % 8) && 953 gtt_entry(vgpu, ppos)) { 954 u64 val; 955 956 if (copy_from_user(&val, buf, sizeof(val))) 957 goto write_err; 958 959 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 960 ppos, true); 961 if (ret <= 0) 962 goto write_err; 963 964 filled = 8; 965 } else if (count >= 4 && !(*ppos % 4)) { 966 u32 val; 967 968 if (copy_from_user(&val, buf, sizeof(val))) 969 goto write_err; 970 971 ret = intel_vgpu_rw(vgpu, (char *)&val, sizeof(val), 972 ppos, true); 973 if (ret <= 0) 974 goto write_err; 975 976 filled = 4; 977 } else if (count >= 2 && !(*ppos % 2)) { 978 u16 val; 979 980 if (copy_from_user(&val, buf, sizeof(val))) 981 goto write_err; 982 983 ret = intel_vgpu_rw(vgpu, (char *)&val, 984 sizeof(val), ppos, true); 985 if (ret <= 0) 986 goto write_err; 987 988 filled = 2; 989 } else { 990 u8 val; 991 992 if (copy_from_user(&val, buf, sizeof(val))) 993 goto write_err; 994 995 ret = intel_vgpu_rw(vgpu, &val, sizeof(val), 996 ppos, true); 997 if (ret <= 0) 998 goto write_err; 999 1000 filled = 1; 1001 } 1002 1003 count -= filled; 1004 done += filled; 1005 *ppos += filled; 1006 buf += filled; 1007 } 1008 1009 return done; 1010 write_err: 1011 return -EFAULT; 1012 } 1013 1014 static int intel_vgpu_mmap(struct vfio_device *vfio_dev, 1015 struct vm_area_struct *vma) 1016 { 1017 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1018 unsigned int index; 1019 u64 virtaddr; 1020 unsigned long req_size, pgoff, req_start; 1021 pgprot_t pg_prot; 1022 1023 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); 1024 if (index >= VFIO_PCI_ROM_REGION_INDEX) 1025 return -EINVAL; 1026 1027 if (vma->vm_end < vma->vm_start) 1028 return -EINVAL; 1029 if ((vma->vm_flags & VM_SHARED) == 0) 1030 return -EINVAL; 1031 if (index != VFIO_PCI_BAR2_REGION_INDEX) 1032 return -EINVAL; 1033 1034 pg_prot = vma->vm_page_prot; 1035 virtaddr = vma->vm_start; 1036 req_size = vma->vm_end - vma->vm_start; 1037 pgoff = vma->vm_pgoff & 1038 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); 1039 req_start = pgoff << PAGE_SHIFT; 1040 1041 if (!intel_vgpu_in_aperture(vgpu, req_start)) 1042 return -EINVAL; 1043 if (req_start + req_size > 1044 vgpu_aperture_offset(vgpu) + vgpu_aperture_sz(vgpu)) 1045 return -EINVAL; 1046 1047 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; 1048 1049 return remap_pfn_range(vma, virtaddr, pgoff, req_size, pg_prot); 1050 } 1051 1052 static int intel_vgpu_get_irq_count(struct intel_vgpu *vgpu, int type) 1053 { 1054 if (type == VFIO_PCI_INTX_IRQ_INDEX || type == VFIO_PCI_MSI_IRQ_INDEX) 1055 return 1; 1056 1057 return 0; 1058 } 1059 1060 static int intel_vgpu_set_intx_mask(struct intel_vgpu *vgpu, 1061 unsigned int index, unsigned int start, 1062 unsigned int count, u32 flags, 1063 void *data) 1064 { 1065 return 0; 1066 } 1067 1068 static int intel_vgpu_set_intx_unmask(struct intel_vgpu *vgpu, 1069 unsigned int index, unsigned int start, 1070 unsigned int count, u32 flags, void *data) 1071 { 1072 return 0; 1073 } 1074 1075 static int intel_vgpu_set_intx_trigger(struct intel_vgpu *vgpu, 1076 unsigned int index, unsigned int start, unsigned int count, 1077 u32 flags, void *data) 1078 { 1079 return 0; 1080 } 1081 1082 static int intel_vgpu_set_msi_trigger(struct intel_vgpu *vgpu, 1083 unsigned int index, unsigned int start, unsigned int count, 1084 u32 flags, void *data) 1085 { 1086 struct eventfd_ctx *trigger; 1087 1088 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { 1089 int fd = *(int *)data; 1090 1091 trigger = eventfd_ctx_fdget(fd); 1092 if (IS_ERR(trigger)) { 1093 gvt_vgpu_err("eventfd_ctx_fdget failed\n"); 1094 return PTR_ERR(trigger); 1095 } 1096 vgpu->msi_trigger = trigger; 1097 } else if ((flags & VFIO_IRQ_SET_DATA_NONE) && !count) 1098 intel_vgpu_release_msi_eventfd_ctx(vgpu); 1099 1100 return 0; 1101 } 1102 1103 static int intel_vgpu_set_irqs(struct intel_vgpu *vgpu, u32 flags, 1104 unsigned int index, unsigned int start, unsigned int count, 1105 void *data) 1106 { 1107 int (*func)(struct intel_vgpu *vgpu, unsigned int index, 1108 unsigned int start, unsigned int count, u32 flags, 1109 void *data) = NULL; 1110 1111 switch (index) { 1112 case VFIO_PCI_INTX_IRQ_INDEX: 1113 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1114 case VFIO_IRQ_SET_ACTION_MASK: 1115 func = intel_vgpu_set_intx_mask; 1116 break; 1117 case VFIO_IRQ_SET_ACTION_UNMASK: 1118 func = intel_vgpu_set_intx_unmask; 1119 break; 1120 case VFIO_IRQ_SET_ACTION_TRIGGER: 1121 func = intel_vgpu_set_intx_trigger; 1122 break; 1123 } 1124 break; 1125 case VFIO_PCI_MSI_IRQ_INDEX: 1126 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) { 1127 case VFIO_IRQ_SET_ACTION_MASK: 1128 case VFIO_IRQ_SET_ACTION_UNMASK: 1129 /* XXX Need masking support exported */ 1130 break; 1131 case VFIO_IRQ_SET_ACTION_TRIGGER: 1132 func = intel_vgpu_set_msi_trigger; 1133 break; 1134 } 1135 break; 1136 } 1137 1138 if (!func) 1139 return -ENOTTY; 1140 1141 return func(vgpu, index, start, count, flags, data); 1142 } 1143 1144 static long intel_vgpu_ioctl(struct vfio_device *vfio_dev, unsigned int cmd, 1145 unsigned long arg) 1146 { 1147 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1148 unsigned long minsz; 1149 1150 gvt_dbg_core("vgpu%d ioctl, cmd: %d\n", vgpu->id, cmd); 1151 1152 if (cmd == VFIO_DEVICE_GET_INFO) { 1153 struct vfio_device_info info; 1154 1155 minsz = offsetofend(struct vfio_device_info, num_irqs); 1156 1157 if (copy_from_user(&info, (void __user *)arg, minsz)) 1158 return -EFAULT; 1159 1160 if (info.argsz < minsz) 1161 return -EINVAL; 1162 1163 info.flags = VFIO_DEVICE_FLAGS_PCI; 1164 info.flags |= VFIO_DEVICE_FLAGS_RESET; 1165 info.num_regions = VFIO_PCI_NUM_REGIONS + 1166 vgpu->num_regions; 1167 info.num_irqs = VFIO_PCI_NUM_IRQS; 1168 1169 return copy_to_user((void __user *)arg, &info, minsz) ? 1170 -EFAULT : 0; 1171 1172 } else if (cmd == VFIO_DEVICE_GET_REGION_INFO) { 1173 struct vfio_region_info info; 1174 struct vfio_info_cap caps = { .buf = NULL, .size = 0 }; 1175 unsigned int i; 1176 int ret; 1177 struct vfio_region_info_cap_sparse_mmap *sparse = NULL; 1178 int nr_areas = 1; 1179 int cap_type_id; 1180 1181 minsz = offsetofend(struct vfio_region_info, offset); 1182 1183 if (copy_from_user(&info, (void __user *)arg, minsz)) 1184 return -EFAULT; 1185 1186 if (info.argsz < minsz) 1187 return -EINVAL; 1188 1189 switch (info.index) { 1190 case VFIO_PCI_CONFIG_REGION_INDEX: 1191 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1192 info.size = vgpu->gvt->device_info.cfg_space_size; 1193 info.flags = VFIO_REGION_INFO_FLAG_READ | 1194 VFIO_REGION_INFO_FLAG_WRITE; 1195 break; 1196 case VFIO_PCI_BAR0_REGION_INDEX: 1197 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1198 info.size = vgpu->cfg_space.bar[info.index].size; 1199 if (!info.size) { 1200 info.flags = 0; 1201 break; 1202 } 1203 1204 info.flags = VFIO_REGION_INFO_FLAG_READ | 1205 VFIO_REGION_INFO_FLAG_WRITE; 1206 break; 1207 case VFIO_PCI_BAR1_REGION_INDEX: 1208 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1209 info.size = 0; 1210 info.flags = 0; 1211 break; 1212 case VFIO_PCI_BAR2_REGION_INDEX: 1213 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1214 info.flags = VFIO_REGION_INFO_FLAG_CAPS | 1215 VFIO_REGION_INFO_FLAG_MMAP | 1216 VFIO_REGION_INFO_FLAG_READ | 1217 VFIO_REGION_INFO_FLAG_WRITE; 1218 info.size = gvt_aperture_sz(vgpu->gvt); 1219 1220 sparse = kzalloc(struct_size(sparse, areas, nr_areas), 1221 GFP_KERNEL); 1222 if (!sparse) 1223 return -ENOMEM; 1224 1225 sparse->header.id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1226 sparse->header.version = 1; 1227 sparse->nr_areas = nr_areas; 1228 cap_type_id = VFIO_REGION_INFO_CAP_SPARSE_MMAP; 1229 sparse->areas[0].offset = 1230 PAGE_ALIGN(vgpu_aperture_offset(vgpu)); 1231 sparse->areas[0].size = vgpu_aperture_sz(vgpu); 1232 break; 1233 1234 case VFIO_PCI_BAR3_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX: 1235 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1236 info.size = 0; 1237 info.flags = 0; 1238 1239 gvt_dbg_core("get region info bar:%d\n", info.index); 1240 break; 1241 1242 case VFIO_PCI_ROM_REGION_INDEX: 1243 case VFIO_PCI_VGA_REGION_INDEX: 1244 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1245 info.size = 0; 1246 info.flags = 0; 1247 1248 gvt_dbg_core("get region info index:%d\n", info.index); 1249 break; 1250 default: 1251 { 1252 struct vfio_region_info_cap_type cap_type = { 1253 .header.id = VFIO_REGION_INFO_CAP_TYPE, 1254 .header.version = 1 }; 1255 1256 if (info.index >= VFIO_PCI_NUM_REGIONS + 1257 vgpu->num_regions) 1258 return -EINVAL; 1259 info.index = 1260 array_index_nospec(info.index, 1261 VFIO_PCI_NUM_REGIONS + 1262 vgpu->num_regions); 1263 1264 i = info.index - VFIO_PCI_NUM_REGIONS; 1265 1266 info.offset = 1267 VFIO_PCI_INDEX_TO_OFFSET(info.index); 1268 info.size = vgpu->region[i].size; 1269 info.flags = vgpu->region[i].flags; 1270 1271 cap_type.type = vgpu->region[i].type; 1272 cap_type.subtype = vgpu->region[i].subtype; 1273 1274 ret = vfio_info_add_capability(&caps, 1275 &cap_type.header, 1276 sizeof(cap_type)); 1277 if (ret) 1278 return ret; 1279 } 1280 } 1281 1282 if ((info.flags & VFIO_REGION_INFO_FLAG_CAPS) && sparse) { 1283 switch (cap_type_id) { 1284 case VFIO_REGION_INFO_CAP_SPARSE_MMAP: 1285 ret = vfio_info_add_capability(&caps, 1286 &sparse->header, 1287 struct_size(sparse, areas, 1288 sparse->nr_areas)); 1289 if (ret) { 1290 kfree(sparse); 1291 return ret; 1292 } 1293 break; 1294 default: 1295 kfree(sparse); 1296 return -EINVAL; 1297 } 1298 } 1299 1300 if (caps.size) { 1301 info.flags |= VFIO_REGION_INFO_FLAG_CAPS; 1302 if (info.argsz < sizeof(info) + caps.size) { 1303 info.argsz = sizeof(info) + caps.size; 1304 info.cap_offset = 0; 1305 } else { 1306 vfio_info_cap_shift(&caps, sizeof(info)); 1307 if (copy_to_user((void __user *)arg + 1308 sizeof(info), caps.buf, 1309 caps.size)) { 1310 kfree(caps.buf); 1311 kfree(sparse); 1312 return -EFAULT; 1313 } 1314 info.cap_offset = sizeof(info); 1315 } 1316 1317 kfree(caps.buf); 1318 } 1319 1320 kfree(sparse); 1321 return copy_to_user((void __user *)arg, &info, minsz) ? 1322 -EFAULT : 0; 1323 } else if (cmd == VFIO_DEVICE_GET_IRQ_INFO) { 1324 struct vfio_irq_info info; 1325 1326 minsz = offsetofend(struct vfio_irq_info, count); 1327 1328 if (copy_from_user(&info, (void __user *)arg, minsz)) 1329 return -EFAULT; 1330 1331 if (info.argsz < minsz || info.index >= VFIO_PCI_NUM_IRQS) 1332 return -EINVAL; 1333 1334 switch (info.index) { 1335 case VFIO_PCI_INTX_IRQ_INDEX: 1336 case VFIO_PCI_MSI_IRQ_INDEX: 1337 break; 1338 default: 1339 return -EINVAL; 1340 } 1341 1342 info.flags = VFIO_IRQ_INFO_EVENTFD; 1343 1344 info.count = intel_vgpu_get_irq_count(vgpu, info.index); 1345 1346 if (info.index == VFIO_PCI_INTX_IRQ_INDEX) 1347 info.flags |= (VFIO_IRQ_INFO_MASKABLE | 1348 VFIO_IRQ_INFO_AUTOMASKED); 1349 else 1350 info.flags |= VFIO_IRQ_INFO_NORESIZE; 1351 1352 return copy_to_user((void __user *)arg, &info, minsz) ? 1353 -EFAULT : 0; 1354 } else if (cmd == VFIO_DEVICE_SET_IRQS) { 1355 struct vfio_irq_set hdr; 1356 u8 *data = NULL; 1357 int ret = 0; 1358 size_t data_size = 0; 1359 1360 minsz = offsetofend(struct vfio_irq_set, count); 1361 1362 if (copy_from_user(&hdr, (void __user *)arg, minsz)) 1363 return -EFAULT; 1364 1365 if (!(hdr.flags & VFIO_IRQ_SET_DATA_NONE)) { 1366 int max = intel_vgpu_get_irq_count(vgpu, hdr.index); 1367 1368 ret = vfio_set_irqs_validate_and_prepare(&hdr, max, 1369 VFIO_PCI_NUM_IRQS, &data_size); 1370 if (ret) { 1371 gvt_vgpu_err("intel:vfio_set_irqs_validate_and_prepare failed\n"); 1372 return -EINVAL; 1373 } 1374 if (data_size) { 1375 data = memdup_user((void __user *)(arg + minsz), 1376 data_size); 1377 if (IS_ERR(data)) 1378 return PTR_ERR(data); 1379 } 1380 } 1381 1382 ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index, 1383 hdr.start, hdr.count, data); 1384 kfree(data); 1385 1386 return ret; 1387 } else if (cmd == VFIO_DEVICE_RESET) { 1388 intel_gvt_reset_vgpu(vgpu); 1389 return 0; 1390 } else if (cmd == VFIO_DEVICE_QUERY_GFX_PLANE) { 1391 struct vfio_device_gfx_plane_info dmabuf; 1392 int ret = 0; 1393 1394 minsz = offsetofend(struct vfio_device_gfx_plane_info, 1395 dmabuf_id); 1396 if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) 1397 return -EFAULT; 1398 if (dmabuf.argsz < minsz) 1399 return -EINVAL; 1400 1401 ret = intel_vgpu_query_plane(vgpu, &dmabuf); 1402 if (ret != 0) 1403 return ret; 1404 1405 return copy_to_user((void __user *)arg, &dmabuf, minsz) ? 1406 -EFAULT : 0; 1407 } else if (cmd == VFIO_DEVICE_GET_GFX_DMABUF) { 1408 __u32 dmabuf_id; 1409 1410 if (get_user(dmabuf_id, (__u32 __user *)arg)) 1411 return -EFAULT; 1412 return intel_vgpu_get_dmabuf(vgpu, dmabuf_id); 1413 } 1414 1415 return -ENOTTY; 1416 } 1417 1418 static ssize_t 1419 vgpu_id_show(struct device *dev, struct device_attribute *attr, 1420 char *buf) 1421 { 1422 struct intel_vgpu *vgpu = dev_get_drvdata(dev); 1423 1424 return sprintf(buf, "%d\n", vgpu->id); 1425 } 1426 1427 static DEVICE_ATTR_RO(vgpu_id); 1428 1429 static struct attribute *intel_vgpu_attrs[] = { 1430 &dev_attr_vgpu_id.attr, 1431 NULL 1432 }; 1433 1434 static const struct attribute_group intel_vgpu_group = { 1435 .name = "intel_vgpu", 1436 .attrs = intel_vgpu_attrs, 1437 }; 1438 1439 static const struct attribute_group *intel_vgpu_groups[] = { 1440 &intel_vgpu_group, 1441 NULL, 1442 }; 1443 1444 static int intel_vgpu_init_dev(struct vfio_device *vfio_dev) 1445 { 1446 struct mdev_device *mdev = to_mdev_device(vfio_dev->dev); 1447 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1448 struct intel_vgpu_type *type = 1449 container_of(mdev->type, struct intel_vgpu_type, type); 1450 1451 vgpu->gvt = kdev_to_i915(mdev->type->parent->dev)->gvt; 1452 return intel_gvt_create_vgpu(vgpu, type->conf); 1453 } 1454 1455 static void intel_vgpu_release_dev(struct vfio_device *vfio_dev) 1456 { 1457 struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); 1458 1459 intel_gvt_destroy_vgpu(vgpu); 1460 vfio_free_device(vfio_dev); 1461 } 1462 1463 static const struct vfio_device_ops intel_vgpu_dev_ops = { 1464 .init = intel_vgpu_init_dev, 1465 .release = intel_vgpu_release_dev, 1466 .open_device = intel_vgpu_open_device, 1467 .close_device = intel_vgpu_close_device, 1468 .read = intel_vgpu_read, 1469 .write = intel_vgpu_write, 1470 .mmap = intel_vgpu_mmap, 1471 .ioctl = intel_vgpu_ioctl, 1472 .dma_unmap = intel_vgpu_dma_unmap, 1473 }; 1474 1475 static int intel_vgpu_probe(struct mdev_device *mdev) 1476 { 1477 struct intel_vgpu *vgpu; 1478 int ret; 1479 1480 vgpu = vfio_alloc_device(intel_vgpu, vfio_device, &mdev->dev, 1481 &intel_vgpu_dev_ops); 1482 if (IS_ERR(vgpu)) { 1483 gvt_err("failed to create intel vgpu: %ld\n", PTR_ERR(vgpu)); 1484 return PTR_ERR(vgpu); 1485 } 1486 1487 dev_set_drvdata(&mdev->dev, vgpu); 1488 ret = vfio_register_emulated_iommu_dev(&vgpu->vfio_device); 1489 if (ret) 1490 goto out_put_vdev; 1491 1492 gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n", 1493 dev_name(mdev_dev(mdev))); 1494 return 0; 1495 1496 out_put_vdev: 1497 vfio_put_device(&vgpu->vfio_device); 1498 return ret; 1499 } 1500 1501 static void intel_vgpu_remove(struct mdev_device *mdev) 1502 { 1503 struct intel_vgpu *vgpu = dev_get_drvdata(&mdev->dev); 1504 1505 if (WARN_ON_ONCE(vgpu->attached)) 1506 return; 1507 1508 vfio_unregister_group_dev(&vgpu->vfio_device); 1509 vfio_put_device(&vgpu->vfio_device); 1510 } 1511 1512 static unsigned int intel_vgpu_get_available(struct mdev_type *mtype) 1513 { 1514 struct intel_vgpu_type *type = 1515 container_of(mtype, struct intel_vgpu_type, type); 1516 struct intel_gvt *gvt = kdev_to_i915(mtype->parent->dev)->gvt; 1517 unsigned int low_gm_avail, high_gm_avail, fence_avail; 1518 1519 mutex_lock(&gvt->lock); 1520 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE - 1521 gvt->gm.vgpu_allocated_low_gm_size; 1522 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE - 1523 gvt->gm.vgpu_allocated_high_gm_size; 1524 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE - 1525 gvt->fence.vgpu_allocated_fence_num; 1526 mutex_unlock(&gvt->lock); 1527 1528 return min3(low_gm_avail / type->conf->low_mm, 1529 high_gm_avail / type->conf->high_mm, 1530 fence_avail / type->conf->fence); 1531 } 1532 1533 static struct mdev_driver intel_vgpu_mdev_driver = { 1534 .device_api = VFIO_DEVICE_API_PCI_STRING, 1535 .driver = { 1536 .name = "intel_vgpu_mdev", 1537 .owner = THIS_MODULE, 1538 .dev_groups = intel_vgpu_groups, 1539 }, 1540 .probe = intel_vgpu_probe, 1541 .remove = intel_vgpu_remove, 1542 .get_available = intel_vgpu_get_available, 1543 .show_description = intel_vgpu_show_description, 1544 }; 1545 1546 int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) 1547 { 1548 struct kvm *kvm = info->vfio_device.kvm; 1549 struct kvm_memory_slot *slot; 1550 int idx; 1551 1552 if (!info->attached) 1553 return -ESRCH; 1554 1555 idx = srcu_read_lock(&kvm->srcu); 1556 slot = gfn_to_memslot(kvm, gfn); 1557 if (!slot) { 1558 srcu_read_unlock(&kvm->srcu, idx); 1559 return -EINVAL; 1560 } 1561 1562 write_lock(&kvm->mmu_lock); 1563 1564 if (kvmgt_gfn_is_write_protected(info, gfn)) 1565 goto out; 1566 1567 kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1568 kvmgt_protect_table_add(info, gfn); 1569 1570 out: 1571 write_unlock(&kvm->mmu_lock); 1572 srcu_read_unlock(&kvm->srcu, idx); 1573 return 0; 1574 } 1575 1576 int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) 1577 { 1578 struct kvm *kvm = info->vfio_device.kvm; 1579 struct kvm_memory_slot *slot; 1580 int idx; 1581 1582 if (!info->attached) 1583 return 0; 1584 1585 idx = srcu_read_lock(&kvm->srcu); 1586 slot = gfn_to_memslot(kvm, gfn); 1587 if (!slot) { 1588 srcu_read_unlock(&kvm->srcu, idx); 1589 return -EINVAL; 1590 } 1591 1592 write_lock(&kvm->mmu_lock); 1593 1594 if (!kvmgt_gfn_is_write_protected(info, gfn)) 1595 goto out; 1596 1597 kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); 1598 kvmgt_protect_table_del(info, gfn); 1599 1600 out: 1601 write_unlock(&kvm->mmu_lock); 1602 srcu_read_unlock(&kvm->srcu, idx); 1603 return 0; 1604 } 1605 1606 static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, 1607 const u8 *val, int len, 1608 struct kvm_page_track_notifier_node *node) 1609 { 1610 struct intel_vgpu *info = 1611 container_of(node, struct intel_vgpu, track_node); 1612 1613 if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) 1614 intel_vgpu_page_track_handler(info, gpa, 1615 (void *)val, len); 1616 } 1617 1618 static void kvmgt_page_track_flush_slot(struct kvm *kvm, 1619 struct kvm_memory_slot *slot, 1620 struct kvm_page_track_notifier_node *node) 1621 { 1622 int i; 1623 gfn_t gfn; 1624 struct intel_vgpu *info = 1625 container_of(node, struct intel_vgpu, track_node); 1626 1627 write_lock(&kvm->mmu_lock); 1628 for (i = 0; i < slot->npages; i++) { 1629 gfn = slot->base_gfn + i; 1630 if (kvmgt_gfn_is_write_protected(info, gfn)) { 1631 kvm_slot_page_track_remove_page(kvm, slot, gfn, 1632 KVM_PAGE_TRACK_WRITE); 1633 kvmgt_protect_table_del(info, gfn); 1634 } 1635 } 1636 write_unlock(&kvm->mmu_lock); 1637 } 1638 1639 void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) 1640 { 1641 int i; 1642 1643 if (!vgpu->region) 1644 return; 1645 1646 for (i = 0; i < vgpu->num_regions; i++) 1647 if (vgpu->region[i].ops->release) 1648 vgpu->region[i].ops->release(vgpu, 1649 &vgpu->region[i]); 1650 vgpu->num_regions = 0; 1651 kfree(vgpu->region); 1652 vgpu->region = NULL; 1653 } 1654 1655 int intel_gvt_dma_map_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, 1656 unsigned long size, dma_addr_t *dma_addr) 1657 { 1658 struct gvt_dma *entry; 1659 int ret; 1660 1661 if (!vgpu->attached) 1662 return -EINVAL; 1663 1664 mutex_lock(&vgpu->cache_lock); 1665 1666 entry = __gvt_cache_find_gfn(vgpu, gfn); 1667 if (!entry) { 1668 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1669 if (ret) 1670 goto err_unlock; 1671 1672 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1673 if (ret) 1674 goto err_unmap; 1675 } else if (entry->size != size) { 1676 /* the same gfn with different size: unmap and re-map */ 1677 gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size); 1678 __gvt_cache_remove_entry(vgpu, entry); 1679 1680 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size); 1681 if (ret) 1682 goto err_unlock; 1683 1684 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size); 1685 if (ret) 1686 goto err_unmap; 1687 } else { 1688 kref_get(&entry->ref); 1689 *dma_addr = entry->dma_addr; 1690 } 1691 1692 mutex_unlock(&vgpu->cache_lock); 1693 return 0; 1694 1695 err_unmap: 1696 gvt_dma_unmap_page(vgpu, gfn, *dma_addr, size); 1697 err_unlock: 1698 mutex_unlock(&vgpu->cache_lock); 1699 return ret; 1700 } 1701 1702 int intel_gvt_dma_pin_guest_page(struct intel_vgpu *vgpu, dma_addr_t dma_addr) 1703 { 1704 struct gvt_dma *entry; 1705 int ret = 0; 1706 1707 if (!vgpu->attached) 1708 return -ENODEV; 1709 1710 mutex_lock(&vgpu->cache_lock); 1711 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1712 if (entry) 1713 kref_get(&entry->ref); 1714 else 1715 ret = -ENOMEM; 1716 mutex_unlock(&vgpu->cache_lock); 1717 1718 return ret; 1719 } 1720 1721 static void __gvt_dma_release(struct kref *ref) 1722 { 1723 struct gvt_dma *entry = container_of(ref, typeof(*entry), ref); 1724 1725 gvt_dma_unmap_page(entry->vgpu, entry->gfn, entry->dma_addr, 1726 entry->size); 1727 __gvt_cache_remove_entry(entry->vgpu, entry); 1728 } 1729 1730 void intel_gvt_dma_unmap_guest_page(struct intel_vgpu *vgpu, 1731 dma_addr_t dma_addr) 1732 { 1733 struct gvt_dma *entry; 1734 1735 if (!vgpu->attached) 1736 return; 1737 1738 mutex_lock(&vgpu->cache_lock); 1739 entry = __gvt_cache_find_dma_addr(vgpu, dma_addr); 1740 if (entry) 1741 kref_put(&entry->ref, __gvt_dma_release); 1742 mutex_unlock(&vgpu->cache_lock); 1743 } 1744 1745 static void init_device_info(struct intel_gvt *gvt) 1746 { 1747 struct intel_gvt_device_info *info = &gvt->device_info; 1748 struct pci_dev *pdev = to_pci_dev(gvt->gt->i915->drm.dev); 1749 1750 info->max_support_vgpus = 8; 1751 info->cfg_space_size = PCI_CFG_SPACE_EXP_SIZE; 1752 info->mmio_size = 2 * 1024 * 1024; 1753 info->mmio_bar = 0; 1754 info->gtt_start_offset = 8 * 1024 * 1024; 1755 info->gtt_entry_size = 8; 1756 info->gtt_entry_size_shift = 3; 1757 info->gmadr_bytes_in_cmd = 8; 1758 info->max_surface_size = 36 * 1024 * 1024; 1759 info->msi_cap_offset = pdev->msi_cap; 1760 } 1761 1762 static void intel_gvt_test_and_emulate_vblank(struct intel_gvt *gvt) 1763 { 1764 struct intel_vgpu *vgpu; 1765 int id; 1766 1767 mutex_lock(&gvt->lock); 1768 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) { 1769 if (test_and_clear_bit(INTEL_GVT_REQUEST_EMULATE_VBLANK + id, 1770 (void *)&gvt->service_request)) { 1771 if (vgpu->active) 1772 intel_vgpu_emulate_vblank(vgpu); 1773 } 1774 } 1775 mutex_unlock(&gvt->lock); 1776 } 1777 1778 static int gvt_service_thread(void *data) 1779 { 1780 struct intel_gvt *gvt = (struct intel_gvt *)data; 1781 int ret; 1782 1783 gvt_dbg_core("service thread start\n"); 1784 1785 while (!kthread_should_stop()) { 1786 ret = wait_event_interruptible(gvt->service_thread_wq, 1787 kthread_should_stop() || gvt->service_request); 1788 1789 if (kthread_should_stop()) 1790 break; 1791 1792 if (WARN_ONCE(ret, "service thread is waken up by signal.\n")) 1793 continue; 1794 1795 intel_gvt_test_and_emulate_vblank(gvt); 1796 1797 if (test_bit(INTEL_GVT_REQUEST_SCHED, 1798 (void *)&gvt->service_request) || 1799 test_bit(INTEL_GVT_REQUEST_EVENT_SCHED, 1800 (void *)&gvt->service_request)) { 1801 intel_gvt_schedule(gvt); 1802 } 1803 } 1804 1805 return 0; 1806 } 1807 1808 static void clean_service_thread(struct intel_gvt *gvt) 1809 { 1810 kthread_stop(gvt->service_thread); 1811 } 1812 1813 static int init_service_thread(struct intel_gvt *gvt) 1814 { 1815 init_waitqueue_head(&gvt->service_thread_wq); 1816 1817 gvt->service_thread = kthread_run(gvt_service_thread, 1818 gvt, "gvt_service_thread"); 1819 if (IS_ERR(gvt->service_thread)) { 1820 gvt_err("fail to start service thread.\n"); 1821 return PTR_ERR(gvt->service_thread); 1822 } 1823 return 0; 1824 } 1825 1826 /** 1827 * intel_gvt_clean_device - clean a GVT device 1828 * @i915: i915 private 1829 * 1830 * This function is called at the driver unloading stage, to free the 1831 * resources owned by a GVT device. 1832 * 1833 */ 1834 static void intel_gvt_clean_device(struct drm_i915_private *i915) 1835 { 1836 struct intel_gvt *gvt = fetch_and_zero(&i915->gvt); 1837 1838 if (drm_WARN_ON(&i915->drm, !gvt)) 1839 return; 1840 1841 mdev_unregister_parent(&gvt->parent); 1842 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1843 intel_gvt_clean_vgpu_types(gvt); 1844 1845 intel_gvt_debugfs_clean(gvt); 1846 clean_service_thread(gvt); 1847 intel_gvt_clean_cmd_parser(gvt); 1848 intel_gvt_clean_sched_policy(gvt); 1849 intel_gvt_clean_workload_scheduler(gvt); 1850 intel_gvt_clean_gtt(gvt); 1851 intel_gvt_free_firmware(gvt); 1852 intel_gvt_clean_mmio_info(gvt); 1853 idr_destroy(&gvt->vgpu_idr); 1854 1855 kfree(i915->gvt); 1856 } 1857 1858 /** 1859 * intel_gvt_init_device - initialize a GVT device 1860 * @i915: drm i915 private data 1861 * 1862 * This function is called at the initialization stage, to initialize 1863 * necessary GVT components. 1864 * 1865 * Returns: 1866 * Zero on success, negative error code if failed. 1867 * 1868 */ 1869 static int intel_gvt_init_device(struct drm_i915_private *i915) 1870 { 1871 struct intel_gvt *gvt; 1872 struct intel_vgpu *vgpu; 1873 int ret; 1874 1875 if (drm_WARN_ON(&i915->drm, i915->gvt)) 1876 return -EEXIST; 1877 1878 gvt = kzalloc(sizeof(struct intel_gvt), GFP_KERNEL); 1879 if (!gvt) 1880 return -ENOMEM; 1881 1882 gvt_dbg_core("init gvt device\n"); 1883 1884 idr_init_base(&gvt->vgpu_idr, 1); 1885 spin_lock_init(&gvt->scheduler.mmio_context_lock); 1886 mutex_init(&gvt->lock); 1887 mutex_init(&gvt->sched_lock); 1888 gvt->gt = to_gt(i915); 1889 i915->gvt = gvt; 1890 1891 init_device_info(gvt); 1892 1893 ret = intel_gvt_setup_mmio_info(gvt); 1894 if (ret) 1895 goto out_clean_idr; 1896 1897 intel_gvt_init_engine_mmio_context(gvt); 1898 1899 ret = intel_gvt_load_firmware(gvt); 1900 if (ret) 1901 goto out_clean_mmio_info; 1902 1903 ret = intel_gvt_init_irq(gvt); 1904 if (ret) 1905 goto out_free_firmware; 1906 1907 ret = intel_gvt_init_gtt(gvt); 1908 if (ret) 1909 goto out_free_firmware; 1910 1911 ret = intel_gvt_init_workload_scheduler(gvt); 1912 if (ret) 1913 goto out_clean_gtt; 1914 1915 ret = intel_gvt_init_sched_policy(gvt); 1916 if (ret) 1917 goto out_clean_workload_scheduler; 1918 1919 ret = intel_gvt_init_cmd_parser(gvt); 1920 if (ret) 1921 goto out_clean_sched_policy; 1922 1923 ret = init_service_thread(gvt); 1924 if (ret) 1925 goto out_clean_cmd_parser; 1926 1927 ret = intel_gvt_init_vgpu_types(gvt); 1928 if (ret) 1929 goto out_clean_thread; 1930 1931 vgpu = intel_gvt_create_idle_vgpu(gvt); 1932 if (IS_ERR(vgpu)) { 1933 ret = PTR_ERR(vgpu); 1934 gvt_err("failed to create idle vgpu\n"); 1935 goto out_clean_types; 1936 } 1937 gvt->idle_vgpu = vgpu; 1938 1939 intel_gvt_debugfs_init(gvt); 1940 1941 ret = mdev_register_parent(&gvt->parent, i915->drm.dev, 1942 &intel_vgpu_mdev_driver, 1943 gvt->mdev_types, gvt->num_types); 1944 if (ret) 1945 goto out_destroy_idle_vgpu; 1946 1947 gvt_dbg_core("gvt device initialization is done\n"); 1948 return 0; 1949 1950 out_destroy_idle_vgpu: 1951 intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu); 1952 intel_gvt_debugfs_clean(gvt); 1953 out_clean_types: 1954 intel_gvt_clean_vgpu_types(gvt); 1955 out_clean_thread: 1956 clean_service_thread(gvt); 1957 out_clean_cmd_parser: 1958 intel_gvt_clean_cmd_parser(gvt); 1959 out_clean_sched_policy: 1960 intel_gvt_clean_sched_policy(gvt); 1961 out_clean_workload_scheduler: 1962 intel_gvt_clean_workload_scheduler(gvt); 1963 out_clean_gtt: 1964 intel_gvt_clean_gtt(gvt); 1965 out_free_firmware: 1966 intel_gvt_free_firmware(gvt); 1967 out_clean_mmio_info: 1968 intel_gvt_clean_mmio_info(gvt); 1969 out_clean_idr: 1970 idr_destroy(&gvt->vgpu_idr); 1971 kfree(gvt); 1972 i915->gvt = NULL; 1973 return ret; 1974 } 1975 1976 static void intel_gvt_pm_resume(struct drm_i915_private *i915) 1977 { 1978 struct intel_gvt *gvt = i915->gvt; 1979 1980 intel_gvt_restore_fence(gvt); 1981 intel_gvt_restore_mmio(gvt); 1982 intel_gvt_restore_ggtt(gvt); 1983 } 1984 1985 static const struct intel_vgpu_ops intel_gvt_vgpu_ops = { 1986 .init_device = intel_gvt_init_device, 1987 .clean_device = intel_gvt_clean_device, 1988 .pm_resume = intel_gvt_pm_resume, 1989 }; 1990 1991 static int __init kvmgt_init(void) 1992 { 1993 int ret; 1994 1995 ret = intel_gvt_set_ops(&intel_gvt_vgpu_ops); 1996 if (ret) 1997 return ret; 1998 1999 ret = mdev_register_driver(&intel_vgpu_mdev_driver); 2000 if (ret) 2001 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2002 return ret; 2003 } 2004 2005 static void __exit kvmgt_exit(void) 2006 { 2007 mdev_unregister_driver(&intel_vgpu_mdev_driver); 2008 intel_gvt_clear_ops(&intel_gvt_vgpu_ops); 2009 } 2010 2011 module_init(kvmgt_init); 2012 module_exit(kvmgt_exit); 2013 2014 MODULE_LICENSE("GPL and additional rights"); 2015 MODULE_AUTHOR("Intel Corporation"); 2016