xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/interrupt.c (revision ddc141e5)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *    Zhi Wang <zhi.a.wang@intel.com>
26  *
27  * Contributors:
28  *    Min he <min.he@intel.com>
29  *
30  */
31 
32 #include "i915_drv.h"
33 #include "gvt.h"
34 #include "trace.h"
35 
36 /* common offset among interrupt control registers */
37 #define regbase_to_isr(base)	(base)
38 #define regbase_to_imr(base)	(base + 0x4)
39 #define regbase_to_iir(base)	(base + 0x8)
40 #define regbase_to_ier(base)	(base + 0xC)
41 
42 #define iir_to_regbase(iir)    (iir - 0x8)
43 #define ier_to_regbase(ier)    (ier - 0xC)
44 
45 #define get_event_virt_handler(irq, e)	(irq->events[e].v_handler)
46 #define get_irq_info(irq, e)		(irq->events[e].info)
47 
48 #define irq_to_gvt(irq) \
49 	container_of(irq, struct intel_gvt, irq)
50 
51 static void update_upstream_irq(struct intel_vgpu *vgpu,
52 		struct intel_gvt_irq_info *info);
53 
54 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
55 	[RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
56 	[RCS_DEBUG] = "Render EU debug from SVG",
57 	[RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
58 	[RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
59 	[RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
60 	[RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
61 	[RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
62 	[RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
63 
64 	[VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
65 	[VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
66 	[VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
67 	[VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
68 	[VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
69 	[VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
70 	[VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
71 	[VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
72 	[VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
73 	[VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
74 
75 	[BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
76 	[BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
77 	[BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
78 	[BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
79 	[BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
80 	[BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
81 
82 	[VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
83 	[VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
84 
85 	[PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
86 	[PIPE_A_CRC_ERR] = "Pipe A CRC error",
87 	[PIPE_A_CRC_DONE] = "Pipe A CRC done",
88 	[PIPE_A_VSYNC] = "Pipe A vsync",
89 	[PIPE_A_LINE_COMPARE] = "Pipe A line compare",
90 	[PIPE_A_ODD_FIELD] = "Pipe A odd field",
91 	[PIPE_A_EVEN_FIELD] = "Pipe A even field",
92 	[PIPE_A_VBLANK] = "Pipe A vblank",
93 	[PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
94 	[PIPE_B_CRC_ERR] = "Pipe B CRC error",
95 	[PIPE_B_CRC_DONE] = "Pipe B CRC done",
96 	[PIPE_B_VSYNC] = "Pipe B vsync",
97 	[PIPE_B_LINE_COMPARE] = "Pipe B line compare",
98 	[PIPE_B_ODD_FIELD] = "Pipe B odd field",
99 	[PIPE_B_EVEN_FIELD] = "Pipe B even field",
100 	[PIPE_B_VBLANK] = "Pipe B vblank",
101 	[PIPE_C_VBLANK] = "Pipe C vblank",
102 	[DPST_PHASE_IN] = "DPST phase in event",
103 	[DPST_HISTOGRAM] = "DPST histogram event",
104 	[GSE] = "GSE",
105 	[DP_A_HOTPLUG] = "DP A Hotplug",
106 	[AUX_CHANNEL_A] = "AUX Channel A",
107 	[PERF_COUNTER] = "Performance counter",
108 	[POISON] = "Poison",
109 	[GTT_FAULT] = "GTT fault",
110 	[PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
111 	[PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
112 	[PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
113 	[SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
114 	[SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
115 	[SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
116 
117 	[PCU_THERMAL] = "PCU Thermal Event",
118 	[PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
119 
120 	[FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
121 	[AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
122 	[AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
123 	[FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
124 	[AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
125 	[AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
126 	[FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
127 	[AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
128 	[AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
129 	[ERR_AND_DBG] = "South Error and Debug Interupts Combined",
130 	[GMBUS] = "Gmbus",
131 	[SDVO_B_HOTPLUG] = "SDVO B hotplug",
132 	[CRT_HOTPLUG] = "CRT Hotplug",
133 	[DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
134 	[DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
135 	[DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
136 	[AUX_CHANNEL_B] = "AUX Channel B",
137 	[AUX_CHANNEL_C] = "AUX Channel C",
138 	[AUX_CHANNEL_D] = "AUX Channel D",
139 	[AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
140 	[AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
141 	[AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
142 
143 	[INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
144 };
145 
146 static inline struct intel_gvt_irq_info *regbase_to_irq_info(
147 		struct intel_gvt *gvt,
148 		unsigned int reg)
149 {
150 	struct intel_gvt_irq *irq = &gvt->irq;
151 	int i;
152 
153 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
154 		if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
155 			return irq->info[i];
156 	}
157 
158 	return NULL;
159 }
160 
161 /**
162  * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
163  * @vgpu: a vGPU
164  * @reg: register offset written by guest
165  * @p_data: register data written by guest
166  * @bytes: register data length
167  *
168  * This function is used to emulate the generic IMR register bit change
169  * behavior.
170  *
171  * Returns:
172  * Zero on success, negative error code if failed.
173  *
174  */
175 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
176 	unsigned int reg, void *p_data, unsigned int bytes)
177 {
178 	struct intel_gvt *gvt = vgpu->gvt;
179 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
180 	u32 imr = *(u32 *)p_data;
181 
182 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
183 		       (vgpu_vreg(vgpu, reg) ^ imr));
184 
185 	vgpu_vreg(vgpu, reg) = imr;
186 
187 	ops->check_pending_irq(vgpu);
188 
189 	return 0;
190 }
191 
192 /**
193  * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
194  * @vgpu: a vGPU
195  * @reg: register offset written by guest
196  * @p_data: register data written by guest
197  * @bytes: register data length
198  *
199  * This function is used to emulate the master IRQ register on gen8+.
200  *
201  * Returns:
202  * Zero on success, negative error code if failed.
203  *
204  */
205 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
206 	unsigned int reg, void *p_data, unsigned int bytes)
207 {
208 	struct intel_gvt *gvt = vgpu->gvt;
209 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
210 	u32 ier = *(u32 *)p_data;
211 	u32 virtual_ier = vgpu_vreg(vgpu, reg);
212 
213 	trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
214 		       (virtual_ier ^ ier));
215 
216 	/*
217 	 * GEN8_MASTER_IRQ is a special irq register,
218 	 * only bit 31 is allowed to be modified
219 	 * and treated as an IER bit.
220 	 */
221 	ier &= GEN8_MASTER_IRQ_CONTROL;
222 	virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
223 	vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
224 	vgpu_vreg(vgpu, reg) |= ier;
225 
226 	ops->check_pending_irq(vgpu);
227 
228 	return 0;
229 }
230 
231 /**
232  * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
233  * @vgpu: a vGPU
234  * @reg: register offset written by guest
235  * @p_data: register data written by guest
236  * @bytes: register data length
237  *
238  * This function is used to emulate the generic IER register behavior.
239  *
240  * Returns:
241  * Zero on success, negative error code if failed.
242  *
243  */
244 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
245 	unsigned int reg, void *p_data, unsigned int bytes)
246 {
247 	struct intel_gvt *gvt = vgpu->gvt;
248 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
249 	struct intel_gvt_irq_info *info;
250 	u32 ier = *(u32 *)p_data;
251 
252 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
253 		       (vgpu_vreg(vgpu, reg) ^ ier));
254 
255 	vgpu_vreg(vgpu, reg) = ier;
256 
257 	info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
258 	if (WARN_ON(!info))
259 		return -EINVAL;
260 
261 	if (info->has_upstream_irq)
262 		update_upstream_irq(vgpu, info);
263 
264 	ops->check_pending_irq(vgpu);
265 
266 	return 0;
267 }
268 
269 /**
270  * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
271  * @vgpu: a vGPU
272  * @reg: register offset written by guest
273  * @p_data: register data written by guest
274  * @bytes: register data length
275  *
276  * This function is used to emulate the generic IIR register behavior.
277  *
278  * Returns:
279  * Zero on success, negative error code if failed.
280  *
281  */
282 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
283 	void *p_data, unsigned int bytes)
284 {
285 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
286 		iir_to_regbase(reg));
287 	u32 iir = *(u32 *)p_data;
288 
289 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
290 		       (vgpu_vreg(vgpu, reg) ^ iir));
291 
292 	if (WARN_ON(!info))
293 		return -EINVAL;
294 
295 	vgpu_vreg(vgpu, reg) &= ~iir;
296 
297 	if (info->has_upstream_irq)
298 		update_upstream_irq(vgpu, info);
299 	return 0;
300 }
301 
302 static struct intel_gvt_irq_map gen8_irq_map[] = {
303 	{ INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
304 	{ INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
305 	{ INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
306 	{ INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
307 	{ INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
308 	{ INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
309 	{ INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
310 	{ INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
311 	{ INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
312 	{ INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
313 	{ INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
314 	{ INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
315 	{ INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
316 	{ -1, -1, ~0 },
317 };
318 
319 static void update_upstream_irq(struct intel_vgpu *vgpu,
320 		struct intel_gvt_irq_info *info)
321 {
322 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
323 	struct intel_gvt_irq_map *map = irq->irq_map;
324 	struct intel_gvt_irq_info *up_irq_info = NULL;
325 	u32 set_bits = 0;
326 	u32 clear_bits = 0;
327 	int bit;
328 	u32 val = vgpu_vreg(vgpu,
329 			regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
330 		& vgpu_vreg(vgpu,
331 			regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
332 
333 	if (!info->has_upstream_irq)
334 		return;
335 
336 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
337 		if (info->group != map->down_irq_group)
338 			continue;
339 
340 		if (!up_irq_info)
341 			up_irq_info = irq->info[map->up_irq_group];
342 		else
343 			WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
344 
345 		bit = map->up_irq_bit;
346 
347 		if (val & map->down_irq_bitmask)
348 			set_bits |= (1 << bit);
349 		else
350 			clear_bits |= (1 << bit);
351 	}
352 
353 	WARN_ON(!up_irq_info);
354 
355 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
356 		u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
357 
358 		vgpu_vreg(vgpu, isr) &= ~clear_bits;
359 		vgpu_vreg(vgpu, isr) |= set_bits;
360 	} else {
361 		u32 iir = regbase_to_iir(
362 			i915_mmio_reg_offset(up_irq_info->reg_base));
363 		u32 imr = regbase_to_imr(
364 			i915_mmio_reg_offset(up_irq_info->reg_base));
365 
366 		vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
367 	}
368 
369 	if (up_irq_info->has_upstream_irq)
370 		update_upstream_irq(vgpu, up_irq_info);
371 }
372 
373 static void init_irq_map(struct intel_gvt_irq *irq)
374 {
375 	struct intel_gvt_irq_map *map;
376 	struct intel_gvt_irq_info *up_info, *down_info;
377 	int up_bit;
378 
379 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
380 		up_info = irq->info[map->up_irq_group];
381 		up_bit = map->up_irq_bit;
382 		down_info = irq->info[map->down_irq_group];
383 
384 		set_bit(up_bit, up_info->downstream_irq_bitmap);
385 		down_info->has_upstream_irq = true;
386 
387 		gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
388 			up_info->group, up_bit,
389 			down_info->group, map->down_irq_bitmask);
390 	}
391 }
392 
393 /* =======================vEvent injection===================== */
394 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
395 {
396 	return intel_gvt_hypervisor_inject_msi(vgpu);
397 }
398 
399 static void propagate_event(struct intel_gvt_irq *irq,
400 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
401 {
402 	struct intel_gvt_irq_info *info;
403 	unsigned int reg_base;
404 	int bit;
405 
406 	info = get_irq_info(irq, event);
407 	if (WARN_ON(!info))
408 		return;
409 
410 	reg_base = i915_mmio_reg_offset(info->reg_base);
411 	bit = irq->events[event].bit;
412 
413 	if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
414 					regbase_to_imr(reg_base)))) {
415 		trace_propagate_event(vgpu->id, irq_name[event], bit);
416 		set_bit(bit, (void *)&vgpu_vreg(vgpu,
417 					regbase_to_iir(reg_base)));
418 	}
419 }
420 
421 /* =======================vEvent Handlers===================== */
422 static void handle_default_event_virt(struct intel_gvt_irq *irq,
423 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
424 {
425 	if (!vgpu->irq.irq_warn_once[event]) {
426 		gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
427 			vgpu->id, event, irq_name[event]);
428 		vgpu->irq.irq_warn_once[event] = true;
429 	}
430 	propagate_event(irq, event, vgpu);
431 }
432 
433 /* =====================GEN specific logic======================= */
434 /* GEN8 interrupt routines. */
435 
436 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
437 static struct intel_gvt_irq_info gen8_##regname##_info = { \
438 	.name = #regname"-IRQ", \
439 	.reg_base = (regbase), \
440 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
441 		INTEL_GVT_EVENT_RESERVED}, \
442 }
443 
444 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
445 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
446 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
447 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
448 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
455 
456 static struct intel_gvt_irq_info gvt_base_pch_info = {
457 	.name = "PCH-IRQ",
458 	.reg_base = SDEISR,
459 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
460 		INTEL_GVT_EVENT_RESERVED},
461 };
462 
463 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
464 {
465 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
466 	int i;
467 
468 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
469 				GEN8_MASTER_IRQ_CONTROL))
470 		return;
471 
472 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
473 		struct intel_gvt_irq_info *info = irq->info[i];
474 		u32 reg_base;
475 
476 		if (!info->has_upstream_irq)
477 			continue;
478 
479 		reg_base = i915_mmio_reg_offset(info->reg_base);
480 		if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
481 				& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
482 			update_upstream_irq(vgpu, info);
483 	}
484 
485 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
486 			& ~GEN8_MASTER_IRQ_CONTROL)
487 		inject_virtual_interrupt(vgpu);
488 }
489 
490 static void gen8_init_irq(
491 		struct intel_gvt_irq *irq)
492 {
493 	struct intel_gvt *gvt = irq_to_gvt(irq);
494 
495 #define SET_BIT_INFO(s, b, e, i)		\
496 	do {					\
497 		s->events[e].bit = b;		\
498 		s->events[e].info = s->info[i];	\
499 		s->info[i]->bit_to_event[b] = e;\
500 	} while (0)
501 
502 #define SET_IRQ_GROUP(s, g, i) \
503 	do { \
504 		s->info[g] = i; \
505 		(i)->group = g; \
506 		set_bit(g, s->irq_info_bitmap); \
507 	} while (0)
508 
509 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
510 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
511 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
512 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
513 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
514 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
515 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
516 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
517 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
518 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
519 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
520 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
521 
522 	/* GEN8 level 2 interrupts. */
523 
524 	/* GEN8 interrupt GT0 events */
525 	SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
526 	SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
527 	SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
528 
529 	SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
530 	SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
531 	SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
532 
533 	/* GEN8 interrupt GT1 events */
534 	SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
535 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
536 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
537 
538 	if (HAS_BSD2(gvt->dev_priv)) {
539 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
540 			INTEL_GVT_IRQ_INFO_GT1);
541 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
542 			INTEL_GVT_IRQ_INFO_GT1);
543 		SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
544 			INTEL_GVT_IRQ_INFO_GT1);
545 	}
546 
547 	/* GEN8 interrupt GT3 events */
548 	SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
549 	SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
550 	SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
551 
552 	SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
553 	SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
554 	SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
555 
556 	/* GEN8 interrupt DE PORT events */
557 	SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
558 	SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
559 
560 	/* GEN8 interrupt DE MISC events */
561 	SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
562 
563 	/* PCH events */
564 	SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
565 	SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
566 	SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
567 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
568 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
569 
570 	if (IS_BROADWELL(gvt->dev_priv)) {
571 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
572 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
573 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
574 
575 		SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
576 		SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
577 
578 		SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
579 		SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
580 
581 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
582 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
583 	} else if (IS_SKYLAKE(gvt->dev_priv) || IS_KABYLAKE(gvt->dev_priv)) {
584 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
585 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
586 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
587 
588 		SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
589 		SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
590 		SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
591 
592 		SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
593 		SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
594 		SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
595 	}
596 
597 	/* GEN8 interrupt PCU events */
598 	SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
599 	SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
600 }
601 
602 static struct intel_gvt_irq_ops gen8_irq_ops = {
603 	.init_irq = gen8_init_irq,
604 	.check_pending_irq = gen8_check_pending_irq,
605 };
606 
607 /**
608  * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
609  * @vgpu: a vGPU
610  * @event: interrupt event
611  *
612  * This function is used to trigger a virtual interrupt event for vGPU.
613  * The caller provides the event to be triggered, the framework itself
614  * will emulate the IRQ register bit change.
615  *
616  */
617 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
618 	enum intel_gvt_event_type event)
619 {
620 	struct intel_gvt *gvt = vgpu->gvt;
621 	struct intel_gvt_irq *irq = &gvt->irq;
622 	gvt_event_virt_handler_t handler;
623 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
624 
625 	handler = get_event_virt_handler(irq, event);
626 	WARN_ON(!handler);
627 
628 	handler(irq, event, vgpu);
629 
630 	ops->check_pending_irq(vgpu);
631 }
632 
633 static void init_events(
634 	struct intel_gvt_irq *irq)
635 {
636 	int i;
637 
638 	for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
639 		irq->events[i].info = NULL;
640 		irq->events[i].v_handler = handle_default_event_virt;
641 	}
642 }
643 
644 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
645 {
646 	struct intel_gvt_vblank_timer *vblank_timer;
647 	struct intel_gvt_irq *irq;
648 	struct intel_gvt *gvt;
649 
650 	vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer);
651 	irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
652 	gvt = container_of(irq, struct intel_gvt, irq);
653 
654 	intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK);
655 	hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
656 	return HRTIMER_RESTART;
657 }
658 
659 /**
660  * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
661  * @gvt: a GVT device
662  *
663  * This function is called at driver unloading stage, to clean up GVT-g IRQ
664  * emulation subsystem.
665  *
666  */
667 void intel_gvt_clean_irq(struct intel_gvt *gvt)
668 {
669 	struct intel_gvt_irq *irq = &gvt->irq;
670 
671 	hrtimer_cancel(&irq->vblank_timer.timer);
672 }
673 
674 #define VBLNAK_TIMER_PERIOD 16000000
675 
676 /**
677  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
678  * @gvt: a GVT device
679  *
680  * This function is called at driver loading stage, to initialize the GVT-g IRQ
681  * emulation subsystem.
682  *
683  * Returns:
684  * Zero on success, negative error code if failed.
685  */
686 int intel_gvt_init_irq(struct intel_gvt *gvt)
687 {
688 	struct intel_gvt_irq *irq = &gvt->irq;
689 	struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
690 
691 	gvt_dbg_core("init irq framework\n");
692 
693 	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)
694 		|| IS_KABYLAKE(gvt->dev_priv)) {
695 		irq->ops = &gen8_irq_ops;
696 		irq->irq_map = gen8_irq_map;
697 	} else {
698 		WARN_ON(1);
699 		return -ENODEV;
700 	}
701 
702 	/* common event initialization */
703 	init_events(irq);
704 
705 	/* gen specific initialization */
706 	irq->ops->init_irq(irq);
707 
708 	init_irq_map(irq);
709 
710 	hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
711 	vblank_timer->timer.function = vblank_timer_fn;
712 	vblank_timer->period = VBLNAK_TIMER_PERIOD;
713 
714 	return 0;
715 }
716