1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min he <min.he@intel.com> 29 * 30 */ 31 32 #include "i915_drv.h" 33 #include "i915_reg.h" 34 #include "gvt.h" 35 #include "trace.h" 36 37 /* common offset among interrupt control registers */ 38 #define regbase_to_isr(base) (base) 39 #define regbase_to_imr(base) (base + 0x4) 40 #define regbase_to_iir(base) (base + 0x8) 41 #define regbase_to_ier(base) (base + 0xC) 42 43 #define iir_to_regbase(iir) (iir - 0x8) 44 #define ier_to_regbase(ier) (ier - 0xC) 45 46 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler) 47 #define get_irq_info(irq, e) (irq->events[e].info) 48 49 #define irq_to_gvt(irq) \ 50 container_of(irq, struct intel_gvt, irq) 51 52 static void update_upstream_irq(struct intel_vgpu *vgpu, 53 struct intel_gvt_irq_info *info); 54 55 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = { 56 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT", 57 [RCS_DEBUG] = "Render EU debug from SVG", 58 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status", 59 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt", 60 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify", 61 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded", 62 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults", 63 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt", 64 65 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT", 66 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status", 67 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt", 68 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify", 69 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded", 70 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults", 71 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt", 72 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT", 73 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify", 74 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt", 75 76 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT", 77 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status", 78 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt", 79 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify", 80 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults", 81 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt", 82 83 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify", 84 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt", 85 86 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun", 87 [PIPE_A_CRC_ERR] = "Pipe A CRC error", 88 [PIPE_A_CRC_DONE] = "Pipe A CRC done", 89 [PIPE_A_VSYNC] = "Pipe A vsync", 90 [PIPE_A_LINE_COMPARE] = "Pipe A line compare", 91 [PIPE_A_ODD_FIELD] = "Pipe A odd field", 92 [PIPE_A_EVEN_FIELD] = "Pipe A even field", 93 [PIPE_A_VBLANK] = "Pipe A vblank", 94 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun", 95 [PIPE_B_CRC_ERR] = "Pipe B CRC error", 96 [PIPE_B_CRC_DONE] = "Pipe B CRC done", 97 [PIPE_B_VSYNC] = "Pipe B vsync", 98 [PIPE_B_LINE_COMPARE] = "Pipe B line compare", 99 [PIPE_B_ODD_FIELD] = "Pipe B odd field", 100 [PIPE_B_EVEN_FIELD] = "Pipe B even field", 101 [PIPE_B_VBLANK] = "Pipe B vblank", 102 [PIPE_C_VBLANK] = "Pipe C vblank", 103 [DPST_PHASE_IN] = "DPST phase in event", 104 [DPST_HISTOGRAM] = "DPST histogram event", 105 [GSE] = "GSE", 106 [DP_A_HOTPLUG] = "DP A Hotplug", 107 [AUX_CHANNEL_A] = "AUX Channel A", 108 [PERF_COUNTER] = "Performance counter", 109 [POISON] = "Poison", 110 [GTT_FAULT] = "GTT fault", 111 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done", 112 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done", 113 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done", 114 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done", 115 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done", 116 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done", 117 118 [PCU_THERMAL] = "PCU Thermal Event", 119 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event", 120 121 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A", 122 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A", 123 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A", 124 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B", 125 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B", 126 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B", 127 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C", 128 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C", 129 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C", 130 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined", 131 [GMBUS] = "Gmbus", 132 [SDVO_B_HOTPLUG] = "SDVO B hotplug", 133 [CRT_HOTPLUG] = "CRT Hotplug", 134 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug", 135 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug", 136 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug", 137 [AUX_CHANNEL_B] = "AUX Channel B", 138 [AUX_CHANNEL_C] = "AUX Channel C", 139 [AUX_CHANNEL_D] = "AUX Channel D", 140 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B", 141 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C", 142 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D", 143 144 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!", 145 }; 146 147 static inline struct intel_gvt_irq_info *regbase_to_irq_info( 148 struct intel_gvt *gvt, 149 unsigned int reg) 150 { 151 struct intel_gvt_irq *irq = &gvt->irq; 152 int i; 153 154 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 155 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) 156 return irq->info[i]; 157 } 158 159 return NULL; 160 } 161 162 /** 163 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler 164 * @vgpu: a vGPU 165 * @reg: register offset written by guest 166 * @p_data: register data written by guest 167 * @bytes: register data length 168 * 169 * This function is used to emulate the generic IMR register bit change 170 * behavior. 171 * 172 * Returns: 173 * Zero on success, negative error code if failed. 174 * 175 */ 176 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu, 177 unsigned int reg, void *p_data, unsigned int bytes) 178 { 179 struct intel_gvt *gvt = vgpu->gvt; 180 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 181 u32 imr = *(u32 *)p_data; 182 183 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg), 184 (vgpu_vreg(vgpu, reg) ^ imr)); 185 186 vgpu_vreg(vgpu, reg) = imr; 187 188 ops->check_pending_irq(vgpu); 189 190 return 0; 191 } 192 193 /** 194 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler 195 * @vgpu: a vGPU 196 * @reg: register offset written by guest 197 * @p_data: register data written by guest 198 * @bytes: register data length 199 * 200 * This function is used to emulate the master IRQ register on gen8+. 201 * 202 * Returns: 203 * Zero on success, negative error code if failed. 204 * 205 */ 206 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu, 207 unsigned int reg, void *p_data, unsigned int bytes) 208 { 209 struct intel_gvt *gvt = vgpu->gvt; 210 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 211 u32 ier = *(u32 *)p_data; 212 u32 virtual_ier = vgpu_vreg(vgpu, reg); 213 214 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier, 215 (virtual_ier ^ ier)); 216 217 /* 218 * GEN8_MASTER_IRQ is a special irq register, 219 * only bit 31 is allowed to be modified 220 * and treated as an IER bit. 221 */ 222 ier &= GEN8_MASTER_IRQ_CONTROL; 223 virtual_ier &= GEN8_MASTER_IRQ_CONTROL; 224 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL; 225 vgpu_vreg(vgpu, reg) |= ier; 226 227 ops->check_pending_irq(vgpu); 228 229 return 0; 230 } 231 232 /** 233 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler 234 * @vgpu: a vGPU 235 * @reg: register offset written by guest 236 * @p_data: register data written by guest 237 * @bytes: register data length 238 * 239 * This function is used to emulate the generic IER register behavior. 240 * 241 * Returns: 242 * Zero on success, negative error code if failed. 243 * 244 */ 245 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu, 246 unsigned int reg, void *p_data, unsigned int bytes) 247 { 248 struct intel_gvt *gvt = vgpu->gvt; 249 struct drm_i915_private *i915 = gvt->gt->i915; 250 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 251 struct intel_gvt_irq_info *info; 252 u32 ier = *(u32 *)p_data; 253 254 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg), 255 (vgpu_vreg(vgpu, reg) ^ ier)); 256 257 vgpu_vreg(vgpu, reg) = ier; 258 259 info = regbase_to_irq_info(gvt, ier_to_regbase(reg)); 260 if (drm_WARN_ON(&i915->drm, !info)) 261 return -EINVAL; 262 263 if (info->has_upstream_irq) 264 update_upstream_irq(vgpu, info); 265 266 ops->check_pending_irq(vgpu); 267 268 return 0; 269 } 270 271 /** 272 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler 273 * @vgpu: a vGPU 274 * @reg: register offset written by guest 275 * @p_data: register data written by guest 276 * @bytes: register data length 277 * 278 * This function is used to emulate the generic IIR register behavior. 279 * 280 * Returns: 281 * Zero on success, negative error code if failed. 282 * 283 */ 284 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg, 285 void *p_data, unsigned int bytes) 286 { 287 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 288 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt, 289 iir_to_regbase(reg)); 290 u32 iir = *(u32 *)p_data; 291 292 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg), 293 (vgpu_vreg(vgpu, reg) ^ iir)); 294 295 if (drm_WARN_ON(&i915->drm, !info)) 296 return -EINVAL; 297 298 vgpu_vreg(vgpu, reg) &= ~iir; 299 300 if (info->has_upstream_irq) 301 update_upstream_irq(vgpu, info); 302 return 0; 303 } 304 305 static struct intel_gvt_irq_map gen8_irq_map[] = { 306 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff }, 307 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 }, 308 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff }, 309 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 }, 310 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff }, 311 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff }, 312 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 }, 313 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 }, 314 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 }, 315 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 }, 316 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 }, 317 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 }, 318 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 }, 319 { -1, -1, ~0 }, 320 }; 321 322 static void update_upstream_irq(struct intel_vgpu *vgpu, 323 struct intel_gvt_irq_info *info) 324 { 325 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 326 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 327 struct intel_gvt_irq_map *map = irq->irq_map; 328 struct intel_gvt_irq_info *up_irq_info = NULL; 329 u32 set_bits = 0; 330 u32 clear_bits = 0; 331 int bit; 332 u32 val = vgpu_vreg(vgpu, 333 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) 334 & vgpu_vreg(vgpu, 335 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); 336 337 if (!info->has_upstream_irq) 338 return; 339 340 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 341 if (info->group != map->down_irq_group) 342 continue; 343 344 if (!up_irq_info) 345 up_irq_info = irq->info[map->up_irq_group]; 346 else 347 drm_WARN_ON(&i915->drm, up_irq_info != 348 irq->info[map->up_irq_group]); 349 350 bit = map->up_irq_bit; 351 352 if (val & map->down_irq_bitmask) 353 set_bits |= (1 << bit); 354 else 355 clear_bits |= (1 << bit); 356 } 357 358 if (drm_WARN_ON(&i915->drm, !up_irq_info)) 359 return; 360 361 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) { 362 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); 363 364 vgpu_vreg(vgpu, isr) &= ~clear_bits; 365 vgpu_vreg(vgpu, isr) |= set_bits; 366 } else { 367 u32 iir = regbase_to_iir( 368 i915_mmio_reg_offset(up_irq_info->reg_base)); 369 u32 imr = regbase_to_imr( 370 i915_mmio_reg_offset(up_irq_info->reg_base)); 371 372 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); 373 } 374 375 if (up_irq_info->has_upstream_irq) 376 update_upstream_irq(vgpu, up_irq_info); 377 } 378 379 static void init_irq_map(struct intel_gvt_irq *irq) 380 { 381 struct intel_gvt_irq_map *map; 382 struct intel_gvt_irq_info *up_info, *down_info; 383 int up_bit; 384 385 for (map = irq->irq_map; map->up_irq_bit != -1; map++) { 386 up_info = irq->info[map->up_irq_group]; 387 up_bit = map->up_irq_bit; 388 down_info = irq->info[map->down_irq_group]; 389 390 set_bit(up_bit, up_info->downstream_irq_bitmap); 391 down_info->has_upstream_irq = true; 392 393 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n", 394 up_info->group, up_bit, 395 down_info->group, map->down_irq_bitmask); 396 } 397 } 398 399 /* =======================vEvent injection===================== */ 400 static int inject_virtual_interrupt(struct intel_vgpu *vgpu) 401 { 402 return intel_gvt_hypervisor_inject_msi(vgpu); 403 } 404 405 static void propagate_event(struct intel_gvt_irq *irq, 406 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 407 { 408 struct intel_gvt_irq_info *info; 409 unsigned int reg_base; 410 int bit; 411 412 info = get_irq_info(irq, event); 413 if (WARN_ON(!info)) 414 return; 415 416 reg_base = i915_mmio_reg_offset(info->reg_base); 417 bit = irq->events[event].bit; 418 419 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu, 420 regbase_to_imr(reg_base)))) { 421 trace_propagate_event(vgpu->id, irq_name[event], bit); 422 set_bit(bit, (void *)&vgpu_vreg(vgpu, 423 regbase_to_iir(reg_base))); 424 } 425 } 426 427 /* =======================vEvent Handlers===================== */ 428 static void handle_default_event_virt(struct intel_gvt_irq *irq, 429 enum intel_gvt_event_type event, struct intel_vgpu *vgpu) 430 { 431 if (!vgpu->irq.irq_warn_once[event]) { 432 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n", 433 vgpu->id, event, irq_name[event]); 434 vgpu->irq.irq_warn_once[event] = true; 435 } 436 propagate_event(irq, event, vgpu); 437 } 438 439 /* =====================GEN specific logic======================= */ 440 /* GEN8 interrupt routines. */ 441 442 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \ 443 static struct intel_gvt_irq_info gen8_##regname##_info = { \ 444 .name = #regname"-IRQ", \ 445 .reg_base = (regbase), \ 446 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \ 447 INTEL_GVT_EVENT_RESERVED}, \ 448 } 449 450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0)); 451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1)); 452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2)); 453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3)); 454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A)); 455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B)); 456 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C)); 457 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR); 458 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR); 459 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR); 460 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ); 461 462 static struct intel_gvt_irq_info gvt_base_pch_info = { 463 .name = "PCH-IRQ", 464 .reg_base = SDEISR, 465 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = 466 INTEL_GVT_EVENT_RESERVED}, 467 }; 468 469 static void gen8_check_pending_irq(struct intel_vgpu *vgpu) 470 { 471 struct intel_gvt_irq *irq = &vgpu->gvt->irq; 472 int i; 473 474 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & 475 GEN8_MASTER_IRQ_CONTROL)) 476 return; 477 478 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) { 479 struct intel_gvt_irq_info *info = irq->info[i]; 480 u32 reg_base; 481 482 if (!info->has_upstream_irq) 483 continue; 484 485 reg_base = i915_mmio_reg_offset(info->reg_base); 486 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base)) 487 & vgpu_vreg(vgpu, regbase_to_ier(reg_base)))) 488 update_upstream_irq(vgpu, info); 489 } 490 491 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) 492 & ~GEN8_MASTER_IRQ_CONTROL) 493 inject_virtual_interrupt(vgpu); 494 } 495 496 static void gen8_init_irq( 497 struct intel_gvt_irq *irq) 498 { 499 struct intel_gvt *gvt = irq_to_gvt(irq); 500 501 #define SET_BIT_INFO(s, b, e, i) \ 502 do { \ 503 s->events[e].bit = b; \ 504 s->events[e].info = s->info[i]; \ 505 s->info[i]->bit_to_event[b] = e;\ 506 } while (0) 507 508 #define SET_IRQ_GROUP(s, g, i) \ 509 do { \ 510 s->info[g] = i; \ 511 (i)->group = g; \ 512 set_bit(g, s->irq_info_bitmap); \ 513 } while (0) 514 515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info); 516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info); 517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info); 518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info); 519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info); 520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info); 521 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info); 522 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info); 523 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info); 524 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info); 525 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info); 526 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info); 527 528 /* GEN8 level 2 interrupts. */ 529 530 /* GEN8 interrupt GT0 events */ 531 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 532 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0); 533 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 534 535 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0); 536 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0); 537 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0); 538 539 /* GEN8 interrupt GT1 events */ 540 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1); 541 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1); 542 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1); 543 544 if (HAS_ENGINE(gvt->gt, VCS1)) { 545 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT, 546 INTEL_GVT_IRQ_INFO_GT1); 547 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW, 548 INTEL_GVT_IRQ_INFO_GT1); 549 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH, 550 INTEL_GVT_IRQ_INFO_GT1); 551 } 552 553 /* GEN8 interrupt GT3 events */ 554 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3); 555 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3); 556 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3); 557 558 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 559 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 560 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 561 562 /* GEN8 interrupt DE PORT events */ 563 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT); 564 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT); 565 566 /* GEN8 interrupt DE MISC events */ 567 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC); 568 569 /* PCH events */ 570 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH); 571 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 572 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 573 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 574 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH); 575 576 if (IS_BROADWELL(gvt->gt->i915)) { 577 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH); 578 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH); 579 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH); 580 581 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 582 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 583 584 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 585 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 586 587 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 588 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 589 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) { 590 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT); 591 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT); 592 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT); 593 594 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 595 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 596 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 597 598 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A); 599 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B); 600 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C); 601 } 602 603 /* GEN8 interrupt PCU events */ 604 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU); 605 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU); 606 } 607 608 static const struct intel_gvt_irq_ops gen8_irq_ops = { 609 .init_irq = gen8_init_irq, 610 .check_pending_irq = gen8_check_pending_irq, 611 }; 612 613 /** 614 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU 615 * @vgpu: a vGPU 616 * @event: interrupt event 617 * 618 * This function is used to trigger a virtual interrupt event for vGPU. 619 * The caller provides the event to be triggered, the framework itself 620 * will emulate the IRQ register bit change. 621 * 622 */ 623 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu, 624 enum intel_gvt_event_type event) 625 { 626 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 627 struct intel_gvt *gvt = vgpu->gvt; 628 struct intel_gvt_irq *irq = &gvt->irq; 629 gvt_event_virt_handler_t handler; 630 const struct intel_gvt_irq_ops *ops = gvt->irq.ops; 631 632 handler = get_event_virt_handler(irq, event); 633 drm_WARN_ON(&i915->drm, !handler); 634 635 handler(irq, event, vgpu); 636 637 ops->check_pending_irq(vgpu); 638 } 639 640 static void init_events( 641 struct intel_gvt_irq *irq) 642 { 643 int i; 644 645 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) { 646 irq->events[i].info = NULL; 647 irq->events[i].v_handler = handle_default_event_virt; 648 } 649 } 650 651 /** 652 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem 653 * @gvt: a GVT device 654 * 655 * This function is called at driver loading stage, to initialize the GVT-g IRQ 656 * emulation subsystem. 657 * 658 * Returns: 659 * Zero on success, negative error code if failed. 660 */ 661 int intel_gvt_init_irq(struct intel_gvt *gvt) 662 { 663 struct intel_gvt_irq *irq = &gvt->irq; 664 665 gvt_dbg_core("init irq framework\n"); 666 667 irq->ops = &gen8_irq_ops; 668 irq->irq_map = gen8_irq_map; 669 670 /* common event initialization */ 671 init_events(irq); 672 673 /* gen specific initialization */ 674 irq->ops->init_irq(irq); 675 676 init_irq_map(irq); 677 678 return 0; 679 } 680