xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/interrupt.c (revision 15d90a6a)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *    Zhi Wang <zhi.a.wang@intel.com>
26  *
27  * Contributors:
28  *    Min he <min.he@intel.com>
29  *
30  */
31 
32 #include "i915_drv.h"
33 #include "gvt.h"
34 #include "trace.h"
35 
36 /* common offset among interrupt control registers */
37 #define regbase_to_isr(base)	(base)
38 #define regbase_to_imr(base)	(base + 0x4)
39 #define regbase_to_iir(base)	(base + 0x8)
40 #define regbase_to_ier(base)	(base + 0xC)
41 
42 #define iir_to_regbase(iir)    (iir - 0x8)
43 #define ier_to_regbase(ier)    (ier - 0xC)
44 
45 #define get_event_virt_handler(irq, e)	(irq->events[e].v_handler)
46 #define get_irq_info(irq, e)		(irq->events[e].info)
47 
48 #define irq_to_gvt(irq) \
49 	container_of(irq, struct intel_gvt, irq)
50 
51 static void update_upstream_irq(struct intel_vgpu *vgpu,
52 		struct intel_gvt_irq_info *info);
53 
54 static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
55 	[RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
56 	[RCS_DEBUG] = "Render EU debug from SVG",
57 	[RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
58 	[RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
59 	[RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
60 	[RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
61 	[RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
62 	[RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
63 
64 	[VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
65 	[VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
66 	[VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
67 	[VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
68 	[VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
69 	[VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
70 	[VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
71 	[VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
72 	[VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
73 	[VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
74 
75 	[BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
76 	[BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
77 	[BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
78 	[BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
79 	[BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
80 	[BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
81 
82 	[VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
83 	[VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
84 
85 	[PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
86 	[PIPE_A_CRC_ERR] = "Pipe A CRC error",
87 	[PIPE_A_CRC_DONE] = "Pipe A CRC done",
88 	[PIPE_A_VSYNC] = "Pipe A vsync",
89 	[PIPE_A_LINE_COMPARE] = "Pipe A line compare",
90 	[PIPE_A_ODD_FIELD] = "Pipe A odd field",
91 	[PIPE_A_EVEN_FIELD] = "Pipe A even field",
92 	[PIPE_A_VBLANK] = "Pipe A vblank",
93 	[PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
94 	[PIPE_B_CRC_ERR] = "Pipe B CRC error",
95 	[PIPE_B_CRC_DONE] = "Pipe B CRC done",
96 	[PIPE_B_VSYNC] = "Pipe B vsync",
97 	[PIPE_B_LINE_COMPARE] = "Pipe B line compare",
98 	[PIPE_B_ODD_FIELD] = "Pipe B odd field",
99 	[PIPE_B_EVEN_FIELD] = "Pipe B even field",
100 	[PIPE_B_VBLANK] = "Pipe B vblank",
101 	[PIPE_C_VBLANK] = "Pipe C vblank",
102 	[DPST_PHASE_IN] = "DPST phase in event",
103 	[DPST_HISTOGRAM] = "DPST histogram event",
104 	[GSE] = "GSE",
105 	[DP_A_HOTPLUG] = "DP A Hotplug",
106 	[AUX_CHANNEL_A] = "AUX Channel A",
107 	[PERF_COUNTER] = "Performance counter",
108 	[POISON] = "Poison",
109 	[GTT_FAULT] = "GTT fault",
110 	[PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
111 	[PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
112 	[PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
113 	[SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
114 	[SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
115 	[SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
116 
117 	[PCU_THERMAL] = "PCU Thermal Event",
118 	[PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
119 
120 	[FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
121 	[AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
122 	[AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
123 	[FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
124 	[AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
125 	[AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
126 	[FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
127 	[AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
128 	[AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
129 	[ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
130 	[GMBUS] = "Gmbus",
131 	[SDVO_B_HOTPLUG] = "SDVO B hotplug",
132 	[CRT_HOTPLUG] = "CRT Hotplug",
133 	[DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
134 	[DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
135 	[DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
136 	[AUX_CHANNEL_B] = "AUX Channel B",
137 	[AUX_CHANNEL_C] = "AUX Channel C",
138 	[AUX_CHANNEL_D] = "AUX Channel D",
139 	[AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
140 	[AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
141 	[AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
142 
143 	[INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
144 };
145 
146 static inline struct intel_gvt_irq_info *regbase_to_irq_info(
147 		struct intel_gvt *gvt,
148 		unsigned int reg)
149 {
150 	struct intel_gvt_irq *irq = &gvt->irq;
151 	int i;
152 
153 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
154 		if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
155 			return irq->info[i];
156 	}
157 
158 	return NULL;
159 }
160 
161 /**
162  * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
163  * @vgpu: a vGPU
164  * @reg: register offset written by guest
165  * @p_data: register data written by guest
166  * @bytes: register data length
167  *
168  * This function is used to emulate the generic IMR register bit change
169  * behavior.
170  *
171  * Returns:
172  * Zero on success, negative error code if failed.
173  *
174  */
175 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
176 	unsigned int reg, void *p_data, unsigned int bytes)
177 {
178 	struct intel_gvt *gvt = vgpu->gvt;
179 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
180 	u32 imr = *(u32 *)p_data;
181 
182 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
183 		       (vgpu_vreg(vgpu, reg) ^ imr));
184 
185 	vgpu_vreg(vgpu, reg) = imr;
186 
187 	ops->check_pending_irq(vgpu);
188 
189 	return 0;
190 }
191 
192 /**
193  * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
194  * @vgpu: a vGPU
195  * @reg: register offset written by guest
196  * @p_data: register data written by guest
197  * @bytes: register data length
198  *
199  * This function is used to emulate the master IRQ register on gen8+.
200  *
201  * Returns:
202  * Zero on success, negative error code if failed.
203  *
204  */
205 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
206 	unsigned int reg, void *p_data, unsigned int bytes)
207 {
208 	struct intel_gvt *gvt = vgpu->gvt;
209 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
210 	u32 ier = *(u32 *)p_data;
211 	u32 virtual_ier = vgpu_vreg(vgpu, reg);
212 
213 	trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
214 		       (virtual_ier ^ ier));
215 
216 	/*
217 	 * GEN8_MASTER_IRQ is a special irq register,
218 	 * only bit 31 is allowed to be modified
219 	 * and treated as an IER bit.
220 	 */
221 	ier &= GEN8_MASTER_IRQ_CONTROL;
222 	virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
223 	vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
224 	vgpu_vreg(vgpu, reg) |= ier;
225 
226 	ops->check_pending_irq(vgpu);
227 
228 	return 0;
229 }
230 
231 /**
232  * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
233  * @vgpu: a vGPU
234  * @reg: register offset written by guest
235  * @p_data: register data written by guest
236  * @bytes: register data length
237  *
238  * This function is used to emulate the generic IER register behavior.
239  *
240  * Returns:
241  * Zero on success, negative error code if failed.
242  *
243  */
244 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
245 	unsigned int reg, void *p_data, unsigned int bytes)
246 {
247 	struct intel_gvt *gvt = vgpu->gvt;
248 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
249 	struct intel_gvt_irq_info *info;
250 	u32 ier = *(u32 *)p_data;
251 
252 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
253 		       (vgpu_vreg(vgpu, reg) ^ ier));
254 
255 	vgpu_vreg(vgpu, reg) = ier;
256 
257 	info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
258 	if (WARN_ON(!info))
259 		return -EINVAL;
260 
261 	if (info->has_upstream_irq)
262 		update_upstream_irq(vgpu, info);
263 
264 	ops->check_pending_irq(vgpu);
265 
266 	return 0;
267 }
268 
269 /**
270  * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
271  * @vgpu: a vGPU
272  * @reg: register offset written by guest
273  * @p_data: register data written by guest
274  * @bytes: register data length
275  *
276  * This function is used to emulate the generic IIR register behavior.
277  *
278  * Returns:
279  * Zero on success, negative error code if failed.
280  *
281  */
282 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
283 	void *p_data, unsigned int bytes)
284 {
285 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
286 		iir_to_regbase(reg));
287 	u32 iir = *(u32 *)p_data;
288 
289 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
290 		       (vgpu_vreg(vgpu, reg) ^ iir));
291 
292 	if (WARN_ON(!info))
293 		return -EINVAL;
294 
295 	vgpu_vreg(vgpu, reg) &= ~iir;
296 
297 	if (info->has_upstream_irq)
298 		update_upstream_irq(vgpu, info);
299 	return 0;
300 }
301 
302 static struct intel_gvt_irq_map gen8_irq_map[] = {
303 	{ INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
304 	{ INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
305 	{ INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
306 	{ INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
307 	{ INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
308 	{ INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
309 	{ INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
310 	{ INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
311 	{ INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
312 	{ INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
313 	{ INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
314 	{ INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
315 	{ INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
316 	{ -1, -1, ~0 },
317 };
318 
319 static void update_upstream_irq(struct intel_vgpu *vgpu,
320 		struct intel_gvt_irq_info *info)
321 {
322 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
323 	struct intel_gvt_irq_map *map = irq->irq_map;
324 	struct intel_gvt_irq_info *up_irq_info = NULL;
325 	u32 set_bits = 0;
326 	u32 clear_bits = 0;
327 	int bit;
328 	u32 val = vgpu_vreg(vgpu,
329 			regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
330 		& vgpu_vreg(vgpu,
331 			regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
332 
333 	if (!info->has_upstream_irq)
334 		return;
335 
336 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
337 		if (info->group != map->down_irq_group)
338 			continue;
339 
340 		if (!up_irq_info)
341 			up_irq_info = irq->info[map->up_irq_group];
342 		else
343 			WARN_ON(up_irq_info != irq->info[map->up_irq_group]);
344 
345 		bit = map->up_irq_bit;
346 
347 		if (val & map->down_irq_bitmask)
348 			set_bits |= (1 << bit);
349 		else
350 			clear_bits |= (1 << bit);
351 	}
352 
353 	if (WARN_ON(!up_irq_info))
354 		return;
355 
356 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
357 		u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
358 
359 		vgpu_vreg(vgpu, isr) &= ~clear_bits;
360 		vgpu_vreg(vgpu, isr) |= set_bits;
361 	} else {
362 		u32 iir = regbase_to_iir(
363 			i915_mmio_reg_offset(up_irq_info->reg_base));
364 		u32 imr = regbase_to_imr(
365 			i915_mmio_reg_offset(up_irq_info->reg_base));
366 
367 		vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
368 	}
369 
370 	if (up_irq_info->has_upstream_irq)
371 		update_upstream_irq(vgpu, up_irq_info);
372 }
373 
374 static void init_irq_map(struct intel_gvt_irq *irq)
375 {
376 	struct intel_gvt_irq_map *map;
377 	struct intel_gvt_irq_info *up_info, *down_info;
378 	int up_bit;
379 
380 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
381 		up_info = irq->info[map->up_irq_group];
382 		up_bit = map->up_irq_bit;
383 		down_info = irq->info[map->down_irq_group];
384 
385 		set_bit(up_bit, up_info->downstream_irq_bitmap);
386 		down_info->has_upstream_irq = true;
387 
388 		gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
389 			up_info->group, up_bit,
390 			down_info->group, map->down_irq_bitmask);
391 	}
392 }
393 
394 /* =======================vEvent injection===================== */
395 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
396 {
397 	return intel_gvt_hypervisor_inject_msi(vgpu);
398 }
399 
400 static void propagate_event(struct intel_gvt_irq *irq,
401 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
402 {
403 	struct intel_gvt_irq_info *info;
404 	unsigned int reg_base;
405 	int bit;
406 
407 	info = get_irq_info(irq, event);
408 	if (WARN_ON(!info))
409 		return;
410 
411 	reg_base = i915_mmio_reg_offset(info->reg_base);
412 	bit = irq->events[event].bit;
413 
414 	if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
415 					regbase_to_imr(reg_base)))) {
416 		trace_propagate_event(vgpu->id, irq_name[event], bit);
417 		set_bit(bit, (void *)&vgpu_vreg(vgpu,
418 					regbase_to_iir(reg_base)));
419 	}
420 }
421 
422 /* =======================vEvent Handlers===================== */
423 static void handle_default_event_virt(struct intel_gvt_irq *irq,
424 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
425 {
426 	if (!vgpu->irq.irq_warn_once[event]) {
427 		gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
428 			vgpu->id, event, irq_name[event]);
429 		vgpu->irq.irq_warn_once[event] = true;
430 	}
431 	propagate_event(irq, event, vgpu);
432 }
433 
434 /* =====================GEN specific logic======================= */
435 /* GEN8 interrupt routines. */
436 
437 #define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
438 static struct intel_gvt_irq_info gen8_##regname##_info = { \
439 	.name = #regname"-IRQ", \
440 	.reg_base = (regbase), \
441 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
442 		INTEL_GVT_EVENT_RESERVED}, \
443 }
444 
445 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
446 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
447 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
448 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
449 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
451 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
452 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
453 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
454 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
456 
457 static struct intel_gvt_irq_info gvt_base_pch_info = {
458 	.name = "PCH-IRQ",
459 	.reg_base = SDEISR,
460 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
461 		INTEL_GVT_EVENT_RESERVED},
462 };
463 
464 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
465 {
466 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;
467 	int i;
468 
469 	if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
470 				GEN8_MASTER_IRQ_CONTROL))
471 		return;
472 
473 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
474 		struct intel_gvt_irq_info *info = irq->info[i];
475 		u32 reg_base;
476 
477 		if (!info->has_upstream_irq)
478 			continue;
479 
480 		reg_base = i915_mmio_reg_offset(info->reg_base);
481 		if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
482 				& vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
483 			update_upstream_irq(vgpu, info);
484 	}
485 
486 	if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
487 			& ~GEN8_MASTER_IRQ_CONTROL)
488 		inject_virtual_interrupt(vgpu);
489 }
490 
491 static void gen8_init_irq(
492 		struct intel_gvt_irq *irq)
493 {
494 	struct intel_gvt *gvt = irq_to_gvt(irq);
495 
496 #define SET_BIT_INFO(s, b, e, i)		\
497 	do {					\
498 		s->events[e].bit = b;		\
499 		s->events[e].info = s->info[i];	\
500 		s->info[i]->bit_to_event[b] = e;\
501 	} while (0)
502 
503 #define SET_IRQ_GROUP(s, g, i) \
504 	do { \
505 		s->info[g] = i; \
506 		(i)->group = g; \
507 		set_bit(g, s->irq_info_bitmap); \
508 	} while (0)
509 
510 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
511 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
512 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
513 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
514 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
515 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
516 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
517 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
518 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
519 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
520 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
521 	SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
522 
523 	/* GEN8 level 2 interrupts. */
524 
525 	/* GEN8 interrupt GT0 events */
526 	SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
527 	SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
528 	SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
529 
530 	SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
531 	SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
532 	SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
533 
534 	/* GEN8 interrupt GT1 events */
535 	SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
536 	SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
537 	SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
538 
539 	if (HAS_BSD2(gvt->dev_priv)) {
540 		SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
541 			INTEL_GVT_IRQ_INFO_GT1);
542 		SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
543 			INTEL_GVT_IRQ_INFO_GT1);
544 		SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
545 			INTEL_GVT_IRQ_INFO_GT1);
546 	}
547 
548 	/* GEN8 interrupt GT3 events */
549 	SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
550 	SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
551 	SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
552 
553 	SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
554 	SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
555 	SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
556 
557 	/* GEN8 interrupt DE PORT events */
558 	SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
559 	SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
560 
561 	/* GEN8 interrupt DE MISC events */
562 	SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
563 
564 	/* PCH events */
565 	SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
566 	SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
567 	SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
568 	SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
569 	SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
570 
571 	if (IS_BROADWELL(gvt->dev_priv)) {
572 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
573 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
574 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
575 
576 		SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
577 		SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
578 
579 		SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
580 		SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
581 
582 		SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
583 		SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
584 	} else if (IS_SKYLAKE(gvt->dev_priv)
585 			|| IS_KABYLAKE(gvt->dev_priv)
586 			|| IS_BROXTON(gvt->dev_priv)) {
587 		SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
588 		SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
589 		SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
590 
591 		SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
592 		SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
593 		SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
594 
595 		SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
596 		SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
597 		SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
598 	}
599 
600 	/* GEN8 interrupt PCU events */
601 	SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
602 	SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
603 }
604 
605 static struct intel_gvt_irq_ops gen8_irq_ops = {
606 	.init_irq = gen8_init_irq,
607 	.check_pending_irq = gen8_check_pending_irq,
608 };
609 
610 /**
611  * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
612  * @vgpu: a vGPU
613  * @event: interrupt event
614  *
615  * This function is used to trigger a virtual interrupt event for vGPU.
616  * The caller provides the event to be triggered, the framework itself
617  * will emulate the IRQ register bit change.
618  *
619  */
620 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
621 	enum intel_gvt_event_type event)
622 {
623 	struct intel_gvt *gvt = vgpu->gvt;
624 	struct intel_gvt_irq *irq = &gvt->irq;
625 	gvt_event_virt_handler_t handler;
626 	struct intel_gvt_irq_ops *ops = gvt->irq.ops;
627 
628 	handler = get_event_virt_handler(irq, event);
629 	WARN_ON(!handler);
630 
631 	handler(irq, event, vgpu);
632 
633 	ops->check_pending_irq(vgpu);
634 }
635 
636 static void init_events(
637 	struct intel_gvt_irq *irq)
638 {
639 	int i;
640 
641 	for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
642 		irq->events[i].info = NULL;
643 		irq->events[i].v_handler = handle_default_event_virt;
644 	}
645 }
646 
647 static enum hrtimer_restart vblank_timer_fn(struct hrtimer *data)
648 {
649 	struct intel_gvt_vblank_timer *vblank_timer;
650 	struct intel_gvt_irq *irq;
651 	struct intel_gvt *gvt;
652 
653 	vblank_timer = container_of(data, struct intel_gvt_vblank_timer, timer);
654 	irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
655 	gvt = container_of(irq, struct intel_gvt, irq);
656 
657 	intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EMULATE_VBLANK);
658 	hrtimer_add_expires_ns(&vblank_timer->timer, vblank_timer->period);
659 	return HRTIMER_RESTART;
660 }
661 
662 /**
663  * intel_gvt_clean_irq - clean up GVT-g IRQ emulation subsystem
664  * @gvt: a GVT device
665  *
666  * This function is called at driver unloading stage, to clean up GVT-g IRQ
667  * emulation subsystem.
668  *
669  */
670 void intel_gvt_clean_irq(struct intel_gvt *gvt)
671 {
672 	struct intel_gvt_irq *irq = &gvt->irq;
673 
674 	hrtimer_cancel(&irq->vblank_timer.timer);
675 }
676 
677 #define VBLNAK_TIMER_PERIOD 16000000
678 
679 /**
680  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
681  * @gvt: a GVT device
682  *
683  * This function is called at driver loading stage, to initialize the GVT-g IRQ
684  * emulation subsystem.
685  *
686  * Returns:
687  * Zero on success, negative error code if failed.
688  */
689 int intel_gvt_init_irq(struct intel_gvt *gvt)
690 {
691 	struct intel_gvt_irq *irq = &gvt->irq;
692 	struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
693 
694 	gvt_dbg_core("init irq framework\n");
695 
696 	irq->ops = &gen8_irq_ops;
697 	irq->irq_map = gen8_irq_map;
698 
699 	/* common event initialization */
700 	init_events(irq);
701 
702 	/* gen specific initialization */
703 	irq->ops->init_irq(irq);
704 
705 	init_irq_map(irq);
706 
707 	hrtimer_init(&vblank_timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
708 	vblank_timer->timer.function = vblank_timer_fn;
709 	vblank_timer->period = VBLNAK_TIMER_PERIOD;
710 
711 	return 0;
712 }
713