1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 59 return 0; 60 } 61 62 bool intel_gvt_match_device(struct intel_gvt *gvt, 63 unsigned long device) 64 { 65 return intel_gvt_get_device_type(gvt) & device; 66 } 67 68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 69 void *p_data, unsigned int bytes) 70 { 71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 72 } 73 74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 75 void *p_data, unsigned int bytes) 76 { 77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 78 } 79 80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 81 unsigned int offset) 82 { 83 struct intel_gvt_mmio_info *e; 84 85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 86 if (e->offset == offset) 87 return e; 88 } 89 return NULL; 90 } 91 92 static int new_mmio_info(struct intel_gvt *gvt, 93 u32 offset, u8 flags, u32 size, 94 u32 addr_mask, u32 ro_mask, u32 device, 95 gvt_mmio_func read, gvt_mmio_func write) 96 { 97 struct intel_gvt_mmio_info *info, *p; 98 u32 start, end, i; 99 100 if (!intel_gvt_match_device(gvt, device)) 101 return 0; 102 103 if (WARN_ON(!IS_ALIGNED(offset, 4))) 104 return -EINVAL; 105 106 start = offset; 107 end = offset + size; 108 109 for (i = start; i < end; i += 4) { 110 info = kzalloc(sizeof(*info), GFP_KERNEL); 111 if (!info) 112 return -ENOMEM; 113 114 info->offset = i; 115 p = find_mmio_info(gvt, info->offset); 116 if (p) { 117 WARN(1, "dup mmio definition offset %x\n", 118 info->offset); 119 kfree(info); 120 121 /* We return -EEXIST here to make GVT-g load fail. 122 * So duplicated MMIO can be found as soon as 123 * possible. 124 */ 125 return -EEXIST; 126 } 127 128 info->ro_mask = ro_mask; 129 info->device = device; 130 info->read = read ? read : intel_vgpu_default_mmio_read; 131 info->write = write ? write : intel_vgpu_default_mmio_write; 132 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 133 INIT_HLIST_NODE(&info->node); 134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 135 gvt->mmio.num_tracked_mmio++; 136 } 137 return 0; 138 } 139 140 /** 141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 142 * @gvt: a GVT device 143 * @offset: register offset 144 * 145 * Returns: 146 * Ring ID on success, negative error code if failed. 147 */ 148 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 149 unsigned int offset) 150 { 151 enum intel_engine_id id; 152 struct intel_engine_cs *engine; 153 154 offset &= ~GENMASK(11, 0); 155 for_each_engine(engine, gvt->dev_priv, id) { 156 if (engine->mmio_base == offset) 157 return id; 158 } 159 return -ENODEV; 160 } 161 162 #define offset_to_fence_num(offset) \ 163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 164 165 #define fence_num_to_offset(num) \ 166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 167 168 169 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 170 { 171 switch (reason) { 172 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 173 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 174 break; 175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 176 pr_err("Graphics resource is not enough for the guest\n"); 177 case GVT_FAILSAFE_GUEST_ERR: 178 pr_err("GVT Internal error for the guest\n"); 179 default: 180 break; 181 } 182 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 183 vgpu->failsafe = true; 184 } 185 186 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 187 unsigned int fence_num, void *p_data, unsigned int bytes) 188 { 189 if (fence_num >= vgpu_fence_sz(vgpu)) { 190 191 /* When guest access oob fence regs without access 192 * pv_info first, we treat guest not supporting GVT, 193 * and we will let vgpu enter failsafe mode. 194 */ 195 if (!vgpu->pv_notified) 196 enter_failsafe_mode(vgpu, 197 GVT_FAILSAFE_UNSUPPORTED_GUEST); 198 199 if (!vgpu->mmio.disable_warn_untrack) { 200 gvt_vgpu_err("found oob fence register access\n"); 201 gvt_vgpu_err("total fence %d, access fence %d\n", 202 vgpu_fence_sz(vgpu), fence_num); 203 } 204 memset(p_data, 0, bytes); 205 return -EINVAL; 206 } 207 return 0; 208 } 209 210 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 211 void *p_data, unsigned int bytes) 212 { 213 int ret; 214 215 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 216 p_data, bytes); 217 if (ret) 218 return ret; 219 read_vreg(vgpu, off, p_data, bytes); 220 return 0; 221 } 222 223 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 224 void *p_data, unsigned int bytes) 225 { 226 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 227 unsigned int fence_num = offset_to_fence_num(off); 228 int ret; 229 230 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 231 if (ret) 232 return ret; 233 write_vreg(vgpu, off, p_data, bytes); 234 235 mmio_hw_access_pre(dev_priv); 236 intel_vgpu_write_fence(vgpu, fence_num, 237 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 238 mmio_hw_access_post(dev_priv); 239 return 0; 240 } 241 242 #define CALC_MODE_MASK_REG(old, new) \ 243 (((new) & GENMASK(31, 16)) \ 244 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 245 | ((new) & ((new) >> 16)))) 246 247 static int mul_force_wake_write(struct intel_vgpu *vgpu, 248 unsigned int offset, void *p_data, unsigned int bytes) 249 { 250 u32 old, new; 251 uint32_t ack_reg_offset; 252 253 old = vgpu_vreg(vgpu, offset); 254 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 255 256 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 257 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 258 switch (offset) { 259 case FORCEWAKE_RENDER_GEN9_REG: 260 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 261 break; 262 case FORCEWAKE_BLITTER_GEN9_REG: 263 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 264 break; 265 case FORCEWAKE_MEDIA_GEN9_REG: 266 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 267 break; 268 default: 269 /*should not hit here*/ 270 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 271 return -EINVAL; 272 } 273 } else { 274 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 275 } 276 277 vgpu_vreg(vgpu, offset) = new; 278 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 279 return 0; 280 } 281 282 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 283 void *p_data, unsigned int bytes) 284 { 285 unsigned int engine_mask = 0; 286 u32 data; 287 288 write_vreg(vgpu, offset, p_data, bytes); 289 data = vgpu_vreg(vgpu, offset); 290 291 if (data & GEN6_GRDOM_FULL) { 292 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 293 engine_mask = ALL_ENGINES; 294 } else { 295 if (data & GEN6_GRDOM_RENDER) { 296 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 297 engine_mask |= (1 << RCS); 298 } 299 if (data & GEN6_GRDOM_MEDIA) { 300 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 301 engine_mask |= (1 << VCS); 302 } 303 if (data & GEN6_GRDOM_BLT) { 304 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 305 engine_mask |= (1 << BCS); 306 } 307 if (data & GEN6_GRDOM_VECS) { 308 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 309 engine_mask |= (1 << VECS); 310 } 311 if (data & GEN8_GRDOM_MEDIA2) { 312 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 313 if (HAS_BSD2(vgpu->gvt->dev_priv)) 314 engine_mask |= (1 << VCS2); 315 } 316 } 317 318 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 319 320 /* sw will wait for the device to ack the reset request */ 321 vgpu_vreg(vgpu, offset) = 0; 322 323 return 0; 324 } 325 326 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 327 void *p_data, unsigned int bytes) 328 { 329 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 330 } 331 332 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 333 void *p_data, unsigned int bytes) 334 { 335 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 336 } 337 338 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 339 unsigned int offset, void *p_data, unsigned int bytes) 340 { 341 write_vreg(vgpu, offset, p_data, bytes); 342 343 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 344 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON; 345 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 346 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 347 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 348 349 } else 350 vgpu_vreg(vgpu, PCH_PP_STATUS) &= 351 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 352 | PP_CYCLE_DELAY_ACTIVE); 353 return 0; 354 } 355 356 static int transconf_mmio_write(struct intel_vgpu *vgpu, 357 unsigned int offset, void *p_data, unsigned int bytes) 358 { 359 write_vreg(vgpu, offset, p_data, bytes); 360 361 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 362 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 363 else 364 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 365 return 0; 366 } 367 368 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 369 void *p_data, unsigned int bytes) 370 { 371 write_vreg(vgpu, offset, p_data, bytes); 372 373 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 374 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 375 else 376 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 377 378 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 379 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 380 else 381 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 382 383 return 0; 384 } 385 386 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 387 void *p_data, unsigned int bytes) 388 { 389 switch (offset) { 390 case 0xe651c: 391 case 0xe661c: 392 case 0xe671c: 393 case 0xe681c: 394 vgpu_vreg(vgpu, offset) = 1 << 17; 395 break; 396 case 0xe6c04: 397 vgpu_vreg(vgpu, offset) = 0x3; 398 break; 399 case 0xe6e1c: 400 vgpu_vreg(vgpu, offset) = 0x2f << 16; 401 break; 402 default: 403 return -EINVAL; 404 } 405 406 read_vreg(vgpu, offset, p_data, bytes); 407 return 0; 408 } 409 410 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 411 void *p_data, unsigned int bytes) 412 { 413 u32 data; 414 415 write_vreg(vgpu, offset, p_data, bytes); 416 data = vgpu_vreg(vgpu, offset); 417 418 if (data & PIPECONF_ENABLE) 419 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 420 else 421 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 422 intel_gvt_check_vblank_emulation(vgpu->gvt); 423 return 0; 424 } 425 426 /* ascendingly sorted */ 427 static i915_reg_t force_nonpriv_white_list[] = { 428 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 429 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 430 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 431 _MMIO(0x2690), 432 _MMIO(0x2694), 433 _MMIO(0x2698), 434 _MMIO(0x4de0), 435 _MMIO(0x4de4), 436 _MMIO(0x4dfc), 437 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 438 _MMIO(0x7014), 439 HDC_CHICKEN0,//_MMIO(0x7300) 440 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 441 _MMIO(0x7700), 442 _MMIO(0x7704), 443 _MMIO(0x7708), 444 _MMIO(0x770c), 445 _MMIO(0xb110), 446 GEN8_L3SQCREG4,//_MMIO(0xb118) 447 _MMIO(0xe100), 448 _MMIO(0xe18c), 449 _MMIO(0xe48c), 450 _MMIO(0xe5f4), 451 }; 452 453 /* a simple bsearch */ 454 static inline bool in_whitelist(unsigned int reg) 455 { 456 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 457 i915_reg_t *array = force_nonpriv_white_list; 458 459 while (left < right) { 460 int mid = (left + right)/2; 461 462 if (reg > array[mid].reg) 463 left = mid + 1; 464 else if (reg < array[mid].reg) 465 right = mid; 466 else 467 return true; 468 } 469 return false; 470 } 471 472 static int force_nonpriv_write(struct intel_vgpu *vgpu, 473 unsigned int offset, void *p_data, unsigned int bytes) 474 { 475 u32 reg_nonpriv = *(u32 *)p_data; 476 int ret = -EINVAL; 477 478 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { 479 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 480 vgpu->id, offset, bytes); 481 return ret; 482 } 483 484 if (in_whitelist(reg_nonpriv)) { 485 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 486 bytes); 487 } else { 488 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", 489 vgpu->id, reg_nonpriv); 490 } 491 return ret; 492 } 493 494 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 495 void *p_data, unsigned int bytes) 496 { 497 write_vreg(vgpu, offset, p_data, bytes); 498 499 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 500 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 501 } else { 502 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 503 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 504 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) 505 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 506 } 507 return 0; 508 } 509 510 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 511 unsigned int offset, void *p_data, unsigned int bytes) 512 { 513 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 514 return 0; 515 } 516 517 #define FDI_LINK_TRAIN_PATTERN1 0 518 #define FDI_LINK_TRAIN_PATTERN2 1 519 520 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 521 { 522 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E)); 523 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 524 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E)); 525 526 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 527 (rx_ctl & FDI_RX_ENABLE) && 528 (rx_ctl & FDI_AUTO_TRAINING) && 529 (tx_ctl & DP_TP_CTL_ENABLE) && 530 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 531 return 1; 532 else 533 return 0; 534 } 535 536 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 537 enum pipe pipe, unsigned int train_pattern) 538 { 539 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 540 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 541 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 542 unsigned int fdi_iir_check_bits; 543 544 fdi_rx_imr = FDI_RX_IMR(pipe); 545 fdi_tx_ctl = FDI_TX_CTL(pipe); 546 fdi_rx_ctl = FDI_RX_CTL(pipe); 547 548 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 549 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 550 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 551 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 552 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 553 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 554 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 555 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 556 } else { 557 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 558 return -EINVAL; 559 } 560 561 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 562 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 563 564 /* If imr bit has been masked */ 565 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 566 return 0; 567 568 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 569 == fdi_tx_check_bits) 570 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 571 == fdi_rx_check_bits)) 572 return 1; 573 else 574 return 0; 575 } 576 577 #define INVALID_INDEX (~0U) 578 579 static unsigned int calc_index(unsigned int offset, unsigned int start, 580 unsigned int next, unsigned int end, i915_reg_t i915_end) 581 { 582 unsigned int range = next - start; 583 584 if (!end) 585 end = i915_mmio_reg_offset(i915_end); 586 if (offset < start || offset > end) 587 return INVALID_INDEX; 588 offset -= start; 589 return offset / range; 590 } 591 592 #define FDI_RX_CTL_TO_PIPE(offset) \ 593 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 594 595 #define FDI_TX_CTL_TO_PIPE(offset) \ 596 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 597 598 #define FDI_RX_IMR_TO_PIPE(offset) \ 599 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 600 601 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 602 unsigned int offset, void *p_data, unsigned int bytes) 603 { 604 i915_reg_t fdi_rx_iir; 605 unsigned int index; 606 int ret; 607 608 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 609 index = FDI_RX_CTL_TO_PIPE(offset); 610 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 611 index = FDI_TX_CTL_TO_PIPE(offset); 612 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 613 index = FDI_RX_IMR_TO_PIPE(offset); 614 else { 615 gvt_vgpu_err("Unsupport registers %x\n", offset); 616 return -EINVAL; 617 } 618 619 write_vreg(vgpu, offset, p_data, bytes); 620 621 fdi_rx_iir = FDI_RX_IIR(index); 622 623 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 624 if (ret < 0) 625 return ret; 626 if (ret) 627 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 628 629 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 630 if (ret < 0) 631 return ret; 632 if (ret) 633 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 634 635 if (offset == _FDI_RXA_CTL) 636 if (fdi_auto_training_started(vgpu)) 637 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |= 638 DP_TP_STATUS_AUTOTRAIN_DONE; 639 return 0; 640 } 641 642 #define DP_TP_CTL_TO_PORT(offset) \ 643 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 644 645 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 646 void *p_data, unsigned int bytes) 647 { 648 i915_reg_t status_reg; 649 unsigned int index; 650 u32 data; 651 652 write_vreg(vgpu, offset, p_data, bytes); 653 654 index = DP_TP_CTL_TO_PORT(offset); 655 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 656 if (data == 0x2) { 657 status_reg = DP_TP_STATUS(index); 658 vgpu_vreg(vgpu, status_reg) |= (1 << 25); 659 } 660 return 0; 661 } 662 663 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 664 unsigned int offset, void *p_data, unsigned int bytes) 665 { 666 u32 reg_val; 667 u32 sticky_mask; 668 669 reg_val = *((u32 *)p_data); 670 sticky_mask = GENMASK(27, 26) | (1 << 24); 671 672 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 673 (vgpu_vreg(vgpu, offset) & sticky_mask); 674 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 675 return 0; 676 } 677 678 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 679 unsigned int offset, void *p_data, unsigned int bytes) 680 { 681 u32 data; 682 683 write_vreg(vgpu, offset, p_data, bytes); 684 data = vgpu_vreg(vgpu, offset); 685 686 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 687 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 688 return 0; 689 } 690 691 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 692 unsigned int offset, void *p_data, unsigned int bytes) 693 { 694 u32 data; 695 696 write_vreg(vgpu, offset, p_data, bytes); 697 data = vgpu_vreg(vgpu, offset); 698 699 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 700 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 701 else 702 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 703 return 0; 704 } 705 706 #define DSPSURF_TO_PIPE(offset) \ 707 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 708 709 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 710 void *p_data, unsigned int bytes) 711 { 712 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 713 unsigned int index = DSPSURF_TO_PIPE(offset); 714 i915_reg_t surflive_reg = DSPSURFLIVE(index); 715 int flip_event[] = { 716 [PIPE_A] = PRIMARY_A_FLIP_DONE, 717 [PIPE_B] = PRIMARY_B_FLIP_DONE, 718 [PIPE_C] = PRIMARY_C_FLIP_DONE, 719 }; 720 721 write_vreg(vgpu, offset, p_data, bytes); 722 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 723 724 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 725 return 0; 726 } 727 728 #define SPRSURF_TO_PIPE(offset) \ 729 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 730 731 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 732 void *p_data, unsigned int bytes) 733 { 734 unsigned int index = SPRSURF_TO_PIPE(offset); 735 i915_reg_t surflive_reg = SPRSURFLIVE(index); 736 int flip_event[] = { 737 [PIPE_A] = SPRITE_A_FLIP_DONE, 738 [PIPE_B] = SPRITE_B_FLIP_DONE, 739 [PIPE_C] = SPRITE_C_FLIP_DONE, 740 }; 741 742 write_vreg(vgpu, offset, p_data, bytes); 743 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 744 745 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 746 return 0; 747 } 748 749 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 750 unsigned int reg) 751 { 752 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 753 enum intel_gvt_event_type event; 754 755 if (reg == _DPA_AUX_CH_CTL) 756 event = AUX_CHANNEL_A; 757 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 758 event = AUX_CHANNEL_B; 759 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 760 event = AUX_CHANNEL_C; 761 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 762 event = AUX_CHANNEL_D; 763 else { 764 WARN_ON(true); 765 return -EINVAL; 766 } 767 768 intel_vgpu_trigger_virtual_event(vgpu, event); 769 return 0; 770 } 771 772 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 773 unsigned int reg, int len, bool data_valid) 774 { 775 /* mark transaction done */ 776 value |= DP_AUX_CH_CTL_DONE; 777 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 778 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 779 780 if (data_valid) 781 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 782 else 783 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 784 785 /* message size */ 786 value &= ~(0xf << 20); 787 value |= (len << 20); 788 vgpu_vreg(vgpu, reg) = value; 789 790 if (value & DP_AUX_CH_CTL_INTERRUPT) 791 return trigger_aux_channel_interrupt(vgpu, reg); 792 return 0; 793 } 794 795 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 796 uint8_t t) 797 { 798 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 799 /* training pattern 1 for CR */ 800 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 801 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 802 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 803 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 804 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 805 DPCD_TRAINING_PATTERN_2) { 806 /* training pattern 2 for EQ */ 807 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 808 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 809 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 810 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 811 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 812 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 813 /* set INTERLANE_ALIGN_DONE */ 814 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 815 DPCD_INTERLANE_ALIGN_DONE; 816 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 817 DPCD_LINK_TRAINING_DISABLED) { 818 /* finish link training */ 819 /* set sink status as synchronized */ 820 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 821 } 822 } 823 824 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 825 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 826 827 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 828 829 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 830 831 #define dpy_is_valid_port(port) \ 832 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 833 834 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 835 unsigned int offset, void *p_data, unsigned int bytes) 836 { 837 struct intel_vgpu_display *display = &vgpu->display; 838 int msg, addr, ctrl, op, len; 839 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 840 struct intel_vgpu_dpcd_data *dpcd = NULL; 841 struct intel_vgpu_port *port = NULL; 842 u32 data; 843 844 if (!dpy_is_valid_port(port_index)) { 845 gvt_vgpu_err("Unsupported DP port access!\n"); 846 return 0; 847 } 848 849 write_vreg(vgpu, offset, p_data, bytes); 850 data = vgpu_vreg(vgpu, offset); 851 852 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 853 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 854 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 855 /* SKL DPB/C/D aux ctl register changed */ 856 return 0; 857 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 858 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 859 /* write to the data registers */ 860 return 0; 861 } 862 863 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 864 /* just want to clear the sticky bits */ 865 vgpu_vreg(vgpu, offset) = 0; 866 return 0; 867 } 868 869 port = &display->ports[port_index]; 870 dpcd = port->dpcd; 871 872 /* read out message from DATA1 register */ 873 msg = vgpu_vreg(vgpu, offset + 4); 874 addr = (msg >> 8) & 0xffff; 875 ctrl = (msg >> 24) & 0xff; 876 len = msg & 0xff; 877 op = ctrl >> 4; 878 879 if (op == GVT_AUX_NATIVE_WRITE) { 880 int t; 881 uint8_t buf[16]; 882 883 if ((addr + len + 1) >= DPCD_SIZE) { 884 /* 885 * Write request exceeds what we supported, 886 * DCPD spec: When a Source Device is writing a DPCD 887 * address not supported by the Sink Device, the Sink 888 * Device shall reply with AUX NACK and “M” equal to 889 * zero. 890 */ 891 892 /* NAK the write */ 893 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 894 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 895 return 0; 896 } 897 898 /* 899 * Write request format: (command + address) occupies 900 * 3 bytes, followed by (len + 1) bytes of data. 901 */ 902 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 903 return -EINVAL; 904 905 /* unpack data from vreg to buf */ 906 for (t = 0; t < 4; t++) { 907 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 908 909 buf[t * 4] = (r >> 24) & 0xff; 910 buf[t * 4 + 1] = (r >> 16) & 0xff; 911 buf[t * 4 + 2] = (r >> 8) & 0xff; 912 buf[t * 4 + 3] = r & 0xff; 913 } 914 915 /* write to virtual DPCD */ 916 if (dpcd && dpcd->data_valid) { 917 for (t = 0; t <= len; t++) { 918 int p = addr + t; 919 920 dpcd->data[p] = buf[t]; 921 /* check for link training */ 922 if (p == DPCD_TRAINING_PATTERN_SET) 923 dp_aux_ch_ctl_link_training(dpcd, 924 buf[t]); 925 } 926 } 927 928 /* ACK the write */ 929 vgpu_vreg(vgpu, offset + 4) = 0; 930 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 931 dpcd && dpcd->data_valid); 932 return 0; 933 } 934 935 if (op == GVT_AUX_NATIVE_READ) { 936 int idx, i, ret = 0; 937 938 if ((addr + len + 1) >= DPCD_SIZE) { 939 /* 940 * read request exceeds what we supported 941 * DPCD spec: A Sink Device receiving a Native AUX CH 942 * read request for an unsupported DPCD address must 943 * reply with an AUX ACK and read data set equal to 944 * zero instead of replying with AUX NACK. 945 */ 946 947 /* ACK the READ*/ 948 vgpu_vreg(vgpu, offset + 4) = 0; 949 vgpu_vreg(vgpu, offset + 8) = 0; 950 vgpu_vreg(vgpu, offset + 12) = 0; 951 vgpu_vreg(vgpu, offset + 16) = 0; 952 vgpu_vreg(vgpu, offset + 20) = 0; 953 954 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 955 true); 956 return 0; 957 } 958 959 for (idx = 1; idx <= 5; idx++) { 960 /* clear the data registers */ 961 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 962 } 963 964 /* 965 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 966 */ 967 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 968 return -EINVAL; 969 970 /* read from virtual DPCD to vreg */ 971 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 972 if (dpcd && dpcd->data_valid) { 973 for (i = 1; i <= (len + 1); i++) { 974 int t; 975 976 t = dpcd->data[addr + i - 1]; 977 t <<= (24 - 8 * (i % 4)); 978 ret |= t; 979 980 if ((i % 4 == 3) || (i == (len + 1))) { 981 vgpu_vreg(vgpu, offset + 982 (i / 4 + 1) * 4) = ret; 983 ret = 0; 984 } 985 } 986 } 987 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 988 dpcd && dpcd->data_valid); 989 return 0; 990 } 991 992 /* i2c transaction starts */ 993 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 994 995 if (data & DP_AUX_CH_CTL_INTERRUPT) 996 trigger_aux_channel_interrupt(vgpu, offset); 997 return 0; 998 } 999 1000 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1001 void *p_data, unsigned int bytes) 1002 { 1003 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1004 write_vreg(vgpu, offset, p_data, bytes); 1005 return 0; 1006 } 1007 1008 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1009 void *p_data, unsigned int bytes) 1010 { 1011 bool vga_disable; 1012 1013 write_vreg(vgpu, offset, p_data, bytes); 1014 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1015 1016 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1017 vga_disable ? "Disable" : "Enable"); 1018 return 0; 1019 } 1020 1021 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1022 unsigned int sbi_offset) 1023 { 1024 struct intel_vgpu_display *display = &vgpu->display; 1025 int num = display->sbi.number; 1026 int i; 1027 1028 for (i = 0; i < num; ++i) 1029 if (display->sbi.registers[i].offset == sbi_offset) 1030 break; 1031 1032 if (i == num) 1033 return 0; 1034 1035 return display->sbi.registers[i].value; 1036 } 1037 1038 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1039 unsigned int offset, u32 value) 1040 { 1041 struct intel_vgpu_display *display = &vgpu->display; 1042 int num = display->sbi.number; 1043 int i; 1044 1045 for (i = 0; i < num; ++i) { 1046 if (display->sbi.registers[i].offset == offset) 1047 break; 1048 } 1049 1050 if (i == num) { 1051 if (num == SBI_REG_MAX) { 1052 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1053 return; 1054 } 1055 display->sbi.number++; 1056 } 1057 1058 display->sbi.registers[i].offset = offset; 1059 display->sbi.registers[i].value = value; 1060 } 1061 1062 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1063 void *p_data, unsigned int bytes) 1064 { 1065 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1066 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1067 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1068 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1069 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1070 sbi_offset); 1071 } 1072 read_vreg(vgpu, offset, p_data, bytes); 1073 return 0; 1074 } 1075 1076 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1077 void *p_data, unsigned int bytes) 1078 { 1079 u32 data; 1080 1081 write_vreg(vgpu, offset, p_data, bytes); 1082 data = vgpu_vreg(vgpu, offset); 1083 1084 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1085 data |= SBI_READY; 1086 1087 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1088 data |= SBI_RESPONSE_SUCCESS; 1089 1090 vgpu_vreg(vgpu, offset) = data; 1091 1092 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1093 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1094 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) & 1095 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1096 1097 write_virtual_sbi_register(vgpu, sbi_offset, 1098 vgpu_vreg(vgpu, SBI_DATA)); 1099 } 1100 return 0; 1101 } 1102 1103 #define _vgtif_reg(x) \ 1104 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1105 1106 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1107 void *p_data, unsigned int bytes) 1108 { 1109 bool invalid_read = false; 1110 1111 read_vreg(vgpu, offset, p_data, bytes); 1112 1113 switch (offset) { 1114 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1115 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1116 invalid_read = true; 1117 break; 1118 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1119 _vgtif_reg(avail_rs.fence_num): 1120 if (offset + bytes > 1121 _vgtif_reg(avail_rs.fence_num) + 4) 1122 invalid_read = true; 1123 break; 1124 case 0x78010: /* vgt_caps */ 1125 case 0x7881c: 1126 break; 1127 default: 1128 invalid_read = true; 1129 break; 1130 } 1131 if (invalid_read) 1132 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1133 offset, bytes, *(u32 *)p_data); 1134 vgpu->pv_notified = true; 1135 return 0; 1136 } 1137 1138 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1139 { 1140 int ret = 0; 1141 1142 switch (notification) { 1143 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1144 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3); 1145 break; 1146 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1147 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3); 1148 break; 1149 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1150 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4); 1151 break; 1152 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1153 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4); 1154 break; 1155 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1156 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1157 case 1: /* Remove this in guest driver. */ 1158 break; 1159 default: 1160 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1161 } 1162 return ret; 1163 } 1164 1165 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1166 { 1167 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1168 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1169 char *env[3] = {NULL, NULL, NULL}; 1170 char vmid_str[20]; 1171 char display_ready_str[20]; 1172 1173 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1174 env[0] = display_ready_str; 1175 1176 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1177 env[1] = vmid_str; 1178 1179 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1180 } 1181 1182 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1183 void *p_data, unsigned int bytes) 1184 { 1185 u32 data; 1186 int ret; 1187 1188 write_vreg(vgpu, offset, p_data, bytes); 1189 data = vgpu_vreg(vgpu, offset); 1190 1191 switch (offset) { 1192 case _vgtif_reg(display_ready): 1193 send_display_ready_uevent(vgpu, data ? 1 : 0); 1194 break; 1195 case _vgtif_reg(g2v_notify): 1196 ret = handle_g2v_notification(vgpu, data); 1197 break; 1198 /* add xhot and yhot to handled list to avoid error log */ 1199 case 0x78830: 1200 case 0x78834: 1201 case _vgtif_reg(pdp[0].lo): 1202 case _vgtif_reg(pdp[0].hi): 1203 case _vgtif_reg(pdp[1].lo): 1204 case _vgtif_reg(pdp[1].hi): 1205 case _vgtif_reg(pdp[2].lo): 1206 case _vgtif_reg(pdp[2].hi): 1207 case _vgtif_reg(pdp[3].lo): 1208 case _vgtif_reg(pdp[3].hi): 1209 case _vgtif_reg(execlist_context_descriptor_lo): 1210 case _vgtif_reg(execlist_context_descriptor_hi): 1211 break; 1212 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1213 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1214 break; 1215 default: 1216 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1217 offset, bytes, data); 1218 break; 1219 } 1220 return 0; 1221 } 1222 1223 static int pf_write(struct intel_vgpu *vgpu, 1224 unsigned int offset, void *p_data, unsigned int bytes) 1225 { 1226 u32 val = *(u32 *)p_data; 1227 1228 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1229 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1230 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1231 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1232 vgpu->id); 1233 return 0; 1234 } 1235 1236 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1237 } 1238 1239 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1240 unsigned int offset, void *p_data, unsigned int bytes) 1241 { 1242 write_vreg(vgpu, offset, p_data, bytes); 1243 1244 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1245 vgpu_vreg(vgpu, offset) |= 1246 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1247 else 1248 vgpu_vreg(vgpu, offset) &= 1249 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1250 return 0; 1251 } 1252 1253 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1254 unsigned int offset, void *p_data, unsigned int bytes) 1255 { 1256 write_vreg(vgpu, offset, p_data, bytes); 1257 1258 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1259 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1260 return 0; 1261 } 1262 1263 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1264 void *p_data, unsigned int bytes) 1265 { 1266 u32 mode; 1267 1268 write_vreg(vgpu, offset, p_data, bytes); 1269 mode = vgpu_vreg(vgpu, offset); 1270 1271 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1272 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1273 vgpu->id); 1274 return 0; 1275 } 1276 1277 return 0; 1278 } 1279 1280 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1281 void *p_data, unsigned int bytes) 1282 { 1283 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1284 u32 trtte = *(u32 *)p_data; 1285 1286 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1287 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1288 vgpu->id); 1289 return -EINVAL; 1290 } 1291 write_vreg(vgpu, offset, p_data, bytes); 1292 /* TRTTE is not per-context */ 1293 1294 mmio_hw_access_pre(dev_priv); 1295 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1296 mmio_hw_access_post(dev_priv); 1297 1298 return 0; 1299 } 1300 1301 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1302 void *p_data, unsigned int bytes) 1303 { 1304 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1305 u32 val = *(u32 *)p_data; 1306 1307 if (val & 1) { 1308 /* unblock hw logic */ 1309 mmio_hw_access_pre(dev_priv); 1310 I915_WRITE(_MMIO(offset), val); 1311 mmio_hw_access_post(dev_priv); 1312 } 1313 write_vreg(vgpu, offset, p_data, bytes); 1314 return 0; 1315 } 1316 1317 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1318 void *p_data, unsigned int bytes) 1319 { 1320 u32 v = 0; 1321 1322 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1323 v |= (1 << 0); 1324 1325 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1326 v |= (1 << 8); 1327 1328 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1329 v |= (1 << 16); 1330 1331 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1332 v |= (1 << 24); 1333 1334 vgpu_vreg(vgpu, offset) = v; 1335 1336 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1337 } 1338 1339 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1340 void *p_data, unsigned int bytes) 1341 { 1342 u32 value = *(u32 *)p_data; 1343 u32 cmd = value & 0xff; 1344 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA); 1345 1346 switch (cmd) { 1347 case GEN9_PCODE_READ_MEM_LATENCY: 1348 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1349 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1350 /** 1351 * "Read memory latency" command on gen9. 1352 * Below memory latency values are read 1353 * from skylake platform. 1354 */ 1355 if (!*data0) 1356 *data0 = 0x1e1a1100; 1357 else 1358 *data0 = 0x61514b3d; 1359 } 1360 break; 1361 case SKL_PCODE_CDCLK_CONTROL: 1362 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1363 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1364 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1365 break; 1366 case GEN6_PCODE_READ_RC6VIDS: 1367 *data0 |= 0x1; 1368 break; 1369 } 1370 1371 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1372 vgpu->id, value, *data0); 1373 /** 1374 * PCODE_READY clear means ready for pcode read/write, 1375 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1376 * always emulate as pcode read/write success and ready for access 1377 * anytime, since we don't touch real physical registers here. 1378 */ 1379 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1380 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1381 } 1382 1383 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1384 void *p_data, unsigned int bytes) 1385 { 1386 u32 value = *(u32 *)p_data; 1387 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1388 1389 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1390 gvt_vgpu_err("VM(%d) write invalid HWSP address, reg:0x%x, value:0x%x\n", 1391 vgpu->id, offset, value); 1392 return -EINVAL; 1393 } 1394 /* 1395 * Need to emulate all the HWSP register write to ensure host can 1396 * update the VM CSB status correctly. Here listed registers can 1397 * support BDW, SKL or other platforms with same HWSP registers. 1398 */ 1399 if (unlikely(ring_id < 0 || ring_id > I915_NUM_ENGINES)) { 1400 gvt_vgpu_err("VM(%d) access unknown hardware status page register:0x%x\n", 1401 vgpu->id, offset); 1402 return -EINVAL; 1403 } 1404 vgpu->hws_pga[ring_id] = value; 1405 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1406 vgpu->id, value, offset); 1407 1408 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1409 } 1410 1411 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1412 unsigned int offset, void *p_data, unsigned int bytes) 1413 { 1414 u32 v = *(u32 *)p_data; 1415 1416 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1417 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1418 v |= (v >> 1); 1419 1420 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1421 } 1422 1423 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1424 void *p_data, unsigned int bytes) 1425 { 1426 u32 v = *(u32 *)p_data; 1427 1428 /* other bits are MBZ. */ 1429 v &= (1 << 31) | (1 << 30); 1430 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1431 1432 vgpu_vreg(vgpu, offset) = v; 1433 1434 return 0; 1435 } 1436 1437 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1438 unsigned int offset, void *p_data, unsigned int bytes) 1439 { 1440 struct intel_gvt *gvt = vgpu->gvt; 1441 struct drm_i915_private *dev_priv = gvt->dev_priv; 1442 int ring_id; 1443 u32 ring_base; 1444 1445 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1446 /** 1447 * Read HW reg in following case 1448 * a. the offset isn't a ring mmio 1449 * b. the offset's ring is running on hw. 1450 * c. the offset is ring time stamp mmio 1451 */ 1452 if (ring_id >= 0) 1453 ring_base = dev_priv->engine[ring_id]->mmio_base; 1454 1455 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1456 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1457 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1458 mmio_hw_access_pre(dev_priv); 1459 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1460 mmio_hw_access_post(dev_priv); 1461 } 1462 1463 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1464 } 1465 1466 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1467 void *p_data, unsigned int bytes) 1468 { 1469 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1470 struct intel_vgpu_execlist *execlist; 1471 u32 data = *(u32 *)p_data; 1472 int ret = 0; 1473 1474 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1)) 1475 return -EINVAL; 1476 1477 execlist = &vgpu->submission.execlist[ring_id]; 1478 1479 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1480 if (execlist->elsp_dwords.index == 3) { 1481 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1482 if(ret) 1483 gvt_vgpu_err("fail submit workload on ring %d\n", 1484 ring_id); 1485 } 1486 1487 ++execlist->elsp_dwords.index; 1488 execlist->elsp_dwords.index &= 0x3; 1489 return ret; 1490 } 1491 1492 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1493 void *p_data, unsigned int bytes) 1494 { 1495 struct intel_vgpu_submission *s = &vgpu->submission; 1496 u32 data = *(u32 *)p_data; 1497 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1498 bool enable_execlist; 1499 int ret; 1500 1501 write_vreg(vgpu, offset, p_data, bytes); 1502 1503 /* when PPGTT mode enabled, we will check if guest has called 1504 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1505 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1506 */ 1507 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1508 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1509 && !vgpu->pv_notified) { 1510 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1511 return 0; 1512 } 1513 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1514 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1515 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1516 1517 gvt_dbg_core("EXECLIST %s on ring %d\n", 1518 (enable_execlist ? "enabling" : "disabling"), 1519 ring_id); 1520 1521 if (!enable_execlist) 1522 return 0; 1523 1524 if (s->active) 1525 return 0; 1526 1527 ret = intel_vgpu_select_submission_ops(vgpu, 1528 INTEL_VGPU_EXECLIST_SUBMISSION); 1529 if (ret) 1530 return ret; 1531 1532 intel_vgpu_start_schedule(vgpu); 1533 } 1534 return 0; 1535 } 1536 1537 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1538 unsigned int offset, void *p_data, unsigned int bytes) 1539 { 1540 unsigned int id = 0; 1541 1542 write_vreg(vgpu, offset, p_data, bytes); 1543 vgpu_vreg(vgpu, offset) = 0; 1544 1545 switch (offset) { 1546 case 0x4260: 1547 id = RCS; 1548 break; 1549 case 0x4264: 1550 id = VCS; 1551 break; 1552 case 0x4268: 1553 id = VCS2; 1554 break; 1555 case 0x426c: 1556 id = BCS; 1557 break; 1558 case 0x4270: 1559 id = VECS; 1560 break; 1561 default: 1562 return -EINVAL; 1563 } 1564 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1565 1566 return 0; 1567 } 1568 1569 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1570 unsigned int offset, void *p_data, unsigned int bytes) 1571 { 1572 u32 data; 1573 1574 write_vreg(vgpu, offset, p_data, bytes); 1575 data = vgpu_vreg(vgpu, offset); 1576 1577 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1578 data |= RESET_CTL_READY_TO_RESET; 1579 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1580 data &= ~RESET_CTL_READY_TO_RESET; 1581 1582 vgpu_vreg(vgpu, offset) = data; 1583 return 0; 1584 } 1585 1586 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1587 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \ 1588 f, s, am, rm, d, r, w); \ 1589 if (ret) \ 1590 return ret; \ 1591 } while (0) 1592 1593 #define MMIO_D(reg, d) \ 1594 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1595 1596 #define MMIO_DH(reg, d, r, w) \ 1597 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1598 1599 #define MMIO_DFH(reg, d, f, r, w) \ 1600 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1601 1602 #define MMIO_GM(reg, d, r, w) \ 1603 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1604 1605 #define MMIO_GM_RDR(reg, d, r, w) \ 1606 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1607 1608 #define MMIO_RO(reg, d, f, rm, r, w) \ 1609 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1610 1611 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1612 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1613 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1614 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1615 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1616 if (HAS_BSD2(dev_priv)) \ 1617 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1618 } while (0) 1619 1620 #define MMIO_RING_D(prefix, d) \ 1621 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1622 1623 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1624 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1625 1626 #define MMIO_RING_GM(prefix, d, r, w) \ 1627 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1628 1629 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1630 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1631 1632 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1633 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1634 1635 static int init_generic_mmio_info(struct intel_gvt *gvt) 1636 { 1637 struct drm_i915_private *dev_priv = gvt->dev_priv; 1638 int ret; 1639 1640 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1641 intel_vgpu_reg_imr_handler); 1642 1643 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1644 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1645 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1646 MMIO_D(SDEISR, D_ALL); 1647 1648 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1649 1650 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1651 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1652 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1653 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1654 1655 #define RING_REG(base) (base + 0x28) 1656 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1657 #undef RING_REG 1658 1659 #define RING_REG(base) (base + 0x134) 1660 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1661 #undef RING_REG 1662 1663 #define RING_REG(base) (base + 0x6c) 1664 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1665 #undef RING_REG 1666 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1667 1668 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL); 1669 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1670 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL); 1671 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1672 1673 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1674 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1675 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1676 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1677 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1678 1679 /* RING MODE */ 1680 #define RING_REG(base) (base + 0x29c) 1681 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1682 ring_mode_mmio_write); 1683 #undef RING_REG 1684 1685 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1686 NULL, NULL); 1687 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1688 NULL, NULL); 1689 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1690 mmio_read_from_hw, NULL); 1691 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1692 mmio_read_from_hw, NULL); 1693 1694 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1695 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1696 NULL, NULL); 1697 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1698 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1699 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1700 1701 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1702 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1703 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1704 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1705 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1706 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1707 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1708 NULL, NULL); 1709 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1710 NULL, NULL); 1711 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL); 1712 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL); 1713 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL); 1714 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL); 1715 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL); 1716 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL); 1717 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL); 1718 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1719 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1720 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1721 1722 /* display */ 1723 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1724 MMIO_D(0x602a0, D_ALL); 1725 1726 MMIO_D(0x65050, D_ALL); 1727 MMIO_D(0x650b4, D_ALL); 1728 1729 MMIO_D(0xc4040, D_ALL); 1730 MMIO_D(DERRMR, D_ALL); 1731 1732 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1733 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1734 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1735 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1736 1737 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1738 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1739 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1740 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1741 1742 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1743 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1744 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1745 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1746 1747 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1748 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1749 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1750 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1751 1752 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1753 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1754 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1755 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1756 1757 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1758 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1759 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1760 1761 MMIO_D(CURPOS(PIPE_A), D_ALL); 1762 MMIO_D(CURPOS(PIPE_B), D_ALL); 1763 MMIO_D(CURPOS(PIPE_C), D_ALL); 1764 1765 MMIO_D(CURBASE(PIPE_A), D_ALL); 1766 MMIO_D(CURBASE(PIPE_B), D_ALL); 1767 MMIO_D(CURBASE(PIPE_C), D_ALL); 1768 1769 MMIO_D(0x700ac, D_ALL); 1770 MMIO_D(0x710ac, D_ALL); 1771 MMIO_D(0x720ac, D_ALL); 1772 1773 MMIO_D(0x70090, D_ALL); 1774 MMIO_D(0x70094, D_ALL); 1775 MMIO_D(0x70098, D_ALL); 1776 MMIO_D(0x7009c, D_ALL); 1777 1778 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1779 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1780 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1781 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1782 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1783 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1784 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1785 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1786 1787 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1788 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1789 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1790 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1791 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1792 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1793 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1794 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1795 1796 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1797 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1798 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1799 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1800 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1801 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1802 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1803 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1804 1805 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1806 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1807 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1808 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1809 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1810 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1811 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1812 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1813 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1814 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1815 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1816 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1817 1818 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1819 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1820 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1821 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1822 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1823 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1824 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1825 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1826 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1827 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1828 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1829 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1830 1831 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1832 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1833 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1834 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1835 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1836 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1837 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1838 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1839 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1840 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1841 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1842 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1843 1844 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1845 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1846 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1847 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1848 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1849 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1850 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1851 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1852 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1853 1854 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1855 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1856 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1857 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1858 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1859 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1860 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1861 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1862 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1863 1864 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1865 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1866 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1867 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1868 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1869 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1870 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1871 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1872 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1873 1874 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1875 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1876 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1877 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1878 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1879 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1880 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1881 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1882 1883 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1884 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1885 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1886 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1887 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1888 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1889 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1890 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1891 1892 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1893 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1894 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1895 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1896 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1897 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1898 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1899 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1900 1901 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1902 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1903 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1904 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1905 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1906 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1907 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1908 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1909 1910 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1911 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1912 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1913 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1914 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1915 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1916 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1917 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1918 1919 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1920 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1921 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1922 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1923 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1924 1925 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1926 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1927 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1928 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1929 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1930 1931 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1932 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1933 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1934 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1935 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1936 1937 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1938 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1939 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1940 MMIO_D(WM1_LP_ILK, D_ALL); 1941 MMIO_D(WM2_LP_ILK, D_ALL); 1942 MMIO_D(WM3_LP_ILK, D_ALL); 1943 MMIO_D(WM1S_LP_ILK, D_ALL); 1944 MMIO_D(WM2S_LP_IVB, D_ALL); 1945 MMIO_D(WM3S_LP_IVB, D_ALL); 1946 1947 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1948 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1949 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1950 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1951 1952 MMIO_D(0x48268, D_ALL); 1953 1954 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1955 gmbus_mmio_write); 1956 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1957 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1958 1959 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1960 dp_aux_ch_ctl_mmio_write); 1961 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1962 dp_aux_ch_ctl_mmio_write); 1963 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1964 dp_aux_ch_ctl_mmio_write); 1965 1966 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 1967 1968 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write); 1969 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write); 1970 1971 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1972 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1973 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1974 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1975 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1976 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1977 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1978 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1979 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1980 1981 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL); 1982 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL); 1983 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL); 1984 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL); 1985 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL); 1986 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL); 1987 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL); 1988 1989 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL); 1990 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL); 1991 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL); 1992 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL); 1993 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL); 1994 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL); 1995 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL); 1996 1997 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL); 1998 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL); 1999 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL); 2000 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL); 2001 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL); 2002 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL); 2003 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL); 2004 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL); 2005 2006 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2007 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2008 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2009 2010 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2011 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2012 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2013 2014 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2015 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2016 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2017 2018 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2019 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2020 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2021 2022 MMIO_D(_FDI_RXA_MISC, D_ALL); 2023 MMIO_D(_FDI_RXB_MISC, D_ALL); 2024 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL); 2025 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL); 2026 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL); 2027 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL); 2028 2029 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2030 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2031 MMIO_D(PCH_PP_STATUS, D_ALL); 2032 MMIO_D(PCH_LVDS, D_ALL); 2033 MMIO_D(_PCH_DPLL_A, D_ALL); 2034 MMIO_D(_PCH_DPLL_B, D_ALL); 2035 MMIO_D(_PCH_FPA0, D_ALL); 2036 MMIO_D(_PCH_FPA1, D_ALL); 2037 MMIO_D(_PCH_FPB0, D_ALL); 2038 MMIO_D(_PCH_FPB1, D_ALL); 2039 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2040 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2041 MMIO_D(PCH_DPLL_SEL, D_ALL); 2042 2043 MMIO_D(0x61208, D_ALL); 2044 MMIO_D(0x6120c, D_ALL); 2045 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2046 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2047 2048 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL); 2049 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL); 2050 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL); 2051 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL); 2052 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read, NULL); 2053 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read, NULL); 2054 2055 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2056 PORTA_HOTPLUG_STATUS_MASK 2057 | PORTB_HOTPLUG_STATUS_MASK 2058 | PORTC_HOTPLUG_STATUS_MASK 2059 | PORTD_HOTPLUG_STATUS_MASK, 2060 NULL, NULL); 2061 2062 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2063 MMIO_D(FUSE_STRAP, D_ALL); 2064 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2065 2066 MMIO_D(DISP_ARB_CTL, D_ALL); 2067 MMIO_D(DISP_ARB_CTL2, D_ALL); 2068 2069 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2070 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2071 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2072 2073 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2074 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2075 MMIO_D(_TRANSA_CHICKEN1, D_ALL); 2076 MMIO_D(_TRANSB_CHICKEN1, D_ALL); 2077 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2078 MMIO_D(_TRANSA_CHICKEN2, D_ALL); 2079 MMIO_D(_TRANSB_CHICKEN2, D_ALL); 2080 2081 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2082 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2083 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2084 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2085 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2086 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2087 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2088 2089 MMIO_D(IPS_CTL, D_ALL); 2090 2091 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2092 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2093 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2094 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2095 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2096 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2097 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2098 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2099 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2100 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2101 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2102 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2103 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2104 2105 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2106 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2107 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2108 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2109 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2110 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2111 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2112 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2113 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2114 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2115 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2116 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2117 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2118 2119 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2120 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2121 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2122 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2123 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2124 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2125 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2126 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2127 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2128 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2129 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2130 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2131 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2132 2133 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2134 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2135 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2136 2137 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2138 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2139 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2140 2141 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2142 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2143 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2144 2145 MMIO_D(0x60110, D_ALL); 2146 MMIO_D(0x61110, D_ALL); 2147 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2148 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2149 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2150 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2151 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2152 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2153 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2154 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2155 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2156 2157 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2158 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2159 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2160 MMIO_D(SPLL_CTL, D_ALL); 2161 MMIO_D(_WRPLL_CTL1, D_ALL); 2162 MMIO_D(_WRPLL_CTL2, D_ALL); 2163 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2164 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2165 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2166 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2167 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2168 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2169 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2170 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2171 2172 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2173 MMIO_D(0x46508, D_ALL); 2174 2175 MMIO_D(0x49080, D_ALL); 2176 MMIO_D(0x49180, D_ALL); 2177 MMIO_D(0x49280, D_ALL); 2178 2179 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2180 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2181 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2182 2183 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2184 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2185 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2186 2187 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2188 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2189 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2190 2191 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2192 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2193 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2194 2195 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2196 MMIO_D(SBI_ADDR, D_ALL); 2197 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2198 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2199 MMIO_D(PIXCLK_GATE, D_ALL); 2200 2201 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL, 2202 dp_aux_ch_ctl_mmio_write); 2203 2204 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2205 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2206 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2207 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2208 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2209 2210 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2211 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2212 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2213 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2214 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2215 2216 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2217 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2218 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2219 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2220 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2221 2222 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2223 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2224 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2225 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2226 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2227 2228 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2229 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2230 2231 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL); 2232 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL); 2233 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL); 2234 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL); 2235 2236 MMIO_D(_TRANSA_MSA_MISC, D_ALL); 2237 MMIO_D(_TRANSB_MSA_MISC, D_ALL); 2238 MMIO_D(_TRANSC_MSA_MISC, D_ALL); 2239 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL); 2240 2241 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2242 MMIO_D(FORCEWAKE_ACK, D_ALL); 2243 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2244 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2245 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2246 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2247 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2248 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2249 MMIO_D(ECOBUS, D_ALL); 2250 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2251 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2252 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2253 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2254 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2255 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2256 MMIO_D(GEN6_RPSTAT1, D_ALL); 2257 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2258 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2259 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2260 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2261 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2262 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2263 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2264 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2265 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2266 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2267 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2268 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2269 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2270 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2271 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2272 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2273 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2274 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2275 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2276 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2277 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2278 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2279 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2280 /* 2281 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2282 * register. 2283 */ 2284 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2285 power_well_ctl_mmio_write); 2286 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2287 power_well_ctl_mmio_write); 2288 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); 2289 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2290 power_well_ctl_mmio_write); 2291 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2292 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2293 2294 MMIO_D(RSTDBYCTL, D_ALL); 2295 2296 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2297 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2298 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2299 2300 MMIO_D(TILECTL, D_ALL); 2301 2302 MMIO_D(GEN6_UCGCTL1, D_ALL); 2303 MMIO_D(GEN6_UCGCTL2, D_ALL); 2304 2305 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2306 2307 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2308 MMIO_D(0x13812c, D_ALL); 2309 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2310 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2311 MMIO_D(HSW_IDICR, D_ALL); 2312 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2313 2314 MMIO_D(0x3c, D_ALL); 2315 MMIO_D(0x860, D_ALL); 2316 MMIO_D(ECOSKPD, D_ALL); 2317 MMIO_D(0x121d0, D_ALL); 2318 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2319 MMIO_D(0x41d0, D_ALL); 2320 MMIO_D(GAC_ECO_BITS, D_ALL); 2321 MMIO_D(0x6200, D_ALL); 2322 MMIO_D(0x6204, D_ALL); 2323 MMIO_D(0x6208, D_ALL); 2324 MMIO_D(0x7118, D_ALL); 2325 MMIO_D(0x7180, D_ALL); 2326 MMIO_D(0x7408, D_ALL); 2327 MMIO_D(0x7c00, D_ALL); 2328 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2329 MMIO_D(0x911c, D_ALL); 2330 MMIO_D(0x9120, D_ALL); 2331 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2332 2333 MMIO_D(GAB_CTL, D_ALL); 2334 MMIO_D(0x48800, D_ALL); 2335 MMIO_D(0xce044, D_ALL); 2336 MMIO_D(0xe6500, D_ALL); 2337 MMIO_D(0xe6504, D_ALL); 2338 MMIO_D(0xe6600, D_ALL); 2339 MMIO_D(0xe6604, D_ALL); 2340 MMIO_D(0xe6700, D_ALL); 2341 MMIO_D(0xe6704, D_ALL); 2342 MMIO_D(0xe6800, D_ALL); 2343 MMIO_D(0xe6804, D_ALL); 2344 MMIO_D(PCH_GMBUS4, D_ALL); 2345 MMIO_D(PCH_GMBUS5, D_ALL); 2346 2347 MMIO_D(0x902c, D_ALL); 2348 MMIO_D(0xec008, D_ALL); 2349 MMIO_D(0xec00c, D_ALL); 2350 MMIO_D(0xec008 + 0x18, D_ALL); 2351 MMIO_D(0xec00c + 0x18, D_ALL); 2352 MMIO_D(0xec008 + 0x18 * 2, D_ALL); 2353 MMIO_D(0xec00c + 0x18 * 2, D_ALL); 2354 MMIO_D(0xec008 + 0x18 * 3, D_ALL); 2355 MMIO_D(0xec00c + 0x18 * 3, D_ALL); 2356 MMIO_D(0xec408, D_ALL); 2357 MMIO_D(0xec40c, D_ALL); 2358 MMIO_D(0xec408 + 0x18, D_ALL); 2359 MMIO_D(0xec40c + 0x18, D_ALL); 2360 MMIO_D(0xec408 + 0x18 * 2, D_ALL); 2361 MMIO_D(0xec40c + 0x18 * 2, D_ALL); 2362 MMIO_D(0xec408 + 0x18 * 3, D_ALL); 2363 MMIO_D(0xec40c + 0x18 * 3, D_ALL); 2364 MMIO_D(0xfc810, D_ALL); 2365 MMIO_D(0xfc81c, D_ALL); 2366 MMIO_D(0xfc828, D_ALL); 2367 MMIO_D(0xfc834, D_ALL); 2368 MMIO_D(0xfcc00, D_ALL); 2369 MMIO_D(0xfcc0c, D_ALL); 2370 MMIO_D(0xfcc18, D_ALL); 2371 MMIO_D(0xfcc24, D_ALL); 2372 MMIO_D(0xfd000, D_ALL); 2373 MMIO_D(0xfd00c, D_ALL); 2374 MMIO_D(0xfd018, D_ALL); 2375 MMIO_D(0xfd024, D_ALL); 2376 MMIO_D(0xfd034, D_ALL); 2377 2378 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2379 MMIO_D(0x2054, D_ALL); 2380 MMIO_D(0x12054, D_ALL); 2381 MMIO_D(0x22054, D_ALL); 2382 MMIO_D(0x1a054, D_ALL); 2383 2384 MMIO_D(0x44070, D_ALL); 2385 MMIO_DFH(0x215c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2386 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2387 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2388 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL); 2389 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL); 2390 2391 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2392 MMIO_D(0x2b00, D_BDW_PLUS); 2393 MMIO_D(0x2360, D_BDW_PLUS); 2394 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2395 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2396 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2397 2398 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2399 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2400 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2401 2402 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2404 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2405 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2406 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2407 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2408 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2409 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2414 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2415 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2416 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2417 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2418 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2419 2420 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2421 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2422 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2423 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2424 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL); 2425 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2426 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2427 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2428 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2429 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2431 return 0; 2432 } 2433 2434 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2435 { 2436 struct drm_i915_private *dev_priv = gvt->dev_priv; 2437 int ret; 2438 2439 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2440 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2441 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2442 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2443 2444 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2445 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2446 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2447 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2448 2449 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2450 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2451 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2452 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2453 2454 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2455 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2456 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2457 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2458 2459 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2460 intel_vgpu_reg_imr_handler); 2461 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2462 intel_vgpu_reg_ier_handler); 2463 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2464 intel_vgpu_reg_iir_handler); 2465 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2466 2467 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2468 intel_vgpu_reg_imr_handler); 2469 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2470 intel_vgpu_reg_ier_handler); 2471 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2472 intel_vgpu_reg_iir_handler); 2473 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2474 2475 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2476 intel_vgpu_reg_imr_handler); 2477 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2478 intel_vgpu_reg_ier_handler); 2479 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2480 intel_vgpu_reg_iir_handler); 2481 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2482 2483 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2484 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2485 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2486 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2487 2488 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2489 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2490 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2491 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2492 2493 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2494 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2495 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2496 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2497 2498 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2499 intel_vgpu_reg_master_irq_handler); 2500 2501 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2502 mmio_read_from_hw, NULL); 2503 2504 #define RING_REG(base) (base + 0xd0) 2505 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2506 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2507 ring_reset_ctl_write); 2508 #undef RING_REG 2509 2510 #define RING_REG(base) (base + 0x230) 2511 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2512 #undef RING_REG 2513 2514 #define RING_REG(base) (base + 0x234) 2515 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2516 NULL, NULL); 2517 #undef RING_REG 2518 2519 #define RING_REG(base) (base + 0x244) 2520 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2521 #undef RING_REG 2522 2523 #define RING_REG(base) (base + 0x370) 2524 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2525 #undef RING_REG 2526 2527 #define RING_REG(base) (base + 0x3a0) 2528 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2529 #undef RING_REG 2530 2531 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2532 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2533 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2534 MMIO_D(0x1c1d0, D_BDW_PLUS); 2535 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2536 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2537 MMIO_D(0x1c054, D_BDW_PLUS); 2538 2539 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2540 2541 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2542 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2543 2544 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2545 2546 #define RING_REG(base) (base + 0x270) 2547 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2548 #undef RING_REG 2549 2550 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2551 2552 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2553 2554 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2555 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2556 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2557 2558 MMIO_D(WM_MISC, D_BDW); 2559 MMIO_D(BDW_EDP_PSR_BASE, D_BDW); 2560 2561 MMIO_D(0x66c00, D_BDW_PLUS); 2562 MMIO_D(0x66c04, D_BDW_PLUS); 2563 2564 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2565 2566 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2567 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2568 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2569 2570 MMIO_D(0xfdc, D_BDW_PLUS); 2571 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2572 NULL, NULL); 2573 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2574 NULL, NULL); 2575 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2576 2577 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2578 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL); 2579 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2580 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL); 2581 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL); 2582 MMIO_D(0xb110, D_BDW); 2583 2584 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2585 NULL, force_nonpriv_write); 2586 2587 MMIO_D(0x44484, D_BDW_PLUS); 2588 MMIO_D(0x4448c, D_BDW_PLUS); 2589 2590 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL); 2591 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2592 2593 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL); 2594 2595 MMIO_D(0x110000, D_BDW_PLUS); 2596 2597 MMIO_D(0x48400, D_BDW_PLUS); 2598 2599 MMIO_D(0x6e570, D_BDW_PLUS); 2600 MMIO_D(0x65f10, D_BDW_PLUS); 2601 2602 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2603 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2604 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2605 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2606 2607 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL); 2608 2609 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2610 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2611 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2612 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2613 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2614 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2615 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2616 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2617 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2618 return 0; 2619 } 2620 2621 static int init_skl_mmio_info(struct intel_gvt *gvt) 2622 { 2623 struct drm_i915_private *dev_priv = gvt->dev_priv; 2624 int ret; 2625 2626 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2627 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2628 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2629 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2630 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2631 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2632 2633 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2634 dp_aux_ch_ctl_mmio_write); 2635 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2636 dp_aux_ch_ctl_mmio_write); 2637 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2638 dp_aux_ch_ctl_mmio_write); 2639 2640 /* 2641 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2642 * register. 2643 */ 2644 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); 2645 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2646 skl_power_well_ctl_write); 2647 2648 MMIO_D(0xa210, D_SKL_PLUS); 2649 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2650 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2651 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2652 MMIO_DH(0x4ddc, D_SKL_PLUS, NULL, NULL); 2653 MMIO_DH(0x42080, D_SKL_PLUS, NULL, NULL); 2654 MMIO_D(0x45504, D_SKL_PLUS); 2655 MMIO_D(0x45520, D_SKL_PLUS); 2656 MMIO_D(0x46000, D_SKL_PLUS); 2657 MMIO_DH(0x46010, D_SKL | D_KBL, NULL, skl_lcpll_write); 2658 MMIO_DH(0x46014, D_SKL | D_KBL, NULL, skl_lcpll_write); 2659 MMIO_D(0x6C040, D_SKL | D_KBL); 2660 MMIO_D(0x6C048, D_SKL | D_KBL); 2661 MMIO_D(0x6C050, D_SKL | D_KBL); 2662 MMIO_D(0x6C044, D_SKL | D_KBL); 2663 MMIO_D(0x6C04C, D_SKL | D_KBL); 2664 MMIO_D(0x6C054, D_SKL | D_KBL); 2665 MMIO_D(0x6c058, D_SKL | D_KBL); 2666 MMIO_D(0x6c05c, D_SKL | D_KBL); 2667 MMIO_DH(0X6c060, D_SKL | D_KBL, dpll_status_read, NULL); 2668 2669 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2670 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2671 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2672 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2673 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2674 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2675 2676 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2677 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2678 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2679 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2680 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2681 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2682 2683 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2684 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2685 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2686 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2687 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2688 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2689 2690 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2691 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2692 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2693 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2694 2695 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2696 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2697 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2698 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2699 2700 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2702 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2703 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2704 2705 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2707 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2708 2709 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2710 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2711 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2712 2713 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2714 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2715 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2716 2717 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2718 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2719 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2720 2721 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2722 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2723 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2724 2725 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2726 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2727 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2728 2729 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2730 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2731 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2732 2733 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2734 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2735 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2736 2737 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2738 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2739 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2740 2741 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2742 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2743 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2744 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2745 2746 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2747 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2748 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2749 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2750 2751 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2752 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2753 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2754 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2755 2756 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2757 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2758 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2759 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2760 2761 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2762 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2763 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2764 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2765 2766 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2767 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2768 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2769 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2770 2771 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2772 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2773 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2774 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL_PLUS, NULL, NULL); 2775 2776 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2777 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2778 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2779 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL_PLUS, NULL, NULL); 2780 2781 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2782 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2783 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2784 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL_PLUS, NULL, NULL); 2785 2786 MMIO_D(0x70380, D_SKL_PLUS); 2787 MMIO_D(0x71380, D_SKL_PLUS); 2788 MMIO_D(0x72380, D_SKL_PLUS); 2789 MMIO_D(0x7039c, D_SKL_PLUS); 2790 2791 MMIO_D(0x8f074, D_SKL | D_KBL); 2792 MMIO_D(0x8f004, D_SKL | D_KBL); 2793 MMIO_D(0x8f034, D_SKL | D_KBL); 2794 2795 MMIO_D(0xb11c, D_SKL | D_KBL); 2796 2797 MMIO_D(0x51000, D_SKL | D_KBL); 2798 MMIO_D(0x6c00c, D_SKL_PLUS); 2799 2800 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2801 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2802 2803 MMIO_D(0xd08, D_SKL_PLUS); 2804 MMIO_DFH(0x20e0, D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2805 MMIO_DFH(0x20ec, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2806 2807 /* TRTT */ 2808 MMIO_DFH(0x4de0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2809 MMIO_DFH(0x4de4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2810 MMIO_DFH(0x4de8, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2811 MMIO_DFH(0x4dec, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2812 MMIO_DFH(0x4df0, D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2813 MMIO_DFH(0x4df4, D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2814 MMIO_DH(0x4dfc, D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); 2815 2816 MMIO_D(0x45008, D_SKL | D_KBL); 2817 2818 MMIO_D(0x46430, D_SKL | D_KBL); 2819 2820 MMIO_D(0x46520, D_SKL | D_KBL); 2821 2822 MMIO_D(0xc403c, D_SKL | D_KBL); 2823 MMIO_D(0xb004, D_SKL_PLUS); 2824 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2825 2826 MMIO_D(0x65900, D_SKL_PLUS); 2827 MMIO_D(0x1082c0, D_SKL | D_KBL); 2828 MMIO_D(0x4068, D_SKL | D_KBL); 2829 MMIO_D(0x67054, D_SKL | D_KBL); 2830 MMIO_D(0x6e560, D_SKL | D_KBL); 2831 MMIO_D(0x6e554, D_SKL | D_KBL); 2832 MMIO_D(0x2b20, D_SKL | D_KBL); 2833 MMIO_D(0x65f00, D_SKL | D_KBL); 2834 MMIO_D(0x65f08, D_SKL | D_KBL); 2835 MMIO_D(0x320f0, D_SKL | D_KBL); 2836 2837 MMIO_D(0x70034, D_SKL_PLUS); 2838 MMIO_D(0x71034, D_SKL_PLUS); 2839 MMIO_D(0x72034, D_SKL_PLUS); 2840 2841 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL_PLUS); 2842 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL_PLUS); 2843 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL_PLUS); 2844 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL_PLUS); 2845 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL_PLUS); 2846 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL_PLUS); 2847 2848 MMIO_D(0x44500, D_SKL_PLUS); 2849 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2850 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, 2851 NULL, NULL); 2852 2853 MMIO_D(0x4ab8, D_KBL); 2854 MMIO_D(0x2248, D_SKL_PLUS | D_KBL); 2855 2856 return 0; 2857 } 2858 2859 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2860 unsigned int offset) 2861 { 2862 unsigned long device = intel_gvt_get_device_type(gvt); 2863 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2864 int num = gvt->mmio.num_mmio_block; 2865 int i; 2866 2867 for (i = 0; i < num; i++, block++) { 2868 if (!(device & block->device)) 2869 continue; 2870 if (offset >= INTEL_GVT_MMIO_OFFSET(block->offset) && 2871 offset < INTEL_GVT_MMIO_OFFSET(block->offset) + block->size) 2872 return block; 2873 } 2874 return NULL; 2875 } 2876 2877 /** 2878 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2879 * @gvt: GVT device 2880 * 2881 * This function is called at the driver unloading stage, to clean up the MMIO 2882 * information table of GVT device 2883 * 2884 */ 2885 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2886 { 2887 struct hlist_node *tmp; 2888 struct intel_gvt_mmio_info *e; 2889 int i; 2890 2891 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2892 kfree(e); 2893 2894 vfree(gvt->mmio.mmio_attribute); 2895 gvt->mmio.mmio_attribute = NULL; 2896 } 2897 2898 /* Special MMIO blocks. */ 2899 static struct gvt_mmio_block mmio_blocks[] = { 2900 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 2901 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 2902 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 2903 pvinfo_mmio_read, pvinfo_mmio_write}, 2904 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 2905 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 2906 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 2907 }; 2908 2909 /** 2910 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2911 * @gvt: GVT device 2912 * 2913 * This function is called at the initialization stage, to setup the MMIO 2914 * information table for GVT device 2915 * 2916 * Returns: 2917 * zero on success, negative if failed. 2918 */ 2919 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2920 { 2921 struct intel_gvt_device_info *info = &gvt->device_info; 2922 struct drm_i915_private *dev_priv = gvt->dev_priv; 2923 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2924 int ret; 2925 2926 gvt->mmio.mmio_attribute = vzalloc(size); 2927 if (!gvt->mmio.mmio_attribute) 2928 return -ENOMEM; 2929 2930 ret = init_generic_mmio_info(gvt); 2931 if (ret) 2932 goto err; 2933 2934 if (IS_BROADWELL(dev_priv)) { 2935 ret = init_broadwell_mmio_info(gvt); 2936 if (ret) 2937 goto err; 2938 } else if (IS_SKYLAKE(dev_priv) 2939 || IS_KABYLAKE(dev_priv)) { 2940 ret = init_broadwell_mmio_info(gvt); 2941 if (ret) 2942 goto err; 2943 ret = init_skl_mmio_info(gvt); 2944 if (ret) 2945 goto err; 2946 } 2947 2948 gvt->mmio.mmio_block = mmio_blocks; 2949 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 2950 2951 return 0; 2952 err: 2953 intel_gvt_clean_mmio_info(gvt); 2954 return ret; 2955 } 2956 2957 /** 2958 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 2959 * @gvt: a GVT device 2960 * @handler: the handler 2961 * @data: private data given to handler 2962 * 2963 * Returns: 2964 * Zero on success, negative error code if failed. 2965 */ 2966 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 2967 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 2968 void *data) 2969 { 2970 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2971 struct intel_gvt_mmio_info *e; 2972 int i, j, ret; 2973 2974 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 2975 ret = handler(gvt, e->offset, data); 2976 if (ret) 2977 return ret; 2978 } 2979 2980 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 2981 for (j = 0; j < block->size; j += 4) { 2982 ret = handler(gvt, 2983 INTEL_GVT_MMIO_OFFSET(block->offset) + j, 2984 data); 2985 if (ret) 2986 return ret; 2987 } 2988 } 2989 return 0; 2990 } 2991 2992 /** 2993 * intel_vgpu_default_mmio_read - default MMIO read handler 2994 * @vgpu: a vGPU 2995 * @offset: access offset 2996 * @p_data: data return buffer 2997 * @bytes: access data length 2998 * 2999 * Returns: 3000 * Zero on success, negative error code if failed. 3001 */ 3002 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3003 void *p_data, unsigned int bytes) 3004 { 3005 read_vreg(vgpu, offset, p_data, bytes); 3006 return 0; 3007 } 3008 3009 /** 3010 * intel_t_default_mmio_write - default MMIO write handler 3011 * @vgpu: a vGPU 3012 * @offset: access offset 3013 * @p_data: write data buffer 3014 * @bytes: access data length 3015 * 3016 * Returns: 3017 * Zero on success, negative error code if failed. 3018 */ 3019 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3020 void *p_data, unsigned int bytes) 3021 { 3022 write_vreg(vgpu, offset, p_data, bytes); 3023 return 0; 3024 } 3025 3026 /** 3027 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3028 * force-nopriv register 3029 * 3030 * @gvt: a GVT device 3031 * @offset: register offset 3032 * 3033 * Returns: 3034 * True if the register is in force-nonpriv whitelist; 3035 * False if outside; 3036 */ 3037 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3038 unsigned int offset) 3039 { 3040 return in_whitelist(offset); 3041 } 3042 3043 /** 3044 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3045 * @vgpu: a vGPU 3046 * @offset: register offset 3047 * @pdata: data buffer 3048 * @bytes: data length 3049 * 3050 * Returns: 3051 * Zero on success, negative error code if failed. 3052 */ 3053 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3054 void *pdata, unsigned int bytes, bool is_read) 3055 { 3056 struct intel_gvt *gvt = vgpu->gvt; 3057 struct intel_gvt_mmio_info *mmio_info; 3058 struct gvt_mmio_block *mmio_block; 3059 gvt_mmio_func func; 3060 int ret; 3061 3062 if (WARN_ON(bytes > 8)) 3063 return -EINVAL; 3064 3065 /* 3066 * Handle special MMIO blocks. 3067 */ 3068 mmio_block = find_mmio_block(gvt, offset); 3069 if (mmio_block) { 3070 func = is_read ? mmio_block->read : mmio_block->write; 3071 if (func) 3072 return func(vgpu, offset, pdata, bytes); 3073 goto default_rw; 3074 } 3075 3076 /* 3077 * Normal tracked MMIOs. 3078 */ 3079 mmio_info = find_mmio_info(gvt, offset); 3080 if (!mmio_info) { 3081 if (!vgpu->mmio.disable_warn_untrack) 3082 gvt_vgpu_err("untracked MMIO %08x len %d\n", 3083 offset, bytes); 3084 goto default_rw; 3085 } 3086 3087 if (is_read) 3088 return mmio_info->read(vgpu, offset, pdata, bytes); 3089 else { 3090 u64 ro_mask = mmio_info->ro_mask; 3091 u32 old_vreg = 0, old_sreg = 0; 3092 u64 data = 0; 3093 3094 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3095 old_vreg = vgpu_vreg(vgpu, offset); 3096 old_sreg = vgpu_sreg(vgpu, offset); 3097 } 3098 3099 if (likely(!ro_mask)) 3100 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3101 else if (!~ro_mask) { 3102 gvt_vgpu_err("try to write RO reg %x\n", offset); 3103 return 0; 3104 } else { 3105 /* keep the RO bits in the virtual register */ 3106 memcpy(&data, pdata, bytes); 3107 data &= ~ro_mask; 3108 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3109 ret = mmio_info->write(vgpu, offset, &data, bytes); 3110 } 3111 3112 /* higher 16bits of mode ctl regs are mask bits for change */ 3113 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3114 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3115 3116 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3117 | (vgpu_vreg(vgpu, offset) & mask); 3118 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3119 | (vgpu_sreg(vgpu, offset) & mask); 3120 } 3121 } 3122 3123 return ret; 3124 3125 default_rw: 3126 return is_read ? 3127 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3128 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3129 } 3130