1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "i915_reg.h" 41 #include "gvt.h" 42 #include "i915_pvinfo.h" 43 #include "intel_mchbar_regs.h" 44 #include "display/intel_display_types.h" 45 #include "display/intel_fbc.h" 46 #include "display/vlv_dsi_pll_regs.h" 47 #include "gt/intel_gt_regs.h" 48 49 /* XXX FIXME i915 has changed PP_XXX definition */ 50 #define PCH_PP_STATUS _MMIO(0xc7200) 51 #define PCH_PP_CONTROL _MMIO(0xc7204) 52 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 53 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 54 #define PCH_PP_DIVISOR _MMIO(0xc7210) 55 56 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 57 { 58 struct drm_i915_private *i915 = gvt->gt->i915; 59 60 if (IS_BROADWELL(i915)) 61 return D_BDW; 62 else if (IS_SKYLAKE(i915)) 63 return D_SKL; 64 else if (IS_KABYLAKE(i915)) 65 return D_KBL; 66 else if (IS_BROXTON(i915)) 67 return D_BXT; 68 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) 69 return D_CFL; 70 71 return 0; 72 } 73 74 bool intel_gvt_match_device(struct intel_gvt *gvt, 75 unsigned long device) 76 { 77 return intel_gvt_get_device_type(gvt) & device; 78 } 79 80 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 81 void *p_data, unsigned int bytes) 82 { 83 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 84 } 85 86 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 87 void *p_data, unsigned int bytes) 88 { 89 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 90 } 91 92 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, 93 unsigned int offset) 94 { 95 struct intel_gvt_mmio_info *e; 96 97 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 98 if (e->offset == offset) 99 return e; 100 } 101 return NULL; 102 } 103 104 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, 105 u16 flags, u32 addr_mask, u32 ro_mask, u32 device, 106 gvt_mmio_func read, gvt_mmio_func write) 107 { 108 struct intel_gvt_mmio_info *p; 109 u32 start, end, i; 110 111 if (!intel_gvt_match_device(gvt, device)) 112 return 0; 113 114 if (WARN_ON(!IS_ALIGNED(offset, 4))) 115 return -EINVAL; 116 117 start = offset; 118 end = offset + size; 119 120 for (i = start; i < end; i += 4) { 121 p = intel_gvt_find_mmio_info(gvt, i); 122 if (!p) { 123 WARN(1, "assign a handler to a non-tracked mmio %x\n", 124 i); 125 return -ENODEV; 126 } 127 p->ro_mask = ro_mask; 128 gvt->mmio.mmio_attribute[i / 4] = flags; 129 if (read) 130 p->read = read; 131 if (write) 132 p->write = write; 133 } 134 return 0; 135 } 136 137 /** 138 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine 139 * @gvt: a GVT device 140 * @offset: register offset 141 * 142 * Returns: 143 * The engine containing the offset within its mmio page. 144 */ 145 const struct intel_engine_cs * 146 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset) 147 { 148 struct intel_engine_cs *engine; 149 enum intel_engine_id id; 150 151 offset &= ~GENMASK(11, 0); 152 for_each_engine(engine, gvt->gt, id) 153 if (engine->mmio_base == offset) 154 return engine; 155 156 return NULL; 157 } 158 159 #define offset_to_fence_num(offset) \ 160 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 161 162 #define fence_num_to_offset(num) \ 163 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 164 165 166 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 167 { 168 switch (reason) { 169 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 170 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 171 break; 172 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 173 pr_err("Graphics resource is not enough for the guest\n"); 174 break; 175 case GVT_FAILSAFE_GUEST_ERR: 176 pr_err("GVT Internal error for the guest\n"); 177 break; 178 default: 179 break; 180 } 181 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 182 vgpu->failsafe = true; 183 } 184 185 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 186 unsigned int fence_num, void *p_data, unsigned int bytes) 187 { 188 unsigned int max_fence = vgpu_fence_sz(vgpu); 189 190 if (fence_num >= max_fence) { 191 gvt_vgpu_err("access oob fence reg %d/%d\n", 192 fence_num, max_fence); 193 194 /* When guest access oob fence regs without access 195 * pv_info first, we treat guest not supporting GVT, 196 * and we will let vgpu enter failsafe mode. 197 */ 198 if (!vgpu->pv_notified) 199 enter_failsafe_mode(vgpu, 200 GVT_FAILSAFE_UNSUPPORTED_GUEST); 201 202 memset(p_data, 0, bytes); 203 return -EINVAL; 204 } 205 return 0; 206 } 207 208 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, 209 unsigned int offset, void *p_data, unsigned int bytes) 210 { 211 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; 212 213 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) { 214 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) 215 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); 216 else if (!ips) 217 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id); 218 else { 219 /* All engines must be enabled together for vGPU, 220 * since we don't know which engine the ppgtt will 221 * bind to when shadowing. 222 */ 223 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n", 224 ips); 225 return -EINVAL; 226 } 227 } 228 229 write_vreg(vgpu, offset, p_data, bytes); 230 return 0; 231 } 232 233 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 234 void *p_data, unsigned int bytes) 235 { 236 int ret; 237 238 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 239 p_data, bytes); 240 if (ret) 241 return ret; 242 read_vreg(vgpu, off, p_data, bytes); 243 return 0; 244 } 245 246 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 247 void *p_data, unsigned int bytes) 248 { 249 struct intel_gvt *gvt = vgpu->gvt; 250 unsigned int fence_num = offset_to_fence_num(off); 251 int ret; 252 253 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 254 if (ret) 255 return ret; 256 write_vreg(vgpu, off, p_data, bytes); 257 258 mmio_hw_access_pre(gvt->gt); 259 intel_vgpu_write_fence(vgpu, fence_num, 260 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 261 mmio_hw_access_post(gvt->gt); 262 return 0; 263 } 264 265 #define CALC_MODE_MASK_REG(old, new) \ 266 (((new) & GENMASK(31, 16)) \ 267 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 268 | ((new) & ((new) >> 16)))) 269 270 static int mul_force_wake_write(struct intel_vgpu *vgpu, 271 unsigned int offset, void *p_data, unsigned int bytes) 272 { 273 u32 old, new; 274 u32 ack_reg_offset; 275 276 old = vgpu_vreg(vgpu, offset); 277 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 278 279 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) { 280 switch (offset) { 281 case FORCEWAKE_RENDER_GEN9_REG: 282 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 283 break; 284 case FORCEWAKE_GT_GEN9_REG: 285 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG; 286 break; 287 case FORCEWAKE_MEDIA_GEN9_REG: 288 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 289 break; 290 default: 291 /*should not hit here*/ 292 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 293 return -EINVAL; 294 } 295 } else { 296 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 297 } 298 299 vgpu_vreg(vgpu, offset) = new; 300 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 301 return 0; 302 } 303 304 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 305 void *p_data, unsigned int bytes) 306 { 307 intel_engine_mask_t engine_mask = 0; 308 u32 data; 309 310 write_vreg(vgpu, offset, p_data, bytes); 311 data = vgpu_vreg(vgpu, offset); 312 313 if (data & GEN6_GRDOM_FULL) { 314 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 315 engine_mask = ALL_ENGINES; 316 } else { 317 if (data & GEN6_GRDOM_RENDER) { 318 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 319 engine_mask |= BIT(RCS0); 320 } 321 if (data & GEN6_GRDOM_MEDIA) { 322 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 323 engine_mask |= BIT(VCS0); 324 } 325 if (data & GEN6_GRDOM_BLT) { 326 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 327 engine_mask |= BIT(BCS0); 328 } 329 if (data & GEN6_GRDOM_VECS) { 330 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 331 engine_mask |= BIT(VECS0); 332 } 333 if (data & GEN8_GRDOM_MEDIA2) { 334 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 335 engine_mask |= BIT(VCS1); 336 } 337 if (data & GEN9_GRDOM_GUC) { 338 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id); 339 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; 340 } 341 engine_mask &= vgpu->gvt->gt->info.engine_mask; 342 } 343 344 /* vgpu_lock already hold by emulate mmio r/w */ 345 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 346 347 /* sw will wait for the device to ack the reset request */ 348 vgpu_vreg(vgpu, offset) = 0; 349 350 return 0; 351 } 352 353 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 354 void *p_data, unsigned int bytes) 355 { 356 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 357 } 358 359 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 360 void *p_data, unsigned int bytes) 361 { 362 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 363 } 364 365 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 366 unsigned int offset, void *p_data, unsigned int bytes) 367 { 368 write_vreg(vgpu, offset, p_data, bytes); 369 370 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 371 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 372 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 373 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 374 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 375 376 } else 377 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 378 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 379 | PP_CYCLE_DELAY_ACTIVE); 380 return 0; 381 } 382 383 static int transconf_mmio_write(struct intel_vgpu *vgpu, 384 unsigned int offset, void *p_data, unsigned int bytes) 385 { 386 write_vreg(vgpu, offset, p_data, bytes); 387 388 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 389 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 390 else 391 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 392 return 0; 393 } 394 395 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 396 void *p_data, unsigned int bytes) 397 { 398 write_vreg(vgpu, offset, p_data, bytes); 399 400 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 401 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 402 else 403 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 404 405 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 406 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 407 else 408 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 409 410 return 0; 411 } 412 413 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 414 void *p_data, unsigned int bytes) 415 { 416 switch (offset) { 417 case 0xe651c: 418 case 0xe661c: 419 case 0xe671c: 420 case 0xe681c: 421 vgpu_vreg(vgpu, offset) = 1 << 17; 422 break; 423 case 0xe6c04: 424 vgpu_vreg(vgpu, offset) = 0x3; 425 break; 426 case 0xe6e1c: 427 vgpu_vreg(vgpu, offset) = 0x2f << 16; 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 read_vreg(vgpu, offset, p_data, bytes); 434 return 0; 435 } 436 437 /* 438 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to 439 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on 440 * setup_virtual_dp_monitor(). 441 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled 442 * DPLL. Later guest driver may setup a different DPLLx when setting mode. 443 * So the correct sequence to find DP stream clock is: 444 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x. 445 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate. 446 * Then Refresh rate then can be calculated based on follow equations: 447 * Pixel clock = h_total * v_total * refresh_rate 448 * stream clock = Pixel clock 449 * ls_clk = DP bitrate 450 * Link M/N = strm_clk / ls_clk 451 */ 452 453 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 454 { 455 u32 dp_br = 0; 456 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)); 457 458 switch (ddi_pll_sel) { 459 case PORT_CLK_SEL_LCPLL_2700: 460 dp_br = 270000 * 2; 461 break; 462 case PORT_CLK_SEL_LCPLL_1350: 463 dp_br = 135000 * 2; 464 break; 465 case PORT_CLK_SEL_LCPLL_810: 466 dp_br = 81000 * 2; 467 break; 468 case PORT_CLK_SEL_SPLL: 469 { 470 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { 471 case SPLL_FREQ_810MHz: 472 dp_br = 81000 * 2; 473 break; 474 case SPLL_FREQ_1350MHz: 475 dp_br = 135000 * 2; 476 break; 477 case SPLL_FREQ_2700MHz: 478 dp_br = 270000 * 2; 479 break; 480 default: 481 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", 482 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); 483 break; 484 } 485 break; 486 } 487 case PORT_CLK_SEL_WRPLL1: 488 case PORT_CLK_SEL_WRPLL2: 489 { 490 u32 wrpll_ctl; 491 int refclk, n, p, r; 492 493 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) 494 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1)); 495 else 496 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2)); 497 498 switch (wrpll_ctl & WRPLL_REF_MASK) { 499 case WRPLL_REF_PCH_SSC: 500 refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; 501 break; 502 case WRPLL_REF_LCPLL: 503 refclk = 2700000; 504 break; 505 default: 506 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", 507 vgpu->id, port_name(port), wrpll_ctl); 508 goto out; 509 } 510 511 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK; 512 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 513 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 514 515 dp_br = (refclk * n / 10) / (p * r) * 2; 516 break; 517 } 518 default: 519 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", 520 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port))); 521 break; 522 } 523 524 out: 525 return dp_br; 526 } 527 528 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 529 { 530 u32 dp_br = 0; 531 int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc; 532 enum dpio_phy phy = DPIO_PHY0; 533 enum dpio_channel ch = DPIO_CH0; 534 struct dpll clock = {0}; 535 u32 temp; 536 537 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */ 538 switch (port) { 539 case PORT_A: 540 phy = DPIO_PHY1; 541 ch = DPIO_CH0; 542 break; 543 case PORT_B: 544 phy = DPIO_PHY0; 545 ch = DPIO_CH0; 546 break; 547 case PORT_C: 548 phy = DPIO_PHY0; 549 ch = DPIO_CH1; 550 break; 551 default: 552 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port)); 553 goto out; 554 } 555 556 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)); 557 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) { 558 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", 559 vgpu->id, port_name(port), temp); 560 goto out; 561 } 562 563 clock.m1 = 2; 564 clock.m2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0)) & PORT_PLL_M2_MASK) << 22; 565 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE) 566 clock.m2 |= vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)) & PORT_PLL_M2_FRAC_MASK; 567 clock.n = (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)) & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 568 clock.p1 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 569 clock.p2 = (vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)) & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 570 clock.m = clock.m1 * clock.m2; 571 clock.p = clock.p1 * clock.p2; 572 573 if (clock.n == 0 || clock.p == 0) { 574 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port)); 575 goto out; 576 } 577 578 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22); 579 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p); 580 581 dp_br = clock.dot / 5; 582 583 out: 584 return dp_br; 585 } 586 587 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) 588 { 589 u32 dp_br = 0; 590 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0; 591 592 /* Find the enabled DPLL for the DDI/PORT */ 593 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) && 594 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) { 595 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & 596 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >> 597 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port); 598 } else { 599 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n", 600 vgpu->id, port_name(port)); 601 return dp_br; 602 } 603 604 /* Find PLL output frequency from correct DPLL, and get bir rate */ 605 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & 606 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >> 607 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) { 608 case DPLL_CTRL1_LINK_RATE_810: 609 dp_br = 81000 * 2; 610 break; 611 case DPLL_CTRL1_LINK_RATE_1080: 612 dp_br = 108000 * 2; 613 break; 614 case DPLL_CTRL1_LINK_RATE_1350: 615 dp_br = 135000 * 2; 616 break; 617 case DPLL_CTRL1_LINK_RATE_1620: 618 dp_br = 162000 * 2; 619 break; 620 case DPLL_CTRL1_LINK_RATE_2160: 621 dp_br = 216000 * 2; 622 break; 623 case DPLL_CTRL1_LINK_RATE_2700: 624 dp_br = 270000 * 2; 625 break; 626 default: 627 dp_br = 0; 628 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n", 629 vgpu->id, port_name(port), dpll_id); 630 } 631 632 return dp_br; 633 } 634 635 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) 636 { 637 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 638 enum port port; 639 u32 dp_br, link_m, link_n, htotal, vtotal; 640 641 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ 642 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & 643 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 644 if (port != PORT_B && port != PORT_D) { 645 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); 646 return; 647 } 648 649 /* Calculate DP bitrate from PLL */ 650 if (IS_BROADWELL(dev_priv)) 651 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port); 652 else if (IS_BROXTON(dev_priv)) 653 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port); 654 else 655 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); 656 657 /* Get DP link symbol clock M/N */ 658 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); 659 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); 660 661 /* Get H/V total from transcoder timing */ 662 htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); 663 vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); 664 665 if (dp_br && link_n && htotal && vtotal) { 666 u64 pixel_clk = 0; 667 u32 new_rate = 0; 668 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k); 669 670 /* Calcuate pixel clock by (ls_clk * M / N) */ 671 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n); 672 pixel_clk *= MSEC_PER_SEC; 673 674 /* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */ 675 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1)); 676 677 if (*old_rate != new_rate) 678 *old_rate = new_rate; 679 680 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n", 681 vgpu->id, pipe_name(PIPE_A), new_rate); 682 } 683 } 684 685 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 686 void *p_data, unsigned int bytes) 687 { 688 u32 data; 689 690 write_vreg(vgpu, offset, p_data, bytes); 691 data = vgpu_vreg(vgpu, offset); 692 693 if (data & PIPECONF_ENABLE) { 694 vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE; 695 vgpu_update_refresh_rate(vgpu); 696 vgpu_update_vblank_emulation(vgpu, true); 697 } else { 698 vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE; 699 vgpu_update_vblank_emulation(vgpu, false); 700 } 701 return 0; 702 } 703 704 /* sorted in ascending order */ 705 static i915_reg_t force_nonpriv_white_list[] = { 706 _MMIO(0xd80), 707 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 708 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 709 CL_PRIMITIVES_COUNT, //_MMIO(0x2340) 710 PS_INVOCATION_COUNT, //_MMIO(0x2348) 711 PS_DEPTH_COUNT, //_MMIO(0x2350) 712 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 713 _MMIO(0x2690), 714 _MMIO(0x2694), 715 _MMIO(0x2698), 716 _MMIO(0x2754), 717 _MMIO(0x28a0), 718 _MMIO(0x4de0), 719 _MMIO(0x4de4), 720 _MMIO(0x4dfc), 721 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 722 _MMIO(0x7014), 723 HDC_CHICKEN0,//_MMIO(0x7300) 724 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 725 _MMIO(0x7700), 726 _MMIO(0x7704), 727 _MMIO(0x7708), 728 _MMIO(0x770c), 729 _MMIO(0x83a8), 730 _MMIO(0xb110), 731 GEN8_L3SQCREG4,//_MMIO(0xb118) 732 _MMIO(0xe100), 733 _MMIO(0xe18c), 734 _MMIO(0xe48c), 735 _MMIO(0xe5f4), 736 _MMIO(0x64844), 737 }; 738 739 /* a simple bsearch */ 740 static inline bool in_whitelist(u32 reg) 741 { 742 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 743 i915_reg_t *array = force_nonpriv_white_list; 744 745 while (left < right) { 746 int mid = (left + right)/2; 747 748 if (reg > array[mid].reg) 749 left = mid + 1; 750 else if (reg < array[mid].reg) 751 right = mid; 752 else 753 return true; 754 } 755 return false; 756 } 757 758 static int force_nonpriv_write(struct intel_vgpu *vgpu, 759 unsigned int offset, void *p_data, unsigned int bytes) 760 { 761 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); 762 const struct intel_engine_cs *engine = 763 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 764 765 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) { 766 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 767 vgpu->id, offset, bytes); 768 return -EINVAL; 769 } 770 771 if (!in_whitelist(reg_nonpriv) && 772 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { 773 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", 774 vgpu->id, reg_nonpriv, offset); 775 } else 776 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 777 778 return 0; 779 } 780 781 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 782 void *p_data, unsigned int bytes) 783 { 784 write_vreg(vgpu, offset, p_data, bytes); 785 786 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 787 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 788 } else { 789 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 790 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 791 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 792 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 793 } 794 return 0; 795 } 796 797 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 798 unsigned int offset, void *p_data, unsigned int bytes) 799 { 800 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 801 return 0; 802 } 803 804 #define FDI_LINK_TRAIN_PATTERN1 0 805 #define FDI_LINK_TRAIN_PATTERN2 1 806 807 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 808 { 809 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 810 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 811 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 812 813 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 814 (rx_ctl & FDI_RX_ENABLE) && 815 (rx_ctl & FDI_AUTO_TRAINING) && 816 (tx_ctl & DP_TP_CTL_ENABLE) && 817 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 818 return 1; 819 else 820 return 0; 821 } 822 823 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 824 enum pipe pipe, unsigned int train_pattern) 825 { 826 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 827 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 828 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 829 unsigned int fdi_iir_check_bits; 830 831 fdi_rx_imr = FDI_RX_IMR(pipe); 832 fdi_tx_ctl = FDI_TX_CTL(pipe); 833 fdi_rx_ctl = FDI_RX_CTL(pipe); 834 835 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 836 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 837 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 838 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 839 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 840 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 841 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 842 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 843 } else { 844 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 845 return -EINVAL; 846 } 847 848 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 849 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 850 851 /* If imr bit has been masked */ 852 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 853 return 0; 854 855 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 856 == fdi_tx_check_bits) 857 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 858 == fdi_rx_check_bits)) 859 return 1; 860 else 861 return 0; 862 } 863 864 #define INVALID_INDEX (~0U) 865 866 static unsigned int calc_index(unsigned int offset, unsigned int start, 867 unsigned int next, unsigned int end, i915_reg_t i915_end) 868 { 869 unsigned int range = next - start; 870 871 if (!end) 872 end = i915_mmio_reg_offset(i915_end); 873 if (offset < start || offset > end) 874 return INVALID_INDEX; 875 offset -= start; 876 return offset / range; 877 } 878 879 #define FDI_RX_CTL_TO_PIPE(offset) \ 880 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 881 882 #define FDI_TX_CTL_TO_PIPE(offset) \ 883 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 884 885 #define FDI_RX_IMR_TO_PIPE(offset) \ 886 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 887 888 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 889 unsigned int offset, void *p_data, unsigned int bytes) 890 { 891 i915_reg_t fdi_rx_iir; 892 unsigned int index; 893 int ret; 894 895 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 896 index = FDI_RX_CTL_TO_PIPE(offset); 897 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 898 index = FDI_TX_CTL_TO_PIPE(offset); 899 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 900 index = FDI_RX_IMR_TO_PIPE(offset); 901 else { 902 gvt_vgpu_err("Unsupport registers %x\n", offset); 903 return -EINVAL; 904 } 905 906 write_vreg(vgpu, offset, p_data, bytes); 907 908 fdi_rx_iir = FDI_RX_IIR(index); 909 910 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 911 if (ret < 0) 912 return ret; 913 if (ret) 914 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 915 916 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 917 if (ret < 0) 918 return ret; 919 if (ret) 920 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 921 922 if (offset == _FDI_RXA_CTL) 923 if (fdi_auto_training_started(vgpu)) 924 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 925 DP_TP_STATUS_AUTOTRAIN_DONE; 926 return 0; 927 } 928 929 #define DP_TP_CTL_TO_PORT(offset) \ 930 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 931 932 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 933 void *p_data, unsigned int bytes) 934 { 935 i915_reg_t status_reg; 936 unsigned int index; 937 u32 data; 938 939 write_vreg(vgpu, offset, p_data, bytes); 940 941 index = DP_TP_CTL_TO_PORT(offset); 942 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 943 if (data == 0x2) { 944 status_reg = DP_TP_STATUS(index); 945 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 946 } 947 return 0; 948 } 949 950 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 951 unsigned int offset, void *p_data, unsigned int bytes) 952 { 953 u32 reg_val; 954 u32 sticky_mask; 955 956 reg_val = *((u32 *)p_data); 957 sticky_mask = GENMASK(27, 26) | (1 << 24); 958 959 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 960 (vgpu_vreg(vgpu, offset) & sticky_mask); 961 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 962 return 0; 963 } 964 965 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 966 unsigned int offset, void *p_data, unsigned int bytes) 967 { 968 u32 data; 969 970 write_vreg(vgpu, offset, p_data, bytes); 971 data = vgpu_vreg(vgpu, offset); 972 973 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 974 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 975 return 0; 976 } 977 978 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 979 unsigned int offset, void *p_data, unsigned int bytes) 980 { 981 u32 data; 982 983 write_vreg(vgpu, offset, p_data, bytes); 984 data = vgpu_vreg(vgpu, offset); 985 986 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 987 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 988 else 989 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 990 return 0; 991 } 992 993 #define DSPSURF_TO_PIPE(offset) \ 994 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 995 996 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 997 void *p_data, unsigned int bytes) 998 { 999 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1000 u32 pipe = DSPSURF_TO_PIPE(offset); 1001 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); 1002 1003 write_vreg(vgpu, offset, p_data, bytes); 1004 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1005 1006 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1007 1008 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) 1009 intel_vgpu_trigger_virtual_event(vgpu, event); 1010 else 1011 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1012 1013 return 0; 1014 } 1015 1016 #define SPRSURF_TO_PIPE(offset) \ 1017 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 1018 1019 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1020 void *p_data, unsigned int bytes) 1021 { 1022 u32 pipe = SPRSURF_TO_PIPE(offset); 1023 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0); 1024 1025 write_vreg(vgpu, offset, p_data, bytes); 1026 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1027 1028 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP) 1029 intel_vgpu_trigger_virtual_event(vgpu, event); 1030 else 1031 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1032 1033 return 0; 1034 } 1035 1036 static int reg50080_mmio_write(struct intel_vgpu *vgpu, 1037 unsigned int offset, void *p_data, 1038 unsigned int bytes) 1039 { 1040 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1041 enum pipe pipe = REG_50080_TO_PIPE(offset); 1042 enum plane_id plane = REG_50080_TO_PLANE(offset); 1043 int event = SKL_FLIP_EVENT(pipe, plane); 1044 1045 write_vreg(vgpu, offset, p_data, bytes); 1046 if (plane == PLANE_PRIMARY) { 1047 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1048 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; 1049 } else { 1050 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); 1051 } 1052 1053 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC) 1054 intel_vgpu_trigger_virtual_event(vgpu, event); 1055 else 1056 set_bit(event, vgpu->irq.flip_done_event[pipe]); 1057 1058 return 0; 1059 } 1060 1061 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 1062 unsigned int reg) 1063 { 1064 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; 1065 enum intel_gvt_event_type event; 1066 1067 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) 1068 event = AUX_CHANNEL_A; 1069 else if (reg == _PCH_DPB_AUX_CH_CTL || 1070 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) 1071 event = AUX_CHANNEL_B; 1072 else if (reg == _PCH_DPC_AUX_CH_CTL || 1073 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) 1074 event = AUX_CHANNEL_C; 1075 else if (reg == _PCH_DPD_AUX_CH_CTL || 1076 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) 1077 event = AUX_CHANNEL_D; 1078 else { 1079 drm_WARN_ON(&dev_priv->drm, true); 1080 return -EINVAL; 1081 } 1082 1083 intel_vgpu_trigger_virtual_event(vgpu, event); 1084 return 0; 1085 } 1086 1087 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 1088 unsigned int reg, int len, bool data_valid) 1089 { 1090 /* mark transaction done */ 1091 value |= DP_AUX_CH_CTL_DONE; 1092 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 1093 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 1094 1095 if (data_valid) 1096 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 1097 else 1098 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 1099 1100 /* message size */ 1101 value &= ~(0xf << 20); 1102 value |= (len << 20); 1103 vgpu_vreg(vgpu, reg) = value; 1104 1105 if (value & DP_AUX_CH_CTL_INTERRUPT) 1106 return trigger_aux_channel_interrupt(vgpu, reg); 1107 return 0; 1108 } 1109 1110 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 1111 u8 t) 1112 { 1113 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 1114 /* training pattern 1 for CR */ 1115 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 1116 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 1117 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 1118 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 1119 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1120 DPCD_TRAINING_PATTERN_2) { 1121 /* training pattern 2 for EQ */ 1122 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 1123 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 1124 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 1125 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 1126 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 1127 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 1128 /* set INTERLANE_ALIGN_DONE */ 1129 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 1130 DPCD_INTERLANE_ALIGN_DONE; 1131 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 1132 DPCD_LINK_TRAINING_DISABLED) { 1133 /* finish link training */ 1134 /* set sink status as synchronized */ 1135 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 1136 } 1137 } 1138 1139 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 1140 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 1141 1142 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 1143 1144 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 1145 1146 #define dpy_is_valid_port(port) \ 1147 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 1148 1149 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 1150 unsigned int offset, void *p_data, unsigned int bytes) 1151 { 1152 struct intel_vgpu_display *display = &vgpu->display; 1153 int msg, addr, ctrl, op, len; 1154 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 1155 struct intel_vgpu_dpcd_data *dpcd = NULL; 1156 struct intel_vgpu_port *port = NULL; 1157 u32 data; 1158 1159 if (!dpy_is_valid_port(port_index)) { 1160 gvt_vgpu_err("Unsupported DP port access!\n"); 1161 return 0; 1162 } 1163 1164 write_vreg(vgpu, offset, p_data, bytes); 1165 data = vgpu_vreg(vgpu, offset); 1166 1167 if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) 1168 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 1169 /* SKL DPB/C/D aux ctl register changed */ 1170 return 0; 1171 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && 1172 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 1173 /* write to the data registers */ 1174 return 0; 1175 } 1176 1177 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 1178 /* just want to clear the sticky bits */ 1179 vgpu_vreg(vgpu, offset) = 0; 1180 return 0; 1181 } 1182 1183 port = &display->ports[port_index]; 1184 dpcd = port->dpcd; 1185 1186 /* read out message from DATA1 register */ 1187 msg = vgpu_vreg(vgpu, offset + 4); 1188 addr = (msg >> 8) & 0xffff; 1189 ctrl = (msg >> 24) & 0xff; 1190 len = msg & 0xff; 1191 op = ctrl >> 4; 1192 1193 if (op == GVT_AUX_NATIVE_WRITE) { 1194 int t; 1195 u8 buf[16]; 1196 1197 if ((addr + len + 1) >= DPCD_SIZE) { 1198 /* 1199 * Write request exceeds what we supported, 1200 * DCPD spec: When a Source Device is writing a DPCD 1201 * address not supported by the Sink Device, the Sink 1202 * Device shall reply with AUX NACK and “M” equal to 1203 * zero. 1204 */ 1205 1206 /* NAK the write */ 1207 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 1208 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 1209 return 0; 1210 } 1211 1212 /* 1213 * Write request format: Headr (command + address + size) occupies 1214 * 4 bytes, followed by (len + 1) bytes of data. See details at 1215 * intel_dp_aux_transfer(). 1216 */ 1217 if ((len + 1 + 4) > AUX_BURST_SIZE) { 1218 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1219 return -EINVAL; 1220 } 1221 1222 /* unpack data from vreg to buf */ 1223 for (t = 0; t < 4; t++) { 1224 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 1225 1226 buf[t * 4] = (r >> 24) & 0xff; 1227 buf[t * 4 + 1] = (r >> 16) & 0xff; 1228 buf[t * 4 + 2] = (r >> 8) & 0xff; 1229 buf[t * 4 + 3] = r & 0xff; 1230 } 1231 1232 /* write to virtual DPCD */ 1233 if (dpcd && dpcd->data_valid) { 1234 for (t = 0; t <= len; t++) { 1235 int p = addr + t; 1236 1237 dpcd->data[p] = buf[t]; 1238 /* check for link training */ 1239 if (p == DPCD_TRAINING_PATTERN_SET) 1240 dp_aux_ch_ctl_link_training(dpcd, 1241 buf[t]); 1242 } 1243 } 1244 1245 /* ACK the write */ 1246 vgpu_vreg(vgpu, offset + 4) = 0; 1247 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 1248 dpcd && dpcd->data_valid); 1249 return 0; 1250 } 1251 1252 if (op == GVT_AUX_NATIVE_READ) { 1253 int idx, i, ret = 0; 1254 1255 if ((addr + len + 1) >= DPCD_SIZE) { 1256 /* 1257 * read request exceeds what we supported 1258 * DPCD spec: A Sink Device receiving a Native AUX CH 1259 * read request for an unsupported DPCD address must 1260 * reply with an AUX ACK and read data set equal to 1261 * zero instead of replying with AUX NACK. 1262 */ 1263 1264 /* ACK the READ*/ 1265 vgpu_vreg(vgpu, offset + 4) = 0; 1266 vgpu_vreg(vgpu, offset + 8) = 0; 1267 vgpu_vreg(vgpu, offset + 12) = 0; 1268 vgpu_vreg(vgpu, offset + 16) = 0; 1269 vgpu_vreg(vgpu, offset + 20) = 0; 1270 1271 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1272 true); 1273 return 0; 1274 } 1275 1276 for (idx = 1; idx <= 5; idx++) { 1277 /* clear the data registers */ 1278 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 1279 } 1280 1281 /* 1282 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 1283 */ 1284 if ((len + 2) > AUX_BURST_SIZE) { 1285 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len); 1286 return -EINVAL; 1287 } 1288 1289 /* read from virtual DPCD to vreg */ 1290 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 1291 if (dpcd && dpcd->data_valid) { 1292 for (i = 1; i <= (len + 1); i++) { 1293 int t; 1294 1295 t = dpcd->data[addr + i - 1]; 1296 t <<= (24 - 8 * (i % 4)); 1297 ret |= t; 1298 1299 if ((i % 4 == 3) || (i == (len + 1))) { 1300 vgpu_vreg(vgpu, offset + 1301 (i / 4 + 1) * 4) = ret; 1302 ret = 0; 1303 } 1304 } 1305 } 1306 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 1307 dpcd && dpcd->data_valid); 1308 return 0; 1309 } 1310 1311 /* i2c transaction starts */ 1312 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 1313 1314 if (data & DP_AUX_CH_CTL_INTERRUPT) 1315 trigger_aux_channel_interrupt(vgpu, offset); 1316 return 0; 1317 } 1318 1319 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1320 void *p_data, unsigned int bytes) 1321 { 1322 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1323 write_vreg(vgpu, offset, p_data, bytes); 1324 return 0; 1325 } 1326 1327 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1328 void *p_data, unsigned int bytes) 1329 { 1330 bool vga_disable; 1331 1332 write_vreg(vgpu, offset, p_data, bytes); 1333 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1334 1335 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1336 vga_disable ? "Disable" : "Enable"); 1337 return 0; 1338 } 1339 1340 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1341 unsigned int sbi_offset) 1342 { 1343 struct intel_vgpu_display *display = &vgpu->display; 1344 int num = display->sbi.number; 1345 int i; 1346 1347 for (i = 0; i < num; ++i) 1348 if (display->sbi.registers[i].offset == sbi_offset) 1349 break; 1350 1351 if (i == num) 1352 return 0; 1353 1354 return display->sbi.registers[i].value; 1355 } 1356 1357 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1358 unsigned int offset, u32 value) 1359 { 1360 struct intel_vgpu_display *display = &vgpu->display; 1361 int num = display->sbi.number; 1362 int i; 1363 1364 for (i = 0; i < num; ++i) { 1365 if (display->sbi.registers[i].offset == offset) 1366 break; 1367 } 1368 1369 if (i == num) { 1370 if (num == SBI_REG_MAX) { 1371 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1372 return; 1373 } 1374 display->sbi.number++; 1375 } 1376 1377 display->sbi.registers[i].offset = offset; 1378 display->sbi.registers[i].value = value; 1379 } 1380 1381 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1382 void *p_data, unsigned int bytes) 1383 { 1384 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1385 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1386 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1387 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1388 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1389 sbi_offset); 1390 } 1391 read_vreg(vgpu, offset, p_data, bytes); 1392 return 0; 1393 } 1394 1395 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1396 void *p_data, unsigned int bytes) 1397 { 1398 u32 data; 1399 1400 write_vreg(vgpu, offset, p_data, bytes); 1401 data = vgpu_vreg(vgpu, offset); 1402 1403 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1404 data |= SBI_READY; 1405 1406 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1407 data |= SBI_RESPONSE_SUCCESS; 1408 1409 vgpu_vreg(vgpu, offset) = data; 1410 1411 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1412 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1413 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1414 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1415 1416 write_virtual_sbi_register(vgpu, sbi_offset, 1417 vgpu_vreg_t(vgpu, SBI_DATA)); 1418 } 1419 return 0; 1420 } 1421 1422 #define _vgtif_reg(x) \ 1423 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1424 1425 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1426 void *p_data, unsigned int bytes) 1427 { 1428 bool invalid_read = false; 1429 1430 read_vreg(vgpu, offset, p_data, bytes); 1431 1432 switch (offset) { 1433 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1434 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1435 invalid_read = true; 1436 break; 1437 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1438 _vgtif_reg(avail_rs.fence_num): 1439 if (offset + bytes > 1440 _vgtif_reg(avail_rs.fence_num) + 4) 1441 invalid_read = true; 1442 break; 1443 case 0x78010: /* vgt_caps */ 1444 case 0x7881c: 1445 break; 1446 default: 1447 invalid_read = true; 1448 break; 1449 } 1450 if (invalid_read) 1451 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1452 offset, bytes, *(u32 *)p_data); 1453 vgpu->pv_notified = true; 1454 return 0; 1455 } 1456 1457 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1458 { 1459 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1460 struct intel_vgpu_mm *mm; 1461 u64 *pdps; 1462 1463 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1464 1465 switch (notification) { 1466 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1467 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1468 fallthrough; 1469 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1470 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1471 return PTR_ERR_OR_ZERO(mm); 1472 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1473 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1474 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1475 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1476 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1477 case 1: /* Remove this in guest driver. */ 1478 break; 1479 default: 1480 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1481 } 1482 return 0; 1483 } 1484 1485 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1486 { 1487 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj; 1488 char *env[3] = {NULL, NULL, NULL}; 1489 char vmid_str[20]; 1490 char display_ready_str[20]; 1491 1492 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1493 env[0] = display_ready_str; 1494 1495 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1496 env[1] = vmid_str; 1497 1498 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1499 } 1500 1501 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1502 void *p_data, unsigned int bytes) 1503 { 1504 u32 data = *(u32 *)p_data; 1505 bool invalid_write = false; 1506 1507 switch (offset) { 1508 case _vgtif_reg(display_ready): 1509 send_display_ready_uevent(vgpu, data ? 1 : 0); 1510 break; 1511 case _vgtif_reg(g2v_notify): 1512 handle_g2v_notification(vgpu, data); 1513 break; 1514 /* add xhot and yhot to handled list to avoid error log */ 1515 case _vgtif_reg(cursor_x_hot): 1516 case _vgtif_reg(cursor_y_hot): 1517 case _vgtif_reg(pdp[0].lo): 1518 case _vgtif_reg(pdp[0].hi): 1519 case _vgtif_reg(pdp[1].lo): 1520 case _vgtif_reg(pdp[1].hi): 1521 case _vgtif_reg(pdp[2].lo): 1522 case _vgtif_reg(pdp[2].hi): 1523 case _vgtif_reg(pdp[3].lo): 1524 case _vgtif_reg(pdp[3].hi): 1525 case _vgtif_reg(execlist_context_descriptor_lo): 1526 case _vgtif_reg(execlist_context_descriptor_hi): 1527 break; 1528 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1529 invalid_write = true; 1530 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1531 break; 1532 default: 1533 invalid_write = true; 1534 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1535 offset, bytes, data); 1536 break; 1537 } 1538 1539 if (!invalid_write) 1540 write_vreg(vgpu, offset, p_data, bytes); 1541 1542 return 0; 1543 } 1544 1545 static int pf_write(struct intel_vgpu *vgpu, 1546 unsigned int offset, void *p_data, unsigned int bytes) 1547 { 1548 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1549 u32 val = *(u32 *)p_data; 1550 1551 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1552 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1553 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1554 drm_WARN_ONCE(&i915->drm, true, 1555 "VM(%d): guest is trying to scaling a plane\n", 1556 vgpu->id); 1557 return 0; 1558 } 1559 1560 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1561 } 1562 1563 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1564 unsigned int offset, void *p_data, unsigned int bytes) 1565 { 1566 write_vreg(vgpu, offset, p_data, bytes); 1567 1568 if (vgpu_vreg(vgpu, offset) & 1569 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL)) 1570 vgpu_vreg(vgpu, offset) |= 1571 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1572 else 1573 vgpu_vreg(vgpu, offset) &= 1574 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL); 1575 return 0; 1576 } 1577 1578 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu, 1579 unsigned int offset, void *p_data, unsigned int bytes) 1580 { 1581 write_vreg(vgpu, offset, p_data, bytes); 1582 1583 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST) 1584 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE; 1585 else 1586 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE; 1587 1588 return 0; 1589 } 1590 1591 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1592 unsigned int offset, void *p_data, unsigned int bytes) 1593 { 1594 write_vreg(vgpu, offset, p_data, bytes); 1595 1596 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1597 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1598 return 0; 1599 } 1600 1601 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1602 void *p_data, unsigned int bytes) 1603 { 1604 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1605 u32 mode; 1606 1607 write_vreg(vgpu, offset, p_data, bytes); 1608 mode = vgpu_vreg(vgpu, offset); 1609 1610 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1611 drm_WARN_ONCE(&i915->drm, 1, 1612 "VM(%d): iGVT-g doesn't support GuC\n", 1613 vgpu->id); 1614 return 0; 1615 } 1616 1617 return 0; 1618 } 1619 1620 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1621 void *p_data, unsigned int bytes) 1622 { 1623 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1624 u32 trtte = *(u32 *)p_data; 1625 1626 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1627 drm_WARN(&i915->drm, 1, 1628 "VM(%d): Use physical address for TRTT!\n", 1629 vgpu->id); 1630 return -EINVAL; 1631 } 1632 write_vreg(vgpu, offset, p_data, bytes); 1633 1634 return 0; 1635 } 1636 1637 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1638 void *p_data, unsigned int bytes) 1639 { 1640 write_vreg(vgpu, offset, p_data, bytes); 1641 return 0; 1642 } 1643 1644 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1645 void *p_data, unsigned int bytes) 1646 { 1647 u32 v = 0; 1648 1649 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1650 v |= (1 << 0); 1651 1652 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1653 v |= (1 << 8); 1654 1655 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1656 v |= (1 << 16); 1657 1658 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1659 v |= (1 << 24); 1660 1661 vgpu_vreg(vgpu, offset) = v; 1662 1663 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1664 } 1665 1666 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1667 void *p_data, unsigned int bytes) 1668 { 1669 u32 value = *(u32 *)p_data; 1670 u32 cmd = value & 0xff; 1671 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1672 1673 switch (cmd) { 1674 case GEN9_PCODE_READ_MEM_LATENCY: 1675 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1676 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1677 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1678 IS_COMETLAKE(vgpu->gvt->gt->i915)) { 1679 /** 1680 * "Read memory latency" command on gen9. 1681 * Below memory latency values are read 1682 * from skylake platform. 1683 */ 1684 if (!*data0) 1685 *data0 = 0x1e1a1100; 1686 else 1687 *data0 = 0x61514b3d; 1688 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) { 1689 /** 1690 * "Read memory latency" command on gen9. 1691 * Below memory latency values are read 1692 * from Broxton MRB. 1693 */ 1694 if (!*data0) 1695 *data0 = 0x16080707; 1696 else 1697 *data0 = 0x16161616; 1698 } 1699 break; 1700 case SKL_PCODE_CDCLK_CONTROL: 1701 if (IS_SKYLAKE(vgpu->gvt->gt->i915) || 1702 IS_KABYLAKE(vgpu->gvt->gt->i915) || 1703 IS_COFFEELAKE(vgpu->gvt->gt->i915) || 1704 IS_COMETLAKE(vgpu->gvt->gt->i915)) 1705 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1706 break; 1707 case GEN6_PCODE_READ_RC6VIDS: 1708 *data0 |= 0x1; 1709 break; 1710 } 1711 1712 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1713 vgpu->id, value, *data0); 1714 /** 1715 * PCODE_READY clear means ready for pcode read/write, 1716 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1717 * always emulate as pcode read/write success and ready for access 1718 * anytime, since we don't touch real physical registers here. 1719 */ 1720 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1721 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1722 } 1723 1724 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1725 void *p_data, unsigned int bytes) 1726 { 1727 u32 value = *(u32 *)p_data; 1728 const struct intel_engine_cs *engine = 1729 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1730 1731 if (value != 0 && 1732 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1733 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1734 offset, value); 1735 return -EINVAL; 1736 } 1737 1738 /* 1739 * Need to emulate all the HWSP register write to ensure host can 1740 * update the VM CSB status correctly. Here listed registers can 1741 * support BDW, SKL or other platforms with same HWSP registers. 1742 */ 1743 if (unlikely(!engine)) { 1744 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1745 offset); 1746 return -EINVAL; 1747 } 1748 vgpu->hws_pga[engine->id] = value; 1749 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1750 vgpu->id, value, offset); 1751 1752 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1753 } 1754 1755 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1756 unsigned int offset, void *p_data, unsigned int bytes) 1757 { 1758 u32 v = *(u32 *)p_data; 1759 1760 if (IS_BROXTON(vgpu->gvt->gt->i915)) 1761 v &= (1 << 31) | (1 << 29); 1762 else 1763 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1764 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1765 v |= (v >> 1); 1766 1767 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1768 } 1769 1770 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1771 void *p_data, unsigned int bytes) 1772 { 1773 u32 v = *(u32 *)p_data; 1774 1775 /* other bits are MBZ. */ 1776 v &= (1 << 31) | (1 << 30); 1777 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1778 1779 vgpu_vreg(vgpu, offset) = v; 1780 1781 return 0; 1782 } 1783 1784 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu, 1785 unsigned int offset, void *p_data, unsigned int bytes) 1786 { 1787 u32 v = *(u32 *)p_data; 1788 1789 if (v & BXT_DE_PLL_PLL_ENABLE) 1790 v |= BXT_DE_PLL_LOCK; 1791 1792 vgpu_vreg(vgpu, offset) = v; 1793 1794 return 0; 1795 } 1796 1797 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu, 1798 unsigned int offset, void *p_data, unsigned int bytes) 1799 { 1800 u32 v = *(u32 *)p_data; 1801 1802 if (v & PORT_PLL_ENABLE) 1803 v |= PORT_PLL_LOCK; 1804 1805 vgpu_vreg(vgpu, offset) = v; 1806 1807 return 0; 1808 } 1809 1810 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu, 1811 unsigned int offset, void *p_data, unsigned int bytes) 1812 { 1813 u32 v = *(u32 *)p_data; 1814 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; 1815 1816 switch (offset) { 1817 case _PHY_CTL_FAMILY_EDP: 1818 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data; 1819 break; 1820 case _PHY_CTL_FAMILY_DDI: 1821 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data; 1822 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data; 1823 break; 1824 } 1825 1826 vgpu_vreg(vgpu, offset) = v; 1827 1828 return 0; 1829 } 1830 1831 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu, 1832 unsigned int offset, void *p_data, unsigned int bytes) 1833 { 1834 u32 v = vgpu_vreg(vgpu, offset); 1835 1836 v &= ~UNIQUE_TRANGE_EN_METHOD; 1837 1838 vgpu_vreg(vgpu, offset) = v; 1839 1840 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1841 } 1842 1843 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu, 1844 unsigned int offset, void *p_data, unsigned int bytes) 1845 { 1846 u32 v = *(u32 *)p_data; 1847 1848 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) { 1849 vgpu_vreg(vgpu, offset - 0x600) = v; 1850 vgpu_vreg(vgpu, offset - 0x800) = v; 1851 } else { 1852 vgpu_vreg(vgpu, offset - 0x400) = v; 1853 vgpu_vreg(vgpu, offset - 0x600) = v; 1854 } 1855 1856 vgpu_vreg(vgpu, offset) = v; 1857 1858 return 0; 1859 } 1860 1861 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu, 1862 unsigned int offset, void *p_data, unsigned int bytes) 1863 { 1864 u32 v = *(u32 *)p_data; 1865 1866 if (v & BIT(0)) { 1867 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &= 1868 ~PHY_RESERVED; 1869 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |= 1870 PHY_POWER_GOOD; 1871 } 1872 1873 if (v & BIT(1)) { 1874 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= 1875 ~PHY_RESERVED; 1876 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= 1877 PHY_POWER_GOOD; 1878 } 1879 1880 1881 vgpu_vreg(vgpu, offset) = v; 1882 1883 return 0; 1884 } 1885 1886 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu, 1887 unsigned int offset, void *p_data, unsigned int bytes) 1888 { 1889 vgpu_vreg(vgpu, offset) = 0; 1890 return 0; 1891 } 1892 1893 /* 1894 * FixMe: 1895 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did: 1896 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.) 1897 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing 1898 * these MI_BATCH_BUFFER. 1899 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT 1900 * PML4 PTE: PAT(0) PCD(1) PWT(1). 1901 * The performance is still expected to be low, will need further improvement. 1902 */ 1903 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset, 1904 void *p_data, unsigned int bytes) 1905 { 1906 u64 pat = 1907 GEN8_PPAT(0, CHV_PPAT_SNOOP) | 1908 GEN8_PPAT(1, 0) | 1909 GEN8_PPAT(2, 0) | 1910 GEN8_PPAT(3, CHV_PPAT_SNOOP) | 1911 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 1912 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 1913 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 1914 GEN8_PPAT(7, CHV_PPAT_SNOOP); 1915 1916 vgpu_vreg(vgpu, offset) = lower_32_bits(pat); 1917 1918 return 0; 1919 } 1920 1921 static int guc_status_read(struct intel_vgpu *vgpu, 1922 unsigned int offset, void *p_data, 1923 unsigned int bytes) 1924 { 1925 /* keep MIA_IN_RESET before clearing */ 1926 read_vreg(vgpu, offset, p_data, bytes); 1927 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET; 1928 return 0; 1929 } 1930 1931 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1932 unsigned int offset, void *p_data, unsigned int bytes) 1933 { 1934 struct intel_gvt *gvt = vgpu->gvt; 1935 const struct intel_engine_cs *engine = 1936 intel_gvt_render_mmio_to_engine(gvt, offset); 1937 1938 /** 1939 * Read HW reg in following case 1940 * a. the offset isn't a ring mmio 1941 * b. the offset's ring is running on hw. 1942 * c. the offset is ring time stamp mmio 1943 */ 1944 1945 if (!engine || 1946 vgpu == gvt->scheduler.engine_owner[engine->id] || 1947 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) || 1948 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) { 1949 mmio_hw_access_pre(gvt->gt); 1950 vgpu_vreg(vgpu, offset) = 1951 intel_uncore_read(gvt->gt->uncore, _MMIO(offset)); 1952 mmio_hw_access_post(gvt->gt); 1953 } 1954 1955 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1956 } 1957 1958 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1959 void *p_data, unsigned int bytes) 1960 { 1961 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 1962 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 1963 struct intel_vgpu_execlist *execlist; 1964 u32 data = *(u32 *)p_data; 1965 int ret = 0; 1966 1967 if (drm_WARN_ON(&i915->drm, !engine)) 1968 return -EINVAL; 1969 1970 /* 1971 * Due to d3_entered is used to indicate skipping PPGTT invalidation on 1972 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after 1973 * vGPU reset if in resuming. 1974 * In S0ix exit, the device power state also transite from D3 to D0 as 1975 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After 1976 * S0ix exit, all engines continue to work. However the d3_entered 1977 * remains set which will break next vGPU reset logic (miss the expected 1978 * PPGTT invalidation). 1979 * Engines can only work in D0. Thus the 1st elsp write gives GVT a 1980 * chance to clear d3_entered. 1981 */ 1982 if (vgpu->d3_entered) 1983 vgpu->d3_entered = false; 1984 1985 execlist = &vgpu->submission.execlist[engine->id]; 1986 1987 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1988 if (execlist->elsp_dwords.index == 3) { 1989 ret = intel_vgpu_submit_execlist(vgpu, engine); 1990 if(ret) 1991 gvt_vgpu_err("fail submit workload on ring %s\n", 1992 engine->name); 1993 } 1994 1995 ++execlist->elsp_dwords.index; 1996 execlist->elsp_dwords.index &= 0x3; 1997 return ret; 1998 } 1999 2000 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 2001 void *p_data, unsigned int bytes) 2002 { 2003 u32 data = *(u32 *)p_data; 2004 const struct intel_engine_cs *engine = 2005 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset); 2006 bool enable_execlist; 2007 int ret; 2008 2009 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1); 2010 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2011 IS_COMETLAKE(vgpu->gvt->gt->i915)) 2012 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2); 2013 write_vreg(vgpu, offset, p_data, bytes); 2014 2015 if (IS_MASKED_BITS_ENABLED(data, 1)) { 2016 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2017 return 0; 2018 } 2019 2020 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) || 2021 IS_COMETLAKE(vgpu->gvt->gt->i915)) && 2022 IS_MASKED_BITS_ENABLED(data, 2)) { 2023 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2024 return 0; 2025 } 2026 2027 /* when PPGTT mode enabled, we will check if guest has called 2028 * pvinfo, if not, we will treat this guest as non-gvtg-aware 2029 * guest, and stop emulating its cfg space, mmio, gtt, etc. 2030 */ 2031 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) || 2032 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) && 2033 !vgpu->pv_notified) { 2034 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2035 return 0; 2036 } 2037 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) || 2038 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) { 2039 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 2040 2041 gvt_dbg_core("EXECLIST %s on ring %s\n", 2042 (enable_execlist ? "enabling" : "disabling"), 2043 engine->name); 2044 2045 if (!enable_execlist) 2046 return 0; 2047 2048 ret = intel_vgpu_select_submission_ops(vgpu, 2049 engine->mask, 2050 INTEL_VGPU_EXECLIST_SUBMISSION); 2051 if (ret) 2052 return ret; 2053 2054 intel_vgpu_start_schedule(vgpu); 2055 } 2056 return 0; 2057 } 2058 2059 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 2060 unsigned int offset, void *p_data, unsigned int bytes) 2061 { 2062 unsigned int id = 0; 2063 2064 write_vreg(vgpu, offset, p_data, bytes); 2065 vgpu_vreg(vgpu, offset) = 0; 2066 2067 switch (offset) { 2068 case 0x4260: 2069 id = RCS0; 2070 break; 2071 case 0x4264: 2072 id = VCS0; 2073 break; 2074 case 0x4268: 2075 id = VCS1; 2076 break; 2077 case 0x426c: 2078 id = BCS0; 2079 break; 2080 case 0x4270: 2081 id = VECS0; 2082 break; 2083 default: 2084 return -EINVAL; 2085 } 2086 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 2087 2088 return 0; 2089 } 2090 2091 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 2092 unsigned int offset, void *p_data, unsigned int bytes) 2093 { 2094 u32 data; 2095 2096 write_vreg(vgpu, offset, p_data, bytes); 2097 data = vgpu_vreg(vgpu, offset); 2098 2099 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET)) 2100 data |= RESET_CTL_READY_TO_RESET; 2101 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 2102 data &= ~RESET_CTL_READY_TO_RESET; 2103 2104 vgpu_vreg(vgpu, offset) = data; 2105 return 0; 2106 } 2107 2108 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu, 2109 unsigned int offset, void *p_data, 2110 unsigned int bytes) 2111 { 2112 u32 data = *(u32 *)p_data; 2113 2114 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); 2115 write_vreg(vgpu, offset, p_data, bytes); 2116 2117 if (IS_MASKED_BITS_ENABLED(data, 0x10) || 2118 IS_MASKED_BITS_ENABLED(data, 0x8)) 2119 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 2120 2121 return 0; 2122 } 2123 2124 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 2125 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 2126 s, f, am, rm, d, r, w); \ 2127 if (ret) \ 2128 return ret; \ 2129 } while (0) 2130 2131 #define MMIO_DH(reg, d, r, w) \ 2132 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 2133 2134 #define MMIO_DFH(reg, d, f, r, w) \ 2135 MMIO_F(reg, 4, f, 0, 0, d, r, w) 2136 2137 #define MMIO_GM(reg, d, r, w) \ 2138 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 2139 2140 #define MMIO_GM_RDR(reg, d, r, w) \ 2141 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 2142 2143 #define MMIO_RO(reg, d, f, rm, r, w) \ 2144 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 2145 2146 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 2147 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 2148 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 2149 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 2150 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 2151 if (HAS_ENGINE(gvt->gt, VCS1)) \ 2152 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 2153 } while (0) 2154 2155 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 2156 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 2157 2158 #define MMIO_RING_GM(prefix, d, r, w) \ 2159 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 2160 2161 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 2162 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 2163 2164 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 2165 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 2166 2167 static int init_generic_mmio_info(struct intel_gvt *gvt) 2168 { 2169 struct drm_i915_private *dev_priv = gvt->gt->i915; 2170 int ret; 2171 2172 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, 2173 intel_vgpu_reg_imr_handler); 2174 2175 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 2176 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 2177 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 2178 2179 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); 2180 2181 2182 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL, 2183 gamw_echo_dev_rw_ia_write); 2184 2185 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2186 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2187 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 2188 2189 #define RING_REG(base) _MMIO((base) + 0x28) 2190 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2191 #undef RING_REG 2192 2193 #define RING_REG(base) _MMIO((base) + 0x134) 2194 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2195 #undef RING_REG 2196 2197 #define RING_REG(base) _MMIO((base) + 0x6c) 2198 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 2199 #undef RING_REG 2200 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 2201 2202 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 2203 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL); 2204 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 2205 2206 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); 2207 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); 2208 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); 2209 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); 2210 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL); 2211 2212 /* RING MODE */ 2213 #define RING_REG(base) _MMIO((base) + 0x29c) 2214 MMIO_RING_DFH(RING_REG, D_ALL, 2215 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL, 2216 ring_mode_mmio_write); 2217 #undef RING_REG 2218 2219 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2220 NULL, NULL); 2221 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2222 NULL, NULL); 2223 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 2224 mmio_read_from_hw, NULL); 2225 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 2226 mmio_read_from_hw, NULL); 2227 2228 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2229 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2230 NULL, NULL); 2231 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2232 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2233 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2234 2235 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2236 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2237 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2238 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL, 2239 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2240 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2241 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 2242 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2243 NULL, NULL); 2244 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 2245 NULL, NULL); 2246 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 2247 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 2248 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 2249 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 2250 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 2251 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 2252 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2253 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2254 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2255 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2256 2257 /* display */ 2258 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 2259 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 2260 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 2261 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 2262 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 2263 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, 2264 reg50080_mmio_write); 2265 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 2266 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, 2267 reg50080_mmio_write); 2268 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 2269 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, 2270 reg50080_mmio_write); 2271 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 2272 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, 2273 reg50080_mmio_write); 2274 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 2275 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, 2276 reg50080_mmio_write); 2277 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 2278 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, 2279 reg50080_mmio_write); 2280 2281 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 2282 gmbus_mmio_write); 2283 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 2284 2285 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2286 dp_aux_ch_ctl_mmio_write); 2287 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2288 dp_aux_ch_ctl_mmio_write); 2289 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 2290 dp_aux_ch_ctl_mmio_write); 2291 2292 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 2293 2294 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 2295 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 2296 2297 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 2298 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 2299 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 2300 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2301 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2302 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2303 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 2304 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 2305 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 2306 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2307 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2308 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2309 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2310 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2311 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2312 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2313 2314 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2315 PORTA_HOTPLUG_STATUS_MASK 2316 | PORTB_HOTPLUG_STATUS_MASK 2317 | PORTC_HOTPLUG_STATUS_MASK 2318 | PORTD_HOTPLUG_STATUS_MASK, 2319 NULL, NULL); 2320 2321 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2322 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2323 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2324 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2325 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2326 2327 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2328 dp_aux_ch_ctl_mmio_write); 2329 2330 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2331 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2332 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2333 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2334 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2335 2336 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2337 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2338 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2339 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2340 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2341 2342 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2343 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2344 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2345 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2346 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2347 2348 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2349 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2350 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2351 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2352 2353 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2354 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2355 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2356 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2357 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2358 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2359 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2360 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write); 2361 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write); 2362 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write); 2363 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write); 2364 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2365 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2366 2367 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2368 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2369 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2370 2371 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2372 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2373 2374 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2375 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2376 2377 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2378 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2379 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2380 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2381 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2382 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2383 2384 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2385 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2386 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2387 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2388 2389 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2390 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2391 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2392 2393 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2394 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2395 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2396 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2397 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2398 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2399 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2400 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2401 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2402 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2404 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2405 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2406 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2407 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2408 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2409 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2410 2411 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2412 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL); 2413 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2414 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2415 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2416 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2417 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2418 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2419 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2420 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2421 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2422 2423 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2424 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write); 2425 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL); 2426 2427 return 0; 2428 } 2429 2430 static int init_bdw_mmio_info(struct intel_gvt *gvt) 2431 { 2432 int ret; 2433 2434 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2435 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2436 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2437 2438 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2439 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2440 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2441 2442 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2443 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2444 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2445 2446 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2447 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2448 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2449 2450 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2451 intel_vgpu_reg_imr_handler); 2452 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2453 intel_vgpu_reg_ier_handler); 2454 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2455 intel_vgpu_reg_iir_handler); 2456 2457 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2458 intel_vgpu_reg_imr_handler); 2459 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2460 intel_vgpu_reg_ier_handler); 2461 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2462 intel_vgpu_reg_iir_handler); 2463 2464 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2465 intel_vgpu_reg_imr_handler); 2466 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2467 intel_vgpu_reg_ier_handler); 2468 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2469 intel_vgpu_reg_iir_handler); 2470 2471 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2472 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2473 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2474 2475 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2476 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2477 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2478 2479 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2480 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2481 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2482 2483 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2484 intel_vgpu_reg_master_irq_handler); 2485 2486 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, 2487 mmio_read_from_hw, NULL); 2488 2489 #define RING_REG(base) _MMIO((base) + 0xd0) 2490 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2491 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2492 ring_reset_ctl_write); 2493 #undef RING_REG 2494 2495 #define RING_REG(base) _MMIO((base) + 0x230) 2496 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2497 #undef RING_REG 2498 2499 #define RING_REG(base) _MMIO((base) + 0x234) 2500 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, 2501 NULL, NULL); 2502 #undef RING_REG 2503 2504 #define RING_REG(base) _MMIO((base) + 0x244) 2505 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2506 #undef RING_REG 2507 2508 #define RING_REG(base) _MMIO((base) + 0x370) 2509 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2510 #undef RING_REG 2511 2512 #define RING_REG(base) _MMIO((base) + 0x3a0) 2513 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2514 #undef RING_REG 2515 2516 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2517 2518 #define RING_REG(base) _MMIO((base) + 0x270) 2519 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2520 #undef RING_REG 2521 2522 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2523 2524 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2525 2526 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2527 NULL, NULL); 2528 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2529 NULL, NULL); 2530 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2531 2532 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2533 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2534 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2535 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2536 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2537 2538 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, 2539 D_BDW_PLUS, NULL, force_nonpriv_write); 2540 2541 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2542 2543 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2544 2545 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2546 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2547 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2548 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2549 2550 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2551 2552 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2553 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2554 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2555 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2556 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2557 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2558 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2559 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2560 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2561 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2562 return 0; 2563 } 2564 2565 static int init_skl_mmio_info(struct intel_gvt *gvt) 2566 { 2567 struct drm_i915_private *dev_priv = gvt->gt->i915; 2568 int ret; 2569 2570 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2571 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2572 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2573 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL); 2574 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2575 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2576 2577 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2578 dp_aux_ch_ctl_mmio_write); 2579 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2580 dp_aux_ch_ctl_mmio_write); 2581 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2582 dp_aux_ch_ctl_mmio_write); 2583 2584 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write); 2585 2586 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); 2587 2588 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2589 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2590 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL); 2591 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2592 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write); 2593 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL); 2594 2595 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2596 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2597 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2598 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2599 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2600 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2601 2602 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2603 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2604 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2605 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2606 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2607 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2608 2609 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2610 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2611 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2612 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2613 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2614 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2615 2616 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2617 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2618 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2619 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2620 2621 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2622 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2623 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2624 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2625 2626 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2627 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2628 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2629 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2630 2631 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2632 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2633 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2634 2635 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2636 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2637 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2638 2639 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2640 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2641 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2642 2643 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2644 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2645 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2646 2647 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2648 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2649 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2650 2651 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2652 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2653 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2654 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2655 2656 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2657 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2658 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2659 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2660 2661 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2662 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2663 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2664 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2665 2666 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2667 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2668 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2669 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2670 2671 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2672 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2673 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2674 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2675 2676 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2677 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2678 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2679 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2680 2681 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2682 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2683 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2684 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2685 2686 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2687 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2688 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2689 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2690 2691 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2692 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2693 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2694 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2695 2696 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2697 2698 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2699 NULL, NULL); 2700 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, 2701 NULL, NULL); 2702 2703 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, 2704 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2705 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2706 NULL, NULL); 2707 2708 /* TRTT */ 2709 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2710 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2711 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2712 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2713 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2714 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE, 2715 NULL, gen9_trtte_write); 2716 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, 2717 NULL, gen9_trtt_chicken_write); 2718 2719 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2720 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2721 2722 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) 2723 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2724 NULL, csfe_chicken1_mmio_write); 2725 #undef CSFE_CHICKEN1_REG 2726 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2727 NULL, NULL); 2728 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2729 NULL, NULL); 2730 2731 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL); 2732 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2733 2734 return 0; 2735 } 2736 2737 static int init_bxt_mmio_info(struct intel_gvt *gvt) 2738 { 2739 int ret; 2740 2741 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write); 2742 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT, 2743 NULL, bxt_phy_ctl_family_write); 2744 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, 2745 NULL, bxt_phy_ctl_family_write); 2746 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, 2747 NULL, bxt_port_pll_enable_write); 2748 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, 2749 NULL, bxt_port_pll_enable_write); 2750 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL, 2751 bxt_port_pll_enable_write); 2752 2753 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT, 2754 NULL, bxt_pcs_dw12_grp_write); 2755 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT, 2756 bxt_port_tx_dw3_read, NULL); 2757 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT, 2758 NULL, bxt_pcs_dw12_grp_write); 2759 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT, 2760 bxt_port_tx_dw3_read, NULL); 2761 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, 2762 NULL, bxt_pcs_dw12_grp_write); 2763 MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT, 2764 bxt_port_tx_dw3_read, NULL); 2765 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write); 2766 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL); 2767 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2768 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); 2769 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2770 0, 0, D_BXT, NULL, NULL); 2771 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2772 0, 0, D_BXT, NULL, NULL); 2773 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2774 0, 0, D_BXT, NULL, NULL); 2775 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, 2776 0, 0, D_BXT, NULL, NULL); 2777 2778 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL); 2779 2780 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write); 2781 2782 return 0; 2783 } 2784 2785 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2786 unsigned int offset) 2787 { 2788 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2789 int num = gvt->mmio.num_mmio_block; 2790 int i; 2791 2792 for (i = 0; i < num; i++, block++) { 2793 if (offset >= i915_mmio_reg_offset(block->offset) && 2794 offset < i915_mmio_reg_offset(block->offset) + block->size) 2795 return block; 2796 } 2797 return NULL; 2798 } 2799 2800 /** 2801 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2802 * @gvt: GVT device 2803 * 2804 * This function is called at the driver unloading stage, to clean up the MMIO 2805 * information table of GVT device 2806 * 2807 */ 2808 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2809 { 2810 struct hlist_node *tmp; 2811 struct intel_gvt_mmio_info *e; 2812 int i; 2813 2814 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2815 kfree(e); 2816 2817 kfree(gvt->mmio.mmio_block); 2818 gvt->mmio.mmio_block = NULL; 2819 gvt->mmio.num_mmio_block = 0; 2820 2821 vfree(gvt->mmio.mmio_attribute); 2822 gvt->mmio.mmio_attribute = NULL; 2823 } 2824 2825 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2826 u32 size) 2827 { 2828 struct intel_gvt *gvt = iter->data; 2829 struct intel_gvt_mmio_info *info, *p; 2830 u32 start, end, i; 2831 2832 if (WARN_ON(!IS_ALIGNED(offset, 4))) 2833 return -EINVAL; 2834 2835 start = offset; 2836 end = offset + size; 2837 2838 for (i = start; i < end; i += 4) { 2839 p = intel_gvt_find_mmio_info(gvt, i); 2840 if (p) { 2841 WARN(1, "dup mmio definition offset %x\n", 2842 info->offset); 2843 2844 /* We return -EEXIST here to make GVT-g load fail. 2845 * So duplicated MMIO can be found as soon as 2846 * possible. 2847 */ 2848 return -EEXIST; 2849 } 2850 2851 info = kzalloc(sizeof(*info), GFP_KERNEL); 2852 if (!info) 2853 return -ENOMEM; 2854 2855 info->offset = i; 2856 info->read = intel_vgpu_default_mmio_read; 2857 info->write = intel_vgpu_default_mmio_write; 2858 INIT_HLIST_NODE(&info->node); 2859 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 2860 gvt->mmio.num_tracked_mmio++; 2861 } 2862 return 0; 2863 } 2864 2865 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter, 2866 u32 offset, u32 size) 2867 { 2868 struct intel_gvt *gvt = iter->data; 2869 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2870 void *ret; 2871 2872 ret = krealloc(block, 2873 (gvt->mmio.num_mmio_block + 1) * sizeof(*block), 2874 GFP_KERNEL); 2875 if (!ret) 2876 return -ENOMEM; 2877 2878 gvt->mmio.mmio_block = block = ret; 2879 2880 block += gvt->mmio.num_mmio_block; 2881 2882 memset(block, 0, sizeof(*block)); 2883 2884 block->offset = _MMIO(offset); 2885 block->size = size; 2886 2887 gvt->mmio.num_mmio_block++; 2888 2889 return 0; 2890 } 2891 2892 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset, 2893 u32 size) 2894 { 2895 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) 2896 return handle_mmio(iter, offset, size); 2897 else 2898 return handle_mmio_block(iter, offset, size); 2899 } 2900 2901 static int init_mmio_info(struct intel_gvt *gvt) 2902 { 2903 struct intel_gvt_mmio_table_iter iter = { 2904 .i915 = gvt->gt->i915, 2905 .data = gvt, 2906 .handle_mmio_cb = handle_mmio_cb, 2907 }; 2908 2909 return intel_gvt_iterate_mmio_table(&iter); 2910 } 2911 2912 static int init_mmio_block_handlers(struct intel_gvt *gvt) 2913 { 2914 struct gvt_mmio_block *block; 2915 2916 block = find_mmio_block(gvt, VGT_PVINFO_PAGE); 2917 if (!block) { 2918 WARN(1, "fail to assign handlers to mmio block %x\n", 2919 i915_mmio_reg_offset(block->offset)); 2920 return -ENODEV; 2921 } 2922 2923 block->read = pvinfo_mmio_read; 2924 block->write = pvinfo_mmio_write; 2925 2926 return 0; 2927 } 2928 2929 /** 2930 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2931 * @gvt: GVT device 2932 * 2933 * This function is called at the initialization stage, to setup the MMIO 2934 * information table for GVT device 2935 * 2936 * Returns: 2937 * zero on success, negative if failed. 2938 */ 2939 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2940 { 2941 struct intel_gvt_device_info *info = &gvt->device_info; 2942 struct drm_i915_private *i915 = gvt->gt->i915; 2943 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2944 int ret; 2945 2946 gvt->mmio.mmio_attribute = vzalloc(size); 2947 if (!gvt->mmio.mmio_attribute) 2948 return -ENOMEM; 2949 2950 ret = init_mmio_info(gvt); 2951 if (ret) 2952 goto err; 2953 2954 ret = init_mmio_block_handlers(gvt); 2955 if (ret) 2956 goto err; 2957 2958 ret = init_generic_mmio_info(gvt); 2959 if (ret) 2960 goto err; 2961 2962 if (IS_BROADWELL(i915)) { 2963 ret = init_bdw_mmio_info(gvt); 2964 if (ret) 2965 goto err; 2966 } else if (IS_SKYLAKE(i915) || 2967 IS_KABYLAKE(i915) || 2968 IS_COFFEELAKE(i915) || 2969 IS_COMETLAKE(i915)) { 2970 ret = init_bdw_mmio_info(gvt); 2971 if (ret) 2972 goto err; 2973 ret = init_skl_mmio_info(gvt); 2974 if (ret) 2975 goto err; 2976 } else if (IS_BROXTON(i915)) { 2977 ret = init_bdw_mmio_info(gvt); 2978 if (ret) 2979 goto err; 2980 ret = init_skl_mmio_info(gvt); 2981 if (ret) 2982 goto err; 2983 ret = init_bxt_mmio_info(gvt); 2984 if (ret) 2985 goto err; 2986 } 2987 2988 return 0; 2989 err: 2990 intel_gvt_clean_mmio_info(gvt); 2991 return ret; 2992 } 2993 2994 /** 2995 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 2996 * @gvt: a GVT device 2997 * @handler: the handler 2998 * @data: private data given to handler 2999 * 3000 * Returns: 3001 * Zero on success, negative error code if failed. 3002 */ 3003 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 3004 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 3005 void *data) 3006 { 3007 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 3008 struct intel_gvt_mmio_info *e; 3009 int i, j, ret; 3010 3011 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 3012 ret = handler(gvt, e->offset, data); 3013 if (ret) 3014 return ret; 3015 } 3016 3017 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 3018 /* pvinfo data doesn't come from hw mmio */ 3019 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE) 3020 continue; 3021 3022 for (j = 0; j < block->size; j += 4) { 3023 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data); 3024 if (ret) 3025 return ret; 3026 } 3027 } 3028 return 0; 3029 } 3030 3031 /** 3032 * intel_vgpu_default_mmio_read - default MMIO read handler 3033 * @vgpu: a vGPU 3034 * @offset: access offset 3035 * @p_data: data return buffer 3036 * @bytes: access data length 3037 * 3038 * Returns: 3039 * Zero on success, negative error code if failed. 3040 */ 3041 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3042 void *p_data, unsigned int bytes) 3043 { 3044 read_vreg(vgpu, offset, p_data, bytes); 3045 return 0; 3046 } 3047 3048 /** 3049 * intel_t_default_mmio_write - default MMIO write handler 3050 * @vgpu: a vGPU 3051 * @offset: access offset 3052 * @p_data: write data buffer 3053 * @bytes: access data length 3054 * 3055 * Returns: 3056 * Zero on success, negative error code if failed. 3057 */ 3058 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3059 void *p_data, unsigned int bytes) 3060 { 3061 write_vreg(vgpu, offset, p_data, bytes); 3062 return 0; 3063 } 3064 3065 /** 3066 * intel_vgpu_mask_mmio_write - write mask register 3067 * @vgpu: a vGPU 3068 * @offset: access offset 3069 * @p_data: write data buffer 3070 * @bytes: access data length 3071 * 3072 * Returns: 3073 * Zero on success, negative error code if failed. 3074 */ 3075 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3076 void *p_data, unsigned int bytes) 3077 { 3078 u32 mask, old_vreg; 3079 3080 old_vreg = vgpu_vreg(vgpu, offset); 3081 write_vreg(vgpu, offset, p_data, bytes); 3082 mask = vgpu_vreg(vgpu, offset) >> 16; 3083 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) | 3084 (vgpu_vreg(vgpu, offset) & mask); 3085 3086 return 0; 3087 } 3088 3089 /** 3090 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3091 * force-nopriv register 3092 * 3093 * @gvt: a GVT device 3094 * @offset: register offset 3095 * 3096 * Returns: 3097 * True if the register is in force-nonpriv whitelist; 3098 * False if outside; 3099 */ 3100 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3101 unsigned int offset) 3102 { 3103 return in_whitelist(offset); 3104 } 3105 3106 /** 3107 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3108 * @vgpu: a vGPU 3109 * @offset: register offset 3110 * @pdata: data buffer 3111 * @bytes: data length 3112 * @is_read: read or write 3113 * 3114 * Returns: 3115 * Zero on success, negative error code if failed. 3116 */ 3117 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3118 void *pdata, unsigned int bytes, bool is_read) 3119 { 3120 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; 3121 struct intel_gvt *gvt = vgpu->gvt; 3122 struct intel_gvt_mmio_info *mmio_info; 3123 struct gvt_mmio_block *mmio_block; 3124 gvt_mmio_func func; 3125 int ret; 3126 3127 if (drm_WARN_ON(&i915->drm, bytes > 8)) 3128 return -EINVAL; 3129 3130 /* 3131 * Handle special MMIO blocks. 3132 */ 3133 mmio_block = find_mmio_block(gvt, offset); 3134 if (mmio_block) { 3135 func = is_read ? mmio_block->read : mmio_block->write; 3136 if (func) 3137 return func(vgpu, offset, pdata, bytes); 3138 goto default_rw; 3139 } 3140 3141 /* 3142 * Normal tracked MMIOs. 3143 */ 3144 mmio_info = intel_gvt_find_mmio_info(gvt, offset); 3145 if (!mmio_info) { 3146 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes); 3147 goto default_rw; 3148 } 3149 3150 if (is_read) 3151 return mmio_info->read(vgpu, offset, pdata, bytes); 3152 else { 3153 u64 ro_mask = mmio_info->ro_mask; 3154 u32 old_vreg = 0; 3155 u64 data = 0; 3156 3157 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3158 old_vreg = vgpu_vreg(vgpu, offset); 3159 } 3160 3161 if (likely(!ro_mask)) 3162 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3163 else if (!~ro_mask) { 3164 gvt_vgpu_err("try to write RO reg %x\n", offset); 3165 return 0; 3166 } else { 3167 /* keep the RO bits in the virtual register */ 3168 memcpy(&data, pdata, bytes); 3169 data &= ~ro_mask; 3170 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3171 ret = mmio_info->write(vgpu, offset, &data, bytes); 3172 } 3173 3174 /* higher 16bits of mode ctl regs are mask bits for change */ 3175 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3176 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3177 3178 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3179 | (vgpu_vreg(vgpu, offset) & mask); 3180 } 3181 } 3182 3183 return ret; 3184 3185 default_rw: 3186 return is_read ? 3187 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3188 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3189 } 3190 3191 void intel_gvt_restore_fence(struct intel_gvt *gvt) 3192 { 3193 struct intel_vgpu *vgpu; 3194 int i, id; 3195 3196 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3197 mmio_hw_access_pre(gvt->gt); 3198 for (i = 0; i < vgpu_fence_sz(vgpu); i++) 3199 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i))); 3200 mmio_hw_access_post(gvt->gt); 3201 } 3202 } 3203 3204 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data) 3205 { 3206 struct intel_vgpu *vgpu = data; 3207 struct drm_i915_private *dev_priv = gvt->gt->i915; 3208 3209 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE) 3210 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset)); 3211 3212 return 0; 3213 } 3214 3215 void intel_gvt_restore_mmio(struct intel_gvt *gvt) 3216 { 3217 struct intel_vgpu *vgpu; 3218 int id; 3219 3220 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) { 3221 mmio_hw_access_pre(gvt->gt); 3222 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu); 3223 mmio_hw_access_post(gvt->gt); 3224 } 3225 } 3226