1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * Zhiyuan Lv <zhiyuan.lv@intel.com> 27 * 28 * Contributors: 29 * Min He <min.he@intel.com> 30 * Tina Zhang <tina.zhang@intel.com> 31 * Pei Zhang <pei.zhang@intel.com> 32 * Niu Bing <bing.niu@intel.com> 33 * Ping Gao <ping.a.gao@intel.com> 34 * Zhi Wang <zhi.a.wang@intel.com> 35 * 36 37 */ 38 39 #include "i915_drv.h" 40 #include "gvt.h" 41 #include "i915_pvinfo.h" 42 43 /* XXX FIXME i915 has changed PP_XXX definition */ 44 #define PCH_PP_STATUS _MMIO(0xc7200) 45 #define PCH_PP_CONTROL _MMIO(0xc7204) 46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208) 47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c) 48 #define PCH_PP_DIVISOR _MMIO(0xc7210) 49 50 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) 51 { 52 if (IS_BROADWELL(gvt->dev_priv)) 53 return D_BDW; 54 else if (IS_SKYLAKE(gvt->dev_priv)) 55 return D_SKL; 56 else if (IS_KABYLAKE(gvt->dev_priv)) 57 return D_KBL; 58 59 return 0; 60 } 61 62 bool intel_gvt_match_device(struct intel_gvt *gvt, 63 unsigned long device) 64 { 65 return intel_gvt_get_device_type(gvt) & device; 66 } 67 68 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset, 69 void *p_data, unsigned int bytes) 70 { 71 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes); 72 } 73 74 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset, 75 void *p_data, unsigned int bytes) 76 { 77 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes); 78 } 79 80 static struct intel_gvt_mmio_info *find_mmio_info(struct intel_gvt *gvt, 81 unsigned int offset) 82 { 83 struct intel_gvt_mmio_info *e; 84 85 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { 86 if (e->offset == offset) 87 return e; 88 } 89 return NULL; 90 } 91 92 static int new_mmio_info(struct intel_gvt *gvt, 93 u32 offset, u8 flags, u32 size, 94 u32 addr_mask, u32 ro_mask, u32 device, 95 gvt_mmio_func read, gvt_mmio_func write) 96 { 97 struct intel_gvt_mmio_info *info, *p; 98 u32 start, end, i; 99 100 if (!intel_gvt_match_device(gvt, device)) 101 return 0; 102 103 if (WARN_ON(!IS_ALIGNED(offset, 4))) 104 return -EINVAL; 105 106 start = offset; 107 end = offset + size; 108 109 for (i = start; i < end; i += 4) { 110 info = kzalloc(sizeof(*info), GFP_KERNEL); 111 if (!info) 112 return -ENOMEM; 113 114 info->offset = i; 115 p = find_mmio_info(gvt, info->offset); 116 if (p) { 117 WARN(1, "dup mmio definition offset %x\n", 118 info->offset); 119 kfree(info); 120 121 /* We return -EEXIST here to make GVT-g load fail. 122 * So duplicated MMIO can be found as soon as 123 * possible. 124 */ 125 return -EEXIST; 126 } 127 128 info->ro_mask = ro_mask; 129 info->device = device; 130 info->read = read ? read : intel_vgpu_default_mmio_read; 131 info->write = write ? write : intel_vgpu_default_mmio_write; 132 gvt->mmio.mmio_attribute[info->offset / 4] = flags; 133 INIT_HLIST_NODE(&info->node); 134 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset); 135 gvt->mmio.num_tracked_mmio++; 136 } 137 return 0; 138 } 139 140 /** 141 * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id 142 * @gvt: a GVT device 143 * @offset: register offset 144 * 145 * Returns: 146 * Ring ID on success, negative error code if failed. 147 */ 148 int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt, 149 unsigned int offset) 150 { 151 enum intel_engine_id id; 152 struct intel_engine_cs *engine; 153 154 offset &= ~GENMASK(11, 0); 155 for_each_engine(engine, gvt->dev_priv, id) { 156 if (engine->mmio_base == offset) 157 return id; 158 } 159 return -ENODEV; 160 } 161 162 #define offset_to_fence_num(offset) \ 163 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3) 164 165 #define fence_num_to_offset(num) \ 166 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) 167 168 169 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason) 170 { 171 switch (reason) { 172 case GVT_FAILSAFE_UNSUPPORTED_GUEST: 173 pr_err("Detected your guest driver doesn't support GVT-g.\n"); 174 break; 175 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE: 176 pr_err("Graphics resource is not enough for the guest\n"); 177 break; 178 case GVT_FAILSAFE_GUEST_ERR: 179 pr_err("GVT Internal error for the guest\n"); 180 break; 181 default: 182 break; 183 } 184 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id); 185 vgpu->failsafe = true; 186 } 187 188 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 189 unsigned int fence_num, void *p_data, unsigned int bytes) 190 { 191 unsigned int max_fence = vgpu_fence_sz(vgpu); 192 193 if (fence_num >= max_fence) { 194 195 /* When guest access oob fence regs without access 196 * pv_info first, we treat guest not supporting GVT, 197 * and we will let vgpu enter failsafe mode. 198 */ 199 if (!vgpu->pv_notified) 200 enter_failsafe_mode(vgpu, 201 GVT_FAILSAFE_UNSUPPORTED_GUEST); 202 203 if (!vgpu->mmio.disable_warn_untrack) { 204 gvt_vgpu_err("found oob fence register access\n"); 205 gvt_vgpu_err("total fence %d, access fence %d\n", 206 max_fence, fence_num); 207 } 208 memset(p_data, 0, bytes); 209 return -EINVAL; 210 } 211 return 0; 212 } 213 214 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off, 215 void *p_data, unsigned int bytes) 216 { 217 int ret; 218 219 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off), 220 p_data, bytes); 221 if (ret) 222 return ret; 223 read_vreg(vgpu, off, p_data, bytes); 224 return 0; 225 } 226 227 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 228 void *p_data, unsigned int bytes) 229 { 230 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 231 unsigned int fence_num = offset_to_fence_num(off); 232 int ret; 233 234 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes); 235 if (ret) 236 return ret; 237 write_vreg(vgpu, off, p_data, bytes); 238 239 mmio_hw_access_pre(dev_priv); 240 intel_vgpu_write_fence(vgpu, fence_num, 241 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num))); 242 mmio_hw_access_post(dev_priv); 243 return 0; 244 } 245 246 #define CALC_MODE_MASK_REG(old, new) \ 247 (((new) & GENMASK(31, 16)) \ 248 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \ 249 | ((new) & ((new) >> 16)))) 250 251 static int mul_force_wake_write(struct intel_vgpu *vgpu, 252 unsigned int offset, void *p_data, unsigned int bytes) 253 { 254 u32 old, new; 255 uint32_t ack_reg_offset; 256 257 old = vgpu_vreg(vgpu, offset); 258 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data); 259 260 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 261 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 262 switch (offset) { 263 case FORCEWAKE_RENDER_GEN9_REG: 264 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG; 265 break; 266 case FORCEWAKE_BLITTER_GEN9_REG: 267 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG; 268 break; 269 case FORCEWAKE_MEDIA_GEN9_REG: 270 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG; 271 break; 272 default: 273 /*should not hit here*/ 274 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); 275 return -EINVAL; 276 } 277 } else { 278 ack_reg_offset = FORCEWAKE_ACK_HSW_REG; 279 } 280 281 vgpu_vreg(vgpu, offset) = new; 282 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); 283 return 0; 284 } 285 286 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 287 void *p_data, unsigned int bytes) 288 { 289 unsigned int engine_mask = 0; 290 u32 data; 291 292 write_vreg(vgpu, offset, p_data, bytes); 293 data = vgpu_vreg(vgpu, offset); 294 295 if (data & GEN6_GRDOM_FULL) { 296 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id); 297 engine_mask = ALL_ENGINES; 298 } else { 299 if (data & GEN6_GRDOM_RENDER) { 300 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id); 301 engine_mask |= (1 << RCS); 302 } 303 if (data & GEN6_GRDOM_MEDIA) { 304 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id); 305 engine_mask |= (1 << VCS); 306 } 307 if (data & GEN6_GRDOM_BLT) { 308 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id); 309 engine_mask |= (1 << BCS); 310 } 311 if (data & GEN6_GRDOM_VECS) { 312 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id); 313 engine_mask |= (1 << VECS); 314 } 315 if (data & GEN8_GRDOM_MEDIA2) { 316 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id); 317 if (HAS_BSD2(vgpu->gvt->dev_priv)) 318 engine_mask |= (1 << VCS2); 319 } 320 } 321 322 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); 323 324 /* sw will wait for the device to ack the reset request */ 325 vgpu_vreg(vgpu, offset) = 0; 326 327 return 0; 328 } 329 330 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 331 void *p_data, unsigned int bytes) 332 { 333 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes); 334 } 335 336 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 337 void *p_data, unsigned int bytes) 338 { 339 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes); 340 } 341 342 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu, 343 unsigned int offset, void *p_data, unsigned int bytes) 344 { 345 write_vreg(vgpu, offset, p_data, bytes); 346 347 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) { 348 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; 349 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE; 350 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN; 351 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE; 352 353 } else 354 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= 355 ~(PP_ON | PP_SEQUENCE_POWER_DOWN 356 | PP_CYCLE_DELAY_ACTIVE); 357 return 0; 358 } 359 360 static int transconf_mmio_write(struct intel_vgpu *vgpu, 361 unsigned int offset, void *p_data, unsigned int bytes) 362 { 363 write_vreg(vgpu, offset, p_data, bytes); 364 365 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE) 366 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE; 367 else 368 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE; 369 return 0; 370 } 371 372 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 373 void *p_data, unsigned int bytes) 374 { 375 write_vreg(vgpu, offset, p_data, bytes); 376 377 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE) 378 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK; 379 else 380 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK; 381 382 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK) 383 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE; 384 else 385 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE; 386 387 return 0; 388 } 389 390 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 391 void *p_data, unsigned int bytes) 392 { 393 switch (offset) { 394 case 0xe651c: 395 case 0xe661c: 396 case 0xe671c: 397 case 0xe681c: 398 vgpu_vreg(vgpu, offset) = 1 << 17; 399 break; 400 case 0xe6c04: 401 vgpu_vreg(vgpu, offset) = 0x3; 402 break; 403 case 0xe6e1c: 404 vgpu_vreg(vgpu, offset) = 0x2f << 16; 405 break; 406 default: 407 return -EINVAL; 408 } 409 410 read_vreg(vgpu, offset, p_data, bytes); 411 return 0; 412 } 413 414 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 415 void *p_data, unsigned int bytes) 416 { 417 u32 data; 418 419 write_vreg(vgpu, offset, p_data, bytes); 420 data = vgpu_vreg(vgpu, offset); 421 422 if (data & PIPECONF_ENABLE) 423 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE; 424 else 425 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE; 426 intel_gvt_check_vblank_emulation(vgpu->gvt); 427 return 0; 428 } 429 430 /* ascendingly sorted */ 431 static i915_reg_t force_nonpriv_white_list[] = { 432 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec) 433 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248) 434 GEN8_CS_CHICKEN1,//_MMIO(0x2580) 435 _MMIO(0x2690), 436 _MMIO(0x2694), 437 _MMIO(0x2698), 438 _MMIO(0x4de0), 439 _MMIO(0x4de4), 440 _MMIO(0x4dfc), 441 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010) 442 _MMIO(0x7014), 443 HDC_CHICKEN0,//_MMIO(0x7300) 444 GEN8_HDC_CHICKEN1,//_MMIO(0x7304) 445 _MMIO(0x7700), 446 _MMIO(0x7704), 447 _MMIO(0x7708), 448 _MMIO(0x770c), 449 _MMIO(0xb110), 450 GEN8_L3SQCREG4,//_MMIO(0xb118) 451 _MMIO(0xe100), 452 _MMIO(0xe18c), 453 _MMIO(0xe48c), 454 _MMIO(0xe5f4), 455 }; 456 457 /* a simple bsearch */ 458 static inline bool in_whitelist(unsigned int reg) 459 { 460 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); 461 i915_reg_t *array = force_nonpriv_white_list; 462 463 while (left < right) { 464 int mid = (left + right)/2; 465 466 if (reg > array[mid].reg) 467 left = mid + 1; 468 else if (reg < array[mid].reg) 469 right = mid; 470 else 471 return true; 472 } 473 return false; 474 } 475 476 static int force_nonpriv_write(struct intel_vgpu *vgpu, 477 unsigned int offset, void *p_data, unsigned int bytes) 478 { 479 u32 reg_nonpriv = *(u32 *)p_data; 480 int ret = -EINVAL; 481 482 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) { 483 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n", 484 vgpu->id, offset, bytes); 485 return ret; 486 } 487 488 if (in_whitelist(reg_nonpriv)) { 489 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, 490 bytes); 491 } else { 492 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n", 493 vgpu->id, reg_nonpriv); 494 } 495 return ret; 496 } 497 498 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 499 void *p_data, unsigned int bytes) 500 { 501 write_vreg(vgpu, offset, p_data, bytes); 502 503 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) { 504 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE; 505 } else { 506 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE; 507 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) 508 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) 509 &= ~DP_TP_STATUS_AUTOTRAIN_DONE; 510 } 511 return 0; 512 } 513 514 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu, 515 unsigned int offset, void *p_data, unsigned int bytes) 516 { 517 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data; 518 return 0; 519 } 520 521 #define FDI_LINK_TRAIN_PATTERN1 0 522 #define FDI_LINK_TRAIN_PATTERN2 1 523 524 static int fdi_auto_training_started(struct intel_vgpu *vgpu) 525 { 526 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); 527 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL); 528 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); 529 530 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) && 531 (rx_ctl & FDI_RX_ENABLE) && 532 (rx_ctl & FDI_AUTO_TRAINING) && 533 (tx_ctl & DP_TP_CTL_ENABLE) && 534 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN)) 535 return 1; 536 else 537 return 0; 538 } 539 540 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, 541 enum pipe pipe, unsigned int train_pattern) 542 { 543 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl; 544 unsigned int fdi_rx_check_bits, fdi_tx_check_bits; 545 unsigned int fdi_rx_train_bits, fdi_tx_train_bits; 546 unsigned int fdi_iir_check_bits; 547 548 fdi_rx_imr = FDI_RX_IMR(pipe); 549 fdi_tx_ctl = FDI_TX_CTL(pipe); 550 fdi_rx_ctl = FDI_RX_CTL(pipe); 551 552 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) { 553 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT; 554 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1; 555 fdi_iir_check_bits = FDI_RX_BIT_LOCK; 556 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) { 557 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT; 558 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2; 559 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK; 560 } else { 561 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern); 562 return -EINVAL; 563 } 564 565 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits; 566 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits; 567 568 /* If imr bit has been masked */ 569 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits) 570 return 0; 571 572 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits) 573 == fdi_tx_check_bits) 574 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits) 575 == fdi_rx_check_bits)) 576 return 1; 577 else 578 return 0; 579 } 580 581 #define INVALID_INDEX (~0U) 582 583 static unsigned int calc_index(unsigned int offset, unsigned int start, 584 unsigned int next, unsigned int end, i915_reg_t i915_end) 585 { 586 unsigned int range = next - start; 587 588 if (!end) 589 end = i915_mmio_reg_offset(i915_end); 590 if (offset < start || offset > end) 591 return INVALID_INDEX; 592 offset -= start; 593 return offset / range; 594 } 595 596 #define FDI_RX_CTL_TO_PIPE(offset) \ 597 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) 598 599 #define FDI_TX_CTL_TO_PIPE(offset) \ 600 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) 601 602 #define FDI_RX_IMR_TO_PIPE(offset) \ 603 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) 604 605 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, 606 unsigned int offset, void *p_data, unsigned int bytes) 607 { 608 i915_reg_t fdi_rx_iir; 609 unsigned int index; 610 int ret; 611 612 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX) 613 index = FDI_RX_CTL_TO_PIPE(offset); 614 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX) 615 index = FDI_TX_CTL_TO_PIPE(offset); 616 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX) 617 index = FDI_RX_IMR_TO_PIPE(offset); 618 else { 619 gvt_vgpu_err("Unsupport registers %x\n", offset); 620 return -EINVAL; 621 } 622 623 write_vreg(vgpu, offset, p_data, bytes); 624 625 fdi_rx_iir = FDI_RX_IIR(index); 626 627 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1); 628 if (ret < 0) 629 return ret; 630 if (ret) 631 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK; 632 633 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2); 634 if (ret < 0) 635 return ret; 636 if (ret) 637 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK; 638 639 if (offset == _FDI_RXA_CTL) 640 if (fdi_auto_training_started(vgpu)) 641 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= 642 DP_TP_STATUS_AUTOTRAIN_DONE; 643 return 0; 644 } 645 646 #define DP_TP_CTL_TO_PORT(offset) \ 647 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) 648 649 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 650 void *p_data, unsigned int bytes) 651 { 652 i915_reg_t status_reg; 653 unsigned int index; 654 u32 data; 655 656 write_vreg(vgpu, offset, p_data, bytes); 657 658 index = DP_TP_CTL_TO_PORT(offset); 659 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8; 660 if (data == 0x2) { 661 status_reg = DP_TP_STATUS(index); 662 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); 663 } 664 return 0; 665 } 666 667 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu, 668 unsigned int offset, void *p_data, unsigned int bytes) 669 { 670 u32 reg_val; 671 u32 sticky_mask; 672 673 reg_val = *((u32 *)p_data); 674 sticky_mask = GENMASK(27, 26) | (1 << 24); 675 676 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) | 677 (vgpu_vreg(vgpu, offset) & sticky_mask); 678 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask); 679 return 0; 680 } 681 682 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu, 683 unsigned int offset, void *p_data, unsigned int bytes) 684 { 685 u32 data; 686 687 write_vreg(vgpu, offset, p_data, bytes); 688 data = vgpu_vreg(vgpu, offset); 689 690 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 691 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 692 return 0; 693 } 694 695 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, 696 unsigned int offset, void *p_data, unsigned int bytes) 697 { 698 u32 data; 699 700 write_vreg(vgpu, offset, p_data, bytes); 701 data = vgpu_vreg(vgpu, offset); 702 703 if (data & FDI_MPHY_IOSFSB_RESET_CTL) 704 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS; 705 else 706 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS; 707 return 0; 708 } 709 710 #define DSPSURF_TO_PIPE(offset) \ 711 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) 712 713 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 714 void *p_data, unsigned int bytes) 715 { 716 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 717 unsigned int index = DSPSURF_TO_PIPE(offset); 718 i915_reg_t surflive_reg = DSPSURFLIVE(index); 719 int flip_event[] = { 720 [PIPE_A] = PRIMARY_A_FLIP_DONE, 721 [PIPE_B] = PRIMARY_B_FLIP_DONE, 722 [PIPE_C] = PRIMARY_C_FLIP_DONE, 723 }; 724 725 write_vreg(vgpu, offset, p_data, bytes); 726 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 727 728 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 729 return 0; 730 } 731 732 #define SPRSURF_TO_PIPE(offset) \ 733 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) 734 735 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 736 void *p_data, unsigned int bytes) 737 { 738 unsigned int index = SPRSURF_TO_PIPE(offset); 739 i915_reg_t surflive_reg = SPRSURFLIVE(index); 740 int flip_event[] = { 741 [PIPE_A] = SPRITE_A_FLIP_DONE, 742 [PIPE_B] = SPRITE_B_FLIP_DONE, 743 [PIPE_C] = SPRITE_C_FLIP_DONE, 744 }; 745 746 write_vreg(vgpu, offset, p_data, bytes); 747 vgpu_vreg_t(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset); 748 749 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]); 750 return 0; 751 } 752 753 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, 754 unsigned int reg) 755 { 756 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 757 enum intel_gvt_event_type event; 758 759 if (reg == _DPA_AUX_CH_CTL) 760 event = AUX_CHANNEL_A; 761 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL) 762 event = AUX_CHANNEL_B; 763 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL) 764 event = AUX_CHANNEL_C; 765 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL) 766 event = AUX_CHANNEL_D; 767 else { 768 WARN_ON(true); 769 return -EINVAL; 770 } 771 772 intel_vgpu_trigger_virtual_event(vgpu, event); 773 return 0; 774 } 775 776 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value, 777 unsigned int reg, int len, bool data_valid) 778 { 779 /* mark transaction done */ 780 value |= DP_AUX_CH_CTL_DONE; 781 value &= ~DP_AUX_CH_CTL_SEND_BUSY; 782 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR; 783 784 if (data_valid) 785 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR; 786 else 787 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR; 788 789 /* message size */ 790 value &= ~(0xf << 20); 791 value |= (len << 20); 792 vgpu_vreg(vgpu, reg) = value; 793 794 if (value & DP_AUX_CH_CTL_INTERRUPT) 795 return trigger_aux_channel_interrupt(vgpu, reg); 796 return 0; 797 } 798 799 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, 800 uint8_t t) 801 { 802 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) { 803 /* training pattern 1 for CR */ 804 /* set LANE0_CR_DONE, LANE1_CR_DONE */ 805 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; 806 /* set LANE2_CR_DONE, LANE3_CR_DONE */ 807 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; 808 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 809 DPCD_TRAINING_PATTERN_2) { 810 /* training pattern 2 for EQ */ 811 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */ 812 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; 813 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; 814 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */ 815 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; 816 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; 817 /* set INTERLANE_ALIGN_DONE */ 818 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= 819 DPCD_INTERLANE_ALIGN_DONE; 820 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == 821 DPCD_LINK_TRAINING_DISABLED) { 822 /* finish link training */ 823 /* set sink status as synchronized */ 824 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; 825 } 826 } 827 828 #define _REG_HSW_DP_AUX_CH_CTL(dp) \ 829 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) 830 831 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) 832 833 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) 834 835 #define dpy_is_valid_port(port) \ 836 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS)) 837 838 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, 839 unsigned int offset, void *p_data, unsigned int bytes) 840 { 841 struct intel_vgpu_display *display = &vgpu->display; 842 int msg, addr, ctrl, op, len; 843 int port_index = OFFSET_TO_DP_AUX_PORT(offset); 844 struct intel_vgpu_dpcd_data *dpcd = NULL; 845 struct intel_vgpu_port *port = NULL; 846 u32 data; 847 848 if (!dpy_is_valid_port(port_index)) { 849 gvt_vgpu_err("Unsupported DP port access!\n"); 850 return 0; 851 } 852 853 write_vreg(vgpu, offset, p_data, bytes); 854 data = vgpu_vreg(vgpu, offset); 855 856 if ((IS_SKYLAKE(vgpu->gvt->dev_priv) 857 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 858 && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { 859 /* SKL DPB/C/D aux ctl register changed */ 860 return 0; 861 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) && 862 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { 863 /* write to the data registers */ 864 return 0; 865 } 866 867 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) { 868 /* just want to clear the sticky bits */ 869 vgpu_vreg(vgpu, offset) = 0; 870 return 0; 871 } 872 873 port = &display->ports[port_index]; 874 dpcd = port->dpcd; 875 876 /* read out message from DATA1 register */ 877 msg = vgpu_vreg(vgpu, offset + 4); 878 addr = (msg >> 8) & 0xffff; 879 ctrl = (msg >> 24) & 0xff; 880 len = msg & 0xff; 881 op = ctrl >> 4; 882 883 if (op == GVT_AUX_NATIVE_WRITE) { 884 int t; 885 uint8_t buf[16]; 886 887 if ((addr + len + 1) >= DPCD_SIZE) { 888 /* 889 * Write request exceeds what we supported, 890 * DCPD spec: When a Source Device is writing a DPCD 891 * address not supported by the Sink Device, the Sink 892 * Device shall reply with AUX NACK and “M” equal to 893 * zero. 894 */ 895 896 /* NAK the write */ 897 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK; 898 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true); 899 return 0; 900 } 901 902 /* 903 * Write request format: (command + address) occupies 904 * 3 bytes, followed by (len + 1) bytes of data. 905 */ 906 if (WARN_ON((len + 4) > AUX_BURST_SIZE)) 907 return -EINVAL; 908 909 /* unpack data from vreg to buf */ 910 for (t = 0; t < 4; t++) { 911 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4); 912 913 buf[t * 4] = (r >> 24) & 0xff; 914 buf[t * 4 + 1] = (r >> 16) & 0xff; 915 buf[t * 4 + 2] = (r >> 8) & 0xff; 916 buf[t * 4 + 3] = r & 0xff; 917 } 918 919 /* write to virtual DPCD */ 920 if (dpcd && dpcd->data_valid) { 921 for (t = 0; t <= len; t++) { 922 int p = addr + t; 923 924 dpcd->data[p] = buf[t]; 925 /* check for link training */ 926 if (p == DPCD_TRAINING_PATTERN_SET) 927 dp_aux_ch_ctl_link_training(dpcd, 928 buf[t]); 929 } 930 } 931 932 /* ACK the write */ 933 vgpu_vreg(vgpu, offset + 4) = 0; 934 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1, 935 dpcd && dpcd->data_valid); 936 return 0; 937 } 938 939 if (op == GVT_AUX_NATIVE_READ) { 940 int idx, i, ret = 0; 941 942 if ((addr + len + 1) >= DPCD_SIZE) { 943 /* 944 * read request exceeds what we supported 945 * DPCD spec: A Sink Device receiving a Native AUX CH 946 * read request for an unsupported DPCD address must 947 * reply with an AUX ACK and read data set equal to 948 * zero instead of replying with AUX NACK. 949 */ 950 951 /* ACK the READ*/ 952 vgpu_vreg(vgpu, offset + 4) = 0; 953 vgpu_vreg(vgpu, offset + 8) = 0; 954 vgpu_vreg(vgpu, offset + 12) = 0; 955 vgpu_vreg(vgpu, offset + 16) = 0; 956 vgpu_vreg(vgpu, offset + 20) = 0; 957 958 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 959 true); 960 return 0; 961 } 962 963 for (idx = 1; idx <= 5; idx++) { 964 /* clear the data registers */ 965 vgpu_vreg(vgpu, offset + 4 * idx) = 0; 966 } 967 968 /* 969 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data. 970 */ 971 if (WARN_ON((len + 2) > AUX_BURST_SIZE)) 972 return -EINVAL; 973 974 /* read from virtual DPCD to vreg */ 975 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */ 976 if (dpcd && dpcd->data_valid) { 977 for (i = 1; i <= (len + 1); i++) { 978 int t; 979 980 t = dpcd->data[addr + i - 1]; 981 t <<= (24 - 8 * (i % 4)); 982 ret |= t; 983 984 if ((i % 4 == 3) || (i == (len + 1))) { 985 vgpu_vreg(vgpu, offset + 986 (i / 4 + 1) * 4) = ret; 987 ret = 0; 988 } 989 } 990 } 991 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2, 992 dpcd && dpcd->data_valid); 993 return 0; 994 } 995 996 /* i2c transaction starts */ 997 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data); 998 999 if (data & DP_AUX_CH_CTL_INTERRUPT) 1000 trigger_aux_channel_interrupt(vgpu, offset); 1001 return 0; 1002 } 1003 1004 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset, 1005 void *p_data, unsigned int bytes) 1006 { 1007 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH); 1008 write_vreg(vgpu, offset, p_data, bytes); 1009 return 0; 1010 } 1011 1012 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1013 void *p_data, unsigned int bytes) 1014 { 1015 bool vga_disable; 1016 1017 write_vreg(vgpu, offset, p_data, bytes); 1018 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE; 1019 1020 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id, 1021 vga_disable ? "Disable" : "Enable"); 1022 return 0; 1023 } 1024 1025 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu, 1026 unsigned int sbi_offset) 1027 { 1028 struct intel_vgpu_display *display = &vgpu->display; 1029 int num = display->sbi.number; 1030 int i; 1031 1032 for (i = 0; i < num; ++i) 1033 if (display->sbi.registers[i].offset == sbi_offset) 1034 break; 1035 1036 if (i == num) 1037 return 0; 1038 1039 return display->sbi.registers[i].value; 1040 } 1041 1042 static void write_virtual_sbi_register(struct intel_vgpu *vgpu, 1043 unsigned int offset, u32 value) 1044 { 1045 struct intel_vgpu_display *display = &vgpu->display; 1046 int num = display->sbi.number; 1047 int i; 1048 1049 for (i = 0; i < num; ++i) { 1050 if (display->sbi.registers[i].offset == offset) 1051 break; 1052 } 1053 1054 if (i == num) { 1055 if (num == SBI_REG_MAX) { 1056 gvt_vgpu_err("SBI caching meets maximum limits\n"); 1057 return; 1058 } 1059 display->sbi.number++; 1060 } 1061 1062 display->sbi.registers[i].offset = offset; 1063 display->sbi.registers[i].value = value; 1064 } 1065 1066 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1067 void *p_data, unsigned int bytes) 1068 { 1069 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1070 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) { 1071 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1072 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1073 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, 1074 sbi_offset); 1075 } 1076 read_vreg(vgpu, offset, p_data, bytes); 1077 return 0; 1078 } 1079 1080 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1081 void *p_data, unsigned int bytes) 1082 { 1083 u32 data; 1084 1085 write_vreg(vgpu, offset, p_data, bytes); 1086 data = vgpu_vreg(vgpu, offset); 1087 1088 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT); 1089 data |= SBI_READY; 1090 1091 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT); 1092 data |= SBI_RESPONSE_SUCCESS; 1093 1094 vgpu_vreg(vgpu, offset) = data; 1095 1096 if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >> 1097 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) { 1098 unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) & 1099 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT; 1100 1101 write_virtual_sbi_register(vgpu, sbi_offset, 1102 vgpu_vreg_t(vgpu, SBI_DATA)); 1103 } 1104 return 0; 1105 } 1106 1107 #define _vgtif_reg(x) \ 1108 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)) 1109 1110 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 1111 void *p_data, unsigned int bytes) 1112 { 1113 bool invalid_read = false; 1114 1115 read_vreg(vgpu, offset, p_data, bytes); 1116 1117 switch (offset) { 1118 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id): 1119 if (offset + bytes > _vgtif_reg(vgt_id) + 4) 1120 invalid_read = true; 1121 break; 1122 case _vgtif_reg(avail_rs.mappable_gmadr.base) ... 1123 _vgtif_reg(avail_rs.fence_num): 1124 if (offset + bytes > 1125 _vgtif_reg(avail_rs.fence_num) + 4) 1126 invalid_read = true; 1127 break; 1128 case 0x78010: /* vgt_caps */ 1129 case 0x7881c: 1130 break; 1131 default: 1132 invalid_read = true; 1133 break; 1134 } 1135 if (invalid_read) 1136 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n", 1137 offset, bytes, *(u32 *)p_data); 1138 vgpu->pv_notified = true; 1139 return 0; 1140 } 1141 1142 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification) 1143 { 1144 intel_gvt_gtt_type_t root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY; 1145 struct intel_vgpu_mm *mm; 1146 u64 *pdps; 1147 1148 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); 1149 1150 switch (notification) { 1151 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE: 1152 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY; 1153 /* fall through */ 1154 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE: 1155 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps); 1156 return PTR_ERR_OR_ZERO(mm); 1157 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY: 1158 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY: 1159 return intel_vgpu_put_ppgtt_mm(vgpu, pdps); 1160 case VGT_G2V_EXECLIST_CONTEXT_CREATE: 1161 case VGT_G2V_EXECLIST_CONTEXT_DESTROY: 1162 case 1: /* Remove this in guest driver. */ 1163 break; 1164 default: 1165 gvt_vgpu_err("Invalid PV notification %d\n", notification); 1166 } 1167 return 0; 1168 } 1169 1170 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) 1171 { 1172 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1173 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj; 1174 char *env[3] = {NULL, NULL, NULL}; 1175 char vmid_str[20]; 1176 char display_ready_str[20]; 1177 1178 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready); 1179 env[0] = display_ready_str; 1180 1181 snprintf(vmid_str, 20, "VMID=%d", vgpu->id); 1182 env[1] = vmid_str; 1183 1184 return kobject_uevent_env(kobj, KOBJ_ADD, env); 1185 } 1186 1187 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1188 void *p_data, unsigned int bytes) 1189 { 1190 u32 data; 1191 int ret; 1192 1193 write_vreg(vgpu, offset, p_data, bytes); 1194 data = vgpu_vreg(vgpu, offset); 1195 1196 switch (offset) { 1197 case _vgtif_reg(display_ready): 1198 send_display_ready_uevent(vgpu, data ? 1 : 0); 1199 break; 1200 case _vgtif_reg(g2v_notify): 1201 ret = handle_g2v_notification(vgpu, data); 1202 break; 1203 /* add xhot and yhot to handled list to avoid error log */ 1204 case 0x78830: 1205 case 0x78834: 1206 case _vgtif_reg(pdp[0].lo): 1207 case _vgtif_reg(pdp[0].hi): 1208 case _vgtif_reg(pdp[1].lo): 1209 case _vgtif_reg(pdp[1].hi): 1210 case _vgtif_reg(pdp[2].lo): 1211 case _vgtif_reg(pdp[2].hi): 1212 case _vgtif_reg(pdp[3].lo): 1213 case _vgtif_reg(pdp[3].hi): 1214 case _vgtif_reg(execlist_context_descriptor_lo): 1215 case _vgtif_reg(execlist_context_descriptor_hi): 1216 break; 1217 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): 1218 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); 1219 break; 1220 default: 1221 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", 1222 offset, bytes, data); 1223 break; 1224 } 1225 return 0; 1226 } 1227 1228 static int pf_write(struct intel_vgpu *vgpu, 1229 unsigned int offset, void *p_data, unsigned int bytes) 1230 { 1231 u32 val = *(u32 *)p_data; 1232 1233 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL || 1234 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL || 1235 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) { 1236 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n", 1237 vgpu->id); 1238 return 0; 1239 } 1240 1241 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes); 1242 } 1243 1244 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu, 1245 unsigned int offset, void *p_data, unsigned int bytes) 1246 { 1247 write_vreg(vgpu, offset, p_data, bytes); 1248 1249 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL)) 1250 vgpu_vreg(vgpu, offset) |= 1251 HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1252 else 1253 vgpu_vreg(vgpu, offset) &= 1254 ~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL); 1255 return 0; 1256 } 1257 1258 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu, 1259 unsigned int offset, void *p_data, unsigned int bytes) 1260 { 1261 write_vreg(vgpu, offset, p_data, bytes); 1262 1263 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM) 1264 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM; 1265 return 0; 1266 } 1267 1268 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset, 1269 void *p_data, unsigned int bytes) 1270 { 1271 u32 mode; 1272 1273 write_vreg(vgpu, offset, p_data, bytes); 1274 mode = vgpu_vreg(vgpu, offset); 1275 1276 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) { 1277 WARN_ONCE(1, "VM(%d): iGVT-g doesn't support GuC\n", 1278 vgpu->id); 1279 return 0; 1280 } 1281 1282 return 0; 1283 } 1284 1285 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset, 1286 void *p_data, unsigned int bytes) 1287 { 1288 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1289 u32 trtte = *(u32 *)p_data; 1290 1291 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { 1292 WARN(1, "VM(%d): Use physical address for TRTT!\n", 1293 vgpu->id); 1294 return -EINVAL; 1295 } 1296 write_vreg(vgpu, offset, p_data, bytes); 1297 /* TRTTE is not per-context */ 1298 1299 mmio_hw_access_pre(dev_priv); 1300 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset)); 1301 mmio_hw_access_post(dev_priv); 1302 1303 return 0; 1304 } 1305 1306 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset, 1307 void *p_data, unsigned int bytes) 1308 { 1309 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; 1310 u32 val = *(u32 *)p_data; 1311 1312 if (val & 1) { 1313 /* unblock hw logic */ 1314 mmio_hw_access_pre(dev_priv); 1315 I915_WRITE(_MMIO(offset), val); 1316 mmio_hw_access_post(dev_priv); 1317 } 1318 write_vreg(vgpu, offset, p_data, bytes); 1319 return 0; 1320 } 1321 1322 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset, 1323 void *p_data, unsigned int bytes) 1324 { 1325 u32 v = 0; 1326 1327 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) 1328 v |= (1 << 0); 1329 1330 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) 1331 v |= (1 << 8); 1332 1333 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) 1334 v |= (1 << 16); 1335 1336 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) 1337 v |= (1 << 24); 1338 1339 vgpu_vreg(vgpu, offset) = v; 1340 1341 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1342 } 1343 1344 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset, 1345 void *p_data, unsigned int bytes) 1346 { 1347 u32 value = *(u32 *)p_data; 1348 u32 cmd = value & 0xff; 1349 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); 1350 1351 switch (cmd) { 1352 case GEN9_PCODE_READ_MEM_LATENCY: 1353 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1354 || IS_KABYLAKE(vgpu->gvt->dev_priv)) { 1355 /** 1356 * "Read memory latency" command on gen9. 1357 * Below memory latency values are read 1358 * from skylake platform. 1359 */ 1360 if (!*data0) 1361 *data0 = 0x1e1a1100; 1362 else 1363 *data0 = 0x61514b3d; 1364 } 1365 break; 1366 case SKL_PCODE_CDCLK_CONTROL: 1367 if (IS_SKYLAKE(vgpu->gvt->dev_priv) 1368 || IS_KABYLAKE(vgpu->gvt->dev_priv)) 1369 *data0 = SKL_CDCLK_READY_FOR_CHANGE; 1370 break; 1371 case GEN6_PCODE_READ_RC6VIDS: 1372 *data0 |= 0x1; 1373 break; 1374 } 1375 1376 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n", 1377 vgpu->id, value, *data0); 1378 /** 1379 * PCODE_READY clear means ready for pcode read/write, 1380 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we 1381 * always emulate as pcode read/write success and ready for access 1382 * anytime, since we don't touch real physical registers here. 1383 */ 1384 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK); 1385 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1386 } 1387 1388 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset, 1389 void *p_data, unsigned int bytes) 1390 { 1391 u32 value = *(u32 *)p_data; 1392 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1393 1394 if (!intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) { 1395 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", 1396 offset, value); 1397 return -EINVAL; 1398 } 1399 /* 1400 * Need to emulate all the HWSP register write to ensure host can 1401 * update the VM CSB status correctly. Here listed registers can 1402 * support BDW, SKL or other platforms with same HWSP registers. 1403 */ 1404 if (unlikely(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) { 1405 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", 1406 offset); 1407 return -EINVAL; 1408 } 1409 vgpu->hws_pga[ring_id] = value; 1410 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", 1411 vgpu->id, value, offset); 1412 1413 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes); 1414 } 1415 1416 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu, 1417 unsigned int offset, void *p_data, unsigned int bytes) 1418 { 1419 u32 v = *(u32 *)p_data; 1420 1421 v &= (1 << 31) | (1 << 29) | (1 << 9) | 1422 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1); 1423 v |= (v >> 1); 1424 1425 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes); 1426 } 1427 1428 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 1429 void *p_data, unsigned int bytes) 1430 { 1431 u32 v = *(u32 *)p_data; 1432 1433 /* other bits are MBZ. */ 1434 v &= (1 << 31) | (1 << 30); 1435 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30)); 1436 1437 vgpu_vreg(vgpu, offset) = v; 1438 1439 return 0; 1440 } 1441 1442 static int mmio_read_from_hw(struct intel_vgpu *vgpu, 1443 unsigned int offset, void *p_data, unsigned int bytes) 1444 { 1445 struct intel_gvt *gvt = vgpu->gvt; 1446 struct drm_i915_private *dev_priv = gvt->dev_priv; 1447 int ring_id; 1448 u32 ring_base; 1449 1450 ring_id = intel_gvt_render_mmio_to_ring_id(gvt, offset); 1451 /** 1452 * Read HW reg in following case 1453 * a. the offset isn't a ring mmio 1454 * b. the offset's ring is running on hw. 1455 * c. the offset is ring time stamp mmio 1456 */ 1457 if (ring_id >= 0) 1458 ring_base = dev_priv->engine[ring_id]->mmio_base; 1459 1460 if (ring_id < 0 || vgpu == gvt->scheduler.engine_owner[ring_id] || 1461 offset == i915_mmio_reg_offset(RING_TIMESTAMP(ring_base)) || 1462 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(ring_base))) { 1463 mmio_hw_access_pre(dev_priv); 1464 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset)); 1465 mmio_hw_access_post(dev_priv); 1466 } 1467 1468 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes); 1469 } 1470 1471 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1472 void *p_data, unsigned int bytes) 1473 { 1474 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1475 struct intel_vgpu_execlist *execlist; 1476 u32 data = *(u32 *)p_data; 1477 int ret = 0; 1478 1479 if (WARN_ON(ring_id < 0 || ring_id >= I915_NUM_ENGINES)) 1480 return -EINVAL; 1481 1482 execlist = &vgpu->submission.execlist[ring_id]; 1483 1484 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data; 1485 if (execlist->elsp_dwords.index == 3) { 1486 ret = intel_vgpu_submit_execlist(vgpu, ring_id); 1487 if(ret) 1488 gvt_vgpu_err("fail submit workload on ring %d\n", 1489 ring_id); 1490 } 1491 1492 ++execlist->elsp_dwords.index; 1493 execlist->elsp_dwords.index &= 0x3; 1494 return ret; 1495 } 1496 1497 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 1498 void *p_data, unsigned int bytes) 1499 { 1500 u32 data = *(u32 *)p_data; 1501 int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset); 1502 bool enable_execlist; 1503 int ret; 1504 1505 write_vreg(vgpu, offset, p_data, bytes); 1506 1507 /* when PPGTT mode enabled, we will check if guest has called 1508 * pvinfo, if not, we will treat this guest as non-gvtg-aware 1509 * guest, and stop emulating its cfg space, mmio, gtt, etc. 1510 */ 1511 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) || 1512 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))) 1513 && !vgpu->pv_notified) { 1514 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST); 1515 return 0; 1516 } 1517 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)) 1518 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) { 1519 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE); 1520 1521 gvt_dbg_core("EXECLIST %s on ring %d\n", 1522 (enable_execlist ? "enabling" : "disabling"), 1523 ring_id); 1524 1525 if (!enable_execlist) 1526 return 0; 1527 1528 ret = intel_vgpu_select_submission_ops(vgpu, 1529 ENGINE_MASK(ring_id), 1530 INTEL_VGPU_EXECLIST_SUBMISSION); 1531 if (ret) 1532 return ret; 1533 1534 intel_vgpu_start_schedule(vgpu); 1535 } 1536 return 0; 1537 } 1538 1539 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 1540 unsigned int offset, void *p_data, unsigned int bytes) 1541 { 1542 unsigned int id = 0; 1543 1544 write_vreg(vgpu, offset, p_data, bytes); 1545 vgpu_vreg(vgpu, offset) = 0; 1546 1547 switch (offset) { 1548 case 0x4260: 1549 id = RCS; 1550 break; 1551 case 0x4264: 1552 id = VCS; 1553 break; 1554 case 0x4268: 1555 id = VCS2; 1556 break; 1557 case 0x426c: 1558 id = BCS; 1559 break; 1560 case 0x4270: 1561 id = VECS; 1562 break; 1563 default: 1564 return -EINVAL; 1565 } 1566 set_bit(id, (void *)vgpu->submission.tlb_handle_pending); 1567 1568 return 0; 1569 } 1570 1571 static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 1572 unsigned int offset, void *p_data, unsigned int bytes) 1573 { 1574 u32 data; 1575 1576 write_vreg(vgpu, offset, p_data, bytes); 1577 data = vgpu_vreg(vgpu, offset); 1578 1579 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET)) 1580 data |= RESET_CTL_READY_TO_RESET; 1581 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) 1582 data &= ~RESET_CTL_READY_TO_RESET; 1583 1584 vgpu_vreg(vgpu, offset) = data; 1585 return 0; 1586 } 1587 1588 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \ 1589 ret = new_mmio_info(gvt, i915_mmio_reg_offset(reg), \ 1590 f, s, am, rm, d, r, w); \ 1591 if (ret) \ 1592 return ret; \ 1593 } while (0) 1594 1595 #define MMIO_D(reg, d) \ 1596 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL) 1597 1598 #define MMIO_DH(reg, d, r, w) \ 1599 MMIO_F(reg, 4, 0, 0, 0, d, r, w) 1600 1601 #define MMIO_DFH(reg, d, f, r, w) \ 1602 MMIO_F(reg, 4, f, 0, 0, d, r, w) 1603 1604 #define MMIO_GM(reg, d, r, w) \ 1605 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w) 1606 1607 #define MMIO_GM_RDR(reg, d, r, w) \ 1608 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w) 1609 1610 #define MMIO_RO(reg, d, f, rm, r, w) \ 1611 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w) 1612 1613 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \ 1614 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \ 1615 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \ 1616 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \ 1617 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \ 1618 if (HAS_BSD2(dev_priv)) \ 1619 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \ 1620 } while (0) 1621 1622 #define MMIO_RING_D(prefix, d) \ 1623 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL) 1624 1625 #define MMIO_RING_DFH(prefix, d, f, r, w) \ 1626 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w) 1627 1628 #define MMIO_RING_GM(prefix, d, r, w) \ 1629 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w) 1630 1631 #define MMIO_RING_GM_RDR(prefix, d, r, w) \ 1632 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w) 1633 1634 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \ 1635 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w) 1636 1637 static int init_generic_mmio_info(struct intel_gvt *gvt) 1638 { 1639 struct drm_i915_private *dev_priv = gvt->dev_priv; 1640 int ret; 1641 1642 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL, 1643 intel_vgpu_reg_imr_handler); 1644 1645 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); 1646 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); 1647 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); 1648 MMIO_D(SDEISR, D_ALL); 1649 1650 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL); 1651 1652 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1653 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1654 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1655 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL); 1656 1657 #define RING_REG(base) _MMIO((base) + 0x28) 1658 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1659 #undef RING_REG 1660 1661 #define RING_REG(base) _MMIO((base) + 0x134) 1662 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL); 1663 #undef RING_REG 1664 1665 #define RING_REG(base) _MMIO((base) + 0x6c) 1666 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); 1667 #undef RING_REG 1668 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); 1669 1670 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); 1671 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); 1672 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); 1673 MMIO_D(GEN7_CXT_SIZE, D_ALL); 1674 1675 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1676 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL); 1677 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 1678 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL); 1679 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL); 1680 1681 /* RING MODE */ 1682 #define RING_REG(base) _MMIO((base) + 0x29c) 1683 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, 1684 ring_mode_mmio_write); 1685 #undef RING_REG 1686 1687 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1688 NULL, NULL); 1689 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1690 NULL, NULL); 1691 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS, 1692 mmio_read_from_hw, NULL); 1693 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS, 1694 mmio_read_from_hw, NULL); 1695 1696 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1697 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1698 NULL, NULL); 1699 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1700 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1701 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1702 1703 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1704 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1705 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1706 MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1707 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1708 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL); 1709 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1710 NULL, NULL); 1711 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, 1712 NULL, NULL); 1713 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); 1714 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); 1715 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); 1716 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); 1717 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); 1718 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); 1719 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); 1720 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1721 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1722 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 1723 1724 /* display */ 1725 MMIO_F(_MMIO(0x60220), 0x20, 0, 0, 0, D_ALL, NULL, NULL); 1726 MMIO_D(_MMIO(0x602a0), D_ALL); 1727 1728 MMIO_D(_MMIO(0x65050), D_ALL); 1729 MMIO_D(_MMIO(0x650b4), D_ALL); 1730 1731 MMIO_D(_MMIO(0xc4040), D_ALL); 1732 MMIO_D(DERRMR, D_ALL); 1733 1734 MMIO_D(PIPEDSL(PIPE_A), D_ALL); 1735 MMIO_D(PIPEDSL(PIPE_B), D_ALL); 1736 MMIO_D(PIPEDSL(PIPE_C), D_ALL); 1737 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL); 1738 1739 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write); 1740 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); 1741 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write); 1742 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write); 1743 1744 MMIO_D(PIPESTAT(PIPE_A), D_ALL); 1745 MMIO_D(PIPESTAT(PIPE_B), D_ALL); 1746 MMIO_D(PIPESTAT(PIPE_C), D_ALL); 1747 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); 1748 1749 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL); 1750 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); 1751 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL); 1752 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL); 1753 1754 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL); 1755 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); 1756 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL); 1757 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL); 1758 1759 MMIO_D(CURCNTR(PIPE_A), D_ALL); 1760 MMIO_D(CURCNTR(PIPE_B), D_ALL); 1761 MMIO_D(CURCNTR(PIPE_C), D_ALL); 1762 1763 MMIO_D(CURPOS(PIPE_A), D_ALL); 1764 MMIO_D(CURPOS(PIPE_B), D_ALL); 1765 MMIO_D(CURPOS(PIPE_C), D_ALL); 1766 1767 MMIO_D(CURBASE(PIPE_A), D_ALL); 1768 MMIO_D(CURBASE(PIPE_B), D_ALL); 1769 MMIO_D(CURBASE(PIPE_C), D_ALL); 1770 1771 MMIO_D(CUR_FBC_CTL(PIPE_A), D_ALL); 1772 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); 1773 MMIO_D(CUR_FBC_CTL(PIPE_C), D_ALL); 1774 1775 MMIO_D(_MMIO(0x700ac), D_ALL); 1776 MMIO_D(_MMIO(0x710ac), D_ALL); 1777 MMIO_D(_MMIO(0x720ac), D_ALL); 1778 1779 MMIO_D(_MMIO(0x70090), D_ALL); 1780 MMIO_D(_MMIO(0x70094), D_ALL); 1781 MMIO_D(_MMIO(0x70098), D_ALL); 1782 MMIO_D(_MMIO(0x7009c), D_ALL); 1783 1784 MMIO_D(DSPCNTR(PIPE_A), D_ALL); 1785 MMIO_D(DSPADDR(PIPE_A), D_ALL); 1786 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL); 1787 MMIO_D(DSPPOS(PIPE_A), D_ALL); 1788 MMIO_D(DSPSIZE(PIPE_A), D_ALL); 1789 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); 1790 MMIO_D(DSPOFFSET(PIPE_A), D_ALL); 1791 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL); 1792 1793 MMIO_D(DSPCNTR(PIPE_B), D_ALL); 1794 MMIO_D(DSPADDR(PIPE_B), D_ALL); 1795 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL); 1796 MMIO_D(DSPPOS(PIPE_B), D_ALL); 1797 MMIO_D(DSPSIZE(PIPE_B), D_ALL); 1798 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); 1799 MMIO_D(DSPOFFSET(PIPE_B), D_ALL); 1800 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL); 1801 1802 MMIO_D(DSPCNTR(PIPE_C), D_ALL); 1803 MMIO_D(DSPADDR(PIPE_C), D_ALL); 1804 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL); 1805 MMIO_D(DSPPOS(PIPE_C), D_ALL); 1806 MMIO_D(DSPSIZE(PIPE_C), D_ALL); 1807 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); 1808 MMIO_D(DSPOFFSET(PIPE_C), D_ALL); 1809 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL); 1810 1811 MMIO_D(SPRCTL(PIPE_A), D_ALL); 1812 MMIO_D(SPRLINOFF(PIPE_A), D_ALL); 1813 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL); 1814 MMIO_D(SPRPOS(PIPE_A), D_ALL); 1815 MMIO_D(SPRSIZE(PIPE_A), D_ALL); 1816 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL); 1817 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL); 1818 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); 1819 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL); 1820 MMIO_D(SPROFFSET(PIPE_A), D_ALL); 1821 MMIO_D(SPRSCALE(PIPE_A), D_ALL); 1822 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL); 1823 1824 MMIO_D(SPRCTL(PIPE_B), D_ALL); 1825 MMIO_D(SPRLINOFF(PIPE_B), D_ALL); 1826 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL); 1827 MMIO_D(SPRPOS(PIPE_B), D_ALL); 1828 MMIO_D(SPRSIZE(PIPE_B), D_ALL); 1829 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL); 1830 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL); 1831 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); 1832 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL); 1833 MMIO_D(SPROFFSET(PIPE_B), D_ALL); 1834 MMIO_D(SPRSCALE(PIPE_B), D_ALL); 1835 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL); 1836 1837 MMIO_D(SPRCTL(PIPE_C), D_ALL); 1838 MMIO_D(SPRLINOFF(PIPE_C), D_ALL); 1839 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL); 1840 MMIO_D(SPRPOS(PIPE_C), D_ALL); 1841 MMIO_D(SPRSIZE(PIPE_C), D_ALL); 1842 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL); 1843 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL); 1844 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write); 1845 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL); 1846 MMIO_D(SPROFFSET(PIPE_C), D_ALL); 1847 MMIO_D(SPRSCALE(PIPE_C), D_ALL); 1848 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL); 1849 1850 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL); 1851 MMIO_D(HBLANK(TRANSCODER_A), D_ALL); 1852 MMIO_D(HSYNC(TRANSCODER_A), D_ALL); 1853 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL); 1854 MMIO_D(VBLANK(TRANSCODER_A), D_ALL); 1855 MMIO_D(VSYNC(TRANSCODER_A), D_ALL); 1856 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL); 1857 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL); 1858 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL); 1859 1860 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL); 1861 MMIO_D(HBLANK(TRANSCODER_B), D_ALL); 1862 MMIO_D(HSYNC(TRANSCODER_B), D_ALL); 1863 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL); 1864 MMIO_D(VBLANK(TRANSCODER_B), D_ALL); 1865 MMIO_D(VSYNC(TRANSCODER_B), D_ALL); 1866 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL); 1867 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL); 1868 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL); 1869 1870 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL); 1871 MMIO_D(HBLANK(TRANSCODER_C), D_ALL); 1872 MMIO_D(HSYNC(TRANSCODER_C), D_ALL); 1873 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL); 1874 MMIO_D(VBLANK(TRANSCODER_C), D_ALL); 1875 MMIO_D(VSYNC(TRANSCODER_C), D_ALL); 1876 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL); 1877 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL); 1878 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL); 1879 1880 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL); 1881 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL); 1882 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL); 1883 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL); 1884 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL); 1885 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL); 1886 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL); 1887 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL); 1888 1889 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL); 1890 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL); 1891 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL); 1892 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL); 1893 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL); 1894 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL); 1895 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL); 1896 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL); 1897 1898 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL); 1899 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL); 1900 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL); 1901 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL); 1902 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL); 1903 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL); 1904 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL); 1905 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL); 1906 1907 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL); 1908 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL); 1909 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL); 1910 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL); 1911 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL); 1912 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL); 1913 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL); 1914 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL); 1915 1916 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL); 1917 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL); 1918 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL); 1919 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL); 1920 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL); 1921 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL); 1922 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL); 1923 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL); 1924 1925 MMIO_D(PF_CTL(PIPE_A), D_ALL); 1926 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL); 1927 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL); 1928 MMIO_D(PF_VSCALE(PIPE_A), D_ALL); 1929 MMIO_D(PF_HSCALE(PIPE_A), D_ALL); 1930 1931 MMIO_D(PF_CTL(PIPE_B), D_ALL); 1932 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL); 1933 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL); 1934 MMIO_D(PF_VSCALE(PIPE_B), D_ALL); 1935 MMIO_D(PF_HSCALE(PIPE_B), D_ALL); 1936 1937 MMIO_D(PF_CTL(PIPE_C), D_ALL); 1938 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL); 1939 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL); 1940 MMIO_D(PF_VSCALE(PIPE_C), D_ALL); 1941 MMIO_D(PF_HSCALE(PIPE_C), D_ALL); 1942 1943 MMIO_D(WM0_PIPEA_ILK, D_ALL); 1944 MMIO_D(WM0_PIPEB_ILK, D_ALL); 1945 MMIO_D(WM0_PIPEC_IVB, D_ALL); 1946 MMIO_D(WM1_LP_ILK, D_ALL); 1947 MMIO_D(WM2_LP_ILK, D_ALL); 1948 MMIO_D(WM3_LP_ILK, D_ALL); 1949 MMIO_D(WM1S_LP_ILK, D_ALL); 1950 MMIO_D(WM2S_LP_IVB, D_ALL); 1951 MMIO_D(WM3S_LP_IVB, D_ALL); 1952 1953 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL); 1954 MMIO_D(BLC_PWM_CPU_CTL, D_ALL); 1955 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL); 1956 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL); 1957 1958 MMIO_D(_MMIO(0x48268), D_ALL); 1959 1960 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, 1961 gmbus_mmio_write); 1962 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); 1963 MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); 1964 1965 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1966 dp_aux_ch_ctl_mmio_write); 1967 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1968 dp_aux_ch_ctl_mmio_write); 1969 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, 1970 dp_aux_ch_ctl_mmio_write); 1971 1972 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); 1973 1974 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write); 1975 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write); 1976 1977 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write); 1978 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); 1979 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write); 1980 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1981 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1982 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1983 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status); 1984 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); 1985 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status); 1986 1987 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_A), D_ALL); 1988 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_A), D_ALL); 1989 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_A), D_ALL); 1990 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_A), D_ALL); 1991 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_A), D_ALL); 1992 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_A), D_ALL); 1993 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_A), D_ALL); 1994 1995 MMIO_D(_MMIO(_PCH_TRANS_HTOTAL_B), D_ALL); 1996 MMIO_D(_MMIO(_PCH_TRANS_HBLANK_B), D_ALL); 1997 MMIO_D(_MMIO(_PCH_TRANS_HSYNC_B), D_ALL); 1998 MMIO_D(_MMIO(_PCH_TRANS_VTOTAL_B), D_ALL); 1999 MMIO_D(_MMIO(_PCH_TRANS_VBLANK_B), D_ALL); 2000 MMIO_D(_MMIO(_PCH_TRANS_VSYNC_B), D_ALL); 2001 MMIO_D(_MMIO(_PCH_TRANS_VSYNCSHIFT_B), D_ALL); 2002 2003 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M1), D_ALL); 2004 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N1), D_ALL); 2005 MMIO_D(_MMIO(_PCH_TRANSA_DATA_M2), D_ALL); 2006 MMIO_D(_MMIO(_PCH_TRANSA_DATA_N2), D_ALL); 2007 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M1), D_ALL); 2008 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N1), D_ALL); 2009 MMIO_D(_MMIO(_PCH_TRANSA_LINK_M2), D_ALL); 2010 MMIO_D(_MMIO(_PCH_TRANSA_LINK_N2), D_ALL); 2011 2012 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL); 2013 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL); 2014 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL); 2015 2016 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL); 2017 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL); 2018 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL); 2019 2020 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL); 2021 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL); 2022 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL); 2023 2024 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL); 2025 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL); 2026 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL); 2027 2028 MMIO_D(_MMIO(_FDI_RXA_MISC), D_ALL); 2029 MMIO_D(_MMIO(_FDI_RXB_MISC), D_ALL); 2030 MMIO_D(_MMIO(_FDI_RXA_TUSIZE1), D_ALL); 2031 MMIO_D(_MMIO(_FDI_RXA_TUSIZE2), D_ALL); 2032 MMIO_D(_MMIO(_FDI_RXB_TUSIZE1), D_ALL); 2033 MMIO_D(_MMIO(_FDI_RXB_TUSIZE2), D_ALL); 2034 2035 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write); 2036 MMIO_D(PCH_PP_DIVISOR, D_ALL); 2037 MMIO_D(PCH_PP_STATUS, D_ALL); 2038 MMIO_D(PCH_LVDS, D_ALL); 2039 MMIO_D(_MMIO(_PCH_DPLL_A), D_ALL); 2040 MMIO_D(_MMIO(_PCH_DPLL_B), D_ALL); 2041 MMIO_D(_MMIO(_PCH_FPA0), D_ALL); 2042 MMIO_D(_MMIO(_PCH_FPA1), D_ALL); 2043 MMIO_D(_MMIO(_PCH_FPB0), D_ALL); 2044 MMIO_D(_MMIO(_PCH_FPB1), D_ALL); 2045 MMIO_D(PCH_DREF_CONTROL, D_ALL); 2046 MMIO_D(PCH_RAWCLK_FREQ, D_ALL); 2047 MMIO_D(PCH_DPLL_SEL, D_ALL); 2048 2049 MMIO_D(_MMIO(0x61208), D_ALL); 2050 MMIO_D(_MMIO(0x6120c), D_ALL); 2051 MMIO_D(PCH_PP_ON_DELAYS, D_ALL); 2052 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL); 2053 2054 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); 2055 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); 2056 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); 2057 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); 2058 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); 2059 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); 2060 2061 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, 2062 PORTA_HOTPLUG_STATUS_MASK 2063 | PORTB_HOTPLUG_STATUS_MASK 2064 | PORTC_HOTPLUG_STATUS_MASK 2065 | PORTD_HOTPLUG_STATUS_MASK, 2066 NULL, NULL); 2067 2068 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write); 2069 MMIO_D(FUSE_STRAP, D_ALL); 2070 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL); 2071 2072 MMIO_D(DISP_ARB_CTL, D_ALL); 2073 MMIO_D(DISP_ARB_CTL2, D_ALL); 2074 2075 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL); 2076 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL); 2077 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL); 2078 2079 MMIO_D(SOUTH_CHICKEN1, D_ALL); 2080 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write); 2081 MMIO_D(_MMIO(_TRANSA_CHICKEN1), D_ALL); 2082 MMIO_D(_MMIO(_TRANSB_CHICKEN1), D_ALL); 2083 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL); 2084 MMIO_D(_MMIO(_TRANSA_CHICKEN2), D_ALL); 2085 MMIO_D(_MMIO(_TRANSB_CHICKEN2), D_ALL); 2086 2087 MMIO_D(ILK_DPFC_CB_BASE, D_ALL); 2088 MMIO_D(ILK_DPFC_CONTROL, D_ALL); 2089 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL); 2090 MMIO_D(ILK_DPFC_STATUS, D_ALL); 2091 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL); 2092 MMIO_D(ILK_DPFC_CHICKEN, D_ALL); 2093 MMIO_D(ILK_FBC_RT_BASE, D_ALL); 2094 2095 MMIO_D(IPS_CTL, D_ALL); 2096 2097 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL); 2098 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL); 2099 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL); 2100 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL); 2101 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL); 2102 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL); 2103 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL); 2104 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL); 2105 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL); 2106 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL); 2107 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL); 2108 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL); 2109 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL); 2110 2111 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL); 2112 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL); 2113 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL); 2114 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL); 2115 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL); 2116 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL); 2117 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL); 2118 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL); 2119 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL); 2120 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL); 2121 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL); 2122 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL); 2123 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL); 2124 2125 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL); 2126 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL); 2127 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL); 2128 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL); 2129 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL); 2130 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL); 2131 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL); 2132 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL); 2133 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL); 2134 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL); 2135 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL); 2136 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL); 2137 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL); 2138 2139 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL); 2140 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL); 2141 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2142 2143 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL); 2144 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL); 2145 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2146 2147 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL); 2148 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL); 2149 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL); 2150 2151 MMIO_D(_MMIO(0x60110), D_ALL); 2152 MMIO_D(_MMIO(0x61110), D_ALL); 2153 MMIO_F(_MMIO(0x70400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2154 MMIO_F(_MMIO(0x71400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2155 MMIO_F(_MMIO(0x72400), 0x40, 0, 0, 0, D_ALL, NULL, NULL); 2156 MMIO_F(_MMIO(0x70440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2157 MMIO_F(_MMIO(0x71440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2158 MMIO_F(_MMIO(0x72440), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2159 MMIO_F(_MMIO(0x7044c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2160 MMIO_F(_MMIO(0x7144c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2161 MMIO_F(_MMIO(0x7244c), 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL); 2162 2163 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL); 2164 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL); 2165 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL); 2166 MMIO_D(SPLL_CTL, D_ALL); 2167 MMIO_D(_MMIO(_WRPLL_CTL1), D_ALL); 2168 MMIO_D(_MMIO(_WRPLL_CTL2), D_ALL); 2169 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL); 2170 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL); 2171 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL); 2172 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL); 2173 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL); 2174 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL); 2175 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL); 2176 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL); 2177 2178 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL); 2179 MMIO_D(_MMIO(0x46508), D_ALL); 2180 2181 MMIO_D(_MMIO(0x49080), D_ALL); 2182 MMIO_D(_MMIO(0x49180), D_ALL); 2183 MMIO_D(_MMIO(0x49280), D_ALL); 2184 2185 MMIO_F(_MMIO(0x49090), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2186 MMIO_F(_MMIO(0x49190), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2187 MMIO_F(_MMIO(0x49290), 0x14, 0, 0, 0, D_ALL, NULL, NULL); 2188 2189 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL); 2190 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL); 2191 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL); 2192 2193 MMIO_D(PIPE_MULT(PIPE_A), D_ALL); 2194 MMIO_D(PIPE_MULT(PIPE_B), D_ALL); 2195 MMIO_D(PIPE_MULT(PIPE_C), D_ALL); 2196 2197 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL); 2198 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL); 2199 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL); 2200 2201 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL); 2202 MMIO_D(SBI_ADDR, D_ALL); 2203 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); 2204 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); 2205 MMIO_D(PIXCLK_GATE, D_ALL); 2206 2207 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, 2208 dp_aux_ch_ctl_mmio_write); 2209 2210 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2211 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2212 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2213 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2214 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); 2215 2216 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); 2217 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); 2218 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); 2219 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); 2220 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); 2221 2222 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); 2223 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); 2224 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write); 2225 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write); 2226 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); 2227 2228 MMIO_F(_MMIO(_DDI_BUF_TRANS_A), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2229 MMIO_F(_MMIO(0x64e60), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2230 MMIO_F(_MMIO(0x64eC0), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2231 MMIO_F(_MMIO(0x64f20), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2232 MMIO_F(_MMIO(0x64f80), 0x50, 0, 0, 0, D_ALL, NULL, NULL); 2233 2234 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL); 2235 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL); 2236 MMIO_D(HSW_AUD_MISC_CTRL(PIPE_A), D_ALL); 2237 2238 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL); 2239 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL); 2240 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL); 2241 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL); 2242 2243 MMIO_D(_MMIO(_TRANSA_MSA_MISC), D_ALL); 2244 MMIO_D(_MMIO(_TRANSB_MSA_MISC), D_ALL); 2245 MMIO_D(_MMIO(_TRANSC_MSA_MISC), D_ALL); 2246 MMIO_D(_MMIO(_TRANS_EDP_MSA_MISC), D_ALL); 2247 2248 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL); 2249 MMIO_D(FORCEWAKE_ACK, D_ALL); 2250 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL); 2251 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL); 2252 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL); 2253 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2254 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write); 2255 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL); 2256 MMIO_D(ECOBUS, D_ALL); 2257 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL); 2258 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL); 2259 MMIO_D(GEN6_RPNSWREQ, D_ALL); 2260 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL); 2261 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL); 2262 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL); 2263 MMIO_D(GEN6_RPSTAT1, D_ALL); 2264 MMIO_D(GEN6_RP_CONTROL, D_ALL); 2265 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL); 2266 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL); 2267 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL); 2268 MMIO_D(GEN6_RP_CUR_UP, D_ALL); 2269 MMIO_D(GEN6_RP_PREV_UP, D_ALL); 2270 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL); 2271 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL); 2272 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL); 2273 MMIO_D(GEN6_RP_UP_EI, D_ALL); 2274 MMIO_D(GEN6_RP_DOWN_EI, D_ALL); 2275 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL); 2276 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL); 2277 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL); 2278 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL); 2279 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL); 2280 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL); 2281 MMIO_D(GEN6_RC_SLEEP, D_ALL); 2282 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL); 2283 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL); 2284 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL); 2285 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL); 2286 MMIO_D(GEN6_PMINTRMSK, D_ALL); 2287 /* 2288 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2289 * register. 2290 */ 2291 MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2292 power_well_ctl_mmio_write); 2293 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2294 power_well_ctl_mmio_write); 2295 MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write); 2296 MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL, 2297 power_well_ctl_mmio_write); 2298 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write); 2299 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write); 2300 2301 MMIO_D(RSTDBYCTL, D_ALL); 2302 2303 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write); 2304 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); 2305 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write); 2306 2307 MMIO_D(TILECTL, D_ALL); 2308 2309 MMIO_D(GEN6_UCGCTL1, D_ALL); 2310 MMIO_D(GEN6_UCGCTL2, D_ALL); 2311 2312 MMIO_F(_MMIO(0x4f000), 0x90, 0, 0, 0, D_ALL, NULL, NULL); 2313 2314 MMIO_D(GEN6_PCODE_DATA, D_ALL); 2315 MMIO_D(_MMIO(0x13812c), D_ALL); 2316 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL); 2317 MMIO_D(HSW_EDRAM_CAP, D_ALL); 2318 MMIO_D(HSW_IDICR, D_ALL); 2319 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL); 2320 2321 MMIO_D(_MMIO(0x3c), D_ALL); 2322 MMIO_D(_MMIO(0x860), D_ALL); 2323 MMIO_D(ECOSKPD, D_ALL); 2324 MMIO_D(_MMIO(0x121d0), D_ALL); 2325 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL); 2326 MMIO_D(_MMIO(0x41d0), D_ALL); 2327 MMIO_D(GAC_ECO_BITS, D_ALL); 2328 MMIO_D(_MMIO(0x6200), D_ALL); 2329 MMIO_D(_MMIO(0x6204), D_ALL); 2330 MMIO_D(_MMIO(0x6208), D_ALL); 2331 MMIO_D(_MMIO(0x7118), D_ALL); 2332 MMIO_D(_MMIO(0x7180), D_ALL); 2333 MMIO_D(_MMIO(0x7408), D_ALL); 2334 MMIO_D(_MMIO(0x7c00), D_ALL); 2335 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write); 2336 MMIO_D(_MMIO(0x911c), D_ALL); 2337 MMIO_D(_MMIO(0x9120), D_ALL); 2338 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL); 2339 2340 MMIO_D(GAB_CTL, D_ALL); 2341 MMIO_D(_MMIO(0x48800), D_ALL); 2342 MMIO_D(_MMIO(0xce044), D_ALL); 2343 MMIO_D(_MMIO(0xe6500), D_ALL); 2344 MMIO_D(_MMIO(0xe6504), D_ALL); 2345 MMIO_D(_MMIO(0xe6600), D_ALL); 2346 MMIO_D(_MMIO(0xe6604), D_ALL); 2347 MMIO_D(_MMIO(0xe6700), D_ALL); 2348 MMIO_D(_MMIO(0xe6704), D_ALL); 2349 MMIO_D(_MMIO(0xe6800), D_ALL); 2350 MMIO_D(_MMIO(0xe6804), D_ALL); 2351 MMIO_D(PCH_GMBUS4, D_ALL); 2352 MMIO_D(PCH_GMBUS5, D_ALL); 2353 2354 MMIO_D(_MMIO(0x902c), D_ALL); 2355 MMIO_D(_MMIO(0xec008), D_ALL); 2356 MMIO_D(_MMIO(0xec00c), D_ALL); 2357 MMIO_D(_MMIO(0xec008 + 0x18), D_ALL); 2358 MMIO_D(_MMIO(0xec00c + 0x18), D_ALL); 2359 MMIO_D(_MMIO(0xec008 + 0x18 * 2), D_ALL); 2360 MMIO_D(_MMIO(0xec00c + 0x18 * 2), D_ALL); 2361 MMIO_D(_MMIO(0xec008 + 0x18 * 3), D_ALL); 2362 MMIO_D(_MMIO(0xec00c + 0x18 * 3), D_ALL); 2363 MMIO_D(_MMIO(0xec408), D_ALL); 2364 MMIO_D(_MMIO(0xec40c), D_ALL); 2365 MMIO_D(_MMIO(0xec408 + 0x18), D_ALL); 2366 MMIO_D(_MMIO(0xec40c + 0x18), D_ALL); 2367 MMIO_D(_MMIO(0xec408 + 0x18 * 2), D_ALL); 2368 MMIO_D(_MMIO(0xec40c + 0x18 * 2), D_ALL); 2369 MMIO_D(_MMIO(0xec408 + 0x18 * 3), D_ALL); 2370 MMIO_D(_MMIO(0xec40c + 0x18 * 3), D_ALL); 2371 MMIO_D(_MMIO(0xfc810), D_ALL); 2372 MMIO_D(_MMIO(0xfc81c), D_ALL); 2373 MMIO_D(_MMIO(0xfc828), D_ALL); 2374 MMIO_D(_MMIO(0xfc834), D_ALL); 2375 MMIO_D(_MMIO(0xfcc00), D_ALL); 2376 MMIO_D(_MMIO(0xfcc0c), D_ALL); 2377 MMIO_D(_MMIO(0xfcc18), D_ALL); 2378 MMIO_D(_MMIO(0xfcc24), D_ALL); 2379 MMIO_D(_MMIO(0xfd000), D_ALL); 2380 MMIO_D(_MMIO(0xfd00c), D_ALL); 2381 MMIO_D(_MMIO(0xfd018), D_ALL); 2382 MMIO_D(_MMIO(0xfd024), D_ALL); 2383 MMIO_D(_MMIO(0xfd034), D_ALL); 2384 2385 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write); 2386 MMIO_D(_MMIO(0x2054), D_ALL); 2387 MMIO_D(_MMIO(0x12054), D_ALL); 2388 MMIO_D(_MMIO(0x22054), D_ALL); 2389 MMIO_D(_MMIO(0x1a054), D_ALL); 2390 2391 MMIO_D(_MMIO(0x44070), D_ALL); 2392 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2393 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2394 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2395 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); 2396 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); 2397 2398 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); 2399 MMIO_D(_MMIO(0x2b00), D_BDW_PLUS); 2400 MMIO_D(_MMIO(0x2360), D_BDW_PLUS); 2401 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2402 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2403 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2404 2405 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2406 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2407 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL); 2408 2409 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2410 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2411 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2412 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2413 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2414 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2415 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2416 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2417 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2418 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2419 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); 2420 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2421 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2422 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2423 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2424 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); 2425 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2426 2427 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2428 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL); 2429 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2430 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2431 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); 2432 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL); 2433 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL); 2434 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2435 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2436 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2437 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2438 return 0; 2439 } 2440 2441 static int init_broadwell_mmio_info(struct intel_gvt *gvt) 2442 { 2443 struct drm_i915_private *dev_priv = gvt->dev_priv; 2444 int ret; 2445 2446 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2447 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2448 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2449 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS); 2450 2451 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2452 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2453 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2454 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS); 2455 2456 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2457 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2458 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2459 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS); 2460 2461 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2462 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2463 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2464 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS); 2465 2466 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, 2467 intel_vgpu_reg_imr_handler); 2468 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, 2469 intel_vgpu_reg_ier_handler); 2470 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, 2471 intel_vgpu_reg_iir_handler); 2472 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS); 2473 2474 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, 2475 intel_vgpu_reg_imr_handler); 2476 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, 2477 intel_vgpu_reg_ier_handler); 2478 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, 2479 intel_vgpu_reg_iir_handler); 2480 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS); 2481 2482 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, 2483 intel_vgpu_reg_imr_handler); 2484 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, 2485 intel_vgpu_reg_ier_handler); 2486 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, 2487 intel_vgpu_reg_iir_handler); 2488 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS); 2489 2490 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2491 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2492 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2493 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS); 2494 2495 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2496 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2497 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2498 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS); 2499 2500 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); 2501 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); 2502 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); 2503 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS); 2504 2505 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, 2506 intel_vgpu_reg_master_irq_handler); 2507 2508 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, 2509 mmio_read_from_hw, NULL); 2510 2511 #define RING_REG(base) _MMIO((base) + 0xd0) 2512 MMIO_RING_F(RING_REG, 4, F_RO, 0, 2513 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL, 2514 ring_reset_ctl_write); 2515 #undef RING_REG 2516 2517 #define RING_REG(base) _MMIO((base) + 0x230) 2518 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); 2519 #undef RING_REG 2520 2521 #define RING_REG(base) _MMIO((base) + 0x234) 2522 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS, 2523 NULL, NULL); 2524 #undef RING_REG 2525 2526 #define RING_REG(base) _MMIO((base) + 0x244) 2527 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2528 #undef RING_REG 2529 2530 #define RING_REG(base) _MMIO((base) + 0x370) 2531 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); 2532 #undef RING_REG 2533 2534 #define RING_REG(base) _MMIO((base) + 0x3a0) 2535 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL); 2536 #undef RING_REG 2537 2538 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS); 2539 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS); 2540 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS); 2541 MMIO_D(_MMIO(0x1c1d0), D_BDW_PLUS); 2542 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS); 2543 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS); 2544 MMIO_D(_MMIO(0x1c054), D_BDW_PLUS); 2545 2546 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write); 2547 2548 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS); 2549 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS); 2550 2551 MMIO_D(GAMTARBMODE, D_BDW_PLUS); 2552 2553 #define RING_REG(base) _MMIO((base) + 0x270) 2554 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL); 2555 #undef RING_REG 2556 2557 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write); 2558 2559 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2560 2561 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS); 2562 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS); 2563 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS); 2564 2565 MMIO_D(WM_MISC, D_BDW); 2566 MMIO_D(_MMIO(BDW_EDP_PSR_BASE), D_BDW); 2567 2568 MMIO_D(_MMIO(0x6671c), D_BDW_PLUS); 2569 MMIO_D(_MMIO(0x66c00), D_BDW_PLUS); 2570 MMIO_D(_MMIO(0x66c04), D_BDW_PLUS); 2571 2572 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS); 2573 2574 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS); 2575 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS); 2576 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS); 2577 2578 MMIO_D(_MMIO(0xfdc), D_BDW_PLUS); 2579 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2580 NULL, NULL); 2581 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, 2582 NULL, NULL); 2583 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2584 2585 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2586 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); 2587 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2588 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); 2589 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); 2590 MMIO_D(_MMIO(0xb110), D_BDW); 2591 2592 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, 2593 NULL, force_nonpriv_write); 2594 2595 MMIO_D(_MMIO(0x44484), D_BDW_PLUS); 2596 MMIO_D(_MMIO(0x4448c), D_BDW_PLUS); 2597 2598 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); 2599 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS); 2600 2601 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); 2602 2603 MMIO_D(_MMIO(0x110000), D_BDW_PLUS); 2604 2605 MMIO_D(_MMIO(0x48400), D_BDW_PLUS); 2606 2607 MMIO_D(_MMIO(0x6e570), D_BDW_PLUS); 2608 MMIO_D(_MMIO(0x65f10), D_BDW_PLUS); 2609 2610 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2611 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2612 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2613 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2614 2615 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); 2616 2617 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2618 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2619 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2620 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2621 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2622 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2623 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2624 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2625 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); 2626 return 0; 2627 } 2628 2629 static int init_skl_mmio_info(struct intel_gvt *gvt) 2630 { 2631 struct drm_i915_private *dev_priv = gvt->dev_priv; 2632 int ret; 2633 2634 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2635 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL); 2636 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2637 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL); 2638 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write); 2639 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL); 2640 2641 MMIO_F(_MMIO(_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2642 dp_aux_ch_ctl_mmio_write); 2643 MMIO_F(_MMIO(_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2644 dp_aux_ch_ctl_mmio_write); 2645 MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, 2646 dp_aux_ch_ctl_mmio_write); 2647 2648 /* 2649 * Use an arbitrary power well controlled by the PWR_WELL_CTL 2650 * register. 2651 */ 2652 MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS); 2653 MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL, 2654 skl_power_well_ctl_write); 2655 2656 MMIO_D(_MMIO(0xa210), D_SKL_PLUS); 2657 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2658 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS); 2659 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2660 MMIO_DH(_MMIO(0x4ddc), D_SKL_PLUS, NULL, NULL); 2661 MMIO_DH(_MMIO(0x42080), D_SKL_PLUS, NULL, NULL); 2662 MMIO_D(_MMIO(0x45504), D_SKL_PLUS); 2663 MMIO_D(_MMIO(0x45520), D_SKL_PLUS); 2664 MMIO_D(_MMIO(0x46000), D_SKL_PLUS); 2665 MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write); 2666 MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write); 2667 MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL); 2668 MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL); 2669 MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL); 2670 MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL); 2671 MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL); 2672 MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL); 2673 MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL); 2674 MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL); 2675 MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL); 2676 2677 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2678 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2679 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2680 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2681 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2682 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2683 2684 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2685 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2686 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2687 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2688 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2689 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2690 2691 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); 2692 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write); 2693 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); 2694 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write); 2695 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); 2696 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write); 2697 2698 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2699 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2700 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2701 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2702 2703 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2704 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2705 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2706 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2707 2708 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2709 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2710 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2711 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2712 2713 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); 2714 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); 2715 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); 2716 2717 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2718 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2719 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2720 2721 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2722 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2723 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2724 2725 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2726 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2727 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2728 2729 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2730 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2731 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL_PLUS, NULL, NULL); 2732 2733 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2734 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2735 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2736 2737 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2738 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2739 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2740 2741 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2742 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2743 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2744 2745 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL); 2746 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL); 2747 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL); 2748 2749 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); 2750 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); 2751 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); 2752 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); 2753 2754 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); 2755 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); 2756 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); 2757 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); 2758 2759 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); 2760 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); 2761 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); 2762 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); 2763 2764 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2765 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2766 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2767 MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2768 2769 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2770 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2771 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2772 MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2773 2774 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2775 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2776 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2777 MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2778 2779 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); 2780 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); 2781 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); 2782 MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); 2783 2784 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); 2785 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); 2786 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); 2787 MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); 2788 2789 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); 2790 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); 2791 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); 2792 MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); 2793 2794 MMIO_D(_MMIO(0x70380), D_SKL_PLUS); 2795 MMIO_D(_MMIO(0x71380), D_SKL_PLUS); 2796 MMIO_D(_MMIO(0x72380), D_SKL_PLUS); 2797 MMIO_D(_MMIO(0x7239c), D_SKL_PLUS); 2798 MMIO_D(_MMIO(0x7039c), D_SKL_PLUS); 2799 2800 MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL); 2801 MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL); 2802 MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL); 2803 2804 MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL); 2805 2806 MMIO_D(_MMIO(0x51000), D_SKL | D_KBL); 2807 MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS); 2808 2809 MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2810 MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL); 2811 2812 MMIO_D(RPM_CONFIG0, D_SKL_PLUS); 2813 MMIO_D(_MMIO(0xd08), D_SKL_PLUS); 2814 MMIO_D(RC6_LOCATION, D_SKL_PLUS); 2815 MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL); 2816 MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); 2817 2818 /* TRTT */ 2819 MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2820 MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2821 MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2822 MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2823 MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL); 2824 MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write); 2825 MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write); 2826 2827 MMIO_D(_MMIO(0x45008), D_SKL | D_KBL); 2828 2829 MMIO_D(_MMIO(0x46430), D_SKL | D_KBL); 2830 2831 MMIO_D(_MMIO(0x46520), D_SKL | D_KBL); 2832 2833 MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL); 2834 MMIO_D(_MMIO(0xb004), D_SKL_PLUS); 2835 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write); 2836 2837 MMIO_D(_MMIO(0x65900), D_SKL_PLUS); 2838 MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL); 2839 MMIO_D(_MMIO(0x4068), D_SKL | D_KBL); 2840 MMIO_D(_MMIO(0x67054), D_SKL | D_KBL); 2841 MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL); 2842 MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL); 2843 MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL); 2844 MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL); 2845 MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL); 2846 MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL); 2847 2848 MMIO_D(_MMIO(0x70034), D_SKL_PLUS); 2849 MMIO_D(_MMIO(0x71034), D_SKL_PLUS); 2850 MMIO_D(_MMIO(0x72034), D_SKL_PLUS); 2851 2852 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A)), D_SKL_PLUS); 2853 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B)), D_SKL_PLUS); 2854 MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C)), D_SKL_PLUS); 2855 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A)), D_SKL_PLUS); 2856 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B)), D_SKL_PLUS); 2857 MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C)), D_SKL_PLUS); 2858 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A)), D_SKL_PLUS); 2859 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B)), D_SKL_PLUS); 2860 MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C)), D_SKL_PLUS); 2861 2862 MMIO_D(_MMIO(0x44500), D_SKL_PLUS); 2863 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); 2864 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS, 2865 NULL, NULL); 2866 2867 MMIO_D(_MMIO(0x4ab8), D_KBL); 2868 MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL); 2869 2870 return 0; 2871 } 2872 2873 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt, 2874 unsigned int offset) 2875 { 2876 unsigned long device = intel_gvt_get_device_type(gvt); 2877 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2878 int num = gvt->mmio.num_mmio_block; 2879 int i; 2880 2881 for (i = 0; i < num; i++, block++) { 2882 if (!(device & block->device)) 2883 continue; 2884 if (offset >= i915_mmio_reg_offset(block->offset) && 2885 offset < i915_mmio_reg_offset(block->offset) + block->size) 2886 return block; 2887 } 2888 return NULL; 2889 } 2890 2891 /** 2892 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device 2893 * @gvt: GVT device 2894 * 2895 * This function is called at the driver unloading stage, to clean up the MMIO 2896 * information table of GVT device 2897 * 2898 */ 2899 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt) 2900 { 2901 struct hlist_node *tmp; 2902 struct intel_gvt_mmio_info *e; 2903 int i; 2904 2905 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node) 2906 kfree(e); 2907 2908 vfree(gvt->mmio.mmio_attribute); 2909 gvt->mmio.mmio_attribute = NULL; 2910 } 2911 2912 /* Special MMIO blocks. */ 2913 static struct gvt_mmio_block mmio_blocks[] = { 2914 {D_SKL_PLUS, _MMIO(CSR_MMIO_START_RANGE), 0x3000, NULL, NULL}, 2915 {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL}, 2916 {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE, 2917 pvinfo_mmio_read, pvinfo_mmio_write}, 2918 {D_ALL, LGC_PALETTE(PIPE_A, 0), 1024, NULL, NULL}, 2919 {D_ALL, LGC_PALETTE(PIPE_B, 0), 1024, NULL, NULL}, 2920 {D_ALL, LGC_PALETTE(PIPE_C, 0), 1024, NULL, NULL}, 2921 }; 2922 2923 /** 2924 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device 2925 * @gvt: GVT device 2926 * 2927 * This function is called at the initialization stage, to setup the MMIO 2928 * information table for GVT device 2929 * 2930 * Returns: 2931 * zero on success, negative if failed. 2932 */ 2933 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt) 2934 { 2935 struct intel_gvt_device_info *info = &gvt->device_info; 2936 struct drm_i915_private *dev_priv = gvt->dev_priv; 2937 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute); 2938 int ret; 2939 2940 gvt->mmio.mmio_attribute = vzalloc(size); 2941 if (!gvt->mmio.mmio_attribute) 2942 return -ENOMEM; 2943 2944 ret = init_generic_mmio_info(gvt); 2945 if (ret) 2946 goto err; 2947 2948 if (IS_BROADWELL(dev_priv)) { 2949 ret = init_broadwell_mmio_info(gvt); 2950 if (ret) 2951 goto err; 2952 } else if (IS_SKYLAKE(dev_priv) 2953 || IS_KABYLAKE(dev_priv)) { 2954 ret = init_broadwell_mmio_info(gvt); 2955 if (ret) 2956 goto err; 2957 ret = init_skl_mmio_info(gvt); 2958 if (ret) 2959 goto err; 2960 } 2961 2962 gvt->mmio.mmio_block = mmio_blocks; 2963 gvt->mmio.num_mmio_block = ARRAY_SIZE(mmio_blocks); 2964 2965 return 0; 2966 err: 2967 intel_gvt_clean_mmio_info(gvt); 2968 return ret; 2969 } 2970 2971 /** 2972 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio 2973 * @gvt: a GVT device 2974 * @handler: the handler 2975 * @data: private data given to handler 2976 * 2977 * Returns: 2978 * Zero on success, negative error code if failed. 2979 */ 2980 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, 2981 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), 2982 void *data) 2983 { 2984 struct gvt_mmio_block *block = gvt->mmio.mmio_block; 2985 struct intel_gvt_mmio_info *e; 2986 int i, j, ret; 2987 2988 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) { 2989 ret = handler(gvt, e->offset, data); 2990 if (ret) 2991 return ret; 2992 } 2993 2994 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { 2995 for (j = 0; j < block->size; j += 4) { 2996 ret = handler(gvt, 2997 i915_mmio_reg_offset(block->offset) + j, 2998 data); 2999 if (ret) 3000 return ret; 3001 } 3002 } 3003 return 0; 3004 } 3005 3006 /** 3007 * intel_vgpu_default_mmio_read - default MMIO read handler 3008 * @vgpu: a vGPU 3009 * @offset: access offset 3010 * @p_data: data return buffer 3011 * @bytes: access data length 3012 * 3013 * Returns: 3014 * Zero on success, negative error code if failed. 3015 */ 3016 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 3017 void *p_data, unsigned int bytes) 3018 { 3019 read_vreg(vgpu, offset, p_data, bytes); 3020 return 0; 3021 } 3022 3023 /** 3024 * intel_t_default_mmio_write - default MMIO write handler 3025 * @vgpu: a vGPU 3026 * @offset: access offset 3027 * @p_data: write data buffer 3028 * @bytes: access data length 3029 * 3030 * Returns: 3031 * Zero on success, negative error code if failed. 3032 */ 3033 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 3034 void *p_data, unsigned int bytes) 3035 { 3036 write_vreg(vgpu, offset, p_data, bytes); 3037 return 0; 3038 } 3039 3040 /** 3041 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be 3042 * force-nopriv register 3043 * 3044 * @gvt: a GVT device 3045 * @offset: register offset 3046 * 3047 * Returns: 3048 * True if the register is in force-nonpriv whitelist; 3049 * False if outside; 3050 */ 3051 bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, 3052 unsigned int offset) 3053 { 3054 return in_whitelist(offset); 3055 } 3056 3057 /** 3058 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers 3059 * @vgpu: a vGPU 3060 * @offset: register offset 3061 * @pdata: data buffer 3062 * @bytes: data length 3063 * 3064 * Returns: 3065 * Zero on success, negative error code if failed. 3066 */ 3067 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 3068 void *pdata, unsigned int bytes, bool is_read) 3069 { 3070 struct intel_gvt *gvt = vgpu->gvt; 3071 struct intel_gvt_mmio_info *mmio_info; 3072 struct gvt_mmio_block *mmio_block; 3073 gvt_mmio_func func; 3074 int ret; 3075 3076 if (WARN_ON(bytes > 8)) 3077 return -EINVAL; 3078 3079 /* 3080 * Handle special MMIO blocks. 3081 */ 3082 mmio_block = find_mmio_block(gvt, offset); 3083 if (mmio_block) { 3084 func = is_read ? mmio_block->read : mmio_block->write; 3085 if (func) 3086 return func(vgpu, offset, pdata, bytes); 3087 goto default_rw; 3088 } 3089 3090 /* 3091 * Normal tracked MMIOs. 3092 */ 3093 mmio_info = find_mmio_info(gvt, offset); 3094 if (!mmio_info) { 3095 if (!vgpu->mmio.disable_warn_untrack) 3096 gvt_vgpu_err("untracked MMIO %08x len %d\n", 3097 offset, bytes); 3098 goto default_rw; 3099 } 3100 3101 if (is_read) 3102 return mmio_info->read(vgpu, offset, pdata, bytes); 3103 else { 3104 u64 ro_mask = mmio_info->ro_mask; 3105 u32 old_vreg = 0, old_sreg = 0; 3106 u64 data = 0; 3107 3108 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3109 old_vreg = vgpu_vreg(vgpu, offset); 3110 old_sreg = vgpu_sreg(vgpu, offset); 3111 } 3112 3113 if (likely(!ro_mask)) 3114 ret = mmio_info->write(vgpu, offset, pdata, bytes); 3115 else if (!~ro_mask) { 3116 gvt_vgpu_err("try to write RO reg %x\n", offset); 3117 return 0; 3118 } else { 3119 /* keep the RO bits in the virtual register */ 3120 memcpy(&data, pdata, bytes); 3121 data &= ~ro_mask; 3122 data |= vgpu_vreg(vgpu, offset) & ro_mask; 3123 ret = mmio_info->write(vgpu, offset, &data, bytes); 3124 } 3125 3126 /* higher 16bits of mode ctl regs are mask bits for change */ 3127 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) { 3128 u32 mask = vgpu_vreg(vgpu, offset) >> 16; 3129 3130 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) 3131 | (vgpu_vreg(vgpu, offset) & mask); 3132 vgpu_sreg(vgpu, offset) = (old_sreg & ~mask) 3133 | (vgpu_sreg(vgpu, offset) & mask); 3134 } 3135 } 3136 3137 return ret; 3138 3139 default_rw: 3140 return is_read ? 3141 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) : 3142 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes); 3143 } 3144